DevIoApic.cpp@ 88631

Last change on this file since 88631 was 88631, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 Slightly more efficient when a VM does not have an IOMMU configured.
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1	/* $Id: DevIoApic.cpp 88631 2021-04-21 11:54:19Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - the mask bit number. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - the mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** Redirection table entry - Valid write mask for 82093AA. */
126	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
127	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
128	\| IOAPIC_RTE_VECTOR)
129	/** Redirection table entry - Valid read mask for 82093AA. */
130	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
131	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
132	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
133
134	/** Redirection table entry - Valid write mask for ICH9. */
135	/** @note The remote IRR bit has been reverted to read-only as it turns out the
136	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
139	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
140	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
141	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
142	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
143	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
144	\| IOAPIC_RTE_VECTOR)
145
146	/** Redirection table entry - Trigger mode edge. */
147	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
148	/** Redirection table entry - Trigger mode level. */
149	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
150	/** Redirection table entry - Destination mode physical. */
151	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
152	/** Redirection table entry - Destination mode logical. */
153	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
154
155
156	/** Index of indirect registers in the I/O APIC register table. */
157	#define IOAPIC_INDIRECT_INDEX_ID 0x0
158	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
159	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
160	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
161	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
162	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
163
164	/** Offset of direct registers in the I/O APIC MMIO space. */
165	#define IOAPIC_DIRECT_OFF_INDEX 0x00
166	#define IOAPIC_DIRECT_OFF_DATA 0x10
167	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
168
169	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
170	#define IOAPIC_WITH_PDM_CRITSECT
171	#ifdef IOAPIC_WITH_PDM_CRITSECT
172	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
173	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
174	#else
175	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
176	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The shared I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The ID register. */
189	uint8_t volatile u8Id;
190	/** The index register. */
191	uint8_t volatile u8Index;
192	/** Number of CPUs. */
193	uint8_t cCpus;
194	/** I/O APIC version. */
195	uint8_t u8ApicVer;
196	/** I/O APIC ID mask. */
197	uint8_t u8IdMask;
198	/** Maximum Redirection Table Entry (RTE) Entry. */
199	uint8_t u8MaxRte;
200	/** Last valid RTE indirect register index. */
201	uint8_t u8LastRteRegIdx;
202	/* Alignment padding. */
203	uint8_t u8Padding0[1];
204	/** Redirection table entry - Valid write mask. */
205	uint64_t u64RteWriteMask;
206	/** Redirection table entry - Valid read mask. */
207	uint64_t u64RteReadMask;
208
209	/** The redirection table registers. */
210	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
211	/** The IRQ tags and source IDs for each pin (tracing purposes). */
212	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
213
214	/** The internal IRR reflecting state of the interrupt lines. */
215	uint32_t uIrr;
216	/** Alignment padding. */
217	uint32_t u32Padding2;
218
219	#ifndef IOAPIC_WITH_PDM_CRITSECT
220	/** The critsect for updating to the RTEs. */
221	PDMCRITSECT CritSect;
222	#endif
223
224	/** The MMIO region. */
225	IOMMMIOHANDLE hMmio;
226
227	#ifdef VBOX_WITH_STATISTICS
228	/** Number of MMIO reads in RZ. */
229	STAMCOUNTER StatMmioReadRZ;
230	/** Number of MMIO reads in R3. */
231	STAMCOUNTER StatMmioReadR3;
232
233	/** Number of MMIO writes in RZ. */
234	STAMCOUNTER StatMmioWriteRZ;
235	/** Number of MMIO writes in R3. */
236	STAMCOUNTER StatMmioWriteR3;
237
238	/** Number of SetIrq calls in RZ. */
239	STAMCOUNTER StatSetIrqRZ;
240	/** Number of SetIrq calls in R3. */
241	STAMCOUNTER StatSetIrqR3;
242
243	/** Number of SetEoi calls in RZ. */
244	STAMCOUNTER StatSetEoiRZ;
245	/** Number of SetEoi calls in R3. */
246	STAMCOUNTER StatSetEoiR3;
247
248	/** Number of redundant edge-triggered interrupts. */
249	STAMCOUNTER StatRedundantEdgeIntr;
250	/** Number of redundant level-triggered interrupts. */
251	STAMCOUNTER StatRedundantLevelIntr;
252	/** Number of suppressed level-triggered interrupts (by remote IRR). */
253	STAMCOUNTER StatSuppressedLevelIntr;
254	/** Number of IOMMU remapped interrupts (signaled by RTE). */
255	STAMCOUNTER StatIommuRemappedIntr;
256	/** Number of IOMMU discarded interrupts (signaled by RTE). */
257	STAMCOUNTER StatIommuDiscardedIntr;
258	/** Number of IOMMU remapped MSIs. */
259	STAMCOUNTER StatIommuRemappedMsi;
260	/** Number of IOMMU denied or failed MSIs. */
261	STAMCOUNTER StatIommuDiscardedMsi;
262	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
263	STAMCOUNTER StatEoiContention;
264	/** Number of returns to ring-3 due to Set RTE lock contention. */
265	STAMCOUNTER StatSetRteContention;
266	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
267	STAMCOUNTER StatLevelIrqSent;
268	/** Number of EOIs received for level-triggered interrupts from the local
269	* APIC(s). */
270	STAMCOUNTER StatEoiReceived;
271	#endif
272	/** Per-vector stats. */
273	STAMCOUNTER aStatVectors[256];
274	} IOAPIC;
275	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
276	/** Pointer to shared IOAPIC data. */
277	typedef IOAPIC *PIOAPIC;
278	/** Pointer to const shared IOAPIC data. */
279	typedef IOAPIC const *PCIOAPIC;
280
281
282	/**
283	* The I/O APIC device state for ring-3.
284	*/
285	typedef struct IOAPICR3
286	{
287	/** The IOAPIC helpers. */
288	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
289	} IOAPICR3;
290	/** Pointer to the I/O APIC device state for ring-3. */
291	typedef IOAPICR3 *PIOAPICR3;
292
293
294	/**
295	* The I/O APIC device state for ring-0.
296	*/
297	typedef struct IOAPICR0
298	{
299	/** The IOAPIC helpers. */
300	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
301	} IOAPICR0;
302	/** Pointer to the I/O APIC device state for ring-0. */
303	typedef IOAPICR0 *PIOAPICR0;
304
305
306	/**
307	* The I/O APIC device state for raw-mode.
308	*/
309	typedef struct IOAPICRC
310	{
311	/** The IOAPIC helpers. */
312	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
313	} IOAPICRC;
314	/** Pointer to the I/O APIC device state for raw-mode. */
315	typedef IOAPICRC *PIOAPICRC;
316
317
318	/** The I/O APIC device state for the current context. */
319	typedef CTX_SUFF(IOAPIC) IOAPICCC;
320	/** Pointer to the I/O APIC device state for the current context. */
321	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
322
323
324	/**
325	* xAPIC interrupt.
326	*/
327	typedef struct XAPICINTR
328	{
329	/** The interrupt vector. */
330	uint8_t u8Vector;
331	/** The destination (mask or ID). */
332	uint8_t u8Dest;
333	/** The destination mode. */
334	uint8_t u8DestMode;
335	/** Delivery mode. */
336	uint8_t u8DeliveryMode;
337	/** Trigger mode. */
338	uint8_t u8TriggerMode;
339	/** Redirection hint. */
340	uint8_t u8RedirHint;
341	/** Polarity. */
342	uint8_t u8Polarity;
343	/** Padding. */
344	uint8_t abPadding0;
345	} XAPICINTR;
346	/** Pointer to an I/O xAPIC interrupt struct. */
347	typedef XAPICINTR *PXAPICINTR;
348	/** Pointer to a const xAPIC interrupt struct. */
349	typedef XAPICINTR const *PCXAPICINTR;
350
351
352	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
353
354	/**
355	* Gets the arbitration register.
356	*
357	* @returns The arbitration.
358	*/
359	DECLINLINE(uint32_t) ioapicGetArb(void)
360	{
361	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
362	return 0;
363	}
364
365
366	/**
367	* Gets the version register.
368	*
369	* @returns The version.
370	*/
371	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
372	{
373	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
374	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
375	return uValue;
376	}
377
378
379	/**
380	* Sets the ID register.
381	*
382	* @param pThis The shared I/O APIC device state.
383	* @param uValue The value to set.
384	*/
385	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
386	{
387	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
388	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
389	}
390
391
392	/**
393	* Gets the ID register.
394	*
395	* @returns The ID.
396	* @param pThis The shared I/O APIC device state.
397	*/
398	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
399	{
400	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
401	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
402	return uValue;
403	}
404
405
406	/**
407	* Sets the index register.
408	*
409	* @param pThis The shared I/O APIC device state.
410	* @param uValue The value to set.
411	*/
412	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
413	{
414	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
415	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
416	}
417
418
419	/**
420	* Gets the index register.
421	*
422	* @returns The index value.
423	*/
424	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
425	{
426	uint32_t const uValue = pThis->u8Index;
427	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
428	return uValue;
429	}
430
431
432	/**
433	* Converts an MSI message to an APIC interrupt.
434	*
435	* @param pMsi The MSI message to convert.
436	* @param pIntr Where to store the APIC interrupt.
437	*/
438	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
439	{
440	/*
441	* Parse the message from the physical address and data
442	* See Intel spec. 10.11.1 "Message Address Register Format".
443	* See Intel spec. 10.11.2 "Message Data Register Format".
444	*/
445	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
446	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
447	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
448
449	pIntr->u8Vector = pMsi->Data.n.u8Vector;
450	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
451	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
452	}
453
454
455	#ifdef VBOX_WITH_IOMMU_AMD
456	/**
457	* Convert an APIC interrupt to an MSI message.
458	*
459	* @param pIntr The APIC interrupt to convert.
460	* @param pMsi Where to store the MSI message.
461	*/
462	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
463	{
464	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
465	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
466	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
467	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
468
469	pMsi->Data.n.u8Vector = pIntr->u8Vector;
470	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
471	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
472
473	/* pMsi->Data.n.u1Level = ??? */
474	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
475	* possible in theory? Maybe document this more explicitly... */
476	}
477	#endif
478
479
480	/**
481	* Signals the next pending interrupt for the specified Redirection Table Entry
482	* (RTE).
483	*
484	* @param pDevIns The device instance.
485	* @param pThis The shared I/O APIC device state.
486	* @param pThisCC The I/O APIC device state for the current context.
487	* @param idxRte The index of the RTE (validated).
488	*
489	* @remarks It is the responsibility of the caller to verify that an interrupt is
490	* pending for the pin corresponding to the RTE before calling this
491	* function.
492	*/
493	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
494	{
495	#ifndef IOAPIC_WITH_PDM_CRITSECT
496	Assert(PDMCritSectIsOwner(&pThis->CritSect));
497	#endif
498
499	/*
500	* Ensure the interrupt isn't masked.
501	*/
502	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
503	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
504	{
505	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
506	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
507	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
508	{
509	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
510	if (u8RemoteIrr)
511	{
512	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
513	return;
514	}
515	}
516
517	XAPICINTR ApicIntr;
518	RT_ZERO(ApicIntr);
519	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
520	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
521	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
522	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
523	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
524	ApicIntr.u8TriggerMode = u8TriggerMode;
525	ApicIntr.u8RedirHint = 0;
526
527	#ifdef VBOX_WITH_IOMMU_AMD
528	/*
529	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
530	* For line-based interrupts we must use the southbridge I/O APIC's BDF as
531	* the origin of the interrupt, see @bugref{9654#c74}.
532	*/
533	MSIMSG MsiOut;
534	MSIMSG MsiIn;
535	RT_ZERO(MsiOut);
536	RT_ZERO(MsiIn);
537	ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
538	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, VBOX_PCI_BDF_SB_IOAPIC, &MsiIn, &MsiOut);
539	if (RT_SUCCESS(rcRemap))
540	STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
541	else if (rcRemap == VERR_IOMMU_NOT_PRESENT)
542	MsiOut = MsiIn;
543	else
544	{
545	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
546	return;
547	}
548
549	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
550
551	# ifdef RT_STRICT
552	if (RT_SUCCESS(rcRemap))
553	{
554	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte)); /* Ensure polarity hasn't changed. */
555	Assert(ApicIntr.u8TriggerMode == u8TriggerMode); /* Ensure trigger mode hasn't changed. */
556	}
557	# endif
558	#endif
559
560	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
561	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
562	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
563	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
564	ApicIntr.u8Vector, ApicIntr.u8Vector));
565
566	/*
567	* Deliver to the local APIC via the system/3-wire-APIC bus.
568	*/
569	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
570	ApicIntr.u8Dest,
571	ApicIntr.u8DestMode,
572	ApicIntr.u8DeliveryMode,
573	ApicIntr.u8Vector,
574	ApicIntr.u8Polarity,
575	ApicIntr.u8TriggerMode,
576	u32TagSrc);
577	/* Can't reschedule to R3. */
578	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
579	#ifdef DEBUG_ramshankar
580	if (rc == VERR_APIC_INTR_DISCARDED)
581	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
582	#endif
583
584	/*
585	* For level-triggered interrupts, we set the remote IRR bit to indicate
586	* the local APIC has accepted the interrupt.
587	*
588	* For edge-triggered interrupts, we should not clear the IRR bit as it
589	* should remain intact to reflect the state of the interrupt line.
590	* The device will explicitly transition to inactive state via the
591	* ioapicSetIrq() callback.
592	*/
593	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
594	&& rc == VINF_SUCCESS)
595	{
596	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
597	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
598	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
599	}
600	}
601	}
602
603
604	/**
605	* Gets the redirection table entry.
606	*
607	* @returns The redirection table entry.
608	* @param pThis The shared I/O APIC device state.
609	* @param uIndex The index value.
610	*/
611	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
612	{
613	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
614	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
615	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
616	UINT32_MAX);
617	uint32_t uValue;
618	if (!(uIndex & 1))
619	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
620	else
621	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
622
623	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
624	return uValue;
625	}
626
627
628	/**
629	* Sets the redirection table entry.
630	*
631	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
632	* @param pDevIns The device instance.
633	* @param pThis The shared I/O APIC device state.
634	* @param pThisCC The I/O APIC device state for the current context.
635	* @param uIndex The index value.
636	* @param uValue The value to set.
637	*/
638	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
639	uint32_t uIndex, uint32_t uValue)
640	{
641	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
642	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
643	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
644	VINF_SUCCESS);
645
646	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
647	if (rc == VINF_SUCCESS)
648	{
649	/*
650	* Write the low or high 32-bit value into the specified 64-bit RTE register,
651	* update only the valid, writable bits.
652	*
653	* We need to preserve the read-only bits as it can have dire consequences
654	* otherwise, see @bugref{8386#c24}.
655	*/
656	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
657	if (!(uIndex & 1))
658	{
659	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
660	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
661	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
662	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
663	}
664	else
665	{
666	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
667	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
668	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
669	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
670	}
671
672	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
673
674	/*
675	* Signal the next pending interrupt for this RTE.
676	*/
677	uint32_t const uPinMask = UINT32_C(1) << idxRte;
678	if (pThis->uIrr & uPinMask)
679	{
680	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
681	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
682	}
683
684	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
685	}
686	else
687	STAM_COUNTER_INC(&pThis->StatSetRteContention);
688
689	return rc;
690	}
691
692
693	/**
694	* Gets the data register.
695	*
696	* @returns The data value.
697	* @param pThis The shared I/O APIC device state.
698	*/
699	static uint32_t ioapicGetData(PCIOAPIC pThis)
700	{
701	uint8_t const uIndex = pThis->u8Index;
702	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
703	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
704	&& uIndex <= pThis->u8LastRteRegIdx)
705	return ioapicGetRedirTableEntry(pThis, uIndex);
706
707	uint32_t uValue;
708	switch (uIndex)
709	{
710	case IOAPIC_INDIRECT_INDEX_ID:
711	uValue = ioapicGetId(pThis);
712	break;
713
714	case IOAPIC_INDIRECT_INDEX_VERSION:
715	uValue = ioapicGetVersion(pThis);
716	break;
717
718	case IOAPIC_INDIRECT_INDEX_ARB:
719	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
720	{
721	uValue = ioapicGetArb();
722	break;
723	}
724	RT_FALL_THRU();
725
726	default:
727	uValue = UINT32_C(0xffffffff);
728	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
729	break;
730	}
731	return uValue;
732	}
733
734
735	/**
736	* Sets the data register.
737	*
738	* @returns Strict VBox status code.
739	* @param pDevIns The device instance.
740	* @param pThis The shared I/O APIC device state.
741	* @param pThisCC The I/O APIC device state for the current context.
742	* @param uValue The value to set.
743	*/
744	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
745	{
746	uint8_t const uIndex = pThis->u8Index;
747	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
748	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
749
750	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
751	&& uIndex <= pThis->u8LastRteRegIdx)
752	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
753
754	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
755	ioapicSetId(pThis, uValue);
756	else
757	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
758
759	return VINF_SUCCESS;
760	}
761
762
763	/**
764	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
765	*/
766	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
767	{
768	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
769	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
770	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
771	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
772
773	bool fRemoteIrrCleared = false;
774	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
775	if (rc == VINF_SUCCESS)
776	{
777	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
778	{
779	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
780	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
781	{
782	#ifdef DEBUG_ramshankar
783	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
784	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
785	#endif
786	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
787	fRemoteIrrCleared = true;
788	STAM_COUNTER_INC(&pThis->StatEoiReceived);
789	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
790
791	/*
792	* Signal the next pending interrupt for this RTE.
793	*/
794	uint32_t const uPinMask = UINT32_C(1) << idxRte;
795	if (pThis->uIrr & uPinMask)
796	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
797	}
798	}
799
800	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
801	#ifndef VBOX_WITH_IOMMU_AMD
802	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
803	#endif
804	}
805	else
806	STAM_COUNTER_INC(&pThis->StatEoiContention);
807
808	return rc;
809	}
810
811
812	/**
813	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
814	*/
815	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
816	{
817	RT_NOREF(uBusDevFn); /** @todo r=ramshankar: Remove this argument if it's also unnecessary with Intel IOMMU. */
818	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
819	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
820	pThis->uIrr \|= a_PinMask; \
821	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
822	} while (0)
823
824	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
825	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
826	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
827
828	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
829
830	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
831	{
832	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
833	AssertRC(rc);
834
835	uint8_t const idxRte = iIrq;
836	uint32_t const uPinMask = UINT32_C(1) << idxRte;
837	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
838	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
839
840	bool fActive = RT_BOOL(iLevel & 1);
841	/** @todo Polarity is busted elsewhere, we need to fix that
842	* first. See @bugref{8386#c7}. */
843	#if 0
844	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
845	fActive ^= u8Polarity; */
846	#endif
847	if (!fActive)
848	{
849	pThis->uIrr &= ~uPinMask;
850	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
851	return;
852	}
853
854	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
855	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
856	if (!fFlipFlop)
857	{
858	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
859	{
860	/*
861	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
862	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
863	*/
864	if (!uPrevIrr)
865	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
866	else
867	{
868	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
869	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
870	}
871	}
872	else
873	{
874	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
875
876	/*
877	* For level-triggered interrupts, redundant interrupts are not a problem
878	* and will eventually be delivered anyway after an EOI, but our PDM devices
879	* should not typically call us with no change to the level.
880	*/
881	if (!uPrevIrr)
882	{ /* likely */ }
883	else
884	{
885	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
886	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
887	}
888
889	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
890	}
891	}
892	else
893	{
894	/*
895	* The device is flip-flopping the interrupt line, which implies we should de-assert
896	* and assert the interrupt line. The interrupt line is left in the asserted state
897	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
898	* hence just the assert is done.
899	*/
900	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
901	}
902
903	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
904	}
905	#undef IOAPIC_ASSERT_IRQ
906	}
907
908
909	/**
910	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
911	*/
912	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
913	{
914	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
915	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
916	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
917
918	XAPICINTR ApicIntr;
919	RT_ZERO(ApicIntr);
920
921	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
922	/*
923	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
924	*
925	* If the Bus:Dev:Fn isn't valid, it is ASSUMED the device generating the
926	* MSI is the IOMMU itself and hence is not subject to remapping.
927	*/
928	if (PCIBDF_IS_VALID(uBusDevFn))
929	{
930	MSIMSG MsiOut;
931	RT_ZERO(MsiOut);
932	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
933	if (RT_SUCCESS(rcRemap))
934	STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
935	else if (rcRemap == VERR_IOMMU_NOT_PRESENT)
936	MsiOut = *pMsi;
937	else
938	{
939	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
940	return;
941	}
942	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
943	}
944	else
945	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
946	#else
947	NOREF(uBusDevFn);
948	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
949	#endif
950
951	/*
952	* Deliver to the local APIC via the system/3-wire-APIC bus.
953	*/
954	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
955
956	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
957	ApicIntr.u8Dest,
958	ApicIntr.u8DestMode,
959	ApicIntr.u8DeliveryMode,
960	ApicIntr.u8Vector,
961	0 /* u8Polarity - N/A */,
962	ApicIntr.u8TriggerMode,
963	uTagSrc);
964	/* Can't reschedule to R3. */
965	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
966	}
967
968
969	/**
970	* @callback_method_impl{FNIOMMMIONEWREAD}
971	*/
972	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
973	{
974	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
975	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
976	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
977	RT_NOREF_PV(pvUser);
978
979	VBOXSTRICTRC rc = VINF_SUCCESS;
980	uint32_t puValue = (uint32_t )pv;
981	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
982	switch (offReg)
983	{
984	case IOAPIC_DIRECT_OFF_INDEX:
985	*puValue = ioapicGetIndex(pThis);
986	break;
987
988	case IOAPIC_DIRECT_OFF_DATA:
989	*puValue = ioapicGetData(pThis);
990	break;
991
992	default:
993	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
994	rc = VINF_IOM_MMIO_UNUSED_FF;
995	break;
996	}
997
998	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
999	return rc;
1000	}
1001
1002
1003	/**
1004	* @callback_method_impl{FNIOMMMIONEWWRITE}
1005	*/
1006	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1007	{
1008	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1009	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1010	RT_NOREF_PV(pvUser);
1011
1012	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1013
1014	Assert(!(off & 3));
1015	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1016
1017	VBOXSTRICTRC rc = VINF_SUCCESS;
1018	uint32_t const uValue = (uint32_t const )pv;
1019	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1020
1021	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1022	switch (offReg)
1023	{
1024	case IOAPIC_DIRECT_OFF_INDEX:
1025	ioapicSetIndex(pThis, uValue);
1026	break;
1027
1028	case IOAPIC_DIRECT_OFF_DATA:
1029	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1030	break;
1031
1032	case IOAPIC_DIRECT_OFF_EOI:
1033	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1034	rc = ioapicSetEoi(pDevIns, uValue);
1035	else
1036	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1037	break;
1038
1039	default:
1040	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1041	break;
1042	}
1043
1044	return rc;
1045	}
1046
1047
1048	#ifdef IN_RING3
1049
1050	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1051	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1052	{
1053	RT_NOREF(pDesc);
1054	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1055	return VINF_SUCCESS;
1056	}
1057
1058
1059	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1060	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1061	{
1062	RT_NOREF(pDesc, pfMask);
1063	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1064	return VINF_SUCCESS;
1065	}
1066
1067
1068	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1069	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1070	{
1071	RT_NOREF(pDesc);
1072	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1073	return VINF_SUCCESS;
1074	}
1075
1076
1077	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1078	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1079	{
1080	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1081	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1082	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1083	RT_NOREF(pDesc, pfMask);
1084	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1085	}
1086
1087
1088	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1089	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1090	{
1091	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1092	RT_NOREF(pDesc);
1093	pValue->u32 = ioapicGetVersion(pThis);
1094	return VINF_SUCCESS;
1095	}
1096
1097
1098	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1099	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1100	{
1101	RT_NOREF(pvUser, pDesc);
1102	pValue->u32 = ioapicGetArb();
1103	return VINF_SUCCESS;
1104	}
1105
1106
1107	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1108	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1109	{
1110	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1111	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1112	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1113	return VINF_SUCCESS;
1114	}
1115
1116
1117	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1118	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1119	{
1120	RT_NOREF(pfMask);
1121	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1122	/* No locks, no checks, just do it. */
1123	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1124	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1125	return VINF_SUCCESS;
1126	}
1127
1128
1129	/** IOREDTBLn sub fields. */
1130	static DBGFREGSUBFIELD const g_aRteSubs[] =
1131	{
1132	{ "vector", 0, 8, 0, 0, NULL, NULL },
1133	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1134	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1135	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1136	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1137	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1138	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1139	{ "mask", 16, 1, 0, 0, NULL, NULL },
1140	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1141	{ "dest", 56, 8, 0, 0, NULL, NULL },
1142	DBGFREGSUBFIELD_TERMINATOR()
1143	};
1144
1145
1146	/** Register descriptors for DBGF. */
1147	static DBGFREGDESC const g_aRegDesc[] =
1148	{
1149	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1150	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1151	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1152	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1153	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1154	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1155	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1156	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1157	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1158	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1159	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1160	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1161	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1162	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1163	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1164	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1165	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1166	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1167	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1168	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1169	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1170	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1171	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1172	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1173	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1174	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1175	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1176	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1177	DBGFREGDESC_TERMINATOR()
1178	};
1179
1180
1181	/**
1182	* @callback_method_impl{FNDBGFHANDLERDEV}
1183	*/
1184	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1185	{
1186	RT_NOREF(pszArgs);
1187	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1188	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1189
1190	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1191
1192	uint32_t const uId = ioapicGetId(pThis);
1193	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1194	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1195
1196	uint32_t const uVer = ioapicGetVersion(pThis);
1197	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1198	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1199	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1200	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1201
1202	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1203	{
1204	uint32_t const uArb = ioapicGetArb();
1205	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1206	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1207	}
1208
1209	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1210
1211	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1212	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1213
1214	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1215	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1216	{
1217	static const char * const s_apszDeliveryModes[] =
1218	{
1219	"Fixed ",
1220	"LowPri",
1221	"SMI ",
1222	"Rsvd ",
1223	"NMI ",
1224	"INIT ",
1225	"Rsvd ",
1226	"ExtINT"
1227	};
1228
1229	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1230	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1231	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1232	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1233	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1234	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1235	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1236	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1237	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1238	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1239	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1240	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1241
1242	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1243	idxRte,
1244	pszDestMode,
1245	uDest,
1246	uMask,
1247	(pThis->uIrr >> idxRte) & 1,
1248	pszTriggerMode,
1249	uRemoteIrr,
1250	pszPolarity,
1251	pszDeliveryStatus,
1252	pszDeliveryMode,
1253	uVector,
1254	u64Rte);
1255	}
1256	}
1257
1258
1259	/**
1260	* @copydoc FNSSMDEVSAVEEXEC
1261	*/
1262	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1263	{
1264	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1265	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1266	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1267
1268	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1269	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1270	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1271	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1272	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1273
1274	return VINF_SUCCESS;
1275	}
1276
1277
1278	/**
1279	* @copydoc FNSSMDEVLOADEXEC
1280	*/
1281	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1282	{
1283	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1284	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1285	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1286
1287	Assert(uPass == SSM_PASS_FINAL);
1288	NOREF(uPass);
1289
1290	/* Weed out invalid versions. */
1291	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1292	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1293	{
1294	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1295	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1296	}
1297
1298	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1299	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1300
1301	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1302	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1303	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1304	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1305
1306	return VINF_SUCCESS;
1307	}
1308
1309
1310	/**
1311	* @interface_method_impl{PDMDEVREG,pfnReset}
1312	*/
1313	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1314	{
1315	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1316	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1317	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1318
1319	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1320	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1321
1322	pThis->uIrr = 0;
1323	pThis->u8Index = 0;
1324	pThis->u8Id = 0;
1325
1326	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1327	{
1328	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1329	pThis->au32TagSrc[idxRte] = 0;
1330	}
1331
1332	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1333	}
1334
1335
1336	/**
1337	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1338	*/
1339	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1340	{
1341	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1342	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1343
1344	pThisRC->pIoApicHlp += offDelta;
1345	}
1346
1347
1348	/**
1349	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1350	*/
1351	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1352	{
1353	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1354	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1355	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1356
1357	# ifndef IOAPIC_WITH_PDM_CRITSECT
1358	/*
1359	* Destroy the RTE critical section.
1360	*/
1361	if (PDMCritSectIsInitialized(&pThis->CritSect))
1362	PDMR3CritSectDelete(&pThis->CritSect);
1363	# else
1364	RT_NOREF_PV(pThis);
1365	# endif
1366
1367	return VINF_SUCCESS;
1368	}
1369
1370
1371	/**
1372	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1373	*/
1374	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1375	{
1376	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1377	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1378	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1379	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1380	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1381	Assert(iInstance == 0); RT_NOREF(iInstance);
1382
1383	/*
1384	* Validate and read the configuration.
1385	*/
1386	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1387
1388	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0
1389	upsets some guest which we haven't yet been tested. */
1390	uint32_t cCpus;
1391	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1392	if (RT_FAILURE(rc))
1393	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1394	pThis->cCpus = (uint8_t)cCpus;
1395
1396	char szChipType[16];
1397	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1398	if (RT_FAILURE(rc))
1399	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1400
1401	if (!strcmp(szChipType, "ICH9"))
1402	{
1403	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1404	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1405	pThis->u8IdMask = 0xff;
1406	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1407	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1408	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1409	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1410	}
1411	else if (!strcmp(szChipType, "82093AA"))
1412	{
1413	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1414	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1415	pThis->u8IdMask = 0x0f;
1416	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1417	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1418	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1419	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1420	}
1421	else if (!strcmp(szChipType, "82379AB"))
1422	{
1423	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1424	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1425	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1426	pThis->u8IdMask = 0x0f;
1427	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1428	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1429	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1430	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1431	}
1432	else
1433	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1434	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1435	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1436
1437	/*
1438	* We will use our own critical section for the IOAPIC device.
1439	*/
1440	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1441	AssertRCReturn(rc, rc);
1442
1443	# ifndef IOAPIC_WITH_PDM_CRITSECT
1444	/*
1445	* Setup the critical section to protect concurrent writes to the RTEs.
1446	*/
1447	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1448	AssertRCReturn(rc, rc);
1449	# endif
1450
1451	/*
1452	* Register the IOAPIC.
1453	*/
1454	PDMIOAPICREG IoApicReg;
1455	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1456	IoApicReg.pfnSetIrq = ioapicSetIrq;
1457	IoApicReg.pfnSendMsi = ioapicSendMsi;
1458	IoApicReg.pfnSetEoi = ioapicSetEoi;
1459	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1460	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1461	AssertRCReturn(rc, rc);
1462
1463	/*
1464	* Register MMIO region.
1465	*/
1466	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1467	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1468	AssertRCReturn(rc, rc);
1469
1470	/*
1471	* Register the saved state.
1472	*/
1473	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1474	AssertRCReturn(rc, rc);
1475
1476	/*
1477	* Register debugger info item.
1478	*/
1479	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1480	AssertRCReturn(rc, rc);
1481
1482	/*
1483	* Register debugger register access.
1484	*/
1485	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1486	AssertRCReturn(rc, rc);
1487
1488	# ifdef VBOX_WITH_STATISTICS
1489	/*
1490	* Statistics.
1491	*/
1492	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1493	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1494	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1495	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1496
1497	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1498	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1499	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1500	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1501
1502	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1503	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1504	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1505
1506	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
1507	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
1508	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
1509	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
1510
1511	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1512	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1513
1514	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1515	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1516	# endif
1517	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1518	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1519	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1520
1521	/*
1522	* Init. the device state.
1523	*/
1524	LogRel(("IOAPIC: Using implementation 2.0! I/O APIC version is %d.%d\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0F));
1525	ioapicR3Reset(pDevIns);
1526
1527	return VINF_SUCCESS;
1528	}
1529
1530	#else /* !IN_RING3 */
1531
1532	/**
1533	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1534	*/
1535	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1536	{
1537	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1538	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1539	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1540
1541	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1542	AssertRCReturn(rc, rc);
1543
1544	PDMIOAPICREG IoApicReg;
1545	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1546	IoApicReg.pfnSetIrq = ioapicSetIrq;
1547	IoApicReg.pfnSendMsi = ioapicSendMsi;
1548	IoApicReg.pfnSetEoi = ioapicSetEoi;
1549	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1550	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1551	AssertRCReturn(rc, rc);
1552
1553	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1554	AssertRCReturn(rc, rc);
1555
1556	return VINF_SUCCESS;
1557	}
1558
1559	#endif /* !IN_RING3 */
1560
1561	/**
1562	* IO APIC device registration structure.
1563	*/
1564	const PDMDEVREG g_DeviceIOAPIC =
1565	{
1566	/* .u32Version = */ PDM_DEVREG_VERSION,
1567	/* .uReserved0 = */ 0,
1568	/* .szName = */ "ioapic",
1569	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1570	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1571	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1572	/* .cMaxInstances = */ 1,
1573	/* .uSharedVersion = */ 42,
1574	/* .cbInstanceShared = */ sizeof(IOAPIC),
1575	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1576	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1577	/* .cMaxPciDevices = */ 0,
1578	/* .cMaxMsixVectors = */ 0,
1579	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1580	#if defined(IN_RING3)
1581	/* .pszRCMod = */ "VBoxDDRC.rc",
1582	/* .pszR0Mod = */ "VBoxDDR0.r0",
1583	/* .pfnConstruct = */ ioapicR3Construct,
1584	/* .pfnDestruct = */ ioapicR3Destruct,
1585	/* .pfnRelocate = */ ioapicR3Relocate,
1586	/* .pfnMemSetup = */ NULL,
1587	/* .pfnPowerOn = */ NULL,
1588	/* .pfnReset = */ ioapicR3Reset,
1589	/* .pfnSuspend = */ NULL,
1590	/* .pfnResume = */ NULL,
1591	/* .pfnAttach = */ NULL,
1592	/* .pfnDetach = */ NULL,
1593	/* .pfnQueryInterface = */ NULL,
1594	/* .pfnInitComplete = */ NULL,
1595	/* .pfnPowerOff = */ NULL,
1596	/* .pfnSoftReset = */ NULL,
1597	/* .pfnReserved0 = */ NULL,
1598	/* .pfnReserved1 = */ NULL,
1599	/* .pfnReserved2 = */ NULL,
1600	/* .pfnReserved3 = */ NULL,
1601	/* .pfnReserved4 = */ NULL,
1602	/* .pfnReserved5 = */ NULL,
1603	/* .pfnReserved6 = */ NULL,
1604	/* .pfnReserved7 = */ NULL,
1605	#elif defined(IN_RING0)
1606	/* .pfnEarlyConstruct = */ NULL,
1607	/* .pfnConstruct = */ ioapicRZConstruct,
1608	/* .pfnDestruct = */ NULL,
1609	/* .pfnFinalDestruct = */ NULL,
1610	/* .pfnRequest = */ NULL,
1611	/* .pfnReserved0 = */ NULL,
1612	/* .pfnReserved1 = */ NULL,
1613	/* .pfnReserved2 = */ NULL,
1614	/* .pfnReserved3 = */ NULL,
1615	/* .pfnReserved4 = */ NULL,
1616	/* .pfnReserved5 = */ NULL,
1617	/* .pfnReserved6 = */ NULL,
1618	/* .pfnReserved7 = */ NULL,
1619	#elif defined(IN_RC)
1620	/* .pfnConstruct = */ ioapicRZConstruct,
1621	/* .pfnReserved0 = */ NULL,
1622	/* .pfnReserved1 = */ NULL,
1623	/* .pfnReserved2 = */ NULL,
1624	/* .pfnReserved3 = */ NULL,
1625	/* .pfnReserved4 = */ NULL,
1626	/* .pfnReserved5 = */ NULL,
1627	/* .pfnReserved6 = */ NULL,
1628	/* .pfnReserved7 = */ NULL,
1629	#else
1630	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1631	#endif
1632	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1633	};
1634
1635
1636	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1637

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 88631

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