DevIoApic.cpp@ 88826

Last change on this file since 88826 was 88826, checked in by vboxsync, 4 years ago
DevIoApic: Code-style nit and a todo. We should be able to release the PDM lock here so IOMMU can re-acquire it if needed for a short amount of time. Afaict, APICBusDeliver doesn't care about PDM lock being held.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 66.6 KB

Line
1	/* $Id: DevIoApic.cpp 88826 2021-05-03 11:12:01Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - the mask bit number. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - the mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** Redirection table entry - Valid write mask for 82093AA. */
126	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
127	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
128	\| IOAPIC_RTE_VECTOR)
129	/** Redirection table entry - Valid read mask for 82093AA. */
130	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
131	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
132	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
133
134	/** Redirection table entry - Valid write mask for ICH9. */
135	/** @note The remote IRR bit has been reverted to read-only as it turns out the
136	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
139	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
140	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
141	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
142	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
143	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
144	\| IOAPIC_RTE_VECTOR)
145
146	/** Redirection table entry - Trigger mode edge. */
147	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
148	/** Redirection table entry - Trigger mode level. */
149	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
150	/** Redirection table entry - Destination mode physical. */
151	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
152	/** Redirection table entry - Destination mode logical. */
153	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
154
155
156	/** Index of indirect registers in the I/O APIC register table. */
157	#define IOAPIC_INDIRECT_INDEX_ID 0x0
158	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
159	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
160	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
161	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
162	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
163
164	/** Offset of direct registers in the I/O APIC MMIO space. */
165	#define IOAPIC_DIRECT_OFF_INDEX 0x00
166	#define IOAPIC_DIRECT_OFF_DATA 0x10
167	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
168
169	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
170	#define IOAPIC_WITH_PDM_CRITSECT
171	#ifdef IOAPIC_WITH_PDM_CRITSECT
172	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
173	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
174	#else
175	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
176	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The shared I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The ID register. */
189	uint8_t volatile u8Id;
190	/** The index register. */
191	uint8_t volatile u8Index;
192	/** Number of CPUs. */
193	uint8_t cCpus;
194	/** I/O APIC version. */
195	uint8_t u8ApicVer;
196	/** I/O APIC ID mask. */
197	uint8_t u8IdMask;
198	/** Maximum Redirection Table Entry (RTE) Entry. */
199	uint8_t u8MaxRte;
200	/** Last valid RTE indirect register index. */
201	uint8_t u8LastRteRegIdx;
202	/* Alignment padding. */
203	uint8_t u8Padding0[1];
204	/** Redirection table entry - Valid write mask. */
205	uint64_t u64RteWriteMask;
206	/** Redirection table entry - Valid read mask. */
207	uint64_t u64RteReadMask;
208
209	/** The redirection table registers. */
210	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
211	/** The IRQ tags and source IDs for each pin (tracing purposes). */
212	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
213
214	/** The internal IRR reflecting state of the interrupt lines. */
215	uint32_t uIrr;
216	/** Alignment padding. */
217	uint32_t u32Padding2;
218
219	#ifndef IOAPIC_WITH_PDM_CRITSECT
220	/** The critsect for updating to the RTEs. */
221	PDMCRITSECT CritSect;
222	#endif
223
224	/** The MMIO region. */
225	IOMMMIOHANDLE hMmio;
226
227	#ifdef VBOX_WITH_STATISTICS
228	/** Number of MMIO reads in RZ. */
229	STAMCOUNTER StatMmioReadRZ;
230	/** Number of MMIO reads in R3. */
231	STAMCOUNTER StatMmioReadR3;
232
233	/** Number of MMIO writes in RZ. */
234	STAMCOUNTER StatMmioWriteRZ;
235	/** Number of MMIO writes in R3. */
236	STAMCOUNTER StatMmioWriteR3;
237
238	/** Number of SetIrq calls in RZ. */
239	STAMCOUNTER StatSetIrqRZ;
240	/** Number of SetIrq calls in R3. */
241	STAMCOUNTER StatSetIrqR3;
242
243	/** Number of SetEoi calls in RZ. */
244	STAMCOUNTER StatSetEoiRZ;
245	/** Number of SetEoi calls in R3. */
246	STAMCOUNTER StatSetEoiR3;
247
248	/** Number of redundant edge-triggered interrupts. */
249	STAMCOUNTER StatRedundantEdgeIntr;
250	/** Number of redundant level-triggered interrupts. */
251	STAMCOUNTER StatRedundantLevelIntr;
252	/** Number of suppressed level-triggered interrupts (by remote IRR). */
253	STAMCOUNTER StatSuppressedLevelIntr;
254	/** Number of IOMMU remapped interrupts (signaled by RTE). */
255	STAMCOUNTER StatIommuRemappedIntr;
256	/** Number of IOMMU discarded interrupts (signaled by RTE). */
257	STAMCOUNTER StatIommuDiscardedIntr;
258	/** Number of IOMMU remapped MSIs. */
259	STAMCOUNTER StatIommuRemappedMsi;
260	/** Number of IOMMU denied or failed MSIs. */
261	STAMCOUNTER StatIommuDiscardedMsi;
262	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
263	STAMCOUNTER StatEoiContention;
264	/** Number of returns to ring-3 due to Set RTE lock contention. */
265	STAMCOUNTER StatSetRteContention;
266	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
267	STAMCOUNTER StatLevelIrqSent;
268	/** Number of EOIs received for level-triggered interrupts from the local
269	* APIC(s). */
270	STAMCOUNTER StatEoiReceived;
271	#endif
272	/** Per-vector stats. */
273	STAMCOUNTER aStatVectors[256];
274	} IOAPIC;
275	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
276	/** Pointer to shared IOAPIC data. */
277	typedef IOAPIC *PIOAPIC;
278	/** Pointer to const shared IOAPIC data. */
279	typedef IOAPIC const *PCIOAPIC;
280
281
282	/**
283	* The I/O APIC device state for ring-3.
284	*/
285	typedef struct IOAPICR3
286	{
287	/** The IOAPIC helpers. */
288	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
289	} IOAPICR3;
290	/** Pointer to the I/O APIC device state for ring-3. */
291	typedef IOAPICR3 *PIOAPICR3;
292
293
294	/**
295	* The I/O APIC device state for ring-0.
296	*/
297	typedef struct IOAPICR0
298	{
299	/** The IOAPIC helpers. */
300	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
301	} IOAPICR0;
302	/** Pointer to the I/O APIC device state for ring-0. */
303	typedef IOAPICR0 *PIOAPICR0;
304
305
306	/**
307	* The I/O APIC device state for raw-mode.
308	*/
309	typedef struct IOAPICRC
310	{
311	/** The IOAPIC helpers. */
312	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
313	} IOAPICRC;
314	/** Pointer to the I/O APIC device state for raw-mode. */
315	typedef IOAPICRC *PIOAPICRC;
316
317
318	/** The I/O APIC device state for the current context. */
319	typedef CTX_SUFF(IOAPIC) IOAPICCC;
320	/** Pointer to the I/O APIC device state for the current context. */
321	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
322
323
324	/**
325	* xAPIC interrupt.
326	*/
327	typedef struct XAPICINTR
328	{
329	/** The interrupt vector. */
330	uint8_t u8Vector;
331	/** The destination (mask or ID). */
332	uint8_t u8Dest;
333	/** The destination mode. */
334	uint8_t u8DestMode;
335	/** Delivery mode. */
336	uint8_t u8DeliveryMode;
337	/** Trigger mode. */
338	uint8_t u8TriggerMode;
339	/** Redirection hint. */
340	uint8_t u8RedirHint;
341	/** Polarity. */
342	uint8_t u8Polarity;
343	/** Padding. */
344	uint8_t abPadding0;
345	} XAPICINTR;
346	/** Pointer to an I/O xAPIC interrupt struct. */
347	typedef XAPICINTR *PXAPICINTR;
348	/** Pointer to a const xAPIC interrupt struct. */
349	typedef XAPICINTR const *PCXAPICINTR;
350
351
352	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
353
354	/**
355	* Gets the arbitration register.
356	*
357	* @returns The arbitration.
358	*/
359	DECLINLINE(uint32_t) ioapicGetArb(void)
360	{
361	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
362	return 0;
363	}
364
365
366	/**
367	* Gets the version register.
368	*
369	* @returns The version.
370	*/
371	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
372	{
373	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
374	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
375	return uValue;
376	}
377
378
379	/**
380	* Sets the ID register.
381	*
382	* @param pThis The shared I/O APIC device state.
383	* @param uValue The value to set.
384	*/
385	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
386	{
387	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
388	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
389	}
390
391
392	/**
393	* Gets the ID register.
394	*
395	* @returns The ID.
396	* @param pThis The shared I/O APIC device state.
397	*/
398	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
399	{
400	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
401	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
402	return uValue;
403	}
404
405
406	/**
407	* Sets the index register.
408	*
409	* @param pThis The shared I/O APIC device state.
410	* @param uValue The value to set.
411	*/
412	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
413	{
414	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
415	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
416	}
417
418
419	/**
420	* Gets the index register.
421	*
422	* @returns The index value.
423	*/
424	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
425	{
426	uint32_t const uValue = pThis->u8Index;
427	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
428	return uValue;
429	}
430
431
432	/**
433	* Converts an MSI message to an APIC interrupt.
434	*
435	* @param pMsi The MSI message to convert.
436	* @param pIntr Where to store the APIC interrupt.
437	*/
438	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
439	{
440	/*
441	* Parse the message from the physical address and data
442	* See Intel spec. 10.11.1 "Message Address Register Format".
443	* See Intel spec. 10.11.2 "Message Data Register Format".
444	*/
445	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
446	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
447	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
448
449	pIntr->u8Vector = pMsi->Data.n.u8Vector;
450	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
451	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
452	}
453
454
455	#ifdef VBOX_WITH_IOMMU_AMD
456	/**
457	* Convert an APIC interrupt to an MSI message.
458	*
459	* @param pIntr The APIC interrupt to convert.
460	* @param pMsi Where to store the MSI message.
461	*/
462	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
463	{
464	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
465	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
466	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
467	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
468
469	pMsi->Data.n.u8Vector = pIntr->u8Vector;
470	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
471	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
472
473	/* pMsi->Data.n.u1Level = ??? */
474	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
475	* possible in theory? Maybe document this more explicitly... */
476	}
477	#endif
478
479
480	/**
481	* Signals the next pending interrupt for the specified Redirection Table Entry
482	* (RTE).
483	*
484	* @param pDevIns The device instance.
485	* @param pThis The shared I/O APIC device state.
486	* @param pThisCC The I/O APIC device state for the current context.
487	* @param idxRte The index of the RTE (validated).
488	*
489	* @remarks It is the responsibility of the caller to verify that an interrupt is
490	* pending for the pin corresponding to the RTE before calling this
491	* function.
492	*/
493	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
494	{
495	#ifndef IOAPIC_WITH_PDM_CRITSECT
496	Assert(PDMCritSectIsOwner(&pThis->CritSect));
497	#endif
498
499	/*
500	* Ensure the interrupt isn't masked.
501	*/
502	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
503	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
504	{ /* likely */ }
505	else
506	return;
507
508	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
509	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
510	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
511	{
512	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
513	if (u8RemoteIrr)
514	{
515	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
516	return;
517	}
518	}
519
520	/** @todo We might be able to release the IOAPIC(PDM) lock here and re-acquire it
521	* before setting the remote IRR bit below. The APIC and IOMMU should not
522	* require the caller to hold the PDM lock. */
523
524	XAPICINTR ApicIntr;
525	RT_ZERO(ApicIntr);
526	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
527	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
528	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
529	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
530	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
531	ApicIntr.u8TriggerMode = u8TriggerMode;
532	//ApicIntr.u8RedirHint = 0;
533
534	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
535	/*
536	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
537	* For line-based interrupts we must use the southbridge I/O APIC's BDF as
538	* the origin of the interrupt, see @bugref{9654#c74}.
539	*/
540	MSIMSG MsiOut;
541	MSIMSG MsiIn;
542	RT_ZERO(MsiOut);
543	RT_ZERO(MsiIn);
544	ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
545	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, VBOX_PCI_BDF_SB_IOAPIC, &MsiIn, &MsiOut);
546	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
547	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
548	MsiOut = MsiIn;
549	else if (RT_SUCCESS(rcRemap))
550	STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
551	else
552	{
553	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
554	return;
555	}
556
557	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
558
559	# ifdef RT_STRICT
560	if (RT_SUCCESS(rcRemap))
561	{
562	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte)); /* Ensure polarity hasn't changed. */
563	Assert(ApicIntr.u8TriggerMode == u8TriggerMode); /* Ensure trigger mode hasn't changed. */
564	}
565	# endif
566	#endif
567
568	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
569	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
570	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
571	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
572	ApicIntr.u8Vector, ApicIntr.u8Vector));
573
574	/*
575	* Deliver to the local APIC via the system/3-wire-APIC bus.
576	*/
577	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
578	ApicIntr.u8Dest,
579	ApicIntr.u8DestMode,
580	ApicIntr.u8DeliveryMode,
581	ApicIntr.u8Vector,
582	ApicIntr.u8Polarity,
583	ApicIntr.u8TriggerMode,
584	u32TagSrc);
585	/* Can't reschedule to R3. */
586	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
587	#ifdef DEBUG_ramshankar
588	if (rc == VERR_APIC_INTR_DISCARDED)
589	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
590	#endif
591
592	/*
593	* For level-triggered interrupts, we set the remote IRR bit to indicate
594	* the local APIC has accepted the interrupt.
595	*
596	* For edge-triggered interrupts, we should not clear the IRR bit as it
597	* should remain intact to reflect the state of the interrupt line.
598	* The device will explicitly transition to inactive state via the
599	* ioapicSetIrq() callback.
600	*/
601	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
602	&& rc == VINF_SUCCESS)
603	{
604	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
605	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
606	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
607	}
608	}
609
610
611	/**
612	* Gets the redirection table entry.
613	*
614	* @returns The redirection table entry.
615	* @param pThis The shared I/O APIC device state.
616	* @param uIndex The index value.
617	*/
618	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
619	{
620	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
621	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
622	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
623	UINT32_MAX);
624	uint32_t uValue;
625	if (!(uIndex & 1))
626	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
627	else
628	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
629
630	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
631	return uValue;
632	}
633
634
635	/**
636	* Sets the redirection table entry.
637	*
638	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
639	* @param pDevIns The device instance.
640	* @param pThis The shared I/O APIC device state.
641	* @param pThisCC The I/O APIC device state for the current context.
642	* @param uIndex The index value.
643	* @param uValue The value to set.
644	*/
645	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
646	uint32_t uIndex, uint32_t uValue)
647	{
648	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
649	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
650	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
651	VINF_SUCCESS);
652
653	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
654	if (rc == VINF_SUCCESS)
655	{
656	/*
657	* Write the low or high 32-bit value into the specified 64-bit RTE register,
658	* update only the valid, writable bits.
659	*
660	* We need to preserve the read-only bits as it can have dire consequences
661	* otherwise, see @bugref{8386#c24}.
662	*/
663	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
664	if (!(uIndex & 1))
665	{
666	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
667	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
668	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
669	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
670	}
671	else
672	{
673	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
674	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
675	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
676	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
677	}
678
679	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
680
681	/*
682	* Signal the next pending interrupt for this RTE.
683	*/
684	uint32_t const uPinMask = UINT32_C(1) << idxRte;
685	if (pThis->uIrr & uPinMask)
686	{
687	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
688	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
689	}
690
691	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
692	}
693	else
694	STAM_COUNTER_INC(&pThis->StatSetRteContention);
695
696	return rc;
697	}
698
699
700	/**
701	* Gets the data register.
702	*
703	* @returns The data value.
704	* @param pThis The shared I/O APIC device state.
705	*/
706	static uint32_t ioapicGetData(PCIOAPIC pThis)
707	{
708	uint8_t const uIndex = pThis->u8Index;
709	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
710	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
711	&& uIndex <= pThis->u8LastRteRegIdx)
712	return ioapicGetRedirTableEntry(pThis, uIndex);
713
714	uint32_t uValue;
715	switch (uIndex)
716	{
717	case IOAPIC_INDIRECT_INDEX_ID:
718	uValue = ioapicGetId(pThis);
719	break;
720
721	case IOAPIC_INDIRECT_INDEX_VERSION:
722	uValue = ioapicGetVersion(pThis);
723	break;
724
725	case IOAPIC_INDIRECT_INDEX_ARB:
726	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
727	{
728	uValue = ioapicGetArb();
729	break;
730	}
731	RT_FALL_THRU();
732
733	default:
734	uValue = UINT32_C(0xffffffff);
735	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
736	break;
737	}
738	return uValue;
739	}
740
741
742	/**
743	* Sets the data register.
744	*
745	* @returns Strict VBox status code.
746	* @param pDevIns The device instance.
747	* @param pThis The shared I/O APIC device state.
748	* @param pThisCC The I/O APIC device state for the current context.
749	* @param uValue The value to set.
750	*/
751	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
752	{
753	uint8_t const uIndex = pThis->u8Index;
754	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
755	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
756
757	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
758	&& uIndex <= pThis->u8LastRteRegIdx)
759	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
760
761	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
762	ioapicSetId(pThis, uValue);
763	else
764	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
765
766	return VINF_SUCCESS;
767	}
768
769
770	/**
771	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
772	*/
773	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
774	{
775	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
776	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
777	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
778	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
779
780	bool fRemoteIrrCleared = false;
781	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
782	if (rc == VINF_SUCCESS)
783	{
784	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
785	{
786	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
787	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
788	{
789	#ifdef DEBUG_ramshankar
790	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
791	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
792	#endif
793	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
794	fRemoteIrrCleared = true;
795	STAM_COUNTER_INC(&pThis->StatEoiReceived);
796	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
797
798	/*
799	* Signal the next pending interrupt for this RTE.
800	*/
801	uint32_t const uPinMask = UINT32_C(1) << idxRte;
802	if (pThis->uIrr & uPinMask)
803	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
804	}
805	}
806
807	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
808	#ifndef VBOX_WITH_IOMMU_AMD
809	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
810	#endif
811	}
812	else
813	STAM_COUNTER_INC(&pThis->StatEoiContention);
814
815	return rc;
816	}
817
818
819	/**
820	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
821	*/
822	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
823	{
824	RT_NOREF(uBusDevFn); /** @todo r=ramshankar: Remove this argument if it's also unnecessary with Intel IOMMU. */
825	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
826	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
827	pThis->uIrr \|= a_PinMask; \
828	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
829	} while (0)
830
831	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
832	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
833	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
834
835	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
836
837	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
838	{
839	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
840	AssertRC(rc);
841
842	uint8_t const idxRte = iIrq;
843	uint32_t const uPinMask = UINT32_C(1) << idxRte;
844	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
845	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
846
847	bool fActive = RT_BOOL(iLevel & 1);
848	/** @todo Polarity is busted elsewhere, we need to fix that
849	* first. See @bugref{8386#c7}. */
850	#if 0
851	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
852	fActive ^= u8Polarity; */
853	#endif
854	if (!fActive)
855	{
856	pThis->uIrr &= ~uPinMask;
857	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
858	return;
859	}
860
861	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
862	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
863	if (!fFlipFlop)
864	{
865	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
866	{
867	/*
868	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
869	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
870	*/
871	if (!uPrevIrr)
872	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
873	else
874	{
875	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
876	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
877	}
878	}
879	else
880	{
881	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
882
883	/*
884	* For level-triggered interrupts, redundant interrupts are not a problem
885	* and will eventually be delivered anyway after an EOI, but our PDM devices
886	* should not typically call us with no change to the level.
887	*/
888	if (!uPrevIrr)
889	{ /* likely */ }
890	else
891	{
892	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
893	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
894	}
895
896	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
897	}
898	}
899	else
900	{
901	/*
902	* The device is flip-flopping the interrupt line, which implies we should de-assert
903	* and assert the interrupt line. The interrupt line is left in the asserted state
904	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
905	* hence just the assert is done.
906	*/
907	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
908	}
909
910	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
911	}
912	#undef IOAPIC_ASSERT_IRQ
913	}
914
915
916	/**
917	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
918	*/
919	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
920	{
921	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
922	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
923	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
924
925	XAPICINTR ApicIntr;
926	RT_ZERO(ApicIntr);
927
928	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
929	/*
930	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
931	*
932	* If the Bus:Dev:Fn isn't valid, it is ASSUMED the device generating the
933	* MSI may be the IOMMU itself and hence is not subject to remapping.
934	*
935	* For AMD IOMMUs, since it's a full fledged PCI device, the BDF will be
936	* valid but will be handled by VERR_IOMMU_CANNOT_CALL_SELF case.
937	*/
938	if (PCIBDF_IS_VALID(uBusDevFn))
939	{
940	MSIMSG MsiOut;
941	RT_ZERO(MsiOut);
942	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
943	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
944	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
945	MsiOut = *pMsi;
946	else if (RT_SUCCESS(rcRemap))
947	STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
948	else
949	{
950	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
951	return;
952	}
953	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
954	}
955	else
956	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
957	#else
958	NOREF(uBusDevFn);
959	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
960	#endif
961
962	/*
963	* Deliver to the local APIC via the system/3-wire-APIC bus.
964	*/
965	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
966
967	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
968	ApicIntr.u8Dest,
969	ApicIntr.u8DestMode,
970	ApicIntr.u8DeliveryMode,
971	ApicIntr.u8Vector,
972	0 /* u8Polarity - N/A */,
973	ApicIntr.u8TriggerMode,
974	uTagSrc);
975	/* Can't reschedule to R3. */
976	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
977	}
978
979
980	/**
981	* @callback_method_impl{FNIOMMMIONEWREAD}
982	*/
983	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
984	{
985	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
986	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
987	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
988	RT_NOREF_PV(pvUser);
989
990	VBOXSTRICTRC rc = VINF_SUCCESS;
991	uint32_t puValue = (uint32_t )pv;
992	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
993	switch (offReg)
994	{
995	case IOAPIC_DIRECT_OFF_INDEX:
996	*puValue = ioapicGetIndex(pThis);
997	break;
998
999	case IOAPIC_DIRECT_OFF_DATA:
1000	*puValue = ioapicGetData(pThis);
1001	break;
1002
1003	default:
1004	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1005	rc = VINF_IOM_MMIO_UNUSED_FF;
1006	break;
1007	}
1008
1009	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
1010	return rc;
1011	}
1012
1013
1014	/**
1015	* @callback_method_impl{FNIOMMMIONEWWRITE}
1016	*/
1017	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1018	{
1019	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1020	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1021	RT_NOREF_PV(pvUser);
1022
1023	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1024
1025	Assert(!(off & 3));
1026	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1027
1028	VBOXSTRICTRC rc = VINF_SUCCESS;
1029	uint32_t const uValue = (uint32_t const )pv;
1030	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1031
1032	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1033	switch (offReg)
1034	{
1035	case IOAPIC_DIRECT_OFF_INDEX:
1036	ioapicSetIndex(pThis, uValue);
1037	break;
1038
1039	case IOAPIC_DIRECT_OFF_DATA:
1040	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1041	break;
1042
1043	case IOAPIC_DIRECT_OFF_EOI:
1044	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1045	rc = ioapicSetEoi(pDevIns, uValue);
1046	else
1047	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1048	break;
1049
1050	default:
1051	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1052	break;
1053	}
1054
1055	return rc;
1056	}
1057
1058
1059	#ifdef IN_RING3
1060
1061	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1062	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1063	{
1064	RT_NOREF(pDesc);
1065	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1066	return VINF_SUCCESS;
1067	}
1068
1069
1070	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1071	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1072	{
1073	RT_NOREF(pDesc, pfMask);
1074	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1075	return VINF_SUCCESS;
1076	}
1077
1078
1079	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1080	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1081	{
1082	RT_NOREF(pDesc);
1083	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1084	return VINF_SUCCESS;
1085	}
1086
1087
1088	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1089	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1090	{
1091	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1092	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1093	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1094	RT_NOREF(pDesc, pfMask);
1095	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1096	}
1097
1098
1099	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1100	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1101	{
1102	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1103	RT_NOREF(pDesc);
1104	pValue->u32 = ioapicGetVersion(pThis);
1105	return VINF_SUCCESS;
1106	}
1107
1108
1109	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1110	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1111	{
1112	RT_NOREF(pvUser, pDesc);
1113	pValue->u32 = ioapicGetArb();
1114	return VINF_SUCCESS;
1115	}
1116
1117
1118	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1119	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1120	{
1121	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1122	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1123	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1124	return VINF_SUCCESS;
1125	}
1126
1127
1128	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1129	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1130	{
1131	RT_NOREF(pfMask);
1132	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1133	/* No locks, no checks, just do it. */
1134	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1135	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1136	return VINF_SUCCESS;
1137	}
1138
1139
1140	/** IOREDTBLn sub fields. */
1141	static DBGFREGSUBFIELD const g_aRteSubs[] =
1142	{
1143	{ "vector", 0, 8, 0, 0, NULL, NULL },
1144	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1145	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1146	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1147	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1148	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1149	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1150	{ "mask", 16, 1, 0, 0, NULL, NULL },
1151	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1152	{ "dest", 56, 8, 0, 0, NULL, NULL },
1153	DBGFREGSUBFIELD_TERMINATOR()
1154	};
1155
1156
1157	/** Register descriptors for DBGF. */
1158	static DBGFREGDESC const g_aRegDesc[] =
1159	{
1160	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1161	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1162	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1163	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1164	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1165	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1166	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1167	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1168	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1169	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1170	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1171	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1172	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1173	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1174	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1175	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1176	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1177	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1178	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1179	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1180	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1181	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1182	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1183	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1184	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1185	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1186	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1187	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1188	DBGFREGDESC_TERMINATOR()
1189	};
1190
1191
1192	/**
1193	* @callback_method_impl{FNDBGFHANDLERDEV}
1194	*/
1195	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1196	{
1197	RT_NOREF(pszArgs);
1198	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1199	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1200
1201	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1202
1203	uint32_t const uId = ioapicGetId(pThis);
1204	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1205	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1206
1207	uint32_t const uVer = ioapicGetVersion(pThis);
1208	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1209	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1210	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1211	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1212
1213	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1214	{
1215	uint32_t const uArb = ioapicGetArb();
1216	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1217	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1218	}
1219
1220	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1221
1222	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1223	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1224
1225	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1226	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1227	{
1228	static const char * const s_apszDeliveryModes[] =
1229	{
1230	"Fixed ",
1231	"LowPri",
1232	"SMI ",
1233	"Rsvd ",
1234	"NMI ",
1235	"INIT ",
1236	"Rsvd ",
1237	"ExtINT"
1238	};
1239
1240	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1241	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1242	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1243	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1244	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1245	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1246	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1247	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1248	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1249	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1250	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1251	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1252
1253	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1254	idxRte,
1255	pszDestMode,
1256	uDest,
1257	uMask,
1258	(pThis->uIrr >> idxRte) & 1,
1259	pszTriggerMode,
1260	uRemoteIrr,
1261	pszPolarity,
1262	pszDeliveryStatus,
1263	pszDeliveryMode,
1264	uVector,
1265	u64Rte);
1266	}
1267	}
1268
1269
1270	/**
1271	* @copydoc FNSSMDEVSAVEEXEC
1272	*/
1273	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1274	{
1275	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1276	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1277	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1278
1279	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1280	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1281	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1282	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1283	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1284
1285	return VINF_SUCCESS;
1286	}
1287
1288
1289	/**
1290	* @copydoc FNSSMDEVLOADEXEC
1291	*/
1292	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1293	{
1294	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1295	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1296	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1297
1298	Assert(uPass == SSM_PASS_FINAL);
1299	NOREF(uPass);
1300
1301	/* Weed out invalid versions. */
1302	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1303	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1304	{
1305	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1306	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1307	}
1308
1309	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1310	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1311
1312	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1313	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1314	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1315	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1316
1317	return VINF_SUCCESS;
1318	}
1319
1320
1321	/**
1322	* @interface_method_impl{PDMDEVREG,pfnReset}
1323	*/
1324	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1325	{
1326	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1327	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1328	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1329
1330	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1331	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1332
1333	pThis->uIrr = 0;
1334	pThis->u8Index = 0;
1335	pThis->u8Id = 0;
1336
1337	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1338	{
1339	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1340	pThis->au32TagSrc[idxRte] = 0;
1341	}
1342
1343	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1344	}
1345
1346
1347	/**
1348	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1349	*/
1350	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1351	{
1352	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1353	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1354
1355	pThisRC->pIoApicHlp += offDelta;
1356	}
1357
1358
1359	/**
1360	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1361	*/
1362	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1363	{
1364	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1365	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1366	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1367
1368	# ifndef IOAPIC_WITH_PDM_CRITSECT
1369	/*
1370	* Destroy the RTE critical section.
1371	*/
1372	if (PDMCritSectIsInitialized(&pThis->CritSect))
1373	PDMR3CritSectDelete(&pThis->CritSect);
1374	# else
1375	RT_NOREF_PV(pThis);
1376	# endif
1377
1378	return VINF_SUCCESS;
1379	}
1380
1381
1382	/**
1383	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1384	*/
1385	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1386	{
1387	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1388	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1389	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1390	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1391	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1392	Assert(iInstance == 0); RT_NOREF(iInstance);
1393
1394	/*
1395	* Validate and read the configuration.
1396	*/
1397	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1398
1399	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0
1400	upsets some guest which we haven't yet been tested. */
1401	uint32_t cCpus;
1402	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1403	if (RT_FAILURE(rc))
1404	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1405	pThis->cCpus = (uint8_t)cCpus;
1406
1407	char szChipType[16];
1408	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1409	if (RT_FAILURE(rc))
1410	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1411
1412	if (!strcmp(szChipType, "ICH9"))
1413	{
1414	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1415	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1416	pThis->u8IdMask = 0xff;
1417	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1418	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1419	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1420	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1421	}
1422	else if (!strcmp(szChipType, "82093AA"))
1423	{
1424	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1425	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1426	pThis->u8IdMask = 0x0f;
1427	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1428	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1429	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1430	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1431	}
1432	else if (!strcmp(szChipType, "82379AB"))
1433	{
1434	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1435	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1436	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1437	pThis->u8IdMask = 0x0f;
1438	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1439	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1440	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1441	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1442	}
1443	else
1444	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1445	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1446	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1447
1448	/*
1449	* We will use our own critical section for the IOAPIC device.
1450	*/
1451	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1452	AssertRCReturn(rc, rc);
1453
1454	# ifndef IOAPIC_WITH_PDM_CRITSECT
1455	/*
1456	* Setup the critical section to protect concurrent writes to the RTEs.
1457	*/
1458	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1459	AssertRCReturn(rc, rc);
1460	# endif
1461
1462	/*
1463	* Register the IOAPIC.
1464	*/
1465	PDMIOAPICREG IoApicReg;
1466	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1467	IoApicReg.pfnSetIrq = ioapicSetIrq;
1468	IoApicReg.pfnSendMsi = ioapicSendMsi;
1469	IoApicReg.pfnSetEoi = ioapicSetEoi;
1470	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1471	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1472	AssertRCReturn(rc, rc);
1473
1474	/*
1475	* Register MMIO region.
1476	*/
1477	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1478	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1479	AssertRCReturn(rc, rc);
1480
1481	/*
1482	* Register the saved state.
1483	*/
1484	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1485	AssertRCReturn(rc, rc);
1486
1487	/*
1488	* Register debugger info item.
1489	*/
1490	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1491	AssertRCReturn(rc, rc);
1492
1493	/*
1494	* Register debugger register access.
1495	*/
1496	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1497	AssertRCReturn(rc, rc);
1498
1499	# ifdef VBOX_WITH_STATISTICS
1500	/*
1501	* Statistics.
1502	*/
1503	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1504	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1505	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1506	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1507
1508	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1509	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1510	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1511	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1512
1513	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1514	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1515	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1516
1517	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
1518	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
1519	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
1520	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
1521
1522	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1523	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1524
1525	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1526	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1527	# endif
1528	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1529	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1530	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1531
1532	/*
1533	* Init. the device state.
1534	*/
1535	LogRel(("IOAPIC: Using implementation 2.0! I/O APIC version is %d.%d\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0F));
1536	ioapicR3Reset(pDevIns);
1537
1538	return VINF_SUCCESS;
1539	}
1540
1541	#else /* !IN_RING3 */
1542
1543	/**
1544	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1545	*/
1546	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1547	{
1548	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1549	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1550	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1551
1552	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1553	AssertRCReturn(rc, rc);
1554
1555	PDMIOAPICREG IoApicReg;
1556	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1557	IoApicReg.pfnSetIrq = ioapicSetIrq;
1558	IoApicReg.pfnSendMsi = ioapicSendMsi;
1559	IoApicReg.pfnSetEoi = ioapicSetEoi;
1560	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1561	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1562	AssertRCReturn(rc, rc);
1563
1564	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1565	AssertRCReturn(rc, rc);
1566
1567	return VINF_SUCCESS;
1568	}
1569
1570	#endif /* !IN_RING3 */
1571
1572	/**
1573	* IO APIC device registration structure.
1574	*/
1575	const PDMDEVREG g_DeviceIOAPIC =
1576	{
1577	/* .u32Version = */ PDM_DEVREG_VERSION,
1578	/* .uReserved0 = */ 0,
1579	/* .szName = */ "ioapic",
1580	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1581	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1582	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1583	/* .cMaxInstances = */ 1,
1584	/* .uSharedVersion = */ 42,
1585	/* .cbInstanceShared = */ sizeof(IOAPIC),
1586	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1587	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1588	/* .cMaxPciDevices = */ 0,
1589	/* .cMaxMsixVectors = */ 0,
1590	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1591	#if defined(IN_RING3)
1592	/* .pszRCMod = */ "VBoxDDRC.rc",
1593	/* .pszR0Mod = */ "VBoxDDR0.r0",
1594	/* .pfnConstruct = */ ioapicR3Construct,
1595	/* .pfnDestruct = */ ioapicR3Destruct,
1596	/* .pfnRelocate = */ ioapicR3Relocate,
1597	/* .pfnMemSetup = */ NULL,
1598	/* .pfnPowerOn = */ NULL,
1599	/* .pfnReset = */ ioapicR3Reset,
1600	/* .pfnSuspend = */ NULL,
1601	/* .pfnResume = */ NULL,
1602	/* .pfnAttach = */ NULL,
1603	/* .pfnDetach = */ NULL,
1604	/* .pfnQueryInterface = */ NULL,
1605	/* .pfnInitComplete = */ NULL,
1606	/* .pfnPowerOff = */ NULL,
1607	/* .pfnSoftReset = */ NULL,
1608	/* .pfnReserved0 = */ NULL,
1609	/* .pfnReserved1 = */ NULL,
1610	/* .pfnReserved2 = */ NULL,
1611	/* .pfnReserved3 = */ NULL,
1612	/* .pfnReserved4 = */ NULL,
1613	/* .pfnReserved5 = */ NULL,
1614	/* .pfnReserved6 = */ NULL,
1615	/* .pfnReserved7 = */ NULL,
1616	#elif defined(IN_RING0)
1617	/* .pfnEarlyConstruct = */ NULL,
1618	/* .pfnConstruct = */ ioapicRZConstruct,
1619	/* .pfnDestruct = */ NULL,
1620	/* .pfnFinalDestruct = */ NULL,
1621	/* .pfnRequest = */ NULL,
1622	/* .pfnReserved0 = */ NULL,
1623	/* .pfnReserved1 = */ NULL,
1624	/* .pfnReserved2 = */ NULL,
1625	/* .pfnReserved3 = */ NULL,
1626	/* .pfnReserved4 = */ NULL,
1627	/* .pfnReserved5 = */ NULL,
1628	/* .pfnReserved6 = */ NULL,
1629	/* .pfnReserved7 = */ NULL,
1630	#elif defined(IN_RC)
1631	/* .pfnConstruct = */ ioapicRZConstruct,
1632	/* .pfnReserved0 = */ NULL,
1633	/* .pfnReserved1 = */ NULL,
1634	/* .pfnReserved2 = */ NULL,
1635	/* .pfnReserved3 = */ NULL,
1636	/* .pfnReserved4 = */ NULL,
1637	/* .pfnReserved5 = */ NULL,
1638	/* .pfnReserved6 = */ NULL,
1639	/* .pfnReserved7 = */ NULL,
1640	#else
1641	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1642	#endif
1643	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1644	};
1645
1646
1647	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1648

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 88826

Download in other formats: