DevIoApic.cpp@ 89098

Last change on this file since 89098 was 89098, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 ConsoleImpl2, DevIoApic: When Main configures the PCI address of the I/O APIC to the BusAssignmentManager, pass it on to the I/O APIC device as well. This will allow us to use different PCI addresses for AMD and Intel IOMMUs if required.
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1	/* $Id: DevIoApic.cpp 89098 2021-05-17 13:58:09Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - Number of bits to shift to get the Mask. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - The Mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** @name DMAR variant interpretation of RTE fields.
126	* @{ */
127	/** Redirection table entry - Number of bits to shift to get Interrupt
128	* Index[14:0]. */
129	#define IOAPIC_RTE_INTR_INDEX_LO_BIT 49
130	/** Redirection table entry - Interrupt Index[14:0]. */
131	#define IOAPIC_RTE_INTR_INDEX_LO UINT64_C(0xfffe000000000000)
132	/** Redirection table entry - Number of bits to shift to get interrupt format. */
133	#define IOAPIC_RTE_INTR_FORMAT_BIT 48
134	/** Redirection table entry - Interrupt format. */
135	#define IOAPIC_RTE_INTR_FORMAT RT_BIT_64(IOAPIC_RTE_INTR_FORMAT_BIT)
136	/** Redirection table entry - Number of bits to shift to get Interrupt Index[15]. */
137	#define IOAPIC_RTE_INTR_INDEX_HI_BIT 11
138	/** Redirection table entry - Interrupt Index[15]. */
139	#define IOAPIC_RTE_INTR_INDEX_HI RT_BIT_64(11)
140
141	/** Redirection table entry - Gets the Interrupt Index[14:0]. */
142	#define IOAPIC_RTE_GET_INTR_INDEX_LO(a_Reg) ((a_Reg) >> IOAPIC_RTE_INTR_INDEX_LO_BIT)
143	/** Redirection table entry - Gets the Interrupt format. */
144	#define IOAPIC_RTE_GET_INTR_FORMAT(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_FORMAT_BIT) & 0x1)
145	/** Redirection table entry - Gets the Interrupt Index[15]. */
146	#define IOAPIC_RTE_GET_INTR_INDEX_HI(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_INDEX_HI_BIT) & 0x1)
147	/** @} */
148
149	/** Redirection table entry - Valid write mask for 82093AA. */
150	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
151	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
152	\| IOAPIC_RTE_VECTOR)
153	/** Redirection table entry - Valid read mask for 82093AA. */
154	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
155	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
156	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
157
158	/** Redirection table entry - Valid write mask for ICH9. */
159	/** @note The remote IRR bit has been reverted to read-only as it turns out the
160	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
161	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
162	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
163	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
164	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
165	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
166	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
167	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
168	\| IOAPIC_RTE_VECTOR)
169
170	/** Redirection table entry - Valid write mask for DMAR variant. */
171	#define IOAPIC_RTE_VALID_WRITE_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO \| IOAPIC_RTE_INTR_FORMAT \| IOAPIC_RTE_MASK \
172	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_INTR_INDEX_HI \
173	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
174	/** Redirection table entry - Valid read mask for DMAR variant. */
175	#define IOAPIC_RTE_VALID_READ_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO \| IOAPIC_RTE_INTR_FORMAT \| IOAPIC_RTE_MASK \
176	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
177	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_INTR_INDEX_HI \| IOAPIC_RTE_DELIVERY_MODE \
178	\| IOAPIC_RTE_VECTOR)
179
180	/** Redirection table entry - Trigger mode edge. */
181	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
182	/** Redirection table entry - Trigger mode level. */
183	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
184	/** Redirection table entry - Destination mode physical. */
185	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
186	/** Redirection table entry - Destination mode logical. */
187	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
188
189
190	/** Index of indirect registers in the I/O APIC register table. */
191	#define IOAPIC_INDIRECT_INDEX_ID 0x0
192	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
193	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
194	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
195	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
196	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
197
198	/** Offset of direct registers in the I/O APIC MMIO space. */
199	#define IOAPIC_DIRECT_OFF_INDEX 0x00
200	#define IOAPIC_DIRECT_OFF_DATA 0x10
201	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
202
203	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
204	#define IOAPIC_WITH_PDM_CRITSECT
205	#ifdef IOAPIC_WITH_PDM_CRITSECT
206	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
207	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
208	# define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnLockIsOwner((a_pDevIns))
209	#else
210	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
211	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
212	# define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectIsOwner((a_pDevIns), &(a_pThis)->CritSect)
213	#endif
214
215
216	/*********************************************************************************************************************************
217	* Structures and Typedefs *
218	*********************************************************************************************************************************/
219	/**
220	* I/O APIC chipset (and variants) we support.
221	*/
222	typedef enum IOAPICTYPE
223	{
224	IOAPICTYPE_ICH9 = 1,
225	IOAPICTYPE_DMAR,
226	IOAPICTYPE_82093AA,
227	IOAPICTYPE_82379AB,
228	IOAPICTYPE_32BIT_HACK = 0x7fffffff
229	} IOAPICTYPE;
230	AssertCompileSize(IOAPICTYPE, 4);
231
232	/**
233	* The shared I/O APIC device state.
234	*/
235	typedef struct IOAPIC
236	{
237	/** The ID register. */
238	uint8_t volatile u8Id;
239	/** The index register. */
240	uint8_t volatile u8Index;
241	/** Number of CPUs. */
242	uint8_t cCpus;
243	/** I/O APIC version. */
244	uint8_t u8ApicVer;
245	/** I/O APIC ID mask. */
246	uint8_t u8IdMask;
247	/** Maximum Redirection Table Entry (RTE) Entry. */
248	uint8_t u8MaxRte;
249	/** Last valid RTE indirect register index. */
250	uint8_t u8LastRteRegIdx;
251	/* Alignment padding. */
252	uint8_t u8Padding0[1];
253	/** Redirection table entry - Valid write mask. */
254	uint64_t u64RteWriteMask;
255	/** Redirection table entry - Valid read mask. */
256	uint64_t u64RteReadMask;
257
258	/** The redirection table registers. */
259	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
260	/** The IRQ tags and source IDs for each pin (tracing purposes). */
261	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
262
263	/** The internal IRR reflecting state of the interrupt lines. */
264	uint32_t uIrr;
265	/** The I/O APIC chipset type. */
266	IOAPICTYPE enmType;
267	/** The I/O APIC PCI address. */
268	PCIBDF uPciAddress;
269	/** Padding. */
270	uint32_t uPadding0;
271
272	#ifndef IOAPIC_WITH_PDM_CRITSECT
273	/** The critsect for updating to the RTEs. */
274	PDMCRITSECT CritSect;
275	#endif
276
277	/** The MMIO region. */
278	IOMMMIOHANDLE hMmio;
279
280	#ifdef VBOX_WITH_STATISTICS
281	/** Number of MMIO reads in RZ. */
282	STAMCOUNTER StatMmioReadRZ;
283	/** Number of MMIO reads in R3. */
284	STAMCOUNTER StatMmioReadR3;
285
286	/** Number of MMIO writes in RZ. */
287	STAMCOUNTER StatMmioWriteRZ;
288	/** Number of MMIO writes in R3. */
289	STAMCOUNTER StatMmioWriteR3;
290
291	/** Number of SetIrq calls in RZ. */
292	STAMCOUNTER StatSetIrqRZ;
293	/** Number of SetIrq calls in R3. */
294	STAMCOUNTER StatSetIrqR3;
295
296	/** Number of SetEoi calls in RZ. */
297	STAMCOUNTER StatSetEoiRZ;
298	/** Number of SetEoi calls in R3. */
299	STAMCOUNTER StatSetEoiR3;
300
301	/** Number of redundant edge-triggered interrupts. */
302	STAMCOUNTER StatRedundantEdgeIntr;
303	/** Number of redundant level-triggered interrupts. */
304	STAMCOUNTER StatRedundantLevelIntr;
305	/** Number of suppressed level-triggered interrupts (by remote IRR). */
306	STAMCOUNTER StatSuppressedLevelIntr;
307	/** Number of IOMMU remapped interrupts (signaled by RTE). */
308	STAMCOUNTER StatIommuRemappedIntr;
309	/** Number of IOMMU discarded interrupts (signaled by RTE). */
310	STAMCOUNTER StatIommuDiscardedIntr;
311	/** Number of IOMMU remapped MSIs. */
312	STAMCOUNTER StatIommuRemappedMsi;
313	/** Number of IOMMU denied or failed MSIs. */
314	STAMCOUNTER StatIommuDiscardedMsi;
315	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
316	STAMCOUNTER StatEoiContention;
317	/** Number of returns to ring-3 due to Set RTE lock contention. */
318	STAMCOUNTER StatSetRteContention;
319	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
320	STAMCOUNTER StatLevelIrqSent;
321	/** Number of EOIs received for level-triggered interrupts from the local
322	* APIC(s). */
323	STAMCOUNTER StatEoiReceived;
324	#endif
325	/** Per-vector stats. */
326	STAMCOUNTER aStatVectors[256];
327	} IOAPIC;
328	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
329	/** Pointer to shared IOAPIC data. */
330	typedef IOAPIC *PIOAPIC;
331	/** Pointer to const shared IOAPIC data. */
332	typedef IOAPIC const *PCIOAPIC;
333
334
335	/**
336	* The I/O APIC device state for ring-3.
337	*/
338	typedef struct IOAPICR3
339	{
340	/** The IOAPIC helpers. */
341	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
342	} IOAPICR3;
343	/** Pointer to the I/O APIC device state for ring-3. */
344	typedef IOAPICR3 *PIOAPICR3;
345
346
347	/**
348	* The I/O APIC device state for ring-0.
349	*/
350	typedef struct IOAPICR0
351	{
352	/** The IOAPIC helpers. */
353	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
354	} IOAPICR0;
355	/** Pointer to the I/O APIC device state for ring-0. */
356	typedef IOAPICR0 *PIOAPICR0;
357
358
359	/**
360	* The I/O APIC device state for raw-mode.
361	*/
362	typedef struct IOAPICRC
363	{
364	/** The IOAPIC helpers. */
365	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
366	} IOAPICRC;
367	/** Pointer to the I/O APIC device state for raw-mode. */
368	typedef IOAPICRC *PIOAPICRC;
369
370
371	/** The I/O APIC device state for the current context. */
372	typedef CTX_SUFF(IOAPIC) IOAPICCC;
373	/** Pointer to the I/O APIC device state for the current context. */
374	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
375
376
377	/**
378	* xAPIC interrupt.
379	*/
380	typedef struct XAPICINTR
381	{
382	/** The interrupt vector. */
383	uint8_t u8Vector;
384	/** The destination (mask or ID). */
385	uint8_t u8Dest;
386	/** The destination mode. */
387	uint8_t u8DestMode;
388	/** Delivery mode. */
389	uint8_t u8DeliveryMode;
390	/** Trigger mode. */
391	uint8_t u8TriggerMode;
392	/** Redirection hint. */
393	uint8_t u8RedirHint;
394	/** Polarity. */
395	uint8_t u8Polarity;
396	/** Padding. */
397	uint8_t abPadding0;
398	} XAPICINTR;
399	/** Pointer to an I/O xAPIC interrupt struct. */
400	typedef XAPICINTR *PXAPICINTR;
401	/** Pointer to a const xAPIC interrupt struct. */
402	typedef XAPICINTR const *PCXAPICINTR;
403
404
405	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
406
407	/**
408	* Gets the arbitration register.
409	*
410	* @returns The arbitration.
411	*/
412	DECLINLINE(uint32_t) ioapicGetArb(void)
413	{
414	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
415	return 0;
416	}
417
418
419	/**
420	* Gets the version register.
421	*
422	* @returns The version.
423	*/
424	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
425	{
426	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
427	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
428	return uValue;
429	}
430
431
432	/**
433	* Sets the ID register.
434	*
435	* @param pThis The shared I/O APIC device state.
436	* @param uValue The value to set.
437	*/
438	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
439	{
440	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
441	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
442	}
443
444
445	/**
446	* Gets the ID register.
447	*
448	* @returns The ID.
449	* @param pThis The shared I/O APIC device state.
450	*/
451	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
452	{
453	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
454	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
455	return uValue;
456	}
457
458
459	/**
460	* Sets the index register.
461	*
462	* @param pThis The shared I/O APIC device state.
463	* @param uValue The value to set.
464	*/
465	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
466	{
467	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
468	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
469	}
470
471
472	/**
473	* Gets the index register.
474	*
475	* @returns The index value.
476	*/
477	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
478	{
479	uint32_t const uValue = pThis->u8Index;
480	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
481	return uValue;
482	}
483
484
485	/**
486	* Converts an MSI message to an APIC interrupt.
487	*
488	* @param pMsi The MSI message to convert.
489	* @param pIntr Where to store the APIC interrupt.
490	*/
491	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
492	{
493	/*
494	* Parse the message from the physical address and data.
495	* Do -not- zero out other fields in the APIC interrupt.
496	*
497	* See Intel spec. 10.11.1 "Message Address Register Format".
498	* See Intel spec. 10.11.2 "Message Data Register Format".
499	*/
500	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
501	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
502	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
503
504	pIntr->u8Vector = pMsi->Data.n.u8Vector;
505	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
506	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
507	}
508
509
510	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
511	/**
512	* Convert an RTE into an MSI message.
513	*
514	* @param u64Rte The RTE to convert.
515	* @param enmType The I/O APIC chipset type.
516	* @param pMsi Where to store the MSI message.
517	*/
518	DECLINLINE(void) ioapicGetMsiFromRte(uint64_t u64Rte, IOAPICTYPE enmType, PMSIMSG pMsi)
519	{
520	bool const fRemappable = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
521	if (!fRemappable)
522	{
523	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
524	pMsi->Addr.n.u8DestId = IOAPIC_RTE_GET_DEST(u64Rte);
525	pMsi->Addr.n.u1RedirHint = 0;
526	pMsi->Addr.n.u1DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
527
528	pMsi->Data.n.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
529	pMsi->Data.n.u3DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
530	pMsi->Data.n.u1TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
531	/* pMsi->Data.n.u1Level = ??? */
532	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
533	* possible in theory? Maybe document this more explicitly... */
534	}
535	else
536	{
537	Assert(enmType == IOAPICTYPE_DMAR);
538	NOREF(enmType);
539
540	/*
541	* The spec. mentions that SHV will be 0 when delivery mode is 0 (fixed), but
542	* not what SHV will be if delivery mode is not 0. I ASSUME copying delivery
543	* mode into SHV here is what hardware actually does.
544	*
545	* See Intel VT-d spec. 5.1.5.1 "I/OxAPIC Programming".
546	*/
547	pMsi->Addr.dmar_remap.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
548	pMsi->Addr.dmar_remap.u14IntrIndexLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
549	pMsi->Addr.dmar_remap.fIntrFormat = 1;
550	pMsi->Addr.dmar_remap.fShv = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
551	pMsi->Addr.dmar_remap.u1IntrIndexHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
552
553	pMsi->Data.dmar_remap.u16SubHandle = 0;
554	}
555	}
556	#endif
557
558
559	/**
560	* Signals the next pending interrupt for the specified Redirection Table Entry
561	* (RTE).
562	*
563	* @param pDevIns The device instance.
564	* @param pThis The shared I/O APIC device state.
565	* @param pThisCC The I/O APIC device state for the current context.
566	* @param idxRte The index of the RTE (validated).
567	*
568	* @remarks It is the responsibility of the caller to verify that an interrupt is
569	* pending for the pin corresponding to the RTE before calling this
570	* function.
571	*/
572	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
573	{
574	Assert(IOAPIC_LOCK_IS_OWNER(pDevIns, pThis, pThisCC));
575
576	/*
577	* Ensure the interrupt isn't masked.
578	*/
579	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
580	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
581	{ /* likely */ }
582	else
583	return;
584
585	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
586	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
587	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
588	{
589	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
590	if (u8RemoteIrr)
591	{
592	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
593	return;
594	}
595	}
596
597	XAPICINTR ApicIntr;
598	RT_ZERO(ApicIntr);
599	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
600	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
601	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
602	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
603	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
604	ApicIntr.u8TriggerMode = u8TriggerMode;
605	//ApicIntr.u8RedirHint = 0;
606
607	/** @todo We might be able to release the IOAPIC(PDM) lock here and re-acquire it
608	* before setting the remote IRR bit below. The APIC and IOMMU should not
609	* require the caller to hold the PDM lock. */
610
611	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
612	/*
613	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
614	* For line-based interrupts we must use the southbridge I/O APIC's BDF as
615	* the origin of the interrupt, see @bugref{9654#c74}.
616	*/
617	MSIMSG MsiIn;
618	RT_ZERO(MsiIn);
619	ioapicGetMsiFromRte(u64Rte, pThis->enmType, &MsiIn);
620
621	MSIMSG MsiOut;
622	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, pThis->uPciAddress, &MsiIn, &MsiOut);
623	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
624	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
625	{ /* likely - assuming majority of VMs don't have IOMMU configured. */ }
626	else if (RT_SUCCESS(rcRemap))
627	{
628	/* Update the APIC interrupt with the remapped data. */
629	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
630
631	/* Ensure polarity hasn't changed (trigger mode might change with Intel IOMMUs). */
632	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte));
633	STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
634	}
635	else
636	{
637	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
638	return;
639	}
640	#endif
641
642	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
643	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
644	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
645	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
646	ApicIntr.u8Vector, ApicIntr.u8Vector));
647
648	/*
649	* Deliver to the local APIC via the system/3-wire-APIC bus.
650	*/
651	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
652	ApicIntr.u8Dest,
653	ApicIntr.u8DestMode,
654	ApicIntr.u8DeliveryMode,
655	ApicIntr.u8Vector,
656	ApicIntr.u8Polarity,
657	ApicIntr.u8TriggerMode,
658	u32TagSrc);
659	/* Can't reschedule to R3. */
660	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
661	#ifdef DEBUG_ramshankar
662	if (rc == VERR_APIC_INTR_DISCARDED)
663	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
664	#endif
665
666	/*
667	* For level-triggered interrupts, we set the remote IRR bit to indicate
668	* the local APIC has accepted the interrupt.
669	*
670	* For edge-triggered interrupts, we should not clear the IRR bit as it
671	* should remain intact to reflect the state of the interrupt line.
672	* The device will explicitly transition to inactive state via the
673	* ioapicSetIrq() callback.
674	*/
675	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
676	&& rc == VINF_SUCCESS)
677	{
678	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
679	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
680	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
681	}
682	}
683
684
685	/**
686	* Gets the redirection table entry.
687	*
688	* @returns The redirection table entry.
689	* @param pThis The shared I/O APIC device state.
690	* @param uIndex The index value.
691	*/
692	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
693	{
694	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
695	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
696	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
697	UINT32_MAX);
698	uint32_t uValue;
699	if (!(uIndex & 1))
700	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
701	else
702	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
703
704	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
705	return uValue;
706	}
707
708
709	/**
710	* Sets the redirection table entry.
711	*
712	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
713	* @param pDevIns The device instance.
714	* @param pThis The shared I/O APIC device state.
715	* @param pThisCC The I/O APIC device state for the current context.
716	* @param uIndex The index value.
717	* @param uValue The value to set.
718	*/
719	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
720	uint32_t uIndex, uint32_t uValue)
721	{
722	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
723	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
724	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
725	VINF_SUCCESS);
726
727	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
728	if (rc == VINF_SUCCESS)
729	{
730	/*
731	* Write the low or high 32-bit value into the specified 64-bit RTE register,
732	* update only the valid, writable bits.
733	*
734	* We need to preserve the read-only bits as it can have dire consequences
735	* otherwise, see @bugref{8386#c24}.
736	*/
737	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
738	if (!(uIndex & 1))
739	{
740	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
741	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
742	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
743	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
744	}
745	else
746	{
747	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
748	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
749	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
750	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
751	}
752
753	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
754
755	/*
756	* Signal the next pending interrupt for this RTE.
757	*/
758	uint32_t const uPinMask = UINT32_C(1) << idxRte;
759	if (pThis->uIrr & uPinMask)
760	{
761	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
762	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
763	}
764
765	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
766	}
767	else
768	STAM_COUNTER_INC(&pThis->StatSetRteContention);
769
770	return rc;
771	}
772
773
774	/**
775	* Gets the data register.
776	*
777	* @returns The data value.
778	* @param pThis The shared I/O APIC device state.
779	*/
780	static uint32_t ioapicGetData(PCIOAPIC pThis)
781	{
782	uint8_t const uIndex = pThis->u8Index;
783	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
784	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
785	&& uIndex <= pThis->u8LastRteRegIdx)
786	return ioapicGetRedirTableEntry(pThis, uIndex);
787
788	uint32_t uValue;
789	switch (uIndex)
790	{
791	case IOAPIC_INDIRECT_INDEX_ID:
792	uValue = ioapicGetId(pThis);
793	break;
794
795	case IOAPIC_INDIRECT_INDEX_VERSION:
796	uValue = ioapicGetVersion(pThis);
797	break;
798
799	case IOAPIC_INDIRECT_INDEX_ARB:
800	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
801	{
802	uValue = ioapicGetArb();
803	break;
804	}
805	RT_FALL_THRU();
806
807	default:
808	uValue = UINT32_C(0xffffffff);
809	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
810	break;
811	}
812	return uValue;
813	}
814
815
816	/**
817	* Sets the data register.
818	*
819	* @returns Strict VBox status code.
820	* @param pDevIns The device instance.
821	* @param pThis The shared I/O APIC device state.
822	* @param pThisCC The I/O APIC device state for the current context.
823	* @param uValue The value to set.
824	*/
825	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
826	{
827	uint8_t const uIndex = pThis->u8Index;
828	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
829	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
830
831	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
832	&& uIndex <= pThis->u8LastRteRegIdx)
833	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
834
835	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
836	ioapicSetId(pThis, uValue);
837	else
838	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
839
840	return VINF_SUCCESS;
841	}
842
843
844	/**
845	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
846	*/
847	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
848	{
849	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
850	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
851	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
852	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
853
854	bool fRemoteIrrCleared = false;
855	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
856	if (rc == VINF_SUCCESS)
857	{
858	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
859	{
860	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
861	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
862	{
863	#ifdef DEBUG_ramshankar
864	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
865	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
866	#endif
867	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
868	fRemoteIrrCleared = true;
869	STAM_COUNTER_INC(&pThis->StatEoiReceived);
870	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
871
872	/*
873	* Signal the next pending interrupt for this RTE.
874	*/
875	uint32_t const uPinMask = UINT32_C(1) << idxRte;
876	if (pThis->uIrr & uPinMask)
877	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
878	}
879	}
880
881	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
882	#ifndef VBOX_WITH_IOMMU_AMD
883	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
884	#endif
885	}
886	else
887	STAM_COUNTER_INC(&pThis->StatEoiContention);
888
889	return rc;
890	}
891
892
893	/**
894	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
895	*/
896	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
897	{
898	RT_NOREF(uBusDevFn); /** @todo r=ramshankar: Remove this argument if it's also unnecessary with Intel IOMMU. */
899	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
900	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
901	pThis->uIrr \|= a_PinMask; \
902	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
903	} while (0)
904
905	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
906	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
907	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
908
909	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
910
911	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
912	{
913	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
914	AssertRC(rc);
915
916	uint8_t const idxRte = iIrq;
917	uint32_t const uPinMask = UINT32_C(1) << idxRte;
918	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
919	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
920
921	bool fActive = RT_BOOL(iLevel & 1);
922	/** @todo Polarity is busted elsewhere, we need to fix that
923	* first. See @bugref{8386#c7}. */
924	#if 0
925	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
926	fActive ^= u8Polarity; */
927	#endif
928	if (!fActive)
929	{
930	pThis->uIrr &= ~uPinMask;
931	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
932	return;
933	}
934
935	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
936	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
937	if (!fFlipFlop)
938	{
939	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
940	{
941	/*
942	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
943	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
944	*/
945	if (!uPrevIrr)
946	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
947	else
948	{
949	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
950	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
951	}
952	}
953	else
954	{
955	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
956
957	/*
958	* For level-triggered interrupts, redundant interrupts are not a problem
959	* and will eventually be delivered anyway after an EOI, but our PDM devices
960	* should not typically call us with no change to the level.
961	*/
962	if (!uPrevIrr)
963	{ /* likely */ }
964	else
965	{
966	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
967	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
968	}
969
970	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
971	}
972	}
973	else
974	{
975	/*
976	* The device is flip-flopping the interrupt line, which implies we should de-assert
977	* and assert the interrupt line. The interrupt line is left in the asserted state
978	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
979	* hence just the assert is done.
980	*/
981	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
982	}
983
984	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
985	}
986	#undef IOAPIC_ASSERT_IRQ
987	}
988
989
990	/**
991	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
992	*/
993	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
994	{
995	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
996	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
997	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
998
999	XAPICINTR ApicIntr;
1000	RT_ZERO(ApicIntr);
1001
1002	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
1003	/*
1004	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
1005	*
1006	* If the Bus:Dev:Fn isn't valid, it is ASSUMED the device generating the
1007	* MSI is the IOMMU itself and hence isn't subjected to remapping. This
1008	* is the case with Intel IOMMUs.
1009	*
1010	* AMD IOMMUs are full fledged PCI devices, hence the BDF will be a
1011	* valid PCI slot, but interrupts generated by the IOMMU will be handled
1012	* by VERR_IOMMU_CANNOT_CALL_SELF case.
1013	*/
1014	if (PCIBDF_IS_VALID(uBusDevFn))
1015	{
1016	MSIMSG MsiOut;
1017	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
1018	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
1019	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
1020	{ /* likely - assuming majority of VMs don't have IOMMU configured. */ }
1021	else if (RT_SUCCESS(rcRemap))
1022	{
1023	STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
1024	pMsi = &MsiOut;
1025	}
1026	else
1027	{
1028	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
1029	return;
1030	}
1031	}
1032	#else
1033	NOREF(uBusDevFn);
1034	#endif
1035
1036	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
1037
1038	/*
1039	* Deliver to the local APIC via the system/3-wire-APIC bus.
1040	*/
1041	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
1042
1043	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
1044	ApicIntr.u8Dest,
1045	ApicIntr.u8DestMode,
1046	ApicIntr.u8DeliveryMode,
1047	ApicIntr.u8Vector,
1048	0 /* u8Polarity - N/A */,
1049	ApicIntr.u8TriggerMode,
1050	uTagSrc);
1051	/* Can't reschedule to R3. */
1052	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
1053	}
1054
1055
1056	/**
1057	* @callback_method_impl{FNIOMMMIONEWREAD}
1058	*/
1059	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1060	{
1061	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1062	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1063	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1064	RT_NOREF_PV(pvUser);
1065
1066	VBOXSTRICTRC rc = VINF_SUCCESS;
1067	uint32_t puValue = (uint32_t )pv;
1068	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
1069	switch (offReg)
1070	{
1071	case IOAPIC_DIRECT_OFF_INDEX:
1072	*puValue = ioapicGetIndex(pThis);
1073	break;
1074
1075	case IOAPIC_DIRECT_OFF_DATA:
1076	*puValue = ioapicGetData(pThis);
1077	break;
1078
1079	default:
1080	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1081	rc = VINF_IOM_MMIO_UNUSED_FF;
1082	break;
1083	}
1084
1085	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
1086	return rc;
1087	}
1088
1089
1090	/**
1091	* @callback_method_impl{FNIOMMMIONEWWRITE}
1092	*/
1093	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1094	{
1095	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1096	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1097	RT_NOREF_PV(pvUser);
1098
1099	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1100
1101	Assert(!(off & 3));
1102	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1103
1104	VBOXSTRICTRC rc = VINF_SUCCESS;
1105	uint32_t const uValue = (uint32_t const )pv;
1106	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1107
1108	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1109	switch (offReg)
1110	{
1111	case IOAPIC_DIRECT_OFF_INDEX:
1112	ioapicSetIndex(pThis, uValue);
1113	break;
1114
1115	case IOAPIC_DIRECT_OFF_DATA:
1116	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1117	break;
1118
1119	case IOAPIC_DIRECT_OFF_EOI:
1120	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1121	rc = ioapicSetEoi(pDevIns, uValue);
1122	else
1123	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1124	break;
1125
1126	default:
1127	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1128	break;
1129	}
1130
1131	return rc;
1132	}
1133
1134
1135	#ifdef IN_RING3
1136
1137	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1138	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1139	{
1140	RT_NOREF(pDesc);
1141	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1142	return VINF_SUCCESS;
1143	}
1144
1145
1146	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1147	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1148	{
1149	RT_NOREF(pDesc, pfMask);
1150	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1151	return VINF_SUCCESS;
1152	}
1153
1154
1155	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1156	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1157	{
1158	RT_NOREF(pDesc);
1159	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1160	return VINF_SUCCESS;
1161	}
1162
1163
1164	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1165	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1166	{
1167	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1168	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1169	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1170	RT_NOREF(pDesc, pfMask);
1171	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1172	}
1173
1174
1175	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1176	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1177	{
1178	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1179	RT_NOREF(pDesc);
1180	pValue->u32 = ioapicGetVersion(pThis);
1181	return VINF_SUCCESS;
1182	}
1183
1184
1185	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1186	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1187	{
1188	RT_NOREF(pvUser, pDesc);
1189	pValue->u32 = ioapicGetArb();
1190	return VINF_SUCCESS;
1191	}
1192
1193
1194	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1195	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1196	{
1197	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1198	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1199	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1200	return VINF_SUCCESS;
1201	}
1202
1203
1204	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1205	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1206	{
1207	RT_NOREF(pfMask);
1208	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1209	/* No locks, no checks, just do it. */
1210	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1211	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1212	return VINF_SUCCESS;
1213	}
1214
1215
1216	/** IOREDTBLn sub fields. */
1217	static DBGFREGSUBFIELD const g_aRteSubs[] =
1218	{
1219	{ "vector", 0, 8, 0, 0, NULL, NULL },
1220	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1221	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1222	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1223	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1224	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1225	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1226	{ "mask", 16, 1, 0, 0, NULL, NULL },
1227	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1228	{ "dest", 56, 8, 0, 0, NULL, NULL },
1229	DBGFREGSUBFIELD_TERMINATOR()
1230	};
1231
1232
1233	/** Register descriptors for DBGF. */
1234	static DBGFREGDESC const g_aRegDesc[] =
1235	{
1236	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1237	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1238	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1239	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1240	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1241	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1242	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1243	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1244	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1245	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1246	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1247	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1248	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1249	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1250	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1251	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1252	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1253	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1254	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1255	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1256	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1257	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1258	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1259	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1260	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1261	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1262	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1263	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1264	DBGFREGDESC_TERMINATOR()
1265	};
1266
1267
1268	/**
1269	* @callback_method_impl{FNDBGFHANDLERDEV}
1270	*/
1271	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1272	{
1273	RT_NOREF(pszArgs);
1274	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1275	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1276
1277	bool const fLegacy = RTStrCmp(pszArgs, "legacy") == 0;
1278
1279	static const char * const s_apszDeliveryModes[] =
1280	{
1281	" fixed",
1282	"lowpri",
1283	" smi",
1284	" rsvd",
1285	" nmi",
1286	" init",
1287	" rsvd",
1288	"extint"
1289	};
1290	static const char * const s_apszDestMode[] = { "phys", "log " };
1291	static const char * const s_apszTrigMode[] = { " edge", "level" };
1292	static const char * const s_apszPolarity[] = { "acthi", "actlo" };
1293	static const char * const s_apszDeliveryStatus[] = { "idle", "pend" };
1294
1295	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1296
1297	uint32_t const uId = ioapicGetId(pThis);
1298	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1299	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1300
1301	uint32_t const uVer = ioapicGetVersion(pThis);
1302	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1303	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1304	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1305	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1306
1307	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1308	{
1309	uint32_t const uArb = ioapicGetArb();
1310	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1311	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1312	}
1313
1314	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1315
1316	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1317	if ( pThis->enmType != IOAPICTYPE_DMAR
1318	\|\| fLegacy)
1319	{
1320	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
1321	pHlp->pfnPrintf(pHlp, " ---------------------------------------------------------------------------------------------\n");
1322
1323	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1324	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1325	{
1326	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1327	const char *pszDestMode = s_apszDestMode[IOAPIC_RTE_GET_DEST_MODE(u64Rte)];
1328	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1329	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1330	const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
1331	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1332	const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
1333	const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
1334	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1335	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1336	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1337	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1338
1339	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1340	idxRte,
1341	pszDestMode,
1342	uDest,
1343	uMask,
1344	(pThis->uIrr >> idxRte) & 1,
1345	pszTriggerMode,
1346	uRemoteIrr,
1347	pszPolarity,
1348	pszDeliveryStatus,
1349	pszDeliveryMode,
1350	uVector,
1351	u64Rte);
1352	}
1353	}
1354	else
1355	{
1356	pHlp->pfnPrintf(pHlp, " idx intr_idx fmt mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
1357	pHlp->pfnPrintf(pHlp, " ----------------------------------------------------------------------------------------\n");
1358
1359	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1360	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1361	{
1362	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1363	const uint16_t idxIntrLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
1364	const uint8_t fIntrFormat = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
1365	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1366	const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
1367	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1368	const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
1369	const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
1370	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1371	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1372	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1373	const uint16_t idxIntrHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
1374	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1375	const uint16_t idxIntr = idxIntrLo \| (idxIntrHi << 15);
1376	pHlp->pfnPrintf(pHlp, " %02d %4u %u %u %u %s %u %s %s %s %3u (%016llx)\n",
1377	idxRte,
1378	idxIntr,
1379	fIntrFormat,
1380	uMask,
1381	(pThis->uIrr >> idxRte) & 1,
1382	pszTriggerMode,
1383	uRemoteIrr,
1384	pszPolarity,
1385	pszDeliveryStatus,
1386	pszDeliveryMode,
1387	uVector,
1388	u64Rte);
1389	}
1390	}
1391	}
1392
1393
1394	/**
1395	* @copydoc FNSSMDEVSAVEEXEC
1396	*/
1397	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1398	{
1399	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1400	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1401	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1402
1403	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1404	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1405	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1406	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1407	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1408
1409	return VINF_SUCCESS;
1410	}
1411
1412
1413	/**
1414	* @copydoc FNSSMDEVLOADEXEC
1415	*/
1416	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1417	{
1418	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1419	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1420	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1421
1422	Assert(uPass == SSM_PASS_FINAL);
1423	NOREF(uPass);
1424
1425	/* Weed out invalid versions. */
1426	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1427	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1428	{
1429	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1430	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1431	}
1432
1433	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1434	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1435
1436	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1437	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1438	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1439	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1440
1441	return VINF_SUCCESS;
1442	}
1443
1444
1445	/**
1446	* @interface_method_impl{PDMDEVREG,pfnReset}
1447	*/
1448	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1449	{
1450	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1451	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1452	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1453
1454	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1455	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1456
1457	pThis->uIrr = 0;
1458	pThis->u8Index = 0;
1459	pThis->u8Id = 0;
1460
1461	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1462	{
1463	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1464	pThis->au32TagSrc[idxRte] = 0;
1465	}
1466
1467	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1468	}
1469
1470
1471	/**
1472	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1473	*/
1474	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1475	{
1476	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1477	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1478
1479	pThisRC->pIoApicHlp += offDelta;
1480	}
1481
1482
1483	/**
1484	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1485	*/
1486	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1487	{
1488	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1489	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1490	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1491
1492	# ifndef IOAPIC_WITH_PDM_CRITSECT
1493	/*
1494	* Destroy the RTE critical section.
1495	*/
1496	if (PDMCritSectIsInitialized(&pThis->CritSect))
1497	PDMR3CritSectDelete(&pThis->CritSect);
1498	# else
1499	RT_NOREF_PV(pThis);
1500	# endif
1501
1502	return VINF_SUCCESS;
1503	}
1504
1505
1506	/**
1507	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1508	*/
1509	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1510	{
1511	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1512	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1513	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1514	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1515	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1516	Assert(iInstance == 0); RT_NOREF(iInstance);
1517
1518	/*
1519	* Validate and read the configuration.
1520	*/
1521	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType\|PCIAddress", "");
1522
1523	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0
1524	upsets some guest which we haven't yet been tested. */
1525	uint32_t cCpus;
1526	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1527	if (RT_FAILURE(rc))
1528	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1529	pThis->cCpus = (uint8_t)cCpus;
1530
1531	char szChipType[16];
1532	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1533	if (RT_FAILURE(rc))
1534	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1535
1536	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
1537	if (RT_FAILURE(rc))
1538	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
1539
1540	if (!strcmp(szChipType, "ICH9"))
1541	{
1542	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1543	pThis->enmType = IOAPICTYPE_ICH9;
1544	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1545	pThis->u8IdMask = 0xff;
1546	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1547	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1548	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1549	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1550	}
1551	else if (!strcmp(szChipType, "DMAR"))
1552	{
1553	/* Intel DMAR compatible I/O APIC integrated into ICH southbridges. */
1554	/* Identical to ICH9, but interprets RTEs and MSI address and data fields differently. */
1555	pThis->enmType = IOAPICTYPE_DMAR;
1556	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1557	pThis->u8IdMask = 0xff;
1558	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1559	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1560	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_DMAR;
1561	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_DMAR;
1562	}
1563	else if (!strcmp(szChipType, "82093AA"))
1564	{
1565	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1566	pThis->enmType = IOAPICTYPE_82093AA;
1567	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1568	pThis->u8IdMask = 0x0f;
1569	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1570	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1571	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1572	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1573	}
1574	else if (!strcmp(szChipType, "82379AB"))
1575	{
1576	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1577	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1578	pThis->enmType = IOAPICTYPE_82379AB;
1579	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1580	pThis->u8IdMask = 0x0f;
1581	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1582	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1583	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1584	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1585	}
1586	else
1587	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1588	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1589	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1590
1591	/*
1592	* We will use our own critical section for the IOAPIC device.
1593	*/
1594	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1595	AssertRCReturn(rc, rc);
1596
1597	# ifndef IOAPIC_WITH_PDM_CRITSECT
1598	/*
1599	* Setup the critical section to protect concurrent writes to the RTEs.
1600	*/
1601	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1602	AssertRCReturn(rc, rc);
1603	# endif
1604
1605	/*
1606	* Register the IOAPIC.
1607	*/
1608	PDMIOAPICREG IoApicReg;
1609	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1610	IoApicReg.pfnSetIrq = ioapicSetIrq;
1611	IoApicReg.pfnSendMsi = ioapicSendMsi;
1612	IoApicReg.pfnSetEoi = ioapicSetEoi;
1613	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1614	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1615	AssertRCReturn(rc, rc);
1616	AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
1617	AssertPtr(pThisCC->pIoApicHlp->pfnLock);
1618	AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
1619	AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
1620	AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
1621
1622	/*
1623	* Register MMIO region.
1624	*/
1625	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1626	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1627	AssertRCReturn(rc, rc);
1628
1629	/*
1630	* Register the saved state.
1631	*/
1632	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1633	AssertRCReturn(rc, rc);
1634
1635	/*
1636	* Register debugger info item.
1637	*/
1638	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1639	AssertRCReturn(rc, rc);
1640
1641	/*
1642	* Register debugger register access.
1643	*/
1644	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1645	AssertRCReturn(rc, rc);
1646
1647	# ifdef VBOX_WITH_STATISTICS
1648	/*
1649	* Statistics.
1650	*/
1651	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1652	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1653	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1654	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1655
1656	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1657	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1658	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1659	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1660
1661	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1662	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1663	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1664
1665	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
1666	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
1667	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
1668	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
1669
1670	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1671	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1672
1673	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1674	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1675	# endif
1676	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1677	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1678	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1679
1680	/*
1681	* Init. the device state.
1682	*/
1683	LogRel(("IOAPIC: Version=%d.%d ChipType=%s\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0f, szChipType));
1684	ioapicR3Reset(pDevIns);
1685
1686	return VINF_SUCCESS;
1687	}
1688
1689	#else /* !IN_RING3 */
1690
1691	/**
1692	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1693	*/
1694	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1695	{
1696	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1697	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1698	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1699
1700	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1701	AssertRCReturn(rc, rc);
1702
1703	PDMIOAPICREG IoApicReg;
1704	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1705	IoApicReg.pfnSetIrq = ioapicSetIrq;
1706	IoApicReg.pfnSendMsi = ioapicSendMsi;
1707	IoApicReg.pfnSetEoi = ioapicSetEoi;
1708	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1709	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1710	AssertRCReturn(rc, rc);
1711	AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
1712	AssertPtr(pThisCC->pIoApicHlp->pfnLock);
1713	AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
1714	AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
1715	AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
1716
1717	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1718	AssertRCReturn(rc, rc);
1719
1720	return VINF_SUCCESS;
1721	}
1722
1723	#endif /* !IN_RING3 */
1724
1725	/**
1726	* IO APIC device registration structure.
1727	*/
1728	const PDMDEVREG g_DeviceIOAPIC =
1729	{
1730	/* .u32Version = */ PDM_DEVREG_VERSION,
1731	/* .uReserved0 = */ 0,
1732	/* .szName = */ "ioapic",
1733	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1734	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1735	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1736	/* .cMaxInstances = */ 1,
1737	/* .uSharedVersion = */ 42,
1738	/* .cbInstanceShared = */ sizeof(IOAPIC),
1739	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1740	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1741	/* .cMaxPciDevices = */ 0,
1742	/* .cMaxMsixVectors = */ 0,
1743	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1744	#if defined(IN_RING3)
1745	/* .pszRCMod = */ "VBoxDDRC.rc",
1746	/* .pszR0Mod = */ "VBoxDDR0.r0",
1747	/* .pfnConstruct = */ ioapicR3Construct,
1748	/* .pfnDestruct = */ ioapicR3Destruct,
1749	/* .pfnRelocate = */ ioapicR3Relocate,
1750	/* .pfnMemSetup = */ NULL,
1751	/* .pfnPowerOn = */ NULL,
1752	/* .pfnReset = */ ioapicR3Reset,
1753	/* .pfnSuspend = */ NULL,
1754	/* .pfnResume = */ NULL,
1755	/* .pfnAttach = */ NULL,
1756	/* .pfnDetach = */ NULL,
1757	/* .pfnQueryInterface = */ NULL,
1758	/* .pfnInitComplete = */ NULL,
1759	/* .pfnPowerOff = */ NULL,
1760	/* .pfnSoftReset = */ NULL,
1761	/* .pfnReserved0 = */ NULL,
1762	/* .pfnReserved1 = */ NULL,
1763	/* .pfnReserved2 = */ NULL,
1764	/* .pfnReserved3 = */ NULL,
1765	/* .pfnReserved4 = */ NULL,
1766	/* .pfnReserved5 = */ NULL,
1767	/* .pfnReserved6 = */ NULL,
1768	/* .pfnReserved7 = */ NULL,
1769	#elif defined(IN_RING0)
1770	/* .pfnEarlyConstruct = */ NULL,
1771	/* .pfnConstruct = */ ioapicRZConstruct,
1772	/* .pfnDestruct = */ NULL,
1773	/* .pfnFinalDestruct = */ NULL,
1774	/* .pfnRequest = */ NULL,
1775	/* .pfnReserved0 = */ NULL,
1776	/* .pfnReserved1 = */ NULL,
1777	/* .pfnReserved2 = */ NULL,
1778	/* .pfnReserved3 = */ NULL,
1779	/* .pfnReserved4 = */ NULL,
1780	/* .pfnReserved5 = */ NULL,
1781	/* .pfnReserved6 = */ NULL,
1782	/* .pfnReserved7 = */ NULL,
1783	#elif defined(IN_RC)
1784	/* .pfnConstruct = */ ioapicRZConstruct,
1785	/* .pfnReserved0 = */ NULL,
1786	/* .pfnReserved1 = */ NULL,
1787	/* .pfnReserved2 = */ NULL,
1788	/* .pfnReserved3 = */ NULL,
1789	/* .pfnReserved4 = */ NULL,
1790	/* .pfnReserved5 = */ NULL,
1791	/* .pfnReserved6 = */ NULL,
1792	/* .pfnReserved7 = */ NULL,
1793	#else
1794	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1795	#endif
1796	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1797	};
1798
1799
1800	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1801

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 89098

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