DevIoApic.cpp@ 89620

Last change on this file since 89620 was 89620, checked in by vboxsync, 3 years ago
Intel IOMMU: bugref:9967 Allow PDMIoApicSetEoi operation to be queued to ring-3 if I/O APIC isn't available in R0. This key change is taking the PDM lock such that it doesn't fail (VINF_SUCCESS instead of VINF_IOM_R3_MMIO_WRITE for rcBusy, which wouldn't have worked anyway when called via APICHvSetEoi for instance). Also cleaned up the prototype of PDMIoApicSendMsi a bit (use PVMCC instead of PPDMDEVINS).
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File size: 74.4 KB

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1	/* $Id: DevIoApic.cpp 89620 2021-06-11 08:51:10Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - Number of bits to shift to get the Mask. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - The Mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** @name DMAR variant interpretation of RTE fields.
126	* @{ */
127	/** Redirection table entry - Number of bits to shift to get Interrupt
128	* Index[14:0]. */
129	#define IOAPIC_RTE_INTR_INDEX_LO_BIT 49
130	/** Redirection table entry - Interrupt Index[14:0]. */
131	#define IOAPIC_RTE_INTR_INDEX_LO UINT64_C(0xfffe000000000000)
132	/** Redirection table entry - Number of bits to shift to get interrupt format. */
133	#define IOAPIC_RTE_INTR_FORMAT_BIT 48
134	/** Redirection table entry - Interrupt format. */
135	#define IOAPIC_RTE_INTR_FORMAT RT_BIT_64(IOAPIC_RTE_INTR_FORMAT_BIT)
136	/** Redirection table entry - Number of bits to shift to get Interrupt Index[15]. */
137	#define IOAPIC_RTE_INTR_INDEX_HI_BIT 11
138	/** Redirection table entry - Interrupt Index[15]. */
139	#define IOAPIC_RTE_INTR_INDEX_HI RT_BIT_64(11)
140
141	/** Redirection table entry - Gets the Interrupt Index[14:0]. */
142	#define IOAPIC_RTE_GET_INTR_INDEX_LO(a_Reg) ((a_Reg) >> IOAPIC_RTE_INTR_INDEX_LO_BIT)
143	/** Redirection table entry - Gets the Interrupt format. */
144	#define IOAPIC_RTE_GET_INTR_FORMAT(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_FORMAT_BIT) & 0x1)
145	/** Redirection table entry - Gets the Interrupt Index[15]. */
146	#define IOAPIC_RTE_GET_INTR_INDEX_HI(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_INDEX_HI_BIT) & 0x1)
147	/** @} */
148
149	/** Redirection table entry - Valid write mask for 82093AA. */
150	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
151	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
152	\| IOAPIC_RTE_VECTOR)
153	/** Redirection table entry - Valid read mask for 82093AA. */
154	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
155	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
156	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
157
158	/** Redirection table entry - Valid write mask for ICH9. */
159	/** @note The remote IRR bit has been reverted to read-only as it turns out the
160	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
161	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
162	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
163	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
164	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
165	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
166	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
167	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
168	\| IOAPIC_RTE_VECTOR)
169
170	/** Redirection table entry - Valid write mask for DMAR variant. */
171	#define IOAPIC_RTE_VALID_WRITE_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO \| IOAPIC_RTE_INTR_FORMAT \| IOAPIC_RTE_MASK \
172	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_INTR_INDEX_HI \
173	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
174	/** Redirection table entry - Valid read mask for DMAR variant. */
175	#define IOAPIC_RTE_VALID_READ_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO \| IOAPIC_RTE_INTR_FORMAT \| IOAPIC_RTE_MASK \
176	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
177	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_INTR_INDEX_HI \| IOAPIC_RTE_DELIVERY_MODE \
178	\| IOAPIC_RTE_VECTOR)
179
180	/** Redirection table entry - Trigger mode edge. */
181	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
182	/** Redirection table entry - Trigger mode level. */
183	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
184	/** Redirection table entry - Destination mode physical. */
185	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
186	/** Redirection table entry - Destination mode logical. */
187	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
188
189
190	/** Index of indirect registers in the I/O APIC register table. */
191	#define IOAPIC_INDIRECT_INDEX_ID 0x0
192	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
193	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
194	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
195	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
196	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
197
198	/** Offset of direct registers in the I/O APIC MMIO space. */
199	#define IOAPIC_DIRECT_OFF_INDEX 0x00
200	#define IOAPIC_DIRECT_OFF_DATA 0x10
201	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
202
203	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
204	#define IOAPIC_WITH_PDM_CRITSECT
205	#ifdef IOAPIC_WITH_PDM_CRITSECT
206	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
207	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
208	# define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnLockIsOwner((a_pDevIns))
209	#else
210	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
211	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
212	# define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectIsOwner((a_pDevIns), &(a_pThis)->CritSect)
213	#endif
214
215
216	/*********************************************************************************************************************************
217	* Structures and Typedefs *
218	*********************************************************************************************************************************/
219	/**
220	* I/O APIC chipset (and variants) we support.
221	*/
222	typedef enum IOAPICTYPE
223	{
224	IOAPICTYPE_ICH9 = 1,
225	IOAPICTYPE_DMAR,
226	IOAPICTYPE_82093AA,
227	IOAPICTYPE_82379AB,
228	IOAPICTYPE_32BIT_HACK = 0x7fffffff
229	} IOAPICTYPE;
230	AssertCompileSize(IOAPICTYPE, 4);
231
232	/**
233	* The shared I/O APIC device state.
234	*/
235	typedef struct IOAPIC
236	{
237	/** The ID register. */
238	uint8_t volatile u8Id;
239	/** The index register. */
240	uint8_t volatile u8Index;
241	/** Number of CPUs. */
242	uint8_t cCpus;
243	/** I/O APIC version. */
244	uint8_t u8ApicVer;
245	/** I/O APIC ID mask. */
246	uint8_t u8IdMask;
247	/** Maximum Redirection Table Entry (RTE) Entry. */
248	uint8_t u8MaxRte;
249	/** Last valid RTE indirect register index. */
250	uint8_t u8LastRteRegIdx;
251	/* Alignment padding. */
252	uint8_t u8Padding0[1];
253	/** Redirection table entry - Valid write mask. */
254	uint64_t u64RteWriteMask;
255	/** Redirection table entry - Valid read mask. */
256	uint64_t u64RteReadMask;
257
258	/** The redirection table registers. */
259	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
260	/** The IRQ tags and source IDs for each pin (tracing purposes). */
261	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
262
263	/** The internal IRR reflecting state of the interrupt lines. */
264	uint32_t uIrr;
265	/** The I/O APIC chipset type. */
266	IOAPICTYPE enmType;
267	/** The I/O APIC PCI address. */
268	PCIBDF uPciAddress;
269	/** Padding. */
270	uint32_t uPadding0;
271
272	#ifndef IOAPIC_WITH_PDM_CRITSECT
273	/** The critsect for updating to the RTEs. */
274	PDMCRITSECT CritSect;
275	#endif
276
277	/** The MMIO region. */
278	IOMMMIOHANDLE hMmio;
279
280	#ifdef VBOX_WITH_STATISTICS
281	/** Number of MMIO reads in RZ. */
282	STAMCOUNTER StatMmioReadRZ;
283	/** Number of MMIO reads in R3. */
284	STAMCOUNTER StatMmioReadR3;
285
286	/** Number of MMIO writes in RZ. */
287	STAMCOUNTER StatMmioWriteRZ;
288	/** Number of MMIO writes in R3. */
289	STAMCOUNTER StatMmioWriteR3;
290
291	/** Number of SetIrq calls in RZ. */
292	STAMCOUNTER StatSetIrqRZ;
293	/** Number of SetIrq calls in R3. */
294	STAMCOUNTER StatSetIrqR3;
295
296	/** Number of SetEoi calls in RZ. */
297	STAMCOUNTER StatSetEoiRZ;
298	/** Number of SetEoi calls in R3. */
299	STAMCOUNTER StatSetEoiR3;
300
301	/** Number of redundant edge-triggered interrupts. */
302	STAMCOUNTER StatRedundantEdgeIntr;
303	/** Number of redundant level-triggered interrupts. */
304	STAMCOUNTER StatRedundantLevelIntr;
305	/** Number of suppressed level-triggered interrupts (by remote IRR). */
306	STAMCOUNTER StatSuppressedLevelIntr;
307	/** Number of IOMMU remapped interrupts (signaled by RTE). */
308	STAMCOUNTER StatIommuRemappedIntr;
309	/** Number of IOMMU discarded interrupts (signaled by RTE). */
310	STAMCOUNTER StatIommuDiscardedIntr;
311	/** Number of IOMMU remapped MSIs. */
312	STAMCOUNTER StatIommuRemappedMsi;
313	/** Number of IOMMU denied or failed MSIs. */
314	STAMCOUNTER StatIommuDiscardedMsi;
315	/** Number of returns to ring-3 due to Set RTE lock contention. */
316	STAMCOUNTER StatSetRteContention;
317	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
318	STAMCOUNTER StatLevelIrqSent;
319	/** Number of EOIs received for level-triggered interrupts from the local
320	* APIC(s). */
321	STAMCOUNTER StatEoiReceived;
322	#endif
323	/** Per-vector stats. */
324	STAMCOUNTER aStatVectors[256];
325	} IOAPIC;
326	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
327	/** Pointer to shared IOAPIC data. */
328	typedef IOAPIC *PIOAPIC;
329	/** Pointer to const shared IOAPIC data. */
330	typedef IOAPIC const *PCIOAPIC;
331
332
333	/**
334	* The I/O APIC device state for ring-3.
335	*/
336	typedef struct IOAPICR3
337	{
338	/** The IOAPIC helpers. */
339	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
340	} IOAPICR3;
341	/** Pointer to the I/O APIC device state for ring-3. */
342	typedef IOAPICR3 *PIOAPICR3;
343
344
345	/**
346	* The I/O APIC device state for ring-0.
347	*/
348	typedef struct IOAPICR0
349	{
350	/** The IOAPIC helpers. */
351	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
352	} IOAPICR0;
353	/** Pointer to the I/O APIC device state for ring-0. */
354	typedef IOAPICR0 *PIOAPICR0;
355
356
357	/**
358	* The I/O APIC device state for raw-mode.
359	*/
360	typedef struct IOAPICRC
361	{
362	/** The IOAPIC helpers. */
363	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
364	} IOAPICRC;
365	/** Pointer to the I/O APIC device state for raw-mode. */
366	typedef IOAPICRC *PIOAPICRC;
367
368
369	/** The I/O APIC device state for the current context. */
370	typedef CTX_SUFF(IOAPIC) IOAPICCC;
371	/** Pointer to the I/O APIC device state for the current context. */
372	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
373
374
375	/**
376	* xAPIC interrupt.
377	*/
378	typedef struct XAPICINTR
379	{
380	/** The interrupt vector. */
381	uint8_t u8Vector;
382	/** The destination (mask or ID). */
383	uint8_t u8Dest;
384	/** The destination mode. */
385	uint8_t u8DestMode;
386	/** Delivery mode. */
387	uint8_t u8DeliveryMode;
388	/** Trigger mode. */
389	uint8_t u8TriggerMode;
390	/** Redirection hint. */
391	uint8_t u8RedirHint;
392	/** Polarity. */
393	uint8_t u8Polarity;
394	/** Padding. */
395	uint8_t abPadding0;
396	} XAPICINTR;
397	/** Pointer to an I/O xAPIC interrupt struct. */
398	typedef XAPICINTR *PXAPICINTR;
399	/** Pointer to a const xAPIC interrupt struct. */
400	typedef XAPICINTR const *PCXAPICINTR;
401
402
403	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
404
405	/**
406	* Gets the arbitration register.
407	*
408	* @returns The arbitration.
409	*/
410	DECLINLINE(uint32_t) ioapicGetArb(void)
411	{
412	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
413	return 0;
414	}
415
416
417	/**
418	* Gets the version register.
419	*
420	* @returns The version.
421	*/
422	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
423	{
424	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
425	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
426	return uValue;
427	}
428
429
430	/**
431	* Sets the ID register.
432	*
433	* @param pThis The shared I/O APIC device state.
434	* @param uValue The value to set.
435	*/
436	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
437	{
438	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
439	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
440	}
441
442
443	/**
444	* Gets the ID register.
445	*
446	* @returns The ID.
447	* @param pThis The shared I/O APIC device state.
448	*/
449	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
450	{
451	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
452	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
453	return uValue;
454	}
455
456
457	/**
458	* Sets the index register.
459	*
460	* @param pThis The shared I/O APIC device state.
461	* @param uValue The value to set.
462	*/
463	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
464	{
465	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
466	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
467	}
468
469
470	/**
471	* Gets the index register.
472	*
473	* @returns The index value.
474	*/
475	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
476	{
477	uint32_t const uValue = pThis->u8Index;
478	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
479	return uValue;
480	}
481
482
483	/**
484	* Converts an MSI message to an APIC interrupt.
485	*
486	* @param pMsi The MSI message to convert.
487	* @param pIntr Where to store the APIC interrupt.
488	*/
489	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
490	{
491	/*
492	* Parse the message from the physical address and data.
493	* Do -not- zero out other fields in the APIC interrupt.
494	*
495	* See Intel spec. 10.11.1 "Message Address Register Format".
496	* See Intel spec. 10.11.2 "Message Data Register Format".
497	*/
498	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
499	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
500	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
501
502	pIntr->u8Vector = pMsi->Data.n.u8Vector;
503	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
504	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
505	}
506
507
508	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
509	/**
510	* Convert an RTE into an MSI message.
511	*
512	* @param u64Rte The RTE to convert.
513	* @param enmType The I/O APIC chipset type.
514	* @param pMsi Where to store the MSI message.
515	*/
516	DECLINLINE(void) ioapicGetMsiFromRte(uint64_t u64Rte, IOAPICTYPE enmType, PMSIMSG pMsi)
517	{
518	bool const fRemappable = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
519	if (!fRemappable)
520	{
521	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
522	pMsi->Addr.n.u8DestId = IOAPIC_RTE_GET_DEST(u64Rte);
523	pMsi->Addr.n.u1RedirHint = 0;
524	pMsi->Addr.n.u1DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
525
526	pMsi->Data.n.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
527	pMsi->Data.n.u3DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
528	pMsi->Data.n.u1TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
529	/* pMsi->Data.n.u1Level = ??? */
530	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
531	* possible in theory? Maybe document this more explicitly... */
532	}
533	else
534	{
535	Assert(enmType == IOAPICTYPE_DMAR);
536	NOREF(enmType);
537
538	/*
539	* The spec. mentions that SHV will be 0 when delivery mode is 0 (fixed), but
540	* not what SHV will be if delivery mode is not 0. I ASSUME copying delivery
541	* mode into SHV here is what hardware actually does.
542	*
543	* See Intel VT-d spec. 5.1.5.1 "I/OxAPIC Programming".
544	*/
545	pMsi->Addr.dmar_remap.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
546	pMsi->Addr.dmar_remap.u14IntrIndexLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
547	pMsi->Addr.dmar_remap.fIntrFormat = 1;
548	pMsi->Addr.dmar_remap.fShv = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
549	pMsi->Addr.dmar_remap.u1IntrIndexHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
550
551	pMsi->Data.dmar_remap.u16SubHandle = 0;
552	}
553	}
554	#endif
555
556
557	/**
558	* Signals the next pending interrupt for the specified Redirection Table Entry
559	* (RTE).
560	*
561	* @param pDevIns The device instance.
562	* @param pThis The shared I/O APIC device state.
563	* @param pThisCC The I/O APIC device state for the current context.
564	* @param idxRte The index of the RTE (validated).
565	*
566	* @remarks It is the responsibility of the caller to verify that an interrupt is
567	* pending for the pin corresponding to the RTE before calling this
568	* function.
569	*/
570	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
571	{
572	Assert(IOAPIC_LOCK_IS_OWNER(pDevIns, pThis, pThisCC));
573
574	/*
575	* Ensure the interrupt isn't masked.
576	*/
577	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
578	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
579	{ /* likely */ }
580	else
581	return;
582
583	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
584	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
585	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
586	{
587	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
588	if (u8RemoteIrr)
589	{
590	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
591	return;
592	}
593	}
594
595	XAPICINTR ApicIntr;
596	RT_ZERO(ApicIntr);
597	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
598	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
599	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
600	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
601	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
602	ApicIntr.u8TriggerMode = u8TriggerMode;
603	//ApicIntr.u8RedirHint = 0;
604
605	/** @todo We might be able to release the IOAPIC(PDM) lock here and re-acquire it
606	* before setting the remote IRR bit below. The APIC and IOMMU should not
607	* require the caller to hold the PDM lock. */
608
609	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
610	/*
611	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
612	* For line-based interrupts we must use the southbridge I/O APIC's BDF as
613	* the origin of the interrupt, see @bugref{9654#c74}.
614	*/
615	MSIMSG MsiIn;
616	RT_ZERO(MsiIn);
617	ioapicGetMsiFromRte(u64Rte, pThis->enmType, &MsiIn);
618
619	MSIMSG MsiOut;
620	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, pThis->uPciAddress, &MsiIn, &MsiOut);
621	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
622	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
623	{ /* likely - assuming majority of VMs don't have IOMMU configured. */ }
624	else if (RT_SUCCESS(rcRemap))
625	{
626	/* Update the APIC interrupt with the remapped data. */
627	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
628
629	/* Ensure polarity hasn't changed (trigger mode might change with Intel IOMMUs). */
630	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte));
631	STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
632	}
633	else
634	{
635	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
636	return;
637	}
638	#endif
639
640	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
641	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
642	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
643	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
644	ApicIntr.u8Vector, ApicIntr.u8Vector));
645
646	/*
647	* Deliver to the local APIC via the system/3-wire-APIC bus.
648	*/
649	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
650	ApicIntr.u8Dest,
651	ApicIntr.u8DestMode,
652	ApicIntr.u8DeliveryMode,
653	ApicIntr.u8Vector,
654	ApicIntr.u8Polarity,
655	ApicIntr.u8TriggerMode,
656	u32TagSrc);
657	/* Can't reschedule to R3. */
658	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
659	#ifdef DEBUG_ramshankar
660	if (rc == VERR_APIC_INTR_DISCARDED)
661	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
662	#endif
663
664	/*
665	* For level-triggered interrupts, we set the remote IRR bit to indicate
666	* the local APIC has accepted the interrupt.
667	*
668	* For edge-triggered interrupts, we should not clear the IRR bit as it
669	* should remain intact to reflect the state of the interrupt line.
670	* The device will explicitly transition to inactive state via the
671	* ioapicSetIrq() callback.
672	*/
673	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
674	&& rc == VINF_SUCCESS)
675	{
676	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
677	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
678	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
679	}
680	}
681
682
683	/**
684	* Gets the redirection table entry.
685	*
686	* @returns The redirection table entry.
687	* @param pThis The shared I/O APIC device state.
688	* @param uIndex The index value.
689	*/
690	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
691	{
692	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
693	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
694	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
695	UINT32_MAX);
696	uint32_t uValue;
697	if (!(uIndex & 1))
698	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
699	else
700	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
701
702	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
703	return uValue;
704	}
705
706
707	/**
708	* Sets the redirection table entry.
709	*
710	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
711	* @param pDevIns The device instance.
712	* @param pThis The shared I/O APIC device state.
713	* @param pThisCC The I/O APIC device state for the current context.
714	* @param uIndex The index value.
715	* @param uValue The value to set.
716	*/
717	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
718	uint32_t uIndex, uint32_t uValue)
719	{
720	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
721	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
722	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
723	VINF_SUCCESS);
724
725	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
726	if (rc == VINF_SUCCESS)
727	{
728	/*
729	* Write the low or high 32-bit value into the specified 64-bit RTE register,
730	* update only the valid, writable bits.
731	*
732	* We need to preserve the read-only bits as it can have dire consequences
733	* otherwise, see @bugref{8386#c24}.
734	*/
735	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
736	if (!(uIndex & 1))
737	{
738	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
739	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
740	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
741	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
742	}
743	else
744	{
745	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
746	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
747	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
748	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
749	}
750
751	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
752
753	/*
754	* Signal the next pending interrupt for this RTE.
755	*/
756	uint32_t const uPinMask = UINT32_C(1) << idxRte;
757	if (pThis->uIrr & uPinMask)
758	{
759	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
760	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
761	}
762
763	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
764	}
765	else
766	STAM_COUNTER_INC(&pThis->StatSetRteContention);
767
768	return rc;
769	}
770
771
772	/**
773	* Gets the data register.
774	*
775	* @returns The data value.
776	* @param pThis The shared I/O APIC device state.
777	*/
778	static uint32_t ioapicGetData(PCIOAPIC pThis)
779	{
780	uint8_t const uIndex = pThis->u8Index;
781	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
782	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
783	&& uIndex <= pThis->u8LastRteRegIdx)
784	return ioapicGetRedirTableEntry(pThis, uIndex);
785
786	uint32_t uValue;
787	switch (uIndex)
788	{
789	case IOAPIC_INDIRECT_INDEX_ID:
790	uValue = ioapicGetId(pThis);
791	break;
792
793	case IOAPIC_INDIRECT_INDEX_VERSION:
794	uValue = ioapicGetVersion(pThis);
795	break;
796
797	case IOAPIC_INDIRECT_INDEX_ARB:
798	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
799	{
800	uValue = ioapicGetArb();
801	break;
802	}
803	RT_FALL_THRU();
804
805	default:
806	uValue = UINT32_C(0xffffffff);
807	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
808	break;
809	}
810	return uValue;
811	}
812
813
814	/**
815	* Sets the data register.
816	*
817	* @returns Strict VBox status code.
818	* @param pDevIns The device instance.
819	* @param pThis The shared I/O APIC device state.
820	* @param pThisCC The I/O APIC device state for the current context.
821	* @param uValue The value to set.
822	*/
823	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
824	{
825	uint8_t const uIndex = pThis->u8Index;
826	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
827	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
828
829	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
830	&& uIndex <= pThis->u8LastRteRegIdx)
831	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
832
833	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
834	ioapicSetId(pThis, uValue);
835	else
836	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
837
838	return VINF_SUCCESS;
839	}
840
841
842	/**
843	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
844	*/
845	static DECLCALLBACK(void) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
846	{
847	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
848	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
849
850	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
851	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
852
853	bool fRemoteIrrCleared = false;
854	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
855	AssertRC(rc);
856
857	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
858	{
859	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
860	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
861	{
862	#ifdef DEBUG_ramshankar
863	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
864	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
865	#endif
866	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
867	fRemoteIrrCleared = true;
868	STAM_COUNTER_INC(&pThis->StatEoiReceived);
869	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
870
871	/*
872	* Signal the next pending interrupt for this RTE.
873	*/
874	uint32_t const uPinMask = UINT32_C(1) << idxRte;
875	if (pThis->uIrr & uPinMask)
876	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
877	}
878	}
879
880	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
881
882	#ifndef VBOX_WITH_IOMMU_AMD
883	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
884	#endif
885	}
886
887
888	/**
889	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
890	*/
891	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
892	{
893	RT_NOREF(uBusDevFn); /** @todo r=ramshankar: Remove this argument if it's also unnecessary with Intel IOMMU. */
894	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
895	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
896	pThis->uIrr \|= a_PinMask; \
897	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
898	} while (0)
899
900	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
901	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
902	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
903
904	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
905
906	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
907	{
908	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
909	AssertRC(rc);
910
911	uint8_t const idxRte = iIrq;
912	uint32_t const uPinMask = UINT32_C(1) << idxRte;
913	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
914	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
915
916	bool fActive = RT_BOOL(iLevel & 1);
917	/** @todo Polarity is busted elsewhere, we need to fix that
918	* first. See @bugref{8386#c7}. */
919	#if 0
920	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
921	fActive ^= u8Polarity; */
922	#endif
923	if (!fActive)
924	{
925	pThis->uIrr &= ~uPinMask;
926	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
927	return;
928	}
929
930	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
931	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
932	if (!fFlipFlop)
933	{
934	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
935	{
936	/*
937	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
938	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
939	*/
940	if (!uPrevIrr)
941	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
942	else
943	{
944	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
945	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
946	}
947	}
948	else
949	{
950	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
951
952	/*
953	* For level-triggered interrupts, redundant interrupts are not a problem
954	* and will eventually be delivered anyway after an EOI, but our PDM devices
955	* should not typically call us with no change to the level.
956	*/
957	if (!uPrevIrr)
958	{ /* likely */ }
959	else
960	{
961	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
962	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
963	}
964
965	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
966	}
967	}
968	else
969	{
970	/*
971	* The device is flip-flopping the interrupt line, which implies we should de-assert
972	* and assert the interrupt line. The interrupt line is left in the asserted state
973	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
974	* hence just the assert is done.
975	*/
976	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
977	}
978
979	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
980	}
981	#undef IOAPIC_ASSERT_IRQ
982	}
983
984
985	/**
986	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
987	*/
988	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
989	{
990	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
991	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
992	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
993
994	XAPICINTR ApicIntr;
995	RT_ZERO(ApicIntr);
996
997	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
998	/*
999	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
1000	*
1001	* If the Bus:Dev:Fn isn't valid, it is ASSUMED the device generating the
1002	* MSI is the IOMMU itself and hence isn't subjected to remapping. This
1003	* is the case with Intel IOMMUs.
1004	*
1005	* AMD IOMMUs are full fledged PCI devices, hence the BDF will be a
1006	* valid PCI slot, but interrupts generated by the IOMMU will be handled
1007	* by VERR_IOMMU_CANNOT_CALL_SELF case.
1008	*/
1009	if (PCIBDF_IS_VALID(uBusDevFn))
1010	{
1011	MSIMSG MsiOut;
1012	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
1013	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
1014	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
1015	{ /* likely - assuming majority of VMs don't have IOMMU configured. */ }
1016	else if (RT_SUCCESS(rcRemap))
1017	{
1018	STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
1019	pMsi = &MsiOut;
1020	}
1021	else
1022	{
1023	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
1024	return;
1025	}
1026	}
1027	#else
1028	NOREF(uBusDevFn);
1029	#endif
1030
1031	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
1032
1033	/*
1034	* Deliver to the local APIC via the system/3-wire-APIC bus.
1035	*/
1036	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
1037
1038	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
1039	ApicIntr.u8Dest,
1040	ApicIntr.u8DestMode,
1041	ApicIntr.u8DeliveryMode,
1042	ApicIntr.u8Vector,
1043	0 /* u8Polarity - N/A */,
1044	ApicIntr.u8TriggerMode,
1045	uTagSrc);
1046	/* Can't reschedule to R3. */
1047	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
1048	}
1049
1050
1051	/**
1052	* @callback_method_impl{FNIOMMMIONEWREAD}
1053	*/
1054	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1055	{
1056	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1057	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1058	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1059	RT_NOREF_PV(pvUser);
1060
1061	VBOXSTRICTRC rc = VINF_SUCCESS;
1062	uint32_t puValue = (uint32_t )pv;
1063	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
1064	switch (offReg)
1065	{
1066	case IOAPIC_DIRECT_OFF_INDEX:
1067	*puValue = ioapicGetIndex(pThis);
1068	break;
1069
1070	case IOAPIC_DIRECT_OFF_DATA:
1071	*puValue = ioapicGetData(pThis);
1072	break;
1073
1074	default:
1075	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1076	rc = VINF_IOM_MMIO_UNUSED_FF;
1077	break;
1078	}
1079
1080	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
1081	return rc;
1082	}
1083
1084
1085	/**
1086	* @callback_method_impl{FNIOMMMIONEWWRITE}
1087	*/
1088	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1089	{
1090	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1091	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1092	RT_NOREF_PV(pvUser);
1093
1094	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1095
1096	Assert(!(off & 3));
1097	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1098
1099	VBOXSTRICTRC rc = VINF_SUCCESS;
1100	uint32_t const uValue = (uint32_t const )pv;
1101	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1102
1103	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1104	switch (offReg)
1105	{
1106	case IOAPIC_DIRECT_OFF_INDEX:
1107	ioapicSetIndex(pThis, uValue);
1108	break;
1109
1110	case IOAPIC_DIRECT_OFF_DATA:
1111	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1112	break;
1113
1114	case IOAPIC_DIRECT_OFF_EOI:
1115	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1116	ioapicSetEoi(pDevIns, uValue);
1117	else
1118	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1119	break;
1120
1121	default:
1122	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1123	break;
1124	}
1125
1126	return rc;
1127	}
1128
1129
1130	#ifdef IN_RING3
1131
1132	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1133	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1134	{
1135	RT_NOREF(pDesc);
1136	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1137	return VINF_SUCCESS;
1138	}
1139
1140
1141	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1142	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1143	{
1144	RT_NOREF(pDesc, pfMask);
1145	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1146	return VINF_SUCCESS;
1147	}
1148
1149
1150	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1151	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1152	{
1153	RT_NOREF(pDesc);
1154	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1155	return VINF_SUCCESS;
1156	}
1157
1158
1159	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1160	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1161	{
1162	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1163	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1164	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1165	RT_NOREF(pDesc, pfMask);
1166	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1167	}
1168
1169
1170	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1171	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1172	{
1173	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1174	RT_NOREF(pDesc);
1175	pValue->u32 = ioapicGetVersion(pThis);
1176	return VINF_SUCCESS;
1177	}
1178
1179
1180	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1181	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1182	{
1183	RT_NOREF(pvUser, pDesc);
1184	pValue->u32 = ioapicGetArb();
1185	return VINF_SUCCESS;
1186	}
1187
1188
1189	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1190	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1191	{
1192	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1193	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1194	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1195	return VINF_SUCCESS;
1196	}
1197
1198
1199	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1200	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1201	{
1202	RT_NOREF(pfMask);
1203	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1204	/* No locks, no checks, just do it. */
1205	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1206	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1207	return VINF_SUCCESS;
1208	}
1209
1210
1211	/** IOREDTBLn sub fields. */
1212	static DBGFREGSUBFIELD const g_aRteSubs[] =
1213	{
1214	{ "vector", 0, 8, 0, 0, NULL, NULL },
1215	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1216	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1217	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1218	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1219	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1220	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1221	{ "mask", 16, 1, 0, 0, NULL, NULL },
1222	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1223	{ "dest", 56, 8, 0, 0, NULL, NULL },
1224	DBGFREGSUBFIELD_TERMINATOR()
1225	};
1226
1227
1228	/** Register descriptors for DBGF. */
1229	static DBGFREGDESC const g_aRegDesc[] =
1230	{
1231	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1232	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1233	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1234	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1235	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1236	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1237	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1238	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1239	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1240	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1241	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1242	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1243	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1244	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1245	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1246	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1247	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1248	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1249	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1250	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1251	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1252	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1253	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1254	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1255	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1256	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1257	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1258	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1259	DBGFREGDESC_TERMINATOR()
1260	};
1261
1262
1263	/**
1264	* @callback_method_impl{FNDBGFHANDLERDEV}
1265	*/
1266	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1267	{
1268	RT_NOREF(pszArgs);
1269	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1270	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1271
1272	bool const fLegacy = RTStrCmp(pszArgs, "legacy") == 0;
1273
1274	static const char * const s_apszDeliveryModes[] =
1275	{
1276	" fixed",
1277	"lowpri",
1278	" smi",
1279	" rsvd",
1280	" nmi",
1281	" init",
1282	" rsvd",
1283	"extint"
1284	};
1285	static const char * const s_apszDestMode[] = { "phys", "log " };
1286	static const char * const s_apszTrigMode[] = { " edge", "level" };
1287	static const char * const s_apszPolarity[] = { "acthi", "actlo" };
1288	static const char * const s_apszDeliveryStatus[] = { "idle", "pend" };
1289
1290	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1291
1292	uint32_t const uId = ioapicGetId(pThis);
1293	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1294	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1295
1296	uint32_t const uVer = ioapicGetVersion(pThis);
1297	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1298	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1299	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1300	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1301
1302	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1303	{
1304	uint32_t const uArb = ioapicGetArb();
1305	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1306	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1307	}
1308
1309	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1310
1311	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1312	if ( pThis->enmType != IOAPICTYPE_DMAR
1313	\|\| fLegacy)
1314	{
1315	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
1316	pHlp->pfnPrintf(pHlp, " ---------------------------------------------------------------------------------------------\n");
1317
1318	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1319	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1320	{
1321	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1322	const char *pszDestMode = s_apszDestMode[IOAPIC_RTE_GET_DEST_MODE(u64Rte)];
1323	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1324	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1325	const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
1326	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1327	const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
1328	const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
1329	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1330	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1331	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1332	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1333
1334	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1335	idxRte,
1336	pszDestMode,
1337	uDest,
1338	uMask,
1339	(pThis->uIrr >> idxRte) & 1,
1340	pszTriggerMode,
1341	uRemoteIrr,
1342	pszPolarity,
1343	pszDeliveryStatus,
1344	pszDeliveryMode,
1345	uVector,
1346	u64Rte);
1347	}
1348	}
1349	else
1350	{
1351	pHlp->pfnPrintf(pHlp, " idx intr_idx fmt mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
1352	pHlp->pfnPrintf(pHlp, " ----------------------------------------------------------------------------------------\n");
1353
1354	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1355	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1356	{
1357	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1358	const uint16_t idxIntrLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
1359	const uint8_t fIntrFormat = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
1360	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1361	const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
1362	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1363	const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
1364	const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
1365	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1366	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1367	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1368	const uint16_t idxIntrHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
1369	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1370	const uint16_t idxIntr = idxIntrLo \| (idxIntrHi << 15);
1371	pHlp->pfnPrintf(pHlp, " %02d %4u %u %u %u %s %u %s %s %s %3u (%016llx)\n",
1372	idxRte,
1373	idxIntr,
1374	fIntrFormat,
1375	uMask,
1376	(pThis->uIrr >> idxRte) & 1,
1377	pszTriggerMode,
1378	uRemoteIrr,
1379	pszPolarity,
1380	pszDeliveryStatus,
1381	pszDeliveryMode,
1382	uVector,
1383	u64Rte);
1384	}
1385	}
1386	}
1387
1388
1389	/**
1390	* @copydoc FNSSMDEVSAVEEXEC
1391	*/
1392	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1393	{
1394	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1395	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1396	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1397
1398	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1399	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1400	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1401	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1402	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1403
1404	return VINF_SUCCESS;
1405	}
1406
1407
1408	/**
1409	* @copydoc FNSSMDEVLOADEXEC
1410	*/
1411	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1412	{
1413	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1414	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1415	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1416
1417	Assert(uPass == SSM_PASS_FINAL);
1418	NOREF(uPass);
1419
1420	/* Weed out invalid versions. */
1421	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1422	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1423	{
1424	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1425	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1426	}
1427
1428	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1429	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1430
1431	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1432	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1433	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1434	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1435
1436	return VINF_SUCCESS;
1437	}
1438
1439
1440	/**
1441	* @interface_method_impl{PDMDEVREG,pfnReset}
1442	*/
1443	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1444	{
1445	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1446	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1447	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1448
1449	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1450	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1451
1452	pThis->uIrr = 0;
1453	pThis->u8Index = 0;
1454	pThis->u8Id = 0;
1455
1456	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1457	{
1458	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1459	pThis->au32TagSrc[idxRte] = 0;
1460	}
1461
1462	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1463	}
1464
1465
1466	/**
1467	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1468	*/
1469	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1470	{
1471	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1472	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1473
1474	pThisRC->pIoApicHlp += offDelta;
1475	}
1476
1477
1478	/**
1479	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1480	*/
1481	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1482	{
1483	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1484	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1485	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1486
1487	# ifndef IOAPIC_WITH_PDM_CRITSECT
1488	/*
1489	* Destroy the RTE critical section.
1490	*/
1491	if (PDMCritSectIsInitialized(&pThis->CritSect))
1492	PDMR3CritSectDelete(&pThis->CritSect);
1493	# else
1494	RT_NOREF_PV(pThis);
1495	# endif
1496
1497	return VINF_SUCCESS;
1498	}
1499
1500
1501	/**
1502	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1503	*/
1504	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1505	{
1506	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1507	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1508	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1509	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1510	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1511	Assert(iInstance == 0); RT_NOREF(iInstance);
1512
1513	/*
1514	* Validate and read the configuration.
1515	*/
1516	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType\|PCIAddress", "");
1517
1518	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0
1519	upsets some guest which we haven't yet been tested. */
1520	uint32_t cCpus;
1521	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1522	if (RT_FAILURE(rc))
1523	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1524	pThis->cCpus = (uint8_t)cCpus;
1525
1526	char szChipType[16];
1527	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1528	if (RT_FAILURE(rc))
1529	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1530
1531	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
1532	if (RT_FAILURE(rc))
1533	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
1534
1535	if (!strcmp(szChipType, "ICH9"))
1536	{
1537	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1538	pThis->enmType = IOAPICTYPE_ICH9;
1539	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1540	pThis->u8IdMask = 0xff;
1541	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1542	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1543	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1544	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1545	}
1546	else if (!strcmp(szChipType, "DMAR"))
1547	{
1548	/* Intel DMAR compatible I/O APIC integrated into ICH southbridges. */
1549	/* Identical to ICH9, but interprets RTEs and MSI address and data fields differently. */
1550	pThis->enmType = IOAPICTYPE_DMAR;
1551	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1552	pThis->u8IdMask = 0xff;
1553	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1554	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1555	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_DMAR;
1556	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_DMAR;
1557	}
1558	else if (!strcmp(szChipType, "82093AA"))
1559	{
1560	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1561	pThis->enmType = IOAPICTYPE_82093AA;
1562	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1563	pThis->u8IdMask = 0x0f;
1564	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1565	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1566	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1567	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1568	}
1569	else if (!strcmp(szChipType, "82379AB"))
1570	{
1571	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1572	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1573	pThis->enmType = IOAPICTYPE_82379AB;
1574	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1575	pThis->u8IdMask = 0x0f;
1576	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1577	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1578	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1579	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1580	}
1581	else
1582	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1583	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1584	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1585
1586	/*
1587	* We will use our own critical section for the IOAPIC device.
1588	*/
1589	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1590	AssertRCReturn(rc, rc);
1591
1592	# ifndef IOAPIC_WITH_PDM_CRITSECT
1593	/*
1594	* Setup the critical section to protect concurrent writes to the RTEs.
1595	*/
1596	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1597	AssertRCReturn(rc, rc);
1598	# endif
1599
1600	/*
1601	* Register the IOAPIC.
1602	*/
1603	PDMIOAPICREG IoApicReg;
1604	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1605	IoApicReg.pfnSetIrq = ioapicSetIrq;
1606	IoApicReg.pfnSendMsi = ioapicSendMsi;
1607	IoApicReg.pfnSetEoi = ioapicSetEoi;
1608	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1609	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1610	AssertRCReturn(rc, rc);
1611	AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
1612	AssertPtr(pThisCC->pIoApicHlp->pfnLock);
1613	AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
1614	AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
1615	AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
1616
1617	/*
1618	* Register MMIO region.
1619	*/
1620	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1621	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1622	AssertRCReturn(rc, rc);
1623
1624	/*
1625	* Register the saved state.
1626	*/
1627	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1628	AssertRCReturn(rc, rc);
1629
1630	/*
1631	* Register debugger info item.
1632	*/
1633	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1634	AssertRCReturn(rc, rc);
1635
1636	/*
1637	* Register debugger register access.
1638	*/
1639	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1640	AssertRCReturn(rc, rc);
1641
1642	# ifdef VBOX_WITH_STATISTICS
1643	/*
1644	* Statistics.
1645	*/
1646	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1647	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1648	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1649	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1650
1651	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1652	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1653	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1654	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1655
1656	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1657	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1658	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1659
1660	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
1661	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
1662	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
1663	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
1664
1665	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1666
1667	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1668	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1669	# endif
1670	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1671	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1672	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1673
1674	/*
1675	* Init. the device state.
1676	*/
1677	LogRel(("IOAPIC: Version=%d.%d ChipType=%s\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0f, szChipType));
1678	ioapicR3Reset(pDevIns);
1679
1680	return VINF_SUCCESS;
1681	}
1682
1683	#else /* !IN_RING3 */
1684
1685	/**
1686	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1687	*/
1688	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1689	{
1690	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1691	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1692	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1693
1694	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1695	AssertRCReturn(rc, rc);
1696
1697	PDMIOAPICREG IoApicReg;
1698	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1699	IoApicReg.pfnSetIrq = ioapicSetIrq;
1700	IoApicReg.pfnSendMsi = ioapicSendMsi;
1701	IoApicReg.pfnSetEoi = ioapicSetEoi;
1702	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1703	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1704	AssertRCReturn(rc, rc);
1705	AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
1706	AssertPtr(pThisCC->pIoApicHlp->pfnLock);
1707	AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
1708	AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
1709	AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
1710
1711	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1712	AssertRCReturn(rc, rc);
1713
1714	return VINF_SUCCESS;
1715	}
1716
1717	#endif /* !IN_RING3 */
1718
1719	/**
1720	* IO APIC device registration structure.
1721	*/
1722	const PDMDEVREG g_DeviceIOAPIC =
1723	{
1724	/* .u32Version = */ PDM_DEVREG_VERSION,
1725	/* .uReserved0 = */ 0,
1726	/* .szName = */ "ioapic",
1727	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1728	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1729	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1730	/* .cMaxInstances = */ 1,
1731	/* .uSharedVersion = */ 42,
1732	/* .cbInstanceShared = */ sizeof(IOAPIC),
1733	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1734	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1735	/* .cMaxPciDevices = */ 0,
1736	/* .cMaxMsixVectors = */ 0,
1737	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1738	#if defined(IN_RING3)
1739	/* .pszRCMod = */ "VBoxDDRC.rc",
1740	/* .pszR0Mod = */ "VBoxDDR0.r0",
1741	/* .pfnConstruct = */ ioapicR3Construct,
1742	/* .pfnDestruct = */ ioapicR3Destruct,
1743	/* .pfnRelocate = */ ioapicR3Relocate,
1744	/* .pfnMemSetup = */ NULL,
1745	/* .pfnPowerOn = */ NULL,
1746	/* .pfnReset = */ ioapicR3Reset,
1747	/* .pfnSuspend = */ NULL,
1748	/* .pfnResume = */ NULL,
1749	/* .pfnAttach = */ NULL,
1750	/* .pfnDetach = */ NULL,
1751	/* .pfnQueryInterface = */ NULL,
1752	/* .pfnInitComplete = */ NULL,
1753	/* .pfnPowerOff = */ NULL,
1754	/* .pfnSoftReset = */ NULL,
1755	/* .pfnReserved0 = */ NULL,
1756	/* .pfnReserved1 = */ NULL,
1757	/* .pfnReserved2 = */ NULL,
1758	/* .pfnReserved3 = */ NULL,
1759	/* .pfnReserved4 = */ NULL,
1760	/* .pfnReserved5 = */ NULL,
1761	/* .pfnReserved6 = */ NULL,
1762	/* .pfnReserved7 = */ NULL,
1763	#elif defined(IN_RING0)
1764	/* .pfnEarlyConstruct = */ NULL,
1765	/* .pfnConstruct = */ ioapicRZConstruct,
1766	/* .pfnDestruct = */ NULL,
1767	/* .pfnFinalDestruct = */ NULL,
1768	/* .pfnRequest = */ NULL,
1769	/* .pfnReserved0 = */ NULL,
1770	/* .pfnReserved1 = */ NULL,
1771	/* .pfnReserved2 = */ NULL,
1772	/* .pfnReserved3 = */ NULL,
1773	/* .pfnReserved4 = */ NULL,
1774	/* .pfnReserved5 = */ NULL,
1775	/* .pfnReserved6 = */ NULL,
1776	/* .pfnReserved7 = */ NULL,
1777	#elif defined(IN_RC)
1778	/* .pfnConstruct = */ ioapicRZConstruct,
1779	/* .pfnReserved0 = */ NULL,
1780	/* .pfnReserved1 = */ NULL,
1781	/* .pfnReserved2 = */ NULL,
1782	/* .pfnReserved3 = */ NULL,
1783	/* .pfnReserved4 = */ NULL,
1784	/* .pfnReserved5 = */ NULL,
1785	/* .pfnReserved6 = */ NULL,
1786	/* .pfnReserved7 = */ NULL,
1787	#else
1788	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1789	#endif
1790	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1791	};
1792
1793
1794	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1795

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 89620

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