VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevLPC.cpp@ 53426

Last change on this file since 53426 was 45025, checked in by vboxsync, 12 years ago

Update PDMDEVREG initialization comment so they refer to pfnMemSetup instead of pfnIOCtl.
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  • Property svn:keywords set to Author Date Id Revision
File size: 12.4 KB
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1/* $Id: DevLPC.cpp 45025 2013-03-13 16:45:15Z vboxsync $ */
2/** @file
3 * DevLPC - LPC device emulation
4 *
5 * @todo This needs to be _replaced_ by a proper chipset device one day. There
6 * are less than 10 C/C++ statements in this file doing active emulation.
7 */
8
9/*
10 * Copyright (C) 2006-2013 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 * --------------------------------------------------------------------
20 *
21 * This code is based on:
22 *
23 * Low Pin Count emulation
24 *
25 * Copyright (c) 2007 Alexander Graf
26 *
27 * This library is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU Lesser General Public
29 * License as published by the Free Software Foundation; either
30 * version 2 of the License, or (at your option) any later version.
31 *
32 * This library is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35 * Lesser General Public License for more details.
36 *
37 * You should have received a copy of the GNU Lesser General Public
38 * License along with this library; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
40 *
41 * *****************************************************************
42 *
43 * This driver emulates an ICH-7 LPC partially. The LPC is basically the
44 * same as the ISA-bridge in the existing PIIX implementation, but
45 * more recent and includes support for HPET and Power Management.
46 *
47 */
48
49/*******************************************************************************
50* Header Files *
51*******************************************************************************/
52#define LOG_GROUP LOG_GROUP_DEV_LPC
53#include <VBox/vmm/pdmdev.h>
54#include <VBox/log.h>
55#include <VBox/vmm/stam.h>
56#include <iprt/assert.h>
57#include <iprt/string.h>
58
59#include "VBoxDD2.h"
60
61#define RCBA_BASE UINT32_C(0xFED1C000)
62
63typedef struct
64{
65 /** PCI device structure. */
66 PCIDEVICE dev;
67
68 /** Pointer to the device instance. - R3 ptr. */
69 PPDMDEVINSR3 pDevIns;
70
71 /* So far, not much of a state */
72} LPCState;
73
74
75#ifndef VBOX_DEVICE_STRUCT_TESTCASE
76
77
78static uint32_t rcba_ram_readl(LPCState* s, RTGCPHYS addr)
79{
80 Log(("rcba_read at %llx\n", (uint64_t)addr));
81 int32_t iIndex = (addr - RCBA_BASE);
82 uint32_t value = 0;
83
84 /* This is the HPET config pointer, HPAS in DSDT */
85 switch (iIndex)
86 {
87 case 0x3404:
88 Log(("rcba_read HPET_CONFIG_POINTER\n"));
89 value = 0xf0; /* enabled at 0xfed00000 */
90 break;
91 case 0x3410:
92 /* This is the HPET config pointer */
93 Log(("rcba_read GCS\n"));
94 value = 0;
95 break;
96 default:
97 Log(("Unknown RCBA read\n"));
98 break;
99 }
100
101 return value;
102}
103
104static void rcba_ram_writel(LPCState* s, RTGCPHYS addr, uint32_t value)
105{
106 Log(("rcba_write %llx = %#x\n", (uint64_t)addr, value));
107 int32_t iIndex = (addr - RCBA_BASE);
108
109 switch (iIndex)
110 {
111 case 0x3410:
112 Log(("rcba_write GCS\n"));
113 break;
114 default:
115 Log(("Unknown RCBA write\n"));
116 break;
117 }
118}
119
120/**
121 * I/O handler for memory-mapped read operations.
122 *
123 * @returns VBox status code.
124 *
125 * @param pDevIns The device instance.
126 * @param pvUser User argument.
127 * @param GCPhysAddr Physical address (in GC) where the read starts.
128 * @param pv Where to store the result.
129 * @param cb Number of bytes read.
130 * @thread EMT
131 */
132PDMBOTHCBDECL(int) lpcMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
133{
134 LPCState *s = PDMINS_2_DATA(pDevIns, LPCState*);
135 Assert(cb == 4); Assert(!(GCPhysAddr & 3));
136 *(uint32_t*)pv = rcba_ram_readl(s, GCPhysAddr);
137 return VINF_SUCCESS;
138}
139
140/**
141 * Memory mapped I/O Handler for write operations.
142 *
143 * @returns VBox status code.
144 *
145 * @param pDevIns The device instance.
146 * @param pvUser User argument.
147 * @param GCPhysAddr Physical address (in GC) where the read starts.
148 * @param pv Where to fetch the value.
149 * @param cb Number of bytes to write.
150 * @thread EMT
151 */
152PDMBOTHCBDECL(int) lpcMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
153{
154 LPCState *s = PDMINS_2_DATA(pDevIns, LPCState*);
155
156 switch (cb)
157 {
158 case 1:
159 case 2:
160 break;
161 case 4:
162 rcba_ram_writel(s, GCPhysAddr, *(uint32_t *)pv);
163 break;
164
165 default:
166 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
167 return VERR_INTERNAL_ERROR;
168 }
169 return VINF_SUCCESS;
170}
171
172#ifdef IN_RING3
173
174/**
175 * Info handler, device version.
176 *
177 * @param pDevIns Device instance which registered the info.
178 * @param pHlp Callback functions for doing output.
179 * @param pszArgs Argument string. Optional and specific to the handler.
180 */
181static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
182{
183 LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
184 LogFlow(("lpcInfo: \n"));
185
186 if (pThis->dev.config[0xde] == 0xbe && pThis->dev.config[0xad] == 0xef)
187 pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n");
188 else
189 pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n",
190 pThis->dev.config[0xde], pThis->dev.config[0xad]);
191
192
193 for (int iLine = 0; iLine < 8; ++iLine)
194 {
195
196 int iBase = iLine < 4 ? 0x60 : 0x64;
197 uint8_t iMap = PCIDevGetByte(&pThis->dev, iBase + iLine);
198
199 if ((iMap & 0x80) != 0)
200 pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + iLine);
201 else
202 pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + iLine, iMap & 0xf);
203 }
204}
205
206/**
207 * @interface_method_impl{PDMDEVREG,pfnConstruct}
208 */
209static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
210{
211 LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
212 int rc;
213 Assert(iInstance == 0);
214
215 pThis->pDevIns = pDevIns;
216
217 /*
218 * Register the PCI device.
219 */
220 PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
221 PCIDevSetDeviceId (&pThis->dev, 0x27b9);
222 PCIDevSetCommand (&pThis->dev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
223 PCIDevSetRevisionId (&pThis->dev, 0x02);
224 PCIDevSetClassSub (&pThis->dev, 0x01); /* PCI-to-ISA Bridge */
225 PCIDevSetClassBase (&pThis->dev, 0x06); /* Bridge */
226 PCIDevSetHeaderType (&pThis->dev, 0x80); /* normal, multifunction device (so that other devices can be its functions) */
227 PCIDevSetSubSystemVendorId(&pThis->dev, 0x8086);
228 PCIDevSetSubSystemId (&pThis->dev, 0x7270);
229 PCIDevSetInterruptPin (&pThis->dev, 0x00); /* The LPC device itself generates no interrupts */
230 PCIDevSetStatus (&pThis->dev, 0x0200); /* PCI_status_devsel_medium */
231
232 /** @todo rewrite using PCI accessors; Update, rewrite this device from
233 * scratch! Possibly against ICH9 or something else matching our
234 * chipset of choice. (Note that the exteremely partial emulation here
235 * is supposed to be of ICH7 if what's on the top of the file is
236 * anything to go by.) */
237 /* See p. 427 of ICH9 specification for register description */
238
239 /* 40h - 43h PMBASE 40-43 ACPI Base Address */
240 pThis->dev.config[0x40] = 0x01; /* IO space */
241 pThis->dev.config[0x41] = 0x80; /* base address / 128, see DevACPI.cpp */
242
243 /* 44h ACPI_CNTL ACPI Control */
244 pThis->dev.config[0x44] = 0x00 | (1<<7); /* SCI is IRQ9, ACPI enabled */
245 /* 48h–4Bh GPIOBASE GPIO Base Address */
246
247 /* 4C GC GPIO Control */
248 pThis->dev.config[0x4c] = 0x4d;
249 /* ???? */
250 pThis->dev.config[0x4e] = 0x03;
251 pThis->dev.config[0x4f] = 0x00;
252
253 /* 60h-63h PIRQ[n]_ROUT PIRQ[A-D] Routing Control */
254 pThis->dev.config[0x60] = 0x0b; /* PCI A -> IRQ 11 */
255 pThis->dev.config[0x61] = 0x09; /* PCI B -> IRQ 9 */
256 pThis->dev.config[0x62] = 0x0b; /* PCI C -> IRQ 11 */
257 pThis->dev.config[0x63] = 0x09; /* PCI D -> IRQ 9 */
258
259 /* 64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO */
260 pThis->dev.config[0x64] = 0x10;
261
262 /* 68h-6Bh PIRQ[n]_ROUT PIRQ[E-H] Routing Control */
263 pThis->dev.config[0x68] = 0x80;
264 pThis->dev.config[0x69] = 0x80;
265 pThis->dev.config[0x6A] = 0x80;
266 pThis->dev.config[0x6B] = 0x80;
267
268 /* 6C-6Dh LPC_IBDF IOxAPIC Bus:Device:Function 00F8h R/W */
269 pThis->dev.config[0x70] = 0x80;
270 pThis->dev.config[0x76] = 0x0c;
271 pThis->dev.config[0x77] = 0x0c;
272 pThis->dev.config[0x78] = 0x02;
273 pThis->dev.config[0x79] = 0x00;
274 /* 80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W */
275 /* 82h-83h LPC_EN LPC I/F Enables 0000h R/W */
276 /* 84h-87h GEN1_DEC LPC I/F Generic Decode Range 1 00000000h R/W */
277 /* 88h-8Bh GEN2_DEC LPC I/F Generic Decode Range 2 00000000h R/W */
278 /* 8Ch-8Eh GEN3_DEC LPC I/F Generic Decode Range 3 00000000h R/W */
279 /* 90h-93h GEN4_DEC LPC I/F Generic Decode Range 4 00000000h R/W */
280
281 /* A0h-CFh Power Management */
282 pThis->dev.config[0xa0] = 0x08;
283 pThis->dev.config[0xa2] = 0x00;
284 pThis->dev.config[0xa3] = 0x00;
285 pThis->dev.config[0xa4] = 0x00;
286 pThis->dev.config[0xa5] = 0x00;
287 pThis->dev.config[0xa6] = 0x00;
288 pThis->dev.config[0xa7] = 0x00;
289 pThis->dev.config[0xa8] = 0x0f;
290 pThis->dev.config[0xaa] = 0x00;
291 pThis->dev.config[0xab] = 0x00;
292 pThis->dev.config[0xac] = 0x00;
293 pThis->dev.config[0xae] = 0x00;
294
295 /* D0h-D3h FWH_SEL1 Firmware Hub Select 1 */
296 /* D4h-D5h FWH_SEL2 Firmware Hub Select 2 */
297 /* D8h-D9h FWH_DEC_EN1 Firmware Hub Decode Enable 1 */
298 /* DCh BIOS_CNTL BIOS Control */
299 /* E0h-E1h FDCAP Feature Detection Capability ID */
300 /* E2h FDLEN Feature Detection Capability Length */
301 /* E3h FDVER Feature Detection Version */
302 /* E4h-EBh FDVCT Feature Vector Description */
303
304 /* F0h-F3h RCBA Root Complex Base Address */
305 pThis->dev.config[0xf0] = (uint8_t)(RCBA_BASE | 1); /* enabled */
306 pThis->dev.config[0xf1] = (uint8_t)(RCBA_BASE >> 8);
307 pThis->dev.config[0xf2] = (uint8_t)(RCBA_BASE >> 16);
308 pThis->dev.config[0xf3] = (uint8_t)(RCBA_BASE >> 24);
309
310 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
311 if (RT_FAILURE(rc))
312 return rc;
313
314 /*
315 * Register the MMIO regions.
316 */
317 rc = PDMDevHlpMMIORegister(pDevIns, RCBA_BASE, 0x4000, pThis,
318 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
319 lpcMMIOWrite, lpcMMIORead, "LPC Memory");
320 if (RT_FAILURE(rc))
321 return rc;
322
323 /* No state in the LPC right now */
324
325 /**
326 * @todo: Register statistics.
327 */
328 PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
329
330 return VINF_SUCCESS;
331}
332
333
334/**
335 * The device registration structure.
336 */
337const PDMDEVREG g_DeviceLPC =
338{
339 /* u32Version */
340 PDM_DEVREG_VERSION,
341 /* szName */
342 "lpc",
343 /* szRCMod */
344 "VBoxDD2GC.gc",
345 /* szR0Mod */
346 "VBoxDD2R0.r0",
347 /* pszDescription */
348 "Low Pin Count (LPC) Bus",
349 /* fFlags */
350 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36,
351 /* fClass */
352 PDM_DEVREG_CLASS_MISC,
353 /* cMaxInstances */
354 1,
355 /* cbInstance */
356 sizeof(LPCState),
357 /* pfnConstruct */
358 lpcConstruct,
359 /* pfnDestruct */
360 NULL,
361 /* pfnRelocate */
362 NULL,
363 /* pfnMemSetup */
364 NULL,
365 /* pfnPowerOn */
366 NULL,
367 /* pfnReset */
368 NULL,
369 /* pfnSuspend */
370 NULL,
371 /* pfnResume */
372 NULL,
373 /* pfnAttach */
374 NULL,
375 /* pfnDetach */
376 NULL,
377 /* pfnQueryInterface. */
378 NULL,
379 /* pfnInitComplete */
380 NULL,
381 /* pfnPowerOff */
382 NULL,
383 /* pfnSoftReset */
384 NULL,
385 /* u32VersionEnd */
386 PDM_DEVREG_VERSION
387};
388
389#endif /* IN_RING3 */
390
391#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
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