VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevLpc-new.cpp@ 81591

Last change on this file since 81591 was 81591, checked in by vboxsync, 5 years ago

Devices: Use PDMDEVINS_2_DATA and PDMDEVINS_2_DATA. bugref:9218
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1/* $Id: DevLpc-new.cpp 81591 2019-10-30 14:14:10Z vboxsync $ */
2/** @file
3 * DevLPC - Minimal ICH9 LPC device emulation.
4 */
5
6/*
7 * Copyright (C) 2018-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_LPC
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/log.h>
26
27#include <iprt/assert.h>
28#include <iprt/string.h>
29
30#include "VBoxDD.h"
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36#define LPC_REG_HPET_CONFIG_POINTER 0x3404
37#define LPC_REG_GCS 0x3410
38
39
40/*********************************************************************************************************************************
41* Structures and Typedefs *
42*********************************************************************************************************************************/
43/**
44 * The ICH9 LPC state.
45 */
46typedef struct LPCSTATE
47{
48 /** Pointer to the ring-3 device instance. */
49 PPDMDEVINSR3 pDevInsR3;
50
51 /** The root complex base address. */
52 RTGCPHYS32 GCPhys32Rcba;
53 /** Set if R0/RC context is enabled. */
54 bool fRZEnabled;
55 /** The ICH version (7 or 9). */
56 uint8_t uIchVersion;
57 /** Explicit padding. */
58 uint8_t abPadding[HC_ARCH_BITS == 32 ? 2 : 6];
59
60 /** Number of MMIO reads. */
61 STAMCOUNTER StatMmioReads;
62 /** Number of MMIO writes. */
63 STAMCOUNTER StatMmioWrites;
64 /** Number of PCI config space reads. */
65 STAMCOUNTER StatPciCfgReads;
66 /** Number of PCI config space writes. */
67 STAMCOUNTER StatPciCfgWrites;
68} LPCSTATE;
69/** Pointer to the LPC state. */
70typedef LPCSTATE *PLPCSTATE;
71
72
73#ifndef VBOX_DEVICE_STRUCT_TESTCASE
74
75/**
76 * @callback_method_impl{FNIOMMMIOREAD}
77 */
78PDMBOTHCBDECL(int) lpcMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
79{
80 RT_NOREF(pvUser, cb);
81 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
82 RTGCPHYS32 const offReg = (RTGCPHYS32)GCPhysAddr - pThis->GCPhys32Rcba;
83 Assert(cb == 4); Assert(!(GCPhysAddr & 3)); /* IOMMMIO_FLAGS_READ_DWORD should make sure of this */
84
85 uint32_t *puValue = (uint32_t *)pv;
86 if (offReg == LPC_REG_HPET_CONFIG_POINTER)
87 {
88 *puValue = 0xf0;
89 Log(("lpcMmioRead: HPET_CONFIG_POINTER: %#x\n", *puValue));
90 }
91 else if (offReg == LPC_REG_GCS)
92 {
93 *puValue = 0;
94 Log(("lpcMmioRead: GCS: %#x\n", *puValue));
95 }
96 else
97 {
98 *puValue = 0;
99 Log(("lpcMmioRead: WARNING! Unknown register %#x!\n", offReg));
100 }
101
102 STAM_REL_COUNTER_INC(&pThis->StatMmioReads);
103 return VINF_SUCCESS;
104}
105
106
107/**
108 * @callback_method_impl{FNIOMMMIOWRITE}
109 */
110PDMBOTHCBDECL(int) lpcMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
111{
112 RT_NOREF(pvUser, pv);
113 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
114 RTGCPHYS32 const offReg = (RTGCPHYS32)GCPhysAddr - pThis->GCPhys32Rcba;
115
116 if (cb == 4)
117 {
118 if (offReg == LPC_REG_GCS)
119 Log(("lpcMmioWrite: Ignorning write to GCS: %.*Rhxs\n", cb, pv));
120 else
121 Log(("lpcMmioWrite: Ignorning write to unknown register %#x: %.*Rhxs\n", offReg, cb, pv));
122 }
123 else
124 Log(("lpcMmioWrite: WARNING! Ignoring non-DWORD write to offReg=%#x: %.*Rhxs\n", offReg, cb, pv));
125
126 STAM_REL_COUNTER_INC(&pThis->StatMmioWrites);
127 return VINF_SUCCESS;
128}
129
130#ifdef IN_RING3
131
132/**
133 * @callback_method_impl{FNPCICONFIGREAD}
134 */
135static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
136 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
137{
138 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
139 Assert(pPciDev == pDevIns->apPciDevs[0]);
140
141 STAM_REL_COUNTER_INC(&pThis->StatPciCfgReads);
142 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
143 switch (cb)
144 {
145 case 1: Log(("lpcR3PciConfigRead: %#04x -> %#04x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
146 case 2: Log(("lpcR3PciConfigRead: %#04x -> %#06x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
147 case 4: Log(("lpcR3PciConfigRead: %#04x -> %#010x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
148 }
149 return rcStrict;
150}
151
152
153/**
154 * @callback_method_impl{FNPCICONFIGWRITE}
155 */
156static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
157 uint32_t uAddress, unsigned cb, uint32_t u32Value)
158{
159 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
160 Assert(pPciDev == pDevIns->apPciDevs[0]);
161
162 STAM_REL_COUNTER_INC(&pThis->StatPciCfgWrites);
163 switch (cb)
164 {
165 case 1: Log(("lpcR3PciConfigWrite: %#04x <- %#04x\n", uAddress, u32Value)); break;
166 case 2: Log(("lpcR3PciConfigWrite: %#04x <- %#06x\n", uAddress, u32Value)); break;
167 case 4: Log(("lpcR3PciConfigWrite: %#04x <- %#010x\n", uAddress, u32Value)); break;
168 }
169
170 return PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
171}
172
173
174/**
175 * Info handler, device version.
176 *
177 * @param pDevIns Device instance which registered the info.
178 * @param pHlp Callback functions for doing output.
179 * @param pszArgs Argument string. Optional and specific to the handler.
180 */
181static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
182{
183 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
184 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
185 RT_NOREF(pszArgs);
186
187 if (pThis->uIchVersion == 7)
188 {
189 uint8_t b1 = PDMPciDevGetByte(pPciDev, 0xde);
190 uint8_t b2 = PDMPciDevGetByte(pPciDev, 0xad);
191 if ( b1 == 0xbe
192 && b2 == 0xef)
193 pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n");
194 else
195 pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n", b1, b2);
196 }
197
198 for (unsigned iLine = 0; iLine < 8; iLine++)
199 {
200 unsigned offBase = iLine < 4 ? 0x60 : 0x68 - 4;
201 uint8_t bMap = PDMPciDevGetByte(pPciDev, offBase + iLine);
202 if (bMap & 0x80)
203 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT disabled\n", 'A' + iLine);
204 else
205 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT -> IRQ%d\n", 'A' + iLine, bMap & 0xf);
206 }
207}
208
209
210/**
211 * @interface_method_impl{PDMDEVREG,pfnConstruct}
212 */
213static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
214{
215 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
216 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
217 Assert(iInstance == 0); RT_NOREF(iInstance);
218
219 /*
220 * Initialize state.
221 */
222 pThis->pDevInsR3 = pDevIns;
223
224 /*
225 * Read configuration.
226 */
227 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RZEnabled|RCBA|ICHVersion", "");
228
229 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
230 if (RT_FAILURE(rc))
231 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
232
233 rc = CFGMR3QueryU8Def(pCfg, "ICHVersion", &pThis->uIchVersion, 7 /** @todo 9 */);
234 if (RT_FAILURE(rc))
235 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ICHVersion\""));
236 if ( pThis->uIchVersion != 7
237 && pThis->uIchVersion != 9)
238 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Invalid \"ICHVersion\" value (must be 7 or 9)"));
239
240 rc = CFGMR3QueryU32Def(pCfg, "RCBA", &pThis->GCPhys32Rcba, UINT32_C(0xfed1c000));
241 if (RT_FAILURE(rc))
242 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RCBA\""));
243
244
245 /*
246 * Register the PCI device.
247 *
248 * See sections 13.1 (page 371) and section 13.8.1 (page 429) in the ICH9
249 * specification.
250 *
251 * We set these up so they don't need much/any configuration from the
252 * guest. This is quite possibly wrong, but at the moment we just need to
253 * have this device working w/o lots of firmware fun.
254 */
255 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
256 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
257
258 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
259 if (pThis->uIchVersion == 7)
260 PDMPciDevSetDeviceId(pPciDev, 0x27b9);
261 else if (pThis->uIchVersion == 9)
262 PDMPciDevSetDeviceId(pPciDev, 0x2918); /** @todo unsure if 0x2918 is the right PCI ID... */
263 else
264 AssertFailedReturn(VERR_INTERNAL_ERROR_3);
265 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
266 PDMPciDevSetStatus(pPciDev, 0x0210); /* Note! Used to be 0x0200 for ICH7. */
267 PDMPciDevSetRevisionId(pPciDev, 0x02);
268 PDMPciDevSetClassSub(pPciDev, 0x01); /* PCI-to-ISA bridge */
269 PDMPciDevSetClassBase(pPciDev, 0x06); /* bridge */
270 PDMPciDevSetHeaderType(pPciDev, 0x80); /* Normal, multifunction device (so that other devices can be its functions) */
271 if (pThis->uIchVersion == 7)
272 {
273 PDMPciDevSetSubSystemVendorId(pPciDev, 0x8086);
274 PDMPciDevSetSubSystemId(pPciDev, 0x7270);
275 }
276 else if (pThis->uIchVersion == 9)
277 {
278 PDMPciDevSetSubSystemVendorId(pPciDev, 0x0000); /** @todo docs stays subsystem IDs are zero, check real HW */
279 PDMPciDevSetSubSystemId(pPciDev, 0x0000);
280 }
281 PDMPciDevSetInterruptPin(pPciDev, 0x00); /* The LPC device itself generates no interrupts */
282 PDMPciDevSetDWord(pPciDev, 0x40, 0x00008001); /* PMBASE: ACPI base address; (PM_PORT_BASE (?) * 2 | PCI_ADDRESS_SPACE_IO) */
283 PDMPciDevSetByte(pPciDev, 0x44, 0x80); /* ACPI_CNTL: SCI is IRQ9, ACPI enabled */ /** @todo documented as defaulting to 0x00. */
284 PDMPciDevSetDWord(pPciDev, 0x48, 0x00000001); /* GPIOBASE (note: used to be zero) */
285 PDMPciDevSetByte(pPciDev, 0x4c, 0x4d); /* GC - GPIO control: ??? */ /** @todo documented as defaulting to 0x00. */
286 if (pThis->uIchVersion == 7)
287 PDMPciDevSetByte(pPciDev, 0x4e, 0x03); /* ??? */
288 PDMPciDevSetByte(pPciDev, 0x60, 0x0b); /* PIRQA_ROUT: PCI A -> IRQ 11 (documented default is 0x80) */
289 PDMPciDevSetByte(pPciDev, 0x61, 0x09); /* PIRQB_ROUT: PCI B -> IRQ 9 (documented default is 0x80) */
290 PDMPciDevSetByte(pPciDev, 0x62, 0x0b); /* PIRQC_ROUT: PCI C -> IRQ 11 (documented default is 0x80) */
291 PDMPciDevSetByte(pPciDev, 0x63, 0x09); /* PIRQD_ROUT: PCI D -> IRQ 9 (documented default is 0x80) */
292 PDMPciDevSetByte(pPciDev, 0x64, 0x10); /* SIRQ_CNTL: Serial IRQ Control 10h R/W, RO */
293 PDMPciDevSetByte(pPciDev, 0x68, 0x80); /* PIRQE_ROUT */
294 PDMPciDevSetByte(pPciDev, 0x69, 0x80); /* PIRQF_ROUT */
295 PDMPciDevSetByte(pPciDev, 0x6a, 0x80); /* PIRQG_ROUT */
296 PDMPciDevSetByte(pPciDev, 0x6b, 0x80); /* PIRQH_ROUT */
297 PDMPciDevSetWord(pPciDev, 0x6c, 0x00f8); /* IPC_IBDF: IOxAPIC bus:device:function. (Note! Used to be zero.) */
298 if (pThis->uIchVersion == 7)
299 {
300 /* No idea what this is/was yet: */
301 PDMPciDevSetByte(pPciDev, 0x70, 0x80);
302 PDMPciDevSetByte(pPciDev, 0x76, 0x0c);
303 PDMPciDevSetByte(pPciDev, 0x77, 0x0c);
304 PDMPciDevSetByte(pPciDev, 0x78, 0x02);
305 PDMPciDevSetByte(pPciDev, 0x79, 0x00);
306 }
307 PDMPciDevSetWord(pPciDev, 0x80, 0x0000); /* LPC_I/O_DEC: I/O decode ranges. */
308 PDMPciDevSetWord(pPciDev, 0x82, 0x0000); /* LPC_EN: LPC I/F enables. */
309 PDMPciDevSetDWord(pPciDev, 0x84, 0x00000000); /* GEN1_DEC: LPC I/F generic decode range 1. */
310 PDMPciDevSetDWord(pPciDev, 0x88, 0x00000000); /* GEN2_DEC: LPC I/F generic decode range 2. */
311 PDMPciDevSetDWord(pPciDev, 0x8c, 0x00000000); /* GEN3_DEC: LPC I/F generic decode range 3. */
312 PDMPciDevSetDWord(pPciDev, 0x90, 0x00000000); /* GEN4_DEC: LPC I/F generic decode range 4. */
313
314 PDMPciDevSetWord(pPciDev, 0xa0, 0x0008); /* GEN_PMCON_1: Documented default is 0x0000 */
315 PDMPciDevSetByte(pPciDev, 0xa2, 0x00); /* GEN_PMON_2: */
316 PDMPciDevSetByte(pPciDev, 0xa4, 0x00); /* GEN_PMON_3: */
317 PDMPciDevSetByte(pPciDev, 0xa6, 0x00); /* GEN_PMON_LOCK: Configuration lock. */
318 if (pThis->uIchVersion == 7)
319 PDMPciDevSetByte(pPciDev, 0xa8, 0x0f); /* Is this part of GEN_PMON_LOCK? */
320 PDMPciDevSetByte(pPciDev, 0xab, 0x00); /* BM_BREAK_EN */
321 PDMPciDevSetDWord(pPciDev, 0xac, 0x00000000); /* PMIR: Power */
322 PDMPciDevSetDWord(pPciDev, 0xb8, 0x00000000); /* GPI_ROUT: GPI Route Control */
323 if (pThis->uIchVersion == 9)
324 {
325 /** @todo the next two values looks bogus. */
326 PDMPciDevSetDWord(pPciDev, 0xd0, 0x00112233); /* FWH_SEL1: Firmware Hub Select 1 */
327 PDMPciDevSetWord(pPciDev, 0xd4, 0x4567); /* FWH_SEL2: Firmware Hub Select 2 */
328 PDMPciDevSetWord(pPciDev, 0xd8, 0xffcf); /* FWH_DEC_EN1: Firmware Hub Decode Enable 1 */
329 PDMPciDevSetByte(pPciDev, 0xdc, 0x00); /* BIOS_CNTL: BIOS control */
330 PDMPciDevSetWord(pPciDev, 0xe0, 0x0009); /* FDCAP: Feature Detection Capability ID */
331 PDMPciDevSetByte(pPciDev, 0xe2, 0x0c); /* FDLEN: Feature Detection Capability Length */
332 PDMPciDevSetByte(pPciDev, 0xe3, 0x10); /* FDVER: Feature Detection Version */
333 PDMPciDevSetByte(pPciDev, 0xe4, 0x20); /* FDVCT[0]: 5=SATA RAID 0/1/5/10 capability (1=disabled) */
334 PDMPciDevSetByte(pPciDev, 0xe5, 0x00); /* FDVCT[1]: */
335 PDMPciDevSetByte(pPciDev, 0xe6, 0x00); /* FDVCT[2]: */
336 PDMPciDevSetByte(pPciDev, 0xe7, 0x00); /* FDVCT[3]: */
337 PDMPciDevSetByte(pPciDev, 0xe8, 0xc0); /* FDVCT[4]: 6-7=Intel active magament technology capability (11=disabled). */
338 PDMPciDevSetByte(pPciDev, 0xe9, 0x00); /* FDVCT[5]: */
339 PDMPciDevSetByte(pPciDev, 0xea, 0x00); /* FDVCT[6]: */
340 PDMPciDevSetByte(pPciDev, 0xeb, 0x00); /* FDVCT[7]: */
341 PDMPciDevSetByte(pPciDev, 0xec, 0x00); /* FDVCT[8]: */
342 PDMPciDevSetByte(pPciDev, 0xed, 0x00); /* FDVCT[9]: */
343 PDMPciDevSetByte(pPciDev, 0xee, 0x00); /* FDVCT[a]: */
344 PDMPciDevSetByte(pPciDev, 0xef, 0x00); /* FDVCT[b]: */
345 }
346
347 /* RCBA: Root complex base address (documented default is 0x00000000). Bit 0 is enable bit. */
348 Assert(!(pThis->GCPhys32Rcba & 0x3fff)); /* 16KB aligned */
349 PDMPciDevSetDWord(pPciDev, 0xf0, pThis->GCPhys32Rcba | 1);
350
351 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_NOT_MANDATORY_NO, 31 /*uPciDevNo*/, 0 /*uPciFunNo*/, "lpc");
352 AssertRCReturn(rc, rc);
353 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, lpcR3PciConfigRead, lpcR3PciConfigWrite);
354 AssertRCReturn(rc, rc);
355
356 /*
357 * Register the MMIO regions.
358 */
359 /** @todo This should actually be done when RCBA is enabled, but was
360 * mentioned above we just want this working. */
361 rc = PDMDevHlpMMIORegister(pDevIns, pThis->GCPhys32Rcba, 0x4000, pThis,
362 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
363 lpcMmioWrite, lpcMmioRead, "LPC Memory");
364 AssertRCReturn(rc, rc);
365
366
367 /*
368 * Debug info and stats.
369 */
370 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReads, STAMTYPE_COUNTER, "/Devices/LPC/MMIOReads", STAMUNIT_OCCURENCES, "MMIO reads");
371 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWrites, STAMTYPE_COUNTER, "/Devices/LPC/MMIOWrites", STAMUNIT_OCCURENCES, "MMIO writes");
372 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgReads, STAMTYPE_COUNTER, "/Devices/LPC/ConfigReads", STAMUNIT_OCCURENCES, "PCI config reads");
373 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgWrites, STAMTYPE_COUNTER, "/Devices/LPC/ConfigWrites", STAMUNIT_OCCURENCES, "PCI config writes");
374
375 PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
376
377 return VINF_SUCCESS;
378}
379
380#endif /* IN_RING3 */
381
382/**
383 * The device registration structure.
384 */
385const PDMDEVREG g_DeviceLPC =
386{
387 /* .u32Version = */ PDM_DEVREG_VERSION,
388 /* .uReserved0 = */ 0,
389 /* .szName = */ "lpc",
390 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS,
391 /* .fClass = */ PDM_DEVREG_CLASS_MISC,
392 /* .cMaxInstances = */ 1,
393 /* .uSharedVersion = */ 42,
394 /* .cbInstanceShared = */ sizeof(LPCSTATE),
395 /* .cbInstanceCC = */ 0,
396 /* .cbInstanceRC = */ 0,
397 /* .cMaxPciDevices = */ 1,
398 /* .cMaxMsixVectors = */ 0,
399 /* .pszDescription = */ "Low Pin Count (LPC) Bus",
400#if defined(IN_RING3)
401 /* .pszRCMod = */ "",
402 /* .pszR0Mod = */ "",
403 /* .pfnConstruct = */ lpcConstruct,
404 /* .pfnDestruct = */ NULL,
405 /* .pfnRelocate = */ NULL,
406 /* .pfnMemSetup = */ NULL,
407 /* .pfnPowerOn = */ NULL,
408 /* .pfnReset = */ NULL,
409 /* .pfnSuspend = */ NULL,
410 /* .pfnResume = */ NULL,
411 /* .pfnAttach = */ NULL,
412 /* .pfnDetach = */ NULL,
413 /* .pfnQueryInterface = */ NULL,
414 /* .pfnInitComplete = */ NULL,
415 /* .pfnPowerOff = */ NULL,
416 /* .pfnSoftReset = */ NULL,
417 /* .pfnReserved0 = */ NULL,
418 /* .pfnReserved1 = */ NULL,
419 /* .pfnReserved2 = */ NULL,
420 /* .pfnReserved3 = */ NULL,
421 /* .pfnReserved4 = */ NULL,
422 /* .pfnReserved5 = */ NULL,
423 /* .pfnReserved6 = */ NULL,
424 /* .pfnReserved7 = */ NULL,
425#elif defined(IN_RING0)
426 /* .pfnEarlyConstruct = */ NULL,
427 /* .pfnConstruct = */ NULL,
428 /* .pfnDestruct = */ NULL,
429 /* .pfnFinalDestruct = */ NULL,
430 /* .pfnRequest = */ NULL,
431 /* .pfnReserved0 = */ NULL,
432 /* .pfnReserved1 = */ NULL,
433 /* .pfnReserved2 = */ NULL,
434 /* .pfnReserved3 = */ NULL,
435 /* .pfnReserved4 = */ NULL,
436 /* .pfnReserved5 = */ NULL,
437 /* .pfnReserved6 = */ NULL,
438 /* .pfnReserved7 = */ NULL,
439#elif defined(IN_RC)
440 /* .pfnConstruct = */ NULL,
441 /* .pfnReserved0 = */ NULL,
442 /* .pfnReserved1 = */ NULL,
443 /* .pfnReserved2 = */ NULL,
444 /* .pfnReserved3 = */ NULL,
445 /* .pfnReserved4 = */ NULL,
446 /* .pfnReserved5 = */ NULL,
447 /* .pfnReserved6 = */ NULL,
448 /* .pfnReserved7 = */ NULL,
449#else
450# error "Not in IN_RING3, IN_RING0 or IN_RC!"
451#endif
452 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
453};
454
455#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
456
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