DevPIC.cpp@ 105959

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1	/* $Id: DevPIC.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	* -------------------------------------------------------------------
27	*
28	* This code is based on:
29	*
30	* QEMU 8259 interrupt controller emulation
31	*
32	* Copyright (c) 2003-2004 Fabrice Bellard
33	*
34	* Permission is hereby granted, free of charge, to any person obtaining a copy
35	* of this software and associated documentation files (the "Software"), to deal
36	* in the Software without restriction, including without limitation the rights
37	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38	* copies of the Software, and to permit persons to whom the Software is
39	* furnished to do so, subject to the following conditions:
40	*
41	* The above copyright notice and this permission notice shall be included in
42	* all copies or substantial portions of the Software.
43	*
44	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
50	* THE SOFTWARE.
51	*
52	*/
53
54
55	/*********************************************************************************************************************************
56	* Header Files *
57	*********************************************************************************************************************************/
58	#define LOG_GROUP LOG_GROUP_DEV_PIC
59	#include <VBox/vmm/pdmdev.h>
60	#include <VBox/log.h>
61	#include <iprt/assert.h>
62	#include <iprt/string.h>
63
64	#include "VBoxDD.h"
65
66
67	/*********************************************************************************************************************************
68	* Defined Constants And Macros *
69	*********************************************************************************************************************************/
70	/** @def PIC_LOCK_RET
71	* Acquires the PDM lock. This is a NOP if locking is disabled. */
72	#define PIC_LOCK_RET(a_pDevIns, a_pThisCC, rcBusy) \
73	do { \
74	int const rcLock = (a_pThisCC)->pPicHlp->pfnLock((a_pDevIns), rcBusy); \
75	if (rcLock == VINF_SUCCESS) \
76	{ /* likely */ } \
77	else \
78	return rcLock; \
79	} while (0)
80	/** @def PIC_UNLOCK
81	* Releases the PDM lock. This is a NOP if locking is disabled. */
82	#define PIC_UNLOCK(a_pDevIns, a_pThisCC) \
83	(a_pThisCC)->pPicHlp->pfnUnlock((a_pDevIns))
84
85
86	/*********************************************************************************************************************************
87	* Structures and Typedefs *
88	*********************************************************************************************************************************/
89	/**
90	* The instance data of one (1) PIC.
91	*/
92	typedef struct PICSTATE
93	{
94	uint8_t last_irr; /*< edge detection /
95	uint8_t irr; /*< interrupt request register /
96	uint8_t imr; /*< interrupt mask register /
97	uint8_t isr; /*< interrupt service register /
98	uint8_t priority_add; /*< highest irq priority /
99	uint8_t irq_base;
100	uint8_t read_reg_select;
101	uint8_t poll;
102	uint8_t special_mask;
103	uint8_t init_state;
104	uint8_t auto_eoi;
105	uint8_t rotate_on_auto_eoi;
106	uint8_t special_fully_nested_mode;
107	uint8_t init4; /*< true if 4 byte init /
108	uint8_t elcr; /*< PIIX edge/trigger selection/
109	uint8_t elcr_mask;
110	/** The IRQ tags and source IDs for each (tracing purposes). */
111	uint32_t auTags[8];
112	/** The PIC index (0 or 1). */
113	uint8_t idxPic;
114	uint8_t abAlignment0[7]; /*< Alignment padding. /
115	/** The two I/O ports at 0x20 or 0xa0. */
116	IOMIOPORTHANDLE hIoPorts0;
117	/** The ELCR I/O port at 0x4d0 or 0x4d1. */
118	IOMIOPORTHANDLE hIoPorts1;
119	} PICSTATE;
120	AssertCompileMemberAlignment(PICSTATE, hIoPorts0, 8);
121	/** Pointer to the state of one PIC. */
122	typedef PICSTATE *PPICSTATE;
123
124
125	/**
126	* The shared PIC device instance data.
127	*/
128	typedef struct DEVPIC
129	{
130	/** The two interrupt controllers. */
131	PICSTATE aPics[2];
132	/** Number of release log entries. Used to prevent flooding. */
133	uint32_t cRelLogEntries;
134	uint32_t u32Padding;
135	#ifdef VBOX_WITH_STATISTICS
136	STAMCOUNTER StatSetIrqRZ;
137	STAMCOUNTER StatSetIrqR3;
138	STAMCOUNTER StatClearedActiveIRQ2;
139	STAMCOUNTER StatClearedActiveMasterIRQ;
140	STAMCOUNTER StatClearedActiveSlaveIRQ;
141	#endif
142	} DEVPIC;
143	/** Pointer to the shared PIC instance data. */
144	typedef DEVPIC *PDEVPIC;
145
146
147	/**
148	* The PIC device instance data for ring-3.
149	*/
150	typedef struct DEVPICR3
151	{
152	/** Pointer to the PIC ring-3 helpers. */
153	R3PTRTYPE(PCPDMPICHLP) pPicHlp;
154	} DEVPICR3;
155	/** Pointer to the ring-3 PIC instance data. */
156	typedef DEVPICR3 *PDEVPICR3;
157
158
159	/**
160	* The PIC device instance data for ring-0.
161	*/
162	typedef struct DEVPICR0
163	{
164	/** Pointer to the PIC ring-0 helpers. */
165	R0PTRTYPE(PCPDMPICHLP) pPicHlp;
166	} DEVPICR0;
167	/** Pointer to the ring-0 PIC instance data. */
168	typedef DEVPICR0 *PDEVPICR0;
169
170
171	/**
172	* The PIC device instance data for raw-mode.
173	*/
174	typedef struct DEVPICRC
175	{
176	/** Pointer to the PIC raw-mode helpers. */
177	RCPTRTYPE(PCPDMPICHLP) pPicHlp;
178	} DEVPICRC;
179	/** Pointer to the raw-mode PIC instance data. */
180	typedef DEVPICRC *PDEVPICRC;
181
182
183	/** The PIC instance data for the current context. */
184	typedef CTX_SUFF(DEVPIC) DEVPICCC;
185	/** Pointer to the PIC instance data for the current context. */
186	typedef CTX_SUFF(PDEVPIC) PDEVPICCC;
187
188
189
190	#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* The rest of the file! */
191
192	#ifdef LOG_ENABLED
193	DECLINLINE(void) DumpPICState(PPICSTATE pPic, const char *pszFn)
194	{
195	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
196	pszFn, pPic->idxPic, pPic->elcr, pPic->last_irr, pPic->irr, pPic->imr, pPic->isr, pPic->irq_base));
197	}
198	#else
199	# define DumpPICState(pThis, szFn) do { } while (0)
200	#endif
201
202	/* set irq level. If an edge is detected, then the IRR is set to 1 */
203	DECLINLINE(void) pic_set_irq1(PPICSTATE pPic, int irq, int level, uint32_t uTagSrc)
204	{
205	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
206	int mask = 1 << irq;
207	if (pPic->elcr & mask)
208	{
209	/* level triggered */
210	if (level)
211	{
212	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", pPic->irr, pPic->irr \| mask));
213	pPic->irr \|= mask;
214	pPic->last_irr \|= mask;
215	}
216	else
217	{
218	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", pPic->irr, pPic->irr & ~mask));
219	pPic->irr &= ~mask;
220	pPic->last_irr &= ~mask;
221	}
222	}
223	else
224	{
225	/* edge triggered */
226	if (level)
227	{
228	if ((pPic->last_irr & mask) == 0)
229	{
230	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", pPic->irr \| mask, pPic->last_irr));
231	pPic->irr \|= mask;
232	}
233	pPic->last_irr \|= mask;
234	}
235	else
236	{
237	pPic->irr &= ~mask;
238	pPic->last_irr &= ~mask;
239	}
240	}
241
242	/* Save the tag. */
243	if (level)
244	{
245	if (!pPic->auTags[irq])
246	pPic->auTags[irq] = uTagSrc;
247	else
248	pPic->auTags[irq] \|= RT_BIT_32(31);
249	}
250
251	DumpPICState(pPic, "pic_set_irq1");
252	}
253
254	/* return the highest priority found in mask (highest = smallest
255	number). Return 8 if no irq */
256	DECLINLINE(int) get_priority(PPICSTATE pPic, int mask)
257	{
258	int priority;
259	if (mask == 0)
260	return 8;
261	priority = 0;
262	while ((mask & (1 << ((priority + pPic->priority_add) & 7))) == 0)
263	priority++;
264	return priority;
265	}
266
267	/* return the pic wanted interrupt. return -1 if none */
268	static int pic_get_irq(PPICSTATE pPic)
269	{
270	int mask, cur_priority, priority;
271	Log(("pic_get_irq%d: mask=%x\n", pPic->idxPic, pPic->irr & ~pPic->imr));
272	DumpPICState(pPic, "pic_get_irq");
273
274	mask = pPic->irr & ~pPic->imr;
275	priority = get_priority(pPic, mask);
276	Log(("pic_get_irq: priority=%x\n", priority));
277	if (priority == 8)
278	return -1;
279	/* compute current priority. If special fully nested mode on the
280	master, the IRQ coming from the slave is not taken into account
281	for the priority computation. */
282	mask = pPic->isr;
283	if (pPic->special_mask)
284	mask &= ~pPic->imr;
285	if (pPic->special_fully_nested_mode && pPic->idxPic == 0)
286	mask &= ~(1 << 2);
287	cur_priority = get_priority(pPic, mask);
288	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", pPic->idxPic,
289	cur_priority, (priority == 8) ? -1 : (priority + pPic->priority_add) & 7));
290	if (priority < cur_priority)
291	{
292	/* higher priority found: an irq should be generated */
293	return (priority + pPic->priority_add) & 7;
294	}
295	return -1;
296	}
297
298	/* raise irq to CPU if necessary. must be called every time the active
299	irq may change */
300	static int pic_update_irq(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC)
301	{
302	int irq2, irq;
303
304	/* first look at slave pic */
305	irq2 = pic_get_irq(&pThis->aPics[1]);
306	Log(("pic_update_irq irq2=%d\n", irq2));
307	if (irq2 >= 0)
308	{
309	/* if irq request by slave pic, signal master PIC */
310	pic_set_irq1(&pThis->aPics[0], 2, 1, pThis->aPics[1].auTags[irq2]);
311	}
312	else
313	{
314	/* If not, clear the IR on the master PIC. */
315	pic_set_irq1(&pThis->aPics[0], 2, 0, 0 /uTagSrc/);
316	}
317	/* look at requested irq */
318	irq = pic_get_irq(&pThis->aPics[0]);
319	if (irq >= 0)
320	{
321	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
322	* spurious slave interrupts in picGetInterrupt.
323	*/
324	if (irq != 2 \|\| irq2 != -1)
325	{
326	for (int i = 0; i < 2; i++)
327	Log(("pic%d: imr=%x irr=%x padd=%d\n", i, pThis->aPics[i].imr, pThis->aPics[i].irr, pThis->aPics[i].priority_add));
328	Log(("pic: cpu_interrupt\n"));
329	pThisCC->pPicHlp->pfnSetInterruptFF(pDevIns);
330	}
331	else
332	{
333	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
334	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
335	/* Clear it here, so lower priority interrupts can still be dispatched. */
336
337	/* if this was the only pending irq, then we must clear the interrupt ff flag */
338	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
339
340	/** @todo Is this correct? */
341	pThis->aPics[0].irr &= ~(1 << 2);
342
343	/* Call ourselves again just in case other interrupts are pending */
344	return pic_update_irq(pDevIns, pThis, pThisCC);
345	}
346	}
347	else
348	{
349	Log(("pic_update_irq: no interrupt is pending!!\n"));
350
351	/* we must clear the interrupt ff flag */
352	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
353	}
354	return VINF_SUCCESS;
355	}
356
357	/**
358	* Set the an IRQ.
359	*
360	* @param pDevIns Device instance of the PICs.
361	* @param iIrq IRQ number to set.
362	* @param iLevel IRQ level.
363	* @param uTagSrc The IRQ tag and source ID (for tracing).
364	*/
365	static DECLCALLBACK(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
366	{
367	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
368	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
369	AssertMsgReturnVoid(iIrq < 16, ("iIrq=%d\n", iIrq));
370
371	Log(("picSetIrq %d %d\n", iIrq, iLevel));
372	DumpPICState(&pThis->aPics[0], "picSetIrq");
373	DumpPICState(&pThis->aPics[1], "picSetIrq");
374	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
375	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
376	{
377	/* A flip-flop lowers the IRQ line and immediately raises it, so
378	* that a rising edge is guaranteed to occur. Note that the IRQ
379	* line must be held high for a while to avoid spurious interrupts.
380	*/
381	pic_set_irq1(&RT_SAFE_SUBSCRIPT(pThis->aPics, iIrq >> 3), iIrq & 7, 0, uTagSrc);
382	pic_update_irq(pDevIns, pThis, pThisCC);
383	}
384	pic_set_irq1(&RT_SAFE_SUBSCRIPT(pThis->aPics, iIrq >> 3), iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc);
385	pic_update_irq(pDevIns, pThis, pThisCC);
386	}
387
388
389	/* acknowledge interrupt 'irq' */
390	DECLINLINE(void) pic_intack(PPICSTATE pPic, int irq)
391	{
392	if (pPic->auto_eoi)
393	{
394	if (pPic->rotate_on_auto_eoi)
395	pPic->priority_add = (irq + 1) & 7;
396	}
397	else
398	pPic->isr \|= (1 << irq);
399
400	/* We don't clear a level sensitive interrupt here */
401	if (!(pPic->elcr & (1 << irq)))
402	{
403	Log2(("pic_intack: irr=%x irrnew=%x\n", pPic->irr, pPic->irr & ~(1 << irq)));
404	pPic->irr &= ~(1 << irq);
405	}
406	}
407
408
409	/**
410	* Get a pending interrupt.
411	*
412	* @returns Pending interrupt number.
413	* @param pDevIns Device instance of the PICs.
414	* @param puTagSrc Where to return the IRQ tag and source ID.
415	*/
416	static DECLCALLBACK(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
417	{
418	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
419	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
420	int irq;
421	int irq2;
422	int intno;
423
424	/* read the irq from the PIC */
425	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
426	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
427
428	irq = pic_get_irq(&pThis->aPics[0]);
429	if (irq >= 0)
430	{
431	pic_intack(&pThis->aPics[0], irq);
432	if (irq == 2)
433	{
434	irq2 = pic_get_irq(&pThis->aPics[1]);
435	if (irq2 >= 0)
436	pic_intack(&pThis->aPics[1], irq2);
437	else
438	{
439	/* Interrupt went away or is now masked. */
440	Log(("picGetInterrupt: spurious IRQ on slave controller, converted to IRQ15\n"));
441	irq2 = 7;
442	}
443	intno = pThis->aPics[1].irq_base + irq2;
444	*puTagSrc = pThis->aPics[0].auTags[irq2];
445	pThis->aPics[0].auTags[irq2] = 0;
446	Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc));
447	irq = irq2 + 8;
448	}
449	else
450	{
451	intno = pThis->aPics[0].irq_base + irq;
452	*puTagSrc = pThis->aPics[0].auTags[irq];
453	pThis->aPics[0].auTags[irq] = 0;
454	Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc));
455	}
456	}
457	else
458	{
459	/* Interrupt went away or is now masked. */
460	Log(("picGetInterrupt: spurious IRQ on master controller, converted to IRQ7\n"));
461	irq = 7;
462	intno = pThis->aPics[0].irq_base + irq;
463	*puTagSrc = 0;
464	}
465	pic_update_irq(pDevIns, pThis, pThisCC);
466
467	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
468
469	return intno;
470	}
471
472	static void pic_reset(PPICSTATE pPic)
473	{
474	pPic->last_irr = 0;
475	pPic->irr = 0;
476	pPic->imr = 0;
477	pPic->isr = 0;
478	pPic->priority_add = 0;
479	pPic->irq_base = 0;
480	pPic->read_reg_select = 0;
481	pPic->poll = 0;
482	pPic->special_mask = 0;
483	pPic->init_state = 0;
484	pPic->auto_eoi = 0;
485	pPic->rotate_on_auto_eoi = 0;
486	pPic->special_fully_nested_mode = 0;
487	pPic->init4 = 0;
488	//pPic->elcr - not cleared;
489	//pPic->elcr_mask - not cleared;
490	RT_ZERO(pPic->auTags);
491	}
492
493
494	static VBOXSTRICTRC pic_ioport_write(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic,
495	uint32_t addr, uint32_t val)
496	{
497	VBOXSTRICTRC rc = VINF_SUCCESS;
498	int irq;
499
500	Log(("pic_write/%zu: addr=0x%02x val=0x%02x\n", pPic - pThis->aPics, addr, val));
501	addr &= 1;
502	if (addr == 0)
503	{
504	if (val & 0x10)
505	{
506	/* init */
507	pic_reset(pPic);
508	/* deassert a pending interrupt */
509	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
510
511	pPic->init_state = 1;
512	pPic->init4 = val & 1;
513	if (!(val & 0x0a))
514	{ /* likely */ }
515	else if (pThis->cRelLogEntries++ < 64)
516	{
517	if (val & 0x02)
518	LogRel(("PIC: Single mode not supported, ignored.\n"));
519	if (val & 0x08)
520	LogRel(("PIC: Level sensitive IRQ setting ignored.\n"));
521	}
522	}
523	else if (val & 0x08)
524	{
525	if (val & 0x04)
526	pPic->poll = 1;
527	if (val & 0x02)
528	pPic->read_reg_select = val & 1;
529	if (val & 0x40)
530	pPic->special_mask = (val >> 5) & 1;
531	}
532	else
533	{
534	int cmd = val >> 5;
535	switch (cmd)
536	{
537	case 0:
538	case 4:
539	pPic->rotate_on_auto_eoi = cmd >> 2;
540	break;
541	case 1: /* end of interrupt */
542	case 5:
543	{
544	int priority = get_priority(pPic, pPic->isr);
545	if (priority != 8) {
546	irq = (priority + pPic->priority_add) & 7;
547	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
548	pPic->isr &= ~(1 << irq);
549	if (cmd == 5)
550	pPic->priority_add = (irq + 1) & 7;
551	rc = pic_update_irq(pDevIns, pThis, pThisCC);
552	Assert(rc == VINF_SUCCESS);
553	DumpPICState(pPic, "eoi");
554	}
555	break;
556	}
557	case 3:
558	{
559	irq = val & 7;
560	Log(("pic_write: EOI2 for irq %d\n", irq));
561	pPic->isr &= ~(1 << irq);
562	rc = pic_update_irq(pDevIns, pThis, pThisCC);
563	Assert(rc == VINF_SUCCESS);
564	DumpPICState(pPic, "eoi2");
565	break;
566	}
567	case 6:
568	{
569	pPic->priority_add = (val + 1) & 7;
570	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, pPic->priority_add));
571	rc = pic_update_irq(pDevIns, pThis, pThisCC);
572	Assert(rc == VINF_SUCCESS);
573	break;
574	}
575	case 7:
576	{
577	irq = val & 7;
578	Log(("pic_write: EOI3 for irq %d\n", irq));
579	pPic->isr &= ~(1 << irq);
580	pPic->priority_add = (irq + 1) & 7;
581	rc = pic_update_irq(pDevIns, pThis, pThisCC);
582	Assert(rc == VINF_SUCCESS);
583	DumpPICState(pPic, "eoi3");
584	break;
585	}
586	default:
587	/* no operation */
588	break;
589	}
590	}
591	}
592	else
593	{
594	switch (pPic->init_state)
595	{
596	case 0:
597	/* normal mode */
598	pPic->imr = val;
599	rc = pic_update_irq(pDevIns, pThis, pThisCC);
600	Assert(rc == VINF_SUCCESS);
601	break;
602	case 1:
603	pPic->irq_base = val & 0xf8;
604	pPic->init_state = 2;
605	Log(("pic_write: set irq base to %x\n", pPic->irq_base));
606	break;
607	case 2:
608	if (pPic->init4)
609	pPic->init_state = 3;
610	else
611	pPic->init_state = 0;
612	break;
613	case 3:
614	pPic->special_fully_nested_mode = (val >> 4) & 1;
615	pPic->auto_eoi = (val >> 1) & 1;
616	pPic->init_state = 0;
617	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", pPic->special_fully_nested_mode, pPic->auto_eoi));
618	break;
619	}
620	}
621	return rc;
622	}
623
624
625	static uint32_t pic_poll_read(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic, uint32_t addr1)
626	{
627	int ret = pic_get_irq(pPic);
628	if (ret >= 0)
629	{
630	if (addr1 >> 7)
631	{
632	Log2(("pic_poll_read: clear slave irq (isr)\n"));
633	pThis->aPics[0].isr &= ~(1 << 2);
634	pThis->aPics[0].irr &= ~(1 << 2);
635	}
636	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
637	pPic->irr &= ~(1 << ret);
638	pPic->isr &= ~(1 << ret);
639	if (addr1 >> 7 \|\| ret != 2)
640	pic_update_irq(pDevIns, pThis, pThisCC);
641	}
642	else
643	{
644	ret = 0;
645	pic_update_irq(pDevIns, pThis, pThisCC);
646	}
647
648	return ret;
649	}
650
651
652	static uint32_t pic_ioport_read(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic, uint32_t addr1, int *pRC)
653	{
654	unsigned int addr;
655	int ret;
656
657	*pRC = VINF_SUCCESS;
658
659	addr = addr1;
660	addr &= 1;
661	if (pPic->poll)
662	{
663	ret = pic_poll_read(pDevIns, pThis, pThisCC, pPic, addr1);
664	pPic->poll = 0;
665	}
666	else
667	{
668	if (addr == 0)
669	{
670	if (pPic->read_reg_select)
671	ret = pPic->isr;
672	else
673	ret = pPic->irr;
674	}
675	else
676	ret = pPic->imr;
677	}
678	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
679	return ret;
680	}
681
682
683
684	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
685
686	/**
687	* @callback_method_impl{FNIOMIOPORTNEWIN}
688	*/
689	static DECLCALLBACK(VBOXSTRICTRC) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
690	{
691	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
692	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
693	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
694	int rc;
695
696	Assert(iPic == 0 \|\| iPic == 1);
697	if (cb == 1)
698	{
699	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
700	*pu32 = pic_ioport_read(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, &rc);
701	PIC_UNLOCK(pDevIns, pThisCC);
702	return rc;
703	}
704	else if (cb == 2)
705	{
706	uint8_t u8Lo, u8Hi = 0;
707	/* Manually split access. Probably not 100% accurate! */
708	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
709	u8Lo = pic_ioport_read(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, &rc);
710	Assert(rc == VINF_SUCCESS);
711	if (!(offPort & 1))
712	u8Hi = pic_ioport_read(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort + 1, &rc);
713	PIC_UNLOCK(pDevIns, pThisCC);
714	*pu32 = RT_MAKE_U16(u8Lo, u8Hi);
715	return rc;
716	}
717	return VERR_IOM_IOPORT_UNUSED;
718	}
719
720
721	/**
722	* @callback_method_impl{FNIOMIOPORTNEWOUT}
723	*/
724	static DECLCALLBACK(VBOXSTRICTRC) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
725	{
726	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
727	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
728	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
729	VBOXSTRICTRC rc;
730
731	Assert(iPic == 0 \|\| iPic == 1);
732
733	if (cb == 1)
734	{
735	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
736	rc = pic_ioport_write(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, u32);
737	PIC_UNLOCK(pDevIns, pThisCC);
738	return rc;
739	}
740	else if (cb == 2)
741	{
742	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
743	/* Manually split access. Probably not 100% accurate! */
744	rc = pic_ioport_write(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, RT_LOBYTE(u32));
745	if (RT_SUCCESS(rc) && !(offPort & 1))
746	rc = pic_ioport_write(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort + 1, RT_HIBYTE(u32));
747	PIC_UNLOCK(pDevIns, pThisCC);
748	return rc;
749	}
750	return VINF_SUCCESS;
751	}
752
753
754	/**
755	* @callback_method_impl{FNIOMIOPORTNEWIN, ELCR}
756	*/
757	static DECLCALLBACK(VBOXSTRICTRC) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
758	{
759	if (cb == 1)
760	{
761	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
762	PPICSTATE pPic = (PPICSTATE)pvUser;
763	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
764	*pu32 = pPic->elcr;
765	PIC_UNLOCK(pDevIns, pThisCC);
766	return VINF_SUCCESS;
767	}
768	RT_NOREF(offPort);
769	return VERR_IOM_IOPORT_UNUSED;
770	}
771
772
773	/**
774	* @callback_method_impl{FNIOMIOPORTNEWOUT, ELCR}
775	*/
776	static DECLCALLBACK(VBOXSTRICTRC) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
777	{
778	if (cb == 1)
779	{
780	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
781	PPICSTATE pPic = (PPICSTATE)pvUser;
782	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
783	pPic->elcr = u32 & pPic->elcr_mask;
784	PIC_UNLOCK(pDevIns, pThisCC);
785	}
786	RT_NOREF(offPort);
787	return VINF_SUCCESS;
788	}
789
790
791	#ifdef IN_RING3
792
793	/**
794	* @callback_method_impl{FNDBGFHANDLERDEV}
795	*/
796	static DECLCALLBACK(void) picR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
797	{
798	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
799	NOREF(pszArgs);
800
801	/*
802	* Show info.
803	*/
804	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
805	{
806	PPICSTATE pPic = &pThis->aPics[i];
807
808	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
809	pHlp->pfnPrintf(pHlp, " IMR :%02x ISR :%02x IRR :%02x LIRR:%02x\n",
810	pPic->imr, pPic->isr, pPic->irr, pPic->last_irr);
811	pHlp->pfnPrintf(pHlp, " Base:%02x PriAdd:%02x RegSel:%02x\n",
812	pPic->irq_base, pPic->priority_add, pPic->read_reg_select);
813	pHlp->pfnPrintf(pHlp, " Poll:%02x SpMask:%02x IState:%02x\n",
814	pPic->poll, pPic->special_mask, pPic->init_state);
815	pHlp->pfnPrintf(pHlp, " AEOI:%02x Rotate:%02x FNest :%02x Ini4:%02x\n",
816	pPic->auto_eoi, pPic->rotate_on_auto_eoi,
817	pPic->special_fully_nested_mode, pPic->init4);
818	pHlp->pfnPrintf(pHlp, " ELCR:%02x ELMask:%02x\n", pPic->elcr, pPic->elcr_mask);
819	}
820	}
821
822
823	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
824
825	/**
826	* @callback_method_impl{FNSSMDEVSAVEEXEC}
827	*/
828	static DECLCALLBACK(int) picR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
829	{
830	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
831	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
832
833	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
834	{
835	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].last_irr);
836	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].irr);
837	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].imr);
838	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].isr);
839	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].priority_add);
840	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].irq_base);
841	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].read_reg_select);
842	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].poll);
843	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].special_mask);
844	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].init_state);
845	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].auto_eoi);
846	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].rotate_on_auto_eoi);
847	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].special_fully_nested_mode);
848	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].init4);
849	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].elcr);
850	}
851	return VINF_SUCCESS;
852	}
853
854
855	/**
856	* @callback_method_impl{FNSSMDEVLOADEXEC}
857	*/
858	static DECLCALLBACK(int) picR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
859	{
860	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
861	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
862
863	if (uVersion != 1)
864	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
865	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
866
867	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
868	{
869	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].last_irr);
870	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].irr);
871	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].imr);
872	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].isr);
873	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].priority_add);
874	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].irq_base);
875	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].read_reg_select);
876	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].poll);
877	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].special_mask);
878	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].init_state);
879	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].auto_eoi);
880	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].rotate_on_auto_eoi);
881	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].special_fully_nested_mode);
882	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].init4);
883	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].elcr);
884	}
885
886	/* Note! PDM will restore the VMCPU_FF_INTERRUPT_PIC state. */
887	return VINF_SUCCESS;
888	}
889
890
891	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
892
893	/**
894	* @interface_method_impl{PDMDEVREG,pfnReset}
895	*/
896	static DECLCALLBACK(void) picR3Reset(PPDMDEVINS pDevIns)
897	{
898	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
899	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
900	unsigned i;
901	LogFlow(("picR3Reset:\n"));
902	pThisCC->pPicHlp->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
903
904	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
905	pic_reset(&pThis->aPics[i]);
906
907	PIC_UNLOCK(pDevIns, pThisCC);
908	}
909
910
911	/**
912	* @interface_method_impl{PDMDEVREG,pfnRelocate}
913	*/
914	static DECLCALLBACK(void) picR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
915	{
916	PDEVPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PDEVPICRC);
917	pThisRC->pPicHlp += offDelta;
918	}
919
920
921	/**
922	* @interface_method_impl{PDMDEVREG,pfnConstruct}
923	*/
924	static DECLCALLBACK(int) picR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
925	{
926	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
927	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
928	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
929	int rc;
930	RT_NOREF(iInstance, pCfg);
931
932	Assert(iInstance == 0);
933
934	/*
935	* Validate and read configuration.
936	*/
937	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
938	Log(("DevPIC: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
939
940	/*
941	* Init the data.
942	*/
943	Assert(RT_ELEMENTS(pThis->aPics) == 2);
944	pThis->aPics[0].elcr_mask = 0xf8;
945	pThis->aPics[1].elcr_mask = 0xde;
946	pThis->aPics[0].idxPic = 0;
947	pThis->aPics[1].idxPic = 1;
948	pThis->cRelLogEntries = 0;
949
950	/*
951	* Register us as the PIC with PDM.
952	*/
953	PDMPICREG PicReg;
954	PicReg.u32Version = PDM_PICREG_VERSION;
955	PicReg.pfnSetIrq = picSetIrq;
956	PicReg.pfnGetInterrupt = picGetInterrupt;
957	PicReg.u32TheEnd = PDM_PICREG_VERSION;
958	rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThisCC->pPicHlp);
959	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpPICRegister -> %Rrc\n", rc), rc);
960	AssertReturn(pThisCC->pPicHlp->u32Version == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
961	AssertReturn(pThisCC->pPicHlp->u32TheEnd == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
962
963	/*
964	* Since the PIC helper interface provides access to the PDM lock,
965	* we need no device level critical section.
966	*/
967	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
968	AssertRCReturn(rc, rc);
969
970	/*
971	* Register I/O ports and save state.
972	*/
973	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x20 /uPort/, 2 /cPorts/, picIOPortWrite, picIOPortRead, (void *)0,
974	"i8259 PIC #0", NULL /paExtDesc/, &pThis->aPics[0].hIoPorts0);
975	AssertRCReturn(rc, rc);
976	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xa0 /uPort/, 2 /cPorts/, picIOPortWrite, picIOPortRead, (void *)1,
977	"i8259 PIC #1", NULL /paExtDesc/, &pThis->aPics[1].hIoPorts0);
978	AssertRCReturn(rc, rc);
979
980
981	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x4d0 /uPort/, 1 /cPorts/, picIOPortElcrWrite, picIOPortElcrRead,
982	&pThis->aPics[0], "i8259 PIC #0 - elcr", NULL /paExtDesc/, &pThis->aPics[0].hIoPorts1);
983	AssertRCReturn(rc, rc);
984	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x4d1 /uPort/, 1 /cPorts/, picIOPortElcrWrite, picIOPortElcrRead,
985	&pThis->aPics[1], "i8259 PIC #1 - elcr", NULL /paExtDesc/, &pThis->aPics[1].hIoPorts1);
986	AssertRCReturn(rc, rc);
987
988	/*
989	* Saved state.
990	*/
991	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion /, sizeof(pThis), picR3SaveExec, picR3LoadExec);
992	AssertRCReturn(rc, rc);
993
994	/*
995	* Register the info item.
996	*/
997	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picR3Info);
998
999	/*
1000	* Initialize the device state.
1001	*/
1002	picR3Reset(pDevIns);
1003
1004	# ifdef VBOX_WITH_STATISTICS
1005	/*
1006	* Statistics.
1007	*/
1008	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "SetIrqRZ", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in ring-0/raw-mode.");
1009	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "SetIrqR3", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in ring-3.");
1010
1011	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1012	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1013	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1014	# endif
1015
1016	return VINF_SUCCESS;
1017	}
1018
1019	#else /* !IN_RING3 */
1020
1021	/**
1022	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1023	*/
1024	static DECLCALLBACK(int) picRZConstruct(PPDMDEVINS pDevIns)
1025	{
1026	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1027	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
1028	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
1029
1030	/* NOP the critsect: */
1031	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1032	AssertRCReturn(rc, rc);
1033
1034	/* Set up the PIC callbacks: */
1035	PDMPICREG PicReg;
1036	PicReg.u32Version = PDM_PICREG_VERSION;
1037	PicReg.pfnSetIrq = picSetIrq;
1038	PicReg.pfnGetInterrupt = picGetInterrupt;
1039	PicReg.u32TheEnd = PDM_PICREG_VERSION;
1040	rc = PDMDevHlpPICSetUpContext(pDevIns, &PicReg, &pThisCC->pPicHlp);
1041	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpPICSetUpContext -> %Rrc\n", rc), rc);
1042	AssertPtrReturn(pThisCC->pPicHlp, VERR_INTERNAL_ERROR_3);
1043	AssertReturn(pThisCC->pPicHlp->u32Version == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
1044	AssertReturn(pThisCC->pPicHlp->u32TheEnd == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
1045
1046	/* I/O port callbacks: */
1047	Assert(RT_ELEMENTS(pThis->aPics) == 2);
1048	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[0].hIoPorts0, picIOPortWrite, picIOPortRead, (void *)0);
1049	AssertRCReturn(rc, rc);
1050	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[1].hIoPorts0, picIOPortWrite, picIOPortRead, (void *)1);
1051	AssertRCReturn(rc, rc);
1052
1053	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[0].hIoPorts1, picIOPortElcrWrite, picIOPortElcrRead, &pThis->aPics[0]);
1054	AssertRCReturn(rc, rc);
1055	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[1].hIoPorts1, picIOPortElcrWrite, picIOPortElcrRead, &pThis->aPics[1]);
1056	AssertRCReturn(rc, rc);
1057
1058	return VINF_SUCCESS;
1059	}
1060
1061	#endif /* !IN_RING3 */
1062
1063	/**
1064	* The device registration structure.
1065	*/
1066	const PDMDEVREG g_DeviceI8259 =
1067	{
1068	/* .u32Version = */ PDM_DEVREG_VERSION,
1069	/* .uReserved0 = */ 0,
1070	/* .szName = */ "i8259",
1071	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1072	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1073	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1074	/* .cMaxInstances = */ 1,
1075	/* .uSharedVersion = */ 42,
1076	/* .cbInstanceShared = */ sizeof(DEVPIC),
1077	/* .cbInstanceCC = */ sizeof(DEVPICCC),
1078	/* .cbInstanceRC = */ sizeof(DEVPICRC),
1079	/* .cMaxPciDevices = */ 0,
1080	/* .cMaxMsixVectors = */ 0,
1081	/* .pszDescription = */ "Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1082	#if defined(IN_RING3)
1083	/* .pszRCMod = */ "VBoxDDRC.rc",
1084	/* .pszR0Mod = */ "VBoxDDR0.r0",
1085	/* .pfnConstruct = */ picR3Construct,
1086	/* .pfnDestruct = */ NULL,
1087	/* .pfnRelocate = */ picR3Relocate,
1088	/* .pfnMemSetup = */ NULL,
1089	/* .pfnPowerOn = */ NULL,
1090	/* .pfnReset = */ picR3Reset,
1091	/* .pfnSuspend = */ NULL,
1092	/* .pfnResume = */ NULL,
1093	/* .pfnAttach = */ NULL,
1094	/* .pfnDetach = */ NULL,
1095	/* .pfnQueryInterface = */ NULL,
1096	/* .pfnInitComplete = */ NULL,
1097	/* .pfnPowerOff = */ NULL,
1098	/* .pfnSoftReset = */ NULL,
1099	/* .pfnReserved0 = */ NULL,
1100	/* .pfnReserved1 = */ NULL,
1101	/* .pfnReserved2 = */ NULL,
1102	/* .pfnReserved3 = */ NULL,
1103	/* .pfnReserved4 = */ NULL,
1104	/* .pfnReserved5 = */ NULL,
1105	/* .pfnReserved6 = */ NULL,
1106	/* .pfnReserved7 = */ NULL,
1107	#elif defined(IN_RING0)
1108	/* .pfnEarlyConstruct = */ NULL,
1109	/* .pfnConstruct = */ picRZConstruct,
1110	/* .pfnDestruct = */ NULL,
1111	/* .pfnFinalDestruct = */ NULL,
1112	/* .pfnRequest = */ NULL,
1113	/* .pfnReserved0 = */ NULL,
1114	/* .pfnReserved1 = */ NULL,
1115	/* .pfnReserved2 = */ NULL,
1116	/* .pfnReserved3 = */ NULL,
1117	/* .pfnReserved4 = */ NULL,
1118	/* .pfnReserved5 = */ NULL,
1119	/* .pfnReserved6 = */ NULL,
1120	/* .pfnReserved7 = */ NULL,
1121	#elif defined(IN_RC)
1122	/* .pfnConstruct = */ picRZConstruct,
1123	/* .pfnReserved0 = */ NULL,
1124	/* .pfnReserved1 = */ NULL,
1125	/* .pfnReserved2 = */ NULL,
1126	/* .pfnReserved3 = */ NULL,
1127	/* .pfnReserved4 = */ NULL,
1128	/* .pfnReserved5 = */ NULL,
1129	/* .pfnReserved6 = */ NULL,
1130	/* .pfnReserved7 = */ NULL,
1131	#else
1132	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1133	#endif
1134	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1135	};
1136
1137	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1138

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 105959

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