DevPIC.cpp@ 34714

Last change on this file since 34714 was 34697, checked in by vboxsync, 14 years ago
PIC: Clear IRR bit when edge triggered IRQ is deasserted.
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1	/* $Id: DevPIC.cpp 34697 2010-12-03 14:10:43Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PIC
22	#include <VBox/pdmdev.h>
23	#include <VBox/log.h>
24	#include <iprt/assert.h>
25	#include <iprt/string.h>
26
27	#include "../Builtins.h"
28
29
30	/*******************************************************************************
31	* Defined Constants And Macros *
32	*******************************************************************************/
33	/** @def PIC_LOCK
34	* Acquires the PDM lock. This is a NOP if locking is disabled. */
35	/** @def PIC_UNLOCK
36	* Releases the PDM lock. This is a NOP if locking is disabled. */
37	#define PIC_LOCK(pThis, rc) \
38	do { \
39	int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
40	if (rc2 != VINF_SUCCESS) \
41	return rc2; \
42	} while (0)
43	#define PIC_UNLOCK(pThis) \
44	(pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
45
46
47	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	RT_C_DECLS_BEGIN
52
53	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
54	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
55	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
56	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
57	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
58	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
59
60	RT_C_DECLS_END
61	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
62
63
64	/*
65	* QEMU 8259 interrupt controller emulation
66	*
67	* Copyright (c) 2003-2004 Fabrice Bellard
68	*
69	* Permission is hereby granted, free of charge, to any person obtaining a copy
70	* of this software and associated documentation files (the "Software"), to deal
71	* in the Software without restriction, including without limitation the rights
72	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
73	* copies of the Software, and to permit persons to whom the Software is
74	* furnished to do so, subject to the following conditions:
75	*
76	* The above copyright notice and this permission notice shall be included in
77	* all copies or substantial portions of the Software.
78	*
79	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
80	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
81	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
82	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
83	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
84	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
85	* THE SOFTWARE.
86	*/
87
88	/* debug PIC */
89	#define DEBUG_PIC
90
91	/#define DEBUG_IRQ_COUNT/
92
93	typedef struct PicState {
94	uint8_t last_irr; /* edge detection */
95	uint8_t irr; /* interrupt request register */
96	uint8_t imr; /* interrupt mask register */
97	uint8_t isr; /* interrupt service register */
98	uint8_t priority_add; /* highest irq priority */
99	uint8_t irq_base;
100	uint8_t read_reg_select;
101	uint8_t poll;
102	uint8_t special_mask;
103	uint8_t init_state;
104	uint8_t auto_eoi;
105	uint8_t rotate_on_auto_eoi;
106	uint8_t special_fully_nested_mode;
107	uint8_t init4; /* true if 4 byte init */
108	uint8_t elcr; /* PIIX edge/trigger selection*/
109	uint8_t elcr_mask;
110	/** Pointer to the device instance, R3 Ptr. */
111	PPDMDEVINSR3 pDevInsR3;
112	/** Pointer to the device instance, R0 Ptr. */
113	PPDMDEVINSR0 pDevInsR0;
114	/** Pointer to the device instance, RC Ptr. */
115	PPDMDEVINSRC pDevInsRC;
116	RTRCPTR Alignment0; /*< Structure size alignment. /
117	} PicState;
118
119	/**
120	* A PIC device instance data.
121	*/
122	typedef struct DEVPIC
123	{
124	/** The two interrupt controllers. */
125	PicState aPics[2];
126	/** Pointer to the device instance - R3 Ptr. */
127	PPDMDEVINSR3 pDevInsR3;
128	/** Pointer to the PIC R3 helpers. */
129	PCPDMPICHLPR3 pPicHlpR3;
130	/** Pointer to the device instance - R0 Ptr. */
131	PPDMDEVINSR0 pDevInsR0;
132	/** Pointer to the PIC R0 helpers. */
133	PCPDMPICHLPR0 pPicHlpR0;
134	/** Pointer to the device instance - RC Ptr. */
135	PPDMDEVINSRC pDevInsRC;
136	/** Pointer to the PIC RC helpers. */
137	PCPDMPICHLPRC pPicHlpRC;
138	#ifdef VBOX_WITH_STATISTICS
139	STAMCOUNTER StatSetIrqGC;
140	STAMCOUNTER StatSetIrqHC;
141	STAMCOUNTER StatClearedActiveIRQ2;
142	STAMCOUNTER StatClearedActiveMasterIRQ;
143	STAMCOUNTER StatClearedActiveSlaveIRQ;
144	#endif
145	} DEVPIC, *PDEVPIC;
146
147
148	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
149	#ifdef LOG_ENABLED
150	static inline void DumpPICState(PicState s, const char szFn)
151	{
152	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
153
154	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
155	szFn, (&pThis->aPics[0] == s) ? 0 : 1,
156	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
157	}
158	#else
159	# define DumpPICState(pThis, szFn) do { } while (0)
160	#endif
161
162	/* set irq level. If an edge is detected, then the IRR is set to 1 */
163	static inline void pic_set_irq1(PicState *s, int irq, int level)
164	{
165	int mask;
166	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
167	mask = 1 << irq;
168	if (s->elcr & mask) {
169	/* level triggered */
170	if (level) {
171	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", s->irr, s->irr \| mask));
172	s->irr \|= mask;
173	s->last_irr \|= mask;
174	} else {
175	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", s->irr, s->irr & ~mask));
176	s->irr &= ~mask;
177	s->last_irr &= ~mask;
178	}
179	} else {
180	/* edge triggered */
181	if (level) {
182	if ((s->last_irr & mask) == 0)
183	{
184	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
185	s->irr \|= mask;
186	}
187	s->last_irr \|= mask;
188	} else {
189	s->irr &= ~mask;
190	s->last_irr &= ~mask;
191	}
192	}
193	DumpPICState(s, "pic_set_irq1");
194	}
195
196	/* return the highest priority found in mask (highest = smallest
197	number). Return 8 if no irq */
198	static inline int get_priority(PicState *s, int mask)
199	{
200	int priority;
201	if (mask == 0)
202	return 8;
203	priority = 0;
204	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
205	priority++;
206	return priority;
207	}
208
209	/* return the pic wanted interrupt. return -1 if none */
210	static int pic_get_irq(PicState *s)
211	{
212	PicState *pics = &(PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC))->aPics[0];
213	int mask, cur_priority, priority;
214	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
215	DumpPICState(s, "pic_get_irq");
216
217	mask = s->irr & ~s->imr;
218	priority = get_priority(s, mask);
219	Log(("pic_get_irq: priority=%x\n", priority));
220	if (priority == 8)
221	return -1;
222	/* compute current priority. If special fully nested mode on the
223	master, the IRQ coming from the slave is not taken into account
224	for the priority computation. */
225	mask = s->isr;
226	if (s->special_fully_nested_mode && s == &pics[0])
227	mask &= ~(1 << 2);
228	cur_priority = get_priority(s, mask);
229	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
230	if (priority < cur_priority) {
231	/* higher priority found: an irq should be generated */
232	return (priority + s->priority_add) & 7;
233	} else {
234	return -1;
235	}
236	}
237
238	/* raise irq to CPU if necessary. must be called every time the active
239	irq may change */
240	static int pic_update_irq(PDEVPIC pThis)
241	{
242	PicState *pics = &pThis->aPics[0];
243	int irq2, irq;
244
245	/* first look at slave pic */
246	irq2 = pic_get_irq(&pics[1]);
247	Log(("pic_update_irq irq2=%d\n", irq2));
248	if (irq2 >= 0) {
249	/* if irq request by slave pic, signal master PIC */
250	pic_set_irq1(&pics[0], 2, 1);
251	} else {
252	/* If not, clear the IR on the master PIC. */
253	pic_set_irq1(&pics[0], 2, 0);
254	}
255	/* look at requested irq */
256	irq = pic_get_irq(&pics[0]);
257	if (irq >= 0)
258	{
259	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
260	* spurious slave interrupts in picGetInterrupt.
261	*/
262	if (irq != 2 \|\| irq2 != -1)
263	{
264	#if defined(DEBUG_PIC)
265	int i;
266	for(i = 0; i < 2; i++) {
267	Log(("pic%d: imr=%x irr=%x padd=%d\n",
268	i, pics[i].imr, pics[i].irr,
269	pics[i].priority_add));
270	}
271	Log(("pic: cpu_interrupt\n"));
272	#endif
273	pThis->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pThis->CTX_SUFF(pDevIns));
274	}
275	else
276	{
277	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
278	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
279	/* Clear it here, so lower priority interrupts can still be dispatched. */
280
281	/* if this was the only pending irq, then we must clear the interrupt ff flag */
282	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
283
284	/** @note Is this correct? */
285	pics[0].irr &= ~(1 << 2);
286
287	/* Call ourselves again just in case other interrupts are pending */
288	return pic_update_irq(pThis);
289	}
290	}
291	else
292	{
293	Log(("pic_update_irq: no interrupt is pending!!\n"));
294
295	/* we must clear the interrupt ff flag */
296	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
297	}
298	return VINF_SUCCESS;
299	}
300
301	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
302	static void pic_update_imr(PDEVPIC pThis, PicState *s, uint8_t val)
303	{
304	int irq, intno;
305	PicState *pActivePIC;
306
307	/* Query the current pending irq, if any. */
308	pActivePIC = &pThis->aPics[0];
309	intno = irq = pic_get_irq(pActivePIC);
310	if (irq == 2)
311	{
312	pActivePIC = &pThis->aPics[1];
313	irq = pic_get_irq(pActivePIC);
314	intno = irq + 8;
315	}
316
317	/* Update IMR */
318	s->imr = val;
319
320	/* If an interrupt is pending and now masked, then clear the FF flag. */
321	if ( irq >= 0
322	&& ((1 << irq) & ~pActivePIC->imr) == 0)
323	{
324	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
325	pThis->aPics[0].elcr, pThis->aPics[0].last_irr, pThis->aPics[0].irr, pThis->aPics[0].imr, pThis->aPics[0].isr, pThis->aPics[0].irq_base));
326	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
327	pThis->aPics[1].elcr, pThis->aPics[1].last_irr, pThis->aPics[1].irr, pThis->aPics[1].imr, pThis->aPics[1].isr, pThis->aPics[1].irq_base));
328
329	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
330	/** @todo Is this correct? */
331	if (intno > 7)
332	{
333	pThis->aPics[0].irr &= ~(1 << 2);
334	STAM_COUNTER_INC(&pThis->StatClearedActiveSlaveIRQ);
335	}
336	else
337	STAM_COUNTER_INC(&pThis->StatClearedActiveMasterIRQ);
338
339	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
340	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
341	}
342	}
343
344
345	/**
346	* Set the an IRQ.
347	*
348	* @param pDevIns Device instance of the PICs.
349	* @param iIrq IRQ number to set.
350	* @param iLevel IRQ level.
351	*/
352	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
353	{
354	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
355	Assert(pThis->CTX_SUFF(pDevIns) == pDevIns);
356	Assert(pThis->aPics[0].CTX_SUFF(pDevIns) == pDevIns);
357	Assert(pThis->aPics[1].CTX_SUFF(pDevIns) == pDevIns);
358	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
359
360	Log(("picSetIrq %d %d\n", iIrq, iLevel));
361	DumpPICState(&pThis->aPics[0], "picSetIrq");
362	DumpPICState(&pThis->aPics[1], "picSetIrq");
363	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
364	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
365	{
366	/* A flip-flop lowers the IRQ line and immediately raises it, so
367	* that a rising edge is guaranteed to occur. Note that the IRQ
368	* line must be held high for a while to avoid spurious interrupts.
369	*/
370	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0);
371	pic_update_irq(pThis);
372	}
373	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
374	pic_update_irq(pThis);
375	}
376
377
378	/* acknowledge interrupt 'irq' */
379	static inline void pic_intack(PicState *s, int irq)
380	{
381	if (s->auto_eoi) {
382	if (s->rotate_on_auto_eoi)
383	s->priority_add = (irq + 1) & 7;
384	} else {
385	s->isr \|= (1 << irq);
386	}
387	/* We don't clear a level sensitive interrupt here */
388	if (!(s->elcr & (1 << irq)))
389	{
390	Log2(("pic_intack: irr=%x irrnew=%x\n", s->irr, s->irr & ~(1 << irq)));
391	s->irr &= ~(1 << irq);
392	}
393	}
394
395
396	/**
397	* Get a pending interrupt.
398	*
399	* @returns Pending interrupt number.
400	* @param pDevIns Device instance of the PICs.
401	*/
402	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
403	{
404	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
405	int irq;
406	int irq2;
407	int intno;
408
409	/* read the irq from the PIC */
410	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
411	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
412
413	irq = pic_get_irq(&pThis->aPics[0]);
414	if (irq >= 0)
415	{
416	pic_intack(&pThis->aPics[0], irq);
417	if (irq == 2)
418	{
419	irq2 = pic_get_irq(&pThis->aPics[1]);
420	if (irq2 >= 0) {
421	pic_intack(&pThis->aPics[1], irq2);
422	}
423	else
424	{
425	/* spurious IRQ on slave controller (impossible) */
426	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
427	irq2 = 7;
428	}
429	intno = pThis->aPics[1].irq_base + irq2;
430	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pThis->aPics[1].irq_base, irq2));
431	irq = irq2 + 8;
432	}
433	else {
434	intno = pThis->aPics[0].irq_base + irq;
435	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pThis->aPics[0].irq_base, irq));
436	}
437	}
438	else
439	{
440	/* spurious IRQ on host controller (impossible) */
441	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
442	irq = 7;
443	intno = pThis->aPics[0].irq_base + irq;
444	}
445	pic_update_irq(pThis);
446
447	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
448
449	return intno;
450	}
451
452	static void pic_reset(PicState *s)
453	{
454	PPDMDEVINSR3 pDevInsR3 = s->pDevInsR3;
455	PPDMDEVINSR0 pDevInsR0 = s->pDevInsR0;
456	PPDMDEVINSRC pDevInsRC = s->pDevInsRC;
457	int elcr_mask = s->elcr_mask;
458	int elcr = s->elcr;
459
460	memset(s, 0, sizeof(PicState));
461
462	s->elcr = elcr;
463	s->elcr_mask = elcr_mask;
464	s->pDevInsRC = pDevInsRC;
465	s->pDevInsR0 = pDevInsR0;
466	s->pDevInsR3 = pDevInsR3;
467	}
468
469
470	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
471	{
472	PicState s = (PicState)opaque;
473	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
474	int rc = VINF_SUCCESS;
475	int priority, cmd, irq;
476
477	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
478	addr &= 1;
479	if (addr == 0) {
480	if (val & 0x10) {
481	/* init */
482	pic_reset(s);
483	/* deassert a pending interrupt */
484	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
485
486	s->init_state = 1;
487	s->init4 = val & 1;
488	if (val & 0x02)
489	AssertReleaseMsgFailed(("single mode not supported"));
490	if (val & 0x08)
491	AssertReleaseMsgFailed(("level sensitive irq not supported"));
492	} else if (val & 0x08) {
493	if (val & 0x04)
494	s->poll = 1;
495	if (val & 0x02)
496	s->read_reg_select = val & 1;
497	if (val & 0x40)
498	s->special_mask = (val >> 5) & 1;
499	} else {
500	cmd = val >> 5;
501	switch(cmd) {
502	case 0:
503	case 4:
504	s->rotate_on_auto_eoi = cmd >> 2;
505	break;
506	case 1: /* end of interrupt */
507	case 5:
508	{
509	priority = get_priority(s, s->isr);
510	if (priority != 8) {
511	irq = (priority + s->priority_add) & 7;
512	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
513	s->isr &= ~(1 << irq);
514	if (cmd == 5)
515	s->priority_add = (irq + 1) & 7;
516	rc = pic_update_irq(pThis);
517	Assert(rc == VINF_SUCCESS);
518	DumpPICState(s, "eoi");
519	}
520	break;
521	}
522	case 3:
523	{
524	irq = val & 7;
525	Log(("pic_write: EOI2 for irq %d\n", irq));
526	s->isr &= ~(1 << irq);
527	rc = pic_update_irq(pThis);
528	Assert(rc == VINF_SUCCESS);
529	DumpPICState(s, "eoi2");
530	break;
531	}
532	case 6:
533	{
534	s->priority_add = (val + 1) & 7;
535	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, s->priority_add));
536	rc = pic_update_irq(pThis);
537	Assert(rc == VINF_SUCCESS);
538	break;
539	}
540	case 7:
541	{
542	irq = val & 7;
543	Log(("pic_write: EOI3 for irq %d\n", irq));
544	s->isr &= ~(1 << irq);
545	s->priority_add = (irq + 1) & 7;
546	rc = pic_update_irq(pThis);
547	Assert(rc == VINF_SUCCESS);
548	DumpPICState(s, "eoi3");
549	break;
550	}
551	default:
552	/* no operation */
553	break;
554	}
555	}
556	} else {
557	switch(s->init_state) {
558	case 0:
559	{
560	/* normal mode */
561	pic_update_imr(pThis, s, val);
562
563	rc = pic_update_irq(pThis);
564	Assert(rc == VINF_SUCCESS);
565	break;
566	}
567	case 1:
568	s->irq_base = val & 0xf8;
569	s->init_state = 2;
570	Log(("pic_write: set irq base to %x\n", s->irq_base));
571	break;
572	case 2:
573	if (s->init4) {
574	s->init_state = 3;
575	} else {
576	s->init_state = 0;
577	}
578	break;
579	case 3:
580	s->special_fully_nested_mode = (val >> 4) & 1;
581	s->auto_eoi = (val >> 1) & 1;
582	s->init_state = 0;
583	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
584	break;
585	}
586	}
587	return rc;
588	}
589
590
591	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
592	{
593	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
594	PicState *pics = &pThis->aPics[0];
595	int ret;
596
597	ret = pic_get_irq(s);
598	if (ret >= 0) {
599	if (addr1 >> 7) {
600	Log2(("pic_poll_read: clear slave irq (isr)\n"));
601	pics[0].isr &= ~(1 << 2);
602	pics[0].irr &= ~(1 << 2);
603	}
604	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
605	s->irr &= ~(1 << ret);
606	s->isr &= ~(1 << ret);
607	if (addr1 >> 7 \|\| ret != 2)
608	pic_update_irq(pThis);
609	} else {
610	ret = 0x07;
611	pic_update_irq(pThis);
612	}
613
614	return ret;
615	}
616
617
618	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
619	{
620	PicState s = (PicState)opaque;
621	unsigned int addr;
622	int ret;
623
624	*pRC = VINF_SUCCESS;
625
626	addr = addr1;
627	addr &= 1;
628	if (s->poll) {
629	ret = pic_poll_read(s, addr1);
630	s->poll = 0;
631	} else {
632	if (addr == 0) {
633	if (s->read_reg_select)
634	ret = s->isr;
635	else
636	ret = s->irr;
637	} else {
638	ret = s->imr;
639	}
640	}
641	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
642	return ret;
643	}
644
645
646
647	/* -=-=-=-=-=- wrappers / stuff -=-=-=-=-=- */
648
649	/**
650	* Port I/O Handler for IN operations.
651	*
652	* @returns VBox status code.
653	*
654	* @param pDevIns The device instance.
655	* @param pvUser User argument - pointer to the PIC in question.
656	* @param uPort Port number used for the IN operation.
657	* @param pu32 Where to store the result.
658	* @param cb Number of bytes read.
659	*/
660	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
661	{
662	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
663	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
664
665	Assert(iPic == 0 \|\| iPic == 1);
666	if (cb == 1)
667	{
668	int rc;
669	PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_READ);
670	*pu32 = pic_ioport_read(&pThis->aPics[iPic], Port, &rc);
671	PIC_UNLOCK(pThis);
672	return rc;
673	}
674	return VERR_IOM_IOPORT_UNUSED;
675	}
676
677	/**
678	* Port I/O Handler for OUT operations.
679	*
680	* @returns VBox status code.
681	*
682	* @param pDevIns The device instance.
683	* @param pvUser User argument - pointer to the PIC in question.
684	* @param uPort Port number used for the IN operation.
685	* @param u32 The value to output.
686	* @param cb The value size in bytes.
687	*/
688	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
689	{
690	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
691	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
692
693	Assert(iPic == 0 \|\| iPic == 1);
694
695	if (cb == 1)
696	{
697	int rc;
698	PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_WRITE);
699	rc = pic_ioport_write(&pThis->aPics[iPic], Port, u32);
700	PIC_UNLOCK(pThis);
701	return rc;
702	}
703	return VINF_SUCCESS;
704	}
705
706
707	/**
708	* Port I/O Handler for IN operations.
709	*
710	* @returns VBox status code.
711	*
712	* @param pDevIns The device instance.
713	* @param pvUser User argument - pointer to the PIC in question.
714	* @param uPort Port number used for the IN operation.
715	* @param pu32 Where to store the result.
716	* @param cb Number of bytes read.
717	*/
718	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
719	{
720	if (cb == 1)
721	{
722	PicState s = (PicState)pvUser;
723	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
724	*pu32 = s->elcr;
725	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
726	return VINF_SUCCESS;
727	}
728	return VERR_IOM_IOPORT_UNUSED;
729	}
730
731	/**
732	* Port I/O Handler for OUT operations.
733	*
734	* @returns VBox status code.
735	*
736	* @param pDevIns The device instance.
737	* @param pvUser User argument - pointer to the PIC in question.
738	* @param uPort Port number used for the IN operation.
739	* @param u32 The value to output.
740	* @param cb The value size in bytes.
741	*/
742	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
743	{
744	if (cb == 1)
745	{
746	PicState s = (PicState)pvUser;
747	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
748	s->elcr = u32 & s->elcr_mask;
749	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
750	}
751	return VINF_SUCCESS;
752	}
753
754
755	#ifdef IN_RING3
756
757	/**
758	* PIC status info callback.
759	*
760	* @param pDevIns The device instance.
761	* @param pHlp The output helpers.
762	* @param pszArgs The arguments.
763	*/
764	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
765	{
766	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
767
768	/*
769	* Show info.
770	*/
771	for (int i=0;i<2;i++)
772	{
773	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
774	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pThis->aPics[i].last_irr);
775	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pThis->aPics[i].irr);
776	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pThis->aPics[i].imr);
777	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pThis->aPics[i].isr);
778	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pThis->aPics[i].priority_add);
779	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pThis->aPics[i].irq_base);
780	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pThis->aPics[i].read_reg_select);
781	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pThis->aPics[i].poll);
782	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pThis->aPics[i].special_mask);
783	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pThis->aPics[i].init_state);
784	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pThis->aPics[i].auto_eoi);
785	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pThis->aPics[i].rotate_on_auto_eoi);
786	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pThis->aPics[i].special_fully_nested_mode);
787	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pThis->aPics[i].init4);
788	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pThis->aPics[i].elcr);
789	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pThis->aPics[i].elcr_mask);
790	}
791	}
792
793	/**
794	* Saves a state of the programmable interrupt controller device.
795	*
796	* @returns VBox status code.
797	* @param pDevIns The device instance.
798	* @param pSSMHandle The handle to save the state to.
799	*/
800	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
801	{
802	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
803	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
804	{
805	SSMR3PutU8(pSSMHandle, pThis->aPics[i].last_irr);
806	SSMR3PutU8(pSSMHandle, pThis->aPics[i].irr);
807	SSMR3PutU8(pSSMHandle, pThis->aPics[i].imr);
808	SSMR3PutU8(pSSMHandle, pThis->aPics[i].isr);
809	SSMR3PutU8(pSSMHandle, pThis->aPics[i].priority_add);
810	SSMR3PutU8(pSSMHandle, pThis->aPics[i].irq_base);
811	SSMR3PutU8(pSSMHandle, pThis->aPics[i].read_reg_select);
812	SSMR3PutU8(pSSMHandle, pThis->aPics[i].poll);
813	SSMR3PutU8(pSSMHandle, pThis->aPics[i].special_mask);
814	SSMR3PutU8(pSSMHandle, pThis->aPics[i].init_state);
815	SSMR3PutU8(pSSMHandle, pThis->aPics[i].auto_eoi);
816	SSMR3PutU8(pSSMHandle, pThis->aPics[i].rotate_on_auto_eoi);
817	SSMR3PutU8(pSSMHandle, pThis->aPics[i].special_fully_nested_mode);
818	SSMR3PutU8(pSSMHandle, pThis->aPics[i].init4);
819	SSMR3PutU8(pSSMHandle, pThis->aPics[i].elcr);
820	}
821	return VINF_SUCCESS;
822	}
823
824
825	/**
826	* Loads a saved programmable interrupt controller device state.
827	*
828	* @returns VBox status code.
829	* @param pDevIns The device instance.
830	* @param pSSMHandle The handle to the saved state.
831	* @param uVersion The data unit version number.
832	* @param uPass The data pass.
833	*/
834	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
835	{
836	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
837
838	if (uVersion != 1)
839	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
840	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
841
842	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
843	{
844	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].last_irr);
845	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].irr);
846	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].imr);
847	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].isr);
848	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].priority_add);
849	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].irq_base);
850	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].read_reg_select);
851	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].poll);
852	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].special_mask);
853	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].init_state);
854	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].auto_eoi);
855	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].rotate_on_auto_eoi);
856	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].special_fully_nested_mode);
857	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].init4);
858	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].elcr);
859	}
860	return VINF_SUCCESS;
861	}
862
863
864	/* -=-=-=-=-=- real code -=-=-=-=-=- */
865
866	/**
867	* Reset notification.
868	*
869	* @returns VBox status.
870	* @param pDevIns The device instance data.
871	*/
872	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
873	{
874	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
875	unsigned i;
876	LogFlow(("picReset:\n"));
877	pThis->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
878
879	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
880	pic_reset(&pThis->aPics[i]);
881
882	PIC_UNLOCK(pThis);
883	}
884
885
886	/**
887	* @copydoc FNPDMDEVRELOCATE
888	*/
889	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
890	{
891	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
892	unsigned i;
893
894	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
895	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
896	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
897	pThis->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
898	}
899
900
901	/**
902	* @copydoc FNPDMDEVCONSTRUCT
903	*/
904	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
905	{
906	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
907	PDMPICREG PicReg;
908	int rc;
909	bool fGCEnabled;
910	bool fR0Enabled;
911	Assert(iInstance == 0);
912
913	/*
914	* Validate and read configuration.
915	*/
916	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
917	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
918
919	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
920	if (RT_FAILURE(rc))
921	return PDMDEV_SET_ERROR(pDevIns, rc,
922	N_("Configuration error: failed to read GCEnabled as boolean"));
923
924	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
925	if (RT_FAILURE(rc))
926	return PDMDEV_SET_ERROR(pDevIns, rc,
927	N_("Configuration error: failed to read R0Enabled as boolean"));
928
929	Log(("DevPIC: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
930
931	/*
932	* Init the data.
933	*/
934	Assert(RT_ELEMENTS(pThis->aPics) == 2);
935	pThis->pDevInsR3 = pDevIns;
936	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
937	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
938	pThis->aPics[0].elcr_mask = 0xf8;
939	pThis->aPics[1].elcr_mask = 0xde;
940	pThis->aPics[0].pDevInsR3 = pDevIns;
941	pThis->aPics[1].pDevInsR3 = pDevIns;
942	pThis->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
943	pThis->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
944	pThis->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
945	pThis->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
946
947	/*
948	* Register us as the PIC with PDM.
949	*/
950	PicReg.u32Version = PDM_PICREG_VERSION;
951	PicReg.pfnSetIrqR3 = picSetIrq;
952	PicReg.pfnGetInterruptR3 = picGetInterrupt;
953
954	if (fGCEnabled)
955	{
956	PicReg.pszSetIrqRC = "picSetIrq";
957	PicReg.pszGetInterruptRC = "picGetInterrupt";
958	}
959	else
960	{
961	PicReg.pszSetIrqRC = NULL;
962	PicReg.pszGetInterruptRC = NULL;
963	}
964
965	if (fR0Enabled)
966	{
967	PicReg.pszSetIrqR0 = "picSetIrq";
968	PicReg.pszGetInterruptR0 = "picGetInterrupt";
969	}
970	else
971	{
972	PicReg.pszSetIrqR0 = NULL;
973	PicReg.pszGetInterruptR0 = NULL;
974	}
975
976	rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThis->pPicHlpR3);
977	AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Rrc\n", rc), rc);
978	if (fGCEnabled)
979	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
980	if (fR0Enabled)
981	pThis->pPicHlpR0 = pThis->pPicHlpR3->pfnGetR0Helpers(pDevIns);
982
983
984	/*
985	* Register I/O ports and save state.
986	*/
987	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
988	if (RT_FAILURE(rc))
989	return rc;
990	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
991	if (RT_FAILURE(rc))
992	return rc;
993	if (fGCEnabled)
994	{
995	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
996	if (RT_FAILURE(rc))
997	return rc;
998	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
999	if (RT_FAILURE(rc))
1000	return rc;
1001	}
1002	if (fR0Enabled)
1003	{
1004	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1005	if (RT_FAILURE(rc))
1006	return rc;
1007	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1008	if (RT_FAILURE(rc))
1009	return rc;
1010	}
1011
1012	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pThis->aPics[0],
1013	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1014	if (RT_FAILURE(rc))
1015	return rc;
1016	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pThis->aPics[1],
1017	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1018	if (RT_FAILURE(rc))
1019	return rc;
1020	if (fGCEnabled)
1021	{
1022	RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns);
1023	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),
1024	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1025	if (RT_FAILURE(rc))
1026	return rc;
1027	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),
1028	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1029	if (RT_FAILURE(rc))
1030	return rc;
1031	}
1032	if (fR0Enabled)
1033	{
1034	RTR0PTR pDataR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1035	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1036	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1037	if (RT_FAILURE(rc))
1038	return rc;
1039	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1040	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1041	if (RT_FAILURE(rc))
1042	return rc;
1043	}
1044
1045	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion /, sizeof(pThis), picSaveExec, picLoadExec);
1046	if (RT_FAILURE(rc))
1047	return rc;
1048
1049
1050	/*
1051	* Register the info item.
1052	*/
1053	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1054
1055	/*
1056	* Initialize the device state.
1057	*/
1058	picReset(pDevIns);
1059
1060	#ifdef VBOX_WITH_STATISTICS
1061	/*
1062	* Statistics.
1063	*/
1064	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1065	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1066
1067	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1068	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1069	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1070	#endif
1071
1072	return VINF_SUCCESS;
1073	}
1074
1075
1076	/**
1077	* The device registration structure.
1078	*/
1079	const PDMDEVREG g_DeviceI8259 =
1080	{
1081	/* u32Version */
1082	PDM_DEVREG_VERSION,
1083	/* szName */
1084	"i8259",
1085	/* szRCMod */
1086	"VBoxDDGC.gc",
1087	/* szR0Mod */
1088	"VBoxDDR0.r0",
1089	/* pszDescription */
1090	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1091	/* fFlags */
1092	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1093	/* fClass */
1094	PDM_DEVREG_CLASS_PIC,
1095	/* cMaxInstances */
1096	1,
1097	/* cbInstance */
1098	sizeof(DEVPIC),
1099	/* pfnConstruct */
1100	picConstruct,
1101	/* pfnDestruct */
1102	NULL,
1103	/* pfnRelocate */
1104	picRelocate,
1105	/* pfnIOCtl */
1106	NULL,
1107	/* pfnPowerOn */
1108	NULL,
1109	/* pfnReset */
1110	picReset,
1111	/* pfnSuspend */
1112	NULL,
1113	/* pfnResume */
1114	NULL,
1115	/* pfnAttach */
1116	NULL,
1117	/* pfnDetach */
1118	NULL,
1119	/* pfnQueryInterface. */
1120	NULL,
1121	/* pfnInitComplete */
1122	NULL,
1123	/* pfnPowerOff */
1124	NULL,
1125	/* pfnSoftReset */
1126	NULL,
1127	/* u32VersionEnd */
1128	PDM_DEVREG_VERSION
1129	};
1130
1131	#endif /* IN_RING3 */
1132	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1133

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 34714

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