DevPIC.cpp@ 10485

Last change on this file since 10485 was 10202, checked in by vboxsync, 16 years ago
removed VBOX_WITH_PDM_LOCK
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 37.2 KB

Line
1	/* $Id: DevPIC.cpp 10202 2008-07-04 07:25:27Z vboxsync $ */
2	/** @file
3	* Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PIC
26	#include <VBox/pdmdev.h>
27	#include <VBox/log.h>
28	#include <iprt/assert.h>
29
30	#include "vl_vbox.h"
31
32
33	/*******************************************************************************
34	* Defined Constants And Macros *
35	*******************************************************************************/
36	/** @def PIC_LOCK
37	* Acquires the PDM lock. This is a NOP if locking is disabled. */
38	/** @def PIC_UNLOCK
39	* Releases the PDM lock. This is a NOP if locking is disabled. */
40	#define PIC_LOCK(pThis, rc) \
41	do { \
42	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
43	if (rc2 != VINF_SUCCESS) \
44	return rc2; \
45	} while (0)
46	#define PIC_UNLOCK(pThis) \
47	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
48
49
50	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
51	/*******************************************************************************
52	* Internal Functions *
53	*******************************************************************************/
54	__BEGIN_DECLS
55
56	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
57	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
58	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
59	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
60	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
61	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
62
63	__END_DECLS
64	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
65
66
67	/*
68	* QEMU 8259 interrupt controller emulation
69	*
70	* Copyright (c) 2003-2004 Fabrice Bellard
71	*
72	* Permission is hereby granted, free of charge, to any person obtaining a copy
73	* of this software and associated documentation files (the "Software"), to deal
74	* in the Software without restriction, including without limitation the rights
75	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
76	* copies of the Software, and to permit persons to whom the Software is
77	* furnished to do so, subject to the following conditions:
78	*
79	* The above copyright notice and this permission notice shall be included in
80	* all copies or substantial portions of the Software.
81	*
82	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
83	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
84	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
85	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
86	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
87	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
88	* THE SOFTWARE.
89	*/
90
91	/* debug PIC */
92	#define DEBUG_PIC
93
94	/#define DEBUG_IRQ_COUNT/
95
96	typedef struct PicState {
97	uint8_t last_irr; /* edge detection */
98	uint8_t irr; /* interrupt request register */
99	uint8_t imr; /* interrupt mask register */
100	uint8_t isr; /* interrupt service register */
101	uint8_t priority_add; /* highest irq priority */
102	uint8_t irq_base;
103	uint8_t read_reg_select;
104	uint8_t poll;
105	uint8_t special_mask;
106	uint8_t init_state;
107	uint8_t auto_eoi;
108	uint8_t rotate_on_auto_eoi;
109	uint8_t special_fully_nested_mode;
110	uint8_t init4; /* true if 4 byte init */
111	uint8_t elcr; /* PIIX edge/trigger selection*/
112	uint8_t elcr_mask;
113	/** Pointer to the device instance, HCPtr. */
114	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;
115	/** Pointer to the device instance, GCPtr. */
116	RCPTRTYPE(PPDMDEVINS) pDevInsGC;
117	#if HC_ARCH_BITS == 64
118	RTRCPTR Alignment0;
119	#endif
120	} PicState;
121
122	/**
123	* A PIC device instance data.
124	*/
125	typedef struct DEVPIC
126	{
127	/** The two interrupt controllers. */
128	PicState aPics[2];
129	/** Pointer to the PIC R3 helpers. */
130	PCPDMPICHLPR3 pPicHlpR3;
131	/** Pointer to the PIC R0 helpers. */
132	PCPDMPICHLPR0 pPicHlpR0;
133	/** Pointer to the PIC GC helpers. */
134	PCPDMPICHLPGC pPicHlpGC;
135	#if HC_ARCH_BITS == 32
136	uint32_t Alignmnet1;
137	#endif
138	/** Pointer to the device instance - GC Ptr. */
139	RCPTRTYPE(PPDMDEVINS) pDevInsGC;
140	/** Pointer to the device instance - GC Ptr. */
141	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;
142	#ifdef VBOX_WITH_STATISTICS
143	STAMCOUNTER StatSetIrqGC;
144	STAMCOUNTER StatSetIrqHC;
145	STAMCOUNTER StatClearedActiveIRQ2;
146	STAMCOUNTER StatClearedActiveMasterIRQ;
147	STAMCOUNTER StatClearedActiveSlaveIRQ;
148	#endif
149	} DEVPIC, *PDEVPIC;
150
151
152	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
153	#ifdef LOG_ENABLED
154	static inline void DumpPICState(PicState s, const char szFn)
155	{
156	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
157
158	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
159	szFn, (&pData->aPics[0] == s) ? 0 : 1,
160	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
161	}
162	#else
163	# define DumpPICState(pData, szFn) do { } while (0)
164	#endif
165
166	/* set irq level. If an edge is detected, then the IRR is set to 1 */
167	static inline void pic_set_irq1(PicState *s, int irq, int level)
168	{
169	int mask;
170	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
171	mask = 1 << irq;
172	if (s->elcr & mask) {
173	/* level triggered */
174	if (level) {
175	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", s->irr, s->irr \| mask));
176	s->irr \|= mask;
177	s->last_irr \|= mask;
178	} else {
179	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", s->irr, s->irr & ~mask));
180	s->irr &= ~mask;
181	s->last_irr &= ~mask;
182	}
183	} else {
184	/* edge triggered */
185	if (level) {
186	if ((s->last_irr & mask) == 0)
187	{
188	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
189	s->irr \|= mask;
190	}
191	s->last_irr \|= mask;
192	} else {
193	s->last_irr &= ~mask;
194	}
195	}
196	DumpPICState(s, "pic_set_irq1");
197	}
198
199	/* return the highest priority found in mask (highest = smallest
200	number). Return 8 if no irq */
201	static inline int get_priority(PicState *s, int mask)
202	{
203	int priority;
204	if (mask == 0)
205	return 8;
206	priority = 0;
207	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
208	priority++;
209	return priority;
210	}
211
212	/* return the pic wanted interrupt. return -1 if none */
213	static int pic_get_irq(PicState *s)
214	{
215	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
216	int mask, cur_priority, priority;
217	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
218	DumpPICState(s, "pic_get_irq");
219
220	mask = s->irr & ~s->imr;
221	priority = get_priority(s, mask);
222	Log(("pic_get_irq: priority=%x\n", priority));
223	if (priority == 8)
224	return -1;
225	/* compute current priority. If special fully nested mode on the
226	master, the IRQ coming from the slave is not taken into account
227	for the priority computation. */
228	mask = s->isr;
229	if (s->special_fully_nested_mode && s == &pics[0])
230	mask &= ~(1 << 2);
231	cur_priority = get_priority(s, mask);
232	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
233	if (priority < cur_priority) {
234	/* higher priority found: an irq should be generated */
235	return (priority + s->priority_add) & 7;
236	} else {
237	return -1;
238	}
239	}
240
241	/* raise irq to CPU if necessary. must be called every time the active
242	irq may change */
243	static int pic_update_irq(PDEVPIC pData)
244	{
245	PicState *pics = &pData->aPics[0];
246	int irq2, irq;
247
248	/* first look at slave pic */
249	irq2 = pic_get_irq(&pics[1]);
250	Log(("pic_update_irq irq2=%d\n", irq2));
251	if (irq2 >= 0) {
252	/* if irq request by slave pic, signal master PIC */
253	pic_set_irq1(&pics[0], 2, 1);
254	pic_set_irq1(&pics[0], 2, 0);
255	}
256	/* look at requested irq */
257	irq = pic_get_irq(&pics[0]);
258	if (irq >= 0)
259	{
260	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
261	* spurious slave interrupts in picGetInterrupt.
262	*/
263	if (irq != 2 \|\| irq2 != -1)
264	{
265	#if defined(DEBUG_PIC)
266	int i;
267	for(i = 0; i < 2; i++) {
268	Log(("pic%d: imr=%x irr=%x padd=%d\n",
269	i, pics[i].imr, pics[i].irr,
270	pics[i].priority_add));
271	}
272	Log(("pic: cpu_interrupt\n"));
273	#endif
274	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
275	}
276	else
277	{
278	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
279	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
280	/* Clear it here, so lower priority interrupts can still be dispatched. */
281
282	/* if this was the only pending irq, then we must clear the interrupt ff flag */
283	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
284
285	/** @note Is this correct? */
286	pics[0].irr &= ~(1 << 2);
287
288	/* Call ourselves again just in case other interrupts are pending */
289	return pic_update_irq(pData);
290	}
291	}
292	else
293	{
294	Log(("pic_update_irq: no interrupt is pending!!\n"));
295
296	/* we must clear the interrupt ff flag */
297	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
298	}
299	return VINF_SUCCESS;
300	}
301
302	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
303	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
304	{
305	int irq, intno;
306	PicState *pActivePIC;
307
308	/* Query the current pending irq, if any. */
309	pActivePIC = &pData->aPics[0];
310	intno = irq = pic_get_irq(pActivePIC);
311	if (irq == 2)
312	{
313	pActivePIC = &pData->aPics[1];
314	irq = pic_get_irq(pActivePIC);
315	intno = irq + 8;
316	}
317
318	/* Update IMR */
319	s->imr = val;
320
321	/* If an interrupt is pending and now masked, then clear the FF flag. */
322	if ( irq >= 0
323	&& ((1 << irq) & ~pActivePIC->imr) == 0)
324	{
325	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
326	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
327	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
328	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
329
330	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
331	/** @todo Is this correct? */
332	if (intno > 7)
333	{
334	pData->aPics[0].irr &= ~(1 << 2);
335	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
336	}
337	else
338	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
339
340	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
341	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
342	}
343	}
344
345
346	/**
347	* Set the an IRQ.
348	*
349	* @param pDevIns Device instance of the PICs.
350	* @param iIrq IRQ number to set.
351	* @param iLevel IRQ level.
352	*/
353	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
354	{
355	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
356	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
357	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
358	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
359	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
360
361	Log(("picSetIrq %d %d\n", iIrq, iLevel));
362	DumpPICState(&pData->aPics[0], "picSetIrq");
363	DumpPICState(&pData->aPics[1], "picSetIrq");
364	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
365	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
366	pic_update_irq(pData);
367	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
368	{
369	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, 0);
370	pic_update_irq(pData);
371	}
372	}
373
374
375	/* acknowledge interrupt 'irq' */
376	static inline void pic_intack(PicState *s, int irq)
377	{
378	if (s->auto_eoi) {
379	if (s->rotate_on_auto_eoi)
380	s->priority_add = (irq + 1) & 7;
381	} else {
382	s->isr \|= (1 << irq);
383	}
384	/* We don't clear a level sensitive interrupt here */
385	if (!(s->elcr & (1 << irq)))
386	{
387	Log2(("pic_intack: irr=%x irrnew=%x\n", s->irr, s->irr & ~(1 << irq)));
388	s->irr &= ~(1 << irq);
389	}
390	}
391
392
393	/**
394	* Get a pending interrupt.
395	*
396	* @returns Pending interrupt number.
397	* @param pDevIns Device instance of the PICs.
398	*/
399	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
400	{
401	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
402	int irq;
403	int irq2;
404	int intno;
405
406	/* read the irq from the PIC */
407	DumpPICState(&pData->aPics[0], "picGetInterrupt");
408	DumpPICState(&pData->aPics[1], "picGetInterrupt");
409
410	irq = pic_get_irq(&pData->aPics[0]);
411	if (irq >= 0)
412	{
413	pic_intack(&pData->aPics[0], irq);
414	if (irq == 2)
415	{
416	irq2 = pic_get_irq(&pData->aPics[1]);
417	if (irq2 >= 0) {
418	pic_intack(&pData->aPics[1], irq2);
419	}
420	else
421	{
422	/* spurious IRQ on slave controller (impossible) */
423	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
424	irq2 = 7;
425	}
426	intno = pData->aPics[1].irq_base + irq2;
427	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
428	irq = irq2 + 8;
429	}
430	else {
431	intno = pData->aPics[0].irq_base + irq;
432	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
433	}
434	}
435	else
436	{
437	/* spurious IRQ on host controller (impossible) */
438	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
439	irq = 7;
440	intno = pData->aPics[0].irq_base + irq;
441	}
442	pic_update_irq(pData);
443
444	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
445
446	return intno;
447	}
448
449	static void pic_reset(PicState *s)
450	{
451	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
452	RCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
453	int tmp, tmp2;
454
455	tmp = s->elcr_mask;
456	tmp2 = s->elcr;
457	memset(s, 0, sizeof(PicState));
458	s->elcr_mask = tmp;
459	s->elcr = tmp2;
460	s->pDevInsHC = pDevInsHC;
461	s->pDevInsGC = pDevInsGC;
462	}
463
464
465	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
466	{
467	PicState s = (PicState)opaque;
468	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
469	int rc = VINF_SUCCESS;
470	int priority, cmd, irq;
471
472	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
473	addr &= 1;
474	if (addr == 0) {
475	if (val & 0x10) {
476	/* init */
477	pic_reset(s);
478	/* deassert a pending interrupt */
479	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
480
481	s->init_state = 1;
482	s->init4 = val & 1;
483	if (val & 0x02)
484	AssertReleaseMsgFailed(("single mode not supported"));
485	if (val & 0x08)
486	AssertReleaseMsgFailed(("level sensitive irq not supported"));
487	} else if (val & 0x08) {
488	if (val & 0x04)
489	s->poll = 1;
490	if (val & 0x02)
491	s->read_reg_select = val & 1;
492	if (val & 0x40)
493	s->special_mask = (val >> 5) & 1;
494	} else {
495	cmd = val >> 5;
496	switch(cmd) {
497	case 0:
498	case 4:
499	s->rotate_on_auto_eoi = cmd >> 2;
500	break;
501	case 1: /* end of interrupt */
502	case 5:
503	{
504	priority = get_priority(s, s->isr);
505	if (priority != 8) {
506	irq = (priority + s->priority_add) & 7;
507	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
508	s->isr &= ~(1 << irq);
509	if (cmd == 5)
510	s->priority_add = (irq + 1) & 7;
511	rc = pic_update_irq(pData);
512	Assert(rc == VINF_SUCCESS);
513	DumpPICState(s, "eoi");
514	}
515	break;
516	}
517	case 3:
518	{
519	irq = val & 7;
520	Log(("pic_write: EOI2 for irq %d\n", irq));
521	s->isr &= ~(1 << irq);
522	rc = pic_update_irq(pData);
523	Assert(rc == VINF_SUCCESS);
524	DumpPICState(s, "eoi2");
525	break;
526	}
527	case 6:
528	{
529	s->priority_add = (val + 1) & 7;
530	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, s->priority_add));
531	rc = pic_update_irq(pData);
532	Assert(rc == VINF_SUCCESS);
533	break;
534	}
535	case 7:
536	{
537	irq = val & 7;
538	Log(("pic_write: EOI3 for irq %d\n", irq));
539	s->isr &= ~(1 << irq);
540	s->priority_add = (irq + 1) & 7;
541	rc = pic_update_irq(pData);
542	Assert(rc == VINF_SUCCESS);
543	DumpPICState(s, "eoi3");
544	break;
545	}
546	default:
547	/* no operation */
548	break;
549	}
550	}
551	} else {
552	switch(s->init_state) {
553	case 0:
554	{
555	/* normal mode */
556	pic_update_imr(pData, s, val);
557
558	rc = pic_update_irq(pData);
559	Assert(rc == VINF_SUCCESS);
560	break;
561	}
562	case 1:
563	s->irq_base = val & 0xf8;
564	s->init_state = 2;
565	Log(("pic_write: set irq base to %x\n", s->irq_base));
566	break;
567	case 2:
568	if (s->init4) {
569	s->init_state = 3;
570	} else {
571	s->init_state = 0;
572	}
573	break;
574	case 3:
575	s->special_fully_nested_mode = (val >> 4) & 1;
576	s->auto_eoi = (val >> 1) & 1;
577	s->init_state = 0;
578	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
579	break;
580	}
581	}
582	return rc;
583	}
584
585
586	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
587	{
588	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
589	PicState *pics = &pData->aPics[0];
590	int ret;
591
592	ret = pic_get_irq(s);
593	if (ret >= 0) {
594	if (addr1 >> 7) {
595	Log2(("pic_poll_read: clear slave irq (isr)\n"));
596	pics[0].isr &= ~(1 << 2);
597	pics[0].irr &= ~(1 << 2);
598	}
599	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
600	s->irr &= ~(1 << ret);
601	s->isr &= ~(1 << ret);
602	if (addr1 >> 7 \|\| ret != 2)
603	pic_update_irq(pData);
604	} else {
605	ret = 0x07;
606	pic_update_irq(pData);
607	}
608
609	return ret;
610	}
611
612
613	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
614	{
615	PicState s = (PicState)opaque;
616	unsigned int addr;
617	int ret;
618
619	*pRC = VINF_SUCCESS;
620
621	addr = addr1;
622	addr &= 1;
623	if (s->poll) {
624	ret = pic_poll_read(s, addr1);
625	s->poll = 0;
626	} else {
627	if (addr == 0) {
628	if (s->read_reg_select)
629	ret = s->isr;
630	else
631	ret = s->irr;
632	} else {
633	ret = s->imr;
634	}
635	}
636	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
637	return ret;
638	}
639
640
641
642	#ifdef IN_RING3
643
644	static void pic_save(QEMUFile f, void opaque)
645	{
646	PicState s = (PicState)opaque;
647
648	qemu_put_8s(f, &s->last_irr);
649	qemu_put_8s(f, &s->irr);
650	qemu_put_8s(f, &s->imr);
651	qemu_put_8s(f, &s->isr);
652	qemu_put_8s(f, &s->priority_add);
653	qemu_put_8s(f, &s->irq_base);
654	qemu_put_8s(f, &s->read_reg_select);
655	qemu_put_8s(f, &s->poll);
656	qemu_put_8s(f, &s->special_mask);
657	qemu_put_8s(f, &s->init_state);
658	qemu_put_8s(f, &s->auto_eoi);
659	qemu_put_8s(f, &s->rotate_on_auto_eoi);
660	qemu_put_8s(f, &s->special_fully_nested_mode);
661	qemu_put_8s(f, &s->init4);
662	qemu_put_8s(f, &s->elcr);
663	}
664
665	static int pic_load(QEMUFile f, void opaque, int version_id)
666	{
667	PicState s = (PicState)opaque;
668
669	if (version_id != 1)
670	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
671
672	qemu_get_8s(f, &s->last_irr);
673	qemu_get_8s(f, &s->irr);
674	qemu_get_8s(f, &s->imr);
675	qemu_get_8s(f, &s->isr);
676	qemu_get_8s(f, &s->priority_add);
677	qemu_get_8s(f, &s->irq_base);
678	qemu_get_8s(f, &s->read_reg_select);
679	qemu_get_8s(f, &s->poll);
680	qemu_get_8s(f, &s->special_mask);
681	qemu_get_8s(f, &s->init_state);
682	qemu_get_8s(f, &s->auto_eoi);
683	qemu_get_8s(f, &s->rotate_on_auto_eoi);
684	qemu_get_8s(f, &s->special_fully_nested_mode);
685	qemu_get_8s(f, &s->init4);
686	qemu_get_8s(f, &s->elcr);
687	return 0;
688	}
689	#endif /* IN_RING3 */
690
691
692	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
693
694	/**
695	* Port I/O Handler for IN operations.
696	*
697	* @returns VBox status code.
698	*
699	* @param pDevIns The device instance.
700	* @param pvUser User argument - pointer to the PIC in question.
701	* @param uPort Port number used for the IN operation.
702	* @param pu32 Where to store the result.
703	* @param cb Number of bytes read.
704	*/
705	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
706	{
707	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
708	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
709
710	Assert(iPic == 0 \|\| iPic == 1);
711	if (cb == 1)
712	{
713	int rc;
714	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
715	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
716	PIC_UNLOCK(pData);
717	return rc;
718	}
719	return VERR_IOM_IOPORT_UNUSED;
720	}
721
722	/**
723	* Port I/O Handler for OUT operations.
724	*
725	* @returns VBox status code.
726	*
727	* @param pDevIns The device instance.
728	* @param pvUser User argument - pointer to the PIC in question.
729	* @param uPort Port number used for the IN operation.
730	* @param u32 The value to output.
731	* @param cb The value size in bytes.
732	*/
733	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
734	{
735	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
736	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
737
738	Assert(iPic == 0 \|\| iPic == 1);
739
740	if (cb == 1)
741	{
742	int rc;
743	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
744	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
745	PIC_UNLOCK(pData);
746	return rc;
747	}
748	return VINF_SUCCESS;
749	}
750
751
752	/**
753	* Port I/O Handler for IN operations.
754	*
755	* @returns VBox status code.
756	*
757	* @param pDevIns The device instance.
758	* @param pvUser User argument - pointer to the PIC in question.
759	* @param uPort Port number used for the IN operation.
760	* @param pu32 Where to store the result.
761	* @param cb Number of bytes read.
762	*/
763	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
764	{
765	if (cb == 1)
766	{
767	PicState s = (PicState)pvUser;
768	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
769	*pu32 = s->elcr;
770	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
771	return VINF_SUCCESS;
772	}
773	return VERR_IOM_IOPORT_UNUSED;
774	}
775
776	/**
777	* Port I/O Handler for OUT operations.
778	*
779	* @returns VBox status code.
780	*
781	* @param pDevIns The device instance.
782	* @param pvUser User argument - pointer to the PIC in question.
783	* @param uPort Port number used for the IN operation.
784	* @param u32 The value to output.
785	* @param cb The value size in bytes.
786	*/
787	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
788	{
789	if (cb == 1)
790	{
791	PicState s = (PicState)pvUser;
792	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
793	s->elcr = u32 & s->elcr_mask;
794	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
795	}
796	return VINF_SUCCESS;
797	}
798
799
800	#ifdef IN_RING3
801
802	#ifdef DEBUG
803	/**
804	* PIC status info callback.
805	*
806	* @param pDevIns The device instance.
807	* @param pHlp The output helpers.
808	* @param pszArgs The arguments.
809	*/
810	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
811	{
812	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
813
814	/*
815	* Show info.
816	*/
817	for (int i=0;i<2;i++)
818	{
819	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
820	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
821	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
822	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
823	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
824	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
825	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
826	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
827	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
828	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
829	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
830	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
831	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
832	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
833	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
834	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
835	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
836	}
837	}
838	#endif /* DEBUG */
839
840	/**
841	* Saves a state of the programmable interrupt controller device.
842	*
843	* @returns VBox status code.
844	* @param pDevIns The device instance.
845	* @param pSSMHandle The handle to save the state to.
846	*/
847	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
848	{
849	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
850	pic_save(pSSMHandle, &pData->aPics[0]);
851	pic_save(pSSMHandle, &pData->aPics[1]);
852	return VINF_SUCCESS;
853	}
854
855
856	/**
857	* Loads a saved programmable interrupt controller device state.
858	*
859	* @returns VBox status code.
860	* @param pDevIns The device instance.
861	* @param pSSMHandle The handle to the saved state.
862	* @param u32Version The data unit version number.
863	*/
864	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
865	{
866	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
867	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
868	if (VBOX_SUCCESS(rc))
869	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
870	return rc;
871	}
872
873
874	/* -=-=-=-=-=- real code -=-=-=-=-=- */
875
876	/**
877	* Reset notification.
878	*
879	* @returns VBox status.
880	* @param pDevIns The device instance data.
881	*/
882	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
883	{
884	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
885	unsigned i;
886	LogFlow(("picReset:\n"));
887	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
888
889	for (i = 0; i < ELEMENTS(pData->aPics); i++)
890	pic_reset(&pData->aPics[i]);
891
892	PIC_UNLOCK(pData);
893	}
894
895
896	/**
897	* @copydoc FNPDMDEVRELOCATE
898	*/
899	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
900	{
901	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
902	unsigned i;
903
904	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
905	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
906	for (i = 0; i < ELEMENTS(pData->aPics); i++)
907	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
908	}
909
910
911	/**
912	* @copydoc FNPDMDEVCONSTRUCT
913	*/
914	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
915	{
916	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
917	PDMPICREG PicReg;
918	int rc;
919	bool fGCEnabled;
920	bool fR0Enabled;
921	Assert(iInstance == 0);
922
923	/*
924	* Validate and read configuration.
925	*/
926	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
927	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
928
929	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
930	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
931	fGCEnabled = true;
932	else if (VBOX_FAILURE(rc))
933	return PDMDEV_SET_ERROR(pDevIns, rc,
934	N_("Configuration error: failed to read GCEnabled as boolean"));
935
936	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
937	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
938	fR0Enabled = true;
939	else if (VBOX_FAILURE(rc))
940	return PDMDEV_SET_ERROR(pDevIns, rc,
941	N_("Configuration error: failed to read R0Enabled as boolean"));
942
943	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
944
945	/*
946	* Init the data.
947	*/
948	Assert(ELEMENTS(pData->aPics) == 2);
949	pData->pDevInsHC = pDevIns;
950	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
951	pData->aPics[0].elcr_mask = 0xf8;
952	pData->aPics[1].elcr_mask = 0xde;
953	pData->aPics[0].pDevInsHC = pDevIns;
954	pData->aPics[1].pDevInsHC = pDevIns;
955	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
956	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
957
958	/*
959	* Register PIC, I/O ports and save state.
960	*/
961	PicReg.u32Version = PDM_PICREG_VERSION;
962	PicReg.pfnSetIrqHC = picSetIrq;
963	PicReg.pfnGetInterruptHC = picGetInterrupt;
964	if (fGCEnabled)
965	{
966	PicReg.pszSetIrqGC = "picSetIrq";
967	PicReg.pszGetInterruptGC = "picGetInterrupt";
968	}
969	else
970	{
971	PicReg.pszSetIrqGC = NULL;
972	PicReg.pszGetInterruptGC = NULL;
973	}
974
975	if (fR0Enabled)
976	{
977	PicReg.pszSetIrqR0 = "picSetIrq";
978	PicReg.pszGetInterruptR0 = "picGetInterrupt";
979	}
980	else
981	{
982	PicReg.pszSetIrqR0 = NULL;
983	PicReg.pszGetInterruptR0 = NULL;
984	}
985
986	Assert(pDevIns->pDevHlp->pfnPICRegister);
987	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
988	if (VBOX_FAILURE(rc))
989	{
990	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
991	return rc;
992	}
993	if (fGCEnabled)
994	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
995	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
996	if (VBOX_FAILURE(rc))
997	return rc;
998	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
999	if (VBOX_FAILURE(rc))
1000	return rc;
1001	if (fGCEnabled)
1002	{
1003	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1004	if (VBOX_FAILURE(rc))
1005	return rc;
1006	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1007	if (VBOX_FAILURE(rc))
1008	return rc;
1009	}
1010	if (fR0Enabled)
1011	{
1012	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
1013
1014	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1015	if (VBOX_FAILURE(rc))
1016	return rc;
1017	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1018	if (VBOX_FAILURE(rc))
1019	return rc;
1020	}
1021
1022	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
1023	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1024	if (VBOX_FAILURE(rc))
1025	return rc;
1026	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
1027	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1028	if (VBOX_FAILURE(rc))
1029	return rc;
1030	if (fGCEnabled)
1031	{
1032	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1033	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1034	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1035	if (VBOX_FAILURE(rc))
1036	return rc;
1037	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1038	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1039	if (VBOX_FAILURE(rc))
1040	return rc;
1041	}
1042	if (fR0Enabled)
1043	{
1044	RTR0PTR pDataR0 = PDMINS2DATA_R0PTR(pDevIns);
1045	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1046	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1047	if (VBOX_FAILURE(rc))
1048	return rc;
1049	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1050	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1051	if (VBOX_FAILURE(rc))
1052	return rc;
1053	}
1054
1055	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1056	NULL, picSaveExec, NULL,
1057	NULL, picLoadExec, NULL);
1058	if (VBOX_FAILURE(rc))
1059	return rc;
1060
1061
1062	#ifdef DEBUG
1063	/*
1064	* Register the info item.
1065	*/
1066	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1067	#endif
1068
1069	/*
1070	* Initialize the device state.
1071	*/
1072	picReset(pDevIns);
1073
1074	#ifdef VBOX_WITH_STATISTICS
1075	/*
1076	* Statistics.
1077	*/
1078	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1079	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1080
1081	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1082	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1083	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1084	#endif
1085
1086	return VINF_SUCCESS;
1087	}
1088
1089
1090	/**
1091	* The device registration structure.
1092	*/
1093	const PDMDEVREG g_DeviceI8259 =
1094	{
1095	/* u32Version */
1096	PDM_DEVREG_VERSION,
1097	/* szDeviceName */
1098	"i8259",
1099	/* szGCMod */
1100	"VBoxDDGC.gc",
1101	/* szR0Mod */
1102	"VBoxDDR0.r0",
1103	/* pszDescription */
1104	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1105	/* fFlags */
1106	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1107	/* fClass */
1108	PDM_DEVREG_CLASS_PIC,
1109	/* cMaxInstances */
1110	1,
1111	/* cbInstance */
1112	sizeof(DEVPIC),
1113	/* pfnConstruct */
1114	picConstruct,
1115	/* pfnDestruct */
1116	NULL,
1117	/* pfnRelocate */
1118	picRelocate,
1119	/* pfnIOCtl */
1120	NULL,
1121	/* pfnPowerOn */
1122	NULL,
1123	/* pfnReset */
1124	picReset,
1125	/* pfnSuspend */
1126	NULL,
1127	/* pfnResume */
1128	NULL,
1129	/* pfnAttach */
1130	NULL,
1131	/* pfnDetach */
1132	NULL,
1133	/* pfnQueryInterface. */
1134	NULL
1135	};
1136
1137	#endif /* IN_RING3 */
1138	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1139

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 10485

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