DevPIC.cpp@ 2564

Last change on this file since 2564 was 2538, checked in by vboxsync, 18 years ago
Quick implementation of IRQ level flip-flip (pass PDM_IRQ_LEVEL_FLIP_FLOP as the level).
Property svn:eol-style set to `native`
File size: 36.4 KB

Line
1	/** @file
2	*
3	* VBox basic PC devices:
4	* Intel 8259 Programmable Interrupt Controller.
5	*/
6
7	/*
8	* Copyright (C) 2006 InnoTek Systemberatung GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* If you received this file as part of a commercial VirtualBox
19	* distribution, then only the terms of your commercial VirtualBox
20	* license agreement apply instead of the previous paragraph.
21	*/
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_PIC
27	#include <VBox/pdm.h>
28	#include <VBox/log.h>
29	#include <iprt/assert.h>
30
31	#include "vl_vbox.h"
32
33
34	/*******************************************************************************
35	* Defined Constants And Macros *
36	*******************************************************************************/
37	/** @def PIC_LOCK
38	* Acquires the PDM lock. This is a NOP if locking is disabled. */
39	/** @def PIC_UNLOCK
40	* Releases the PDM lock. This is a NOP if locking is disabled. */
41	#ifdef VBOX_WITH_PDM_LOCK
42	# define PIC_LOCK(pThis, rc) \
43	do { \
44	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
45	if (rc2 != VINF_SUCCESS) \
46	return rc2; \
47	} while (0)
48	# define PIC_UNLOCK(pThis) \
49	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
50	#else /* !VBOX_WITH_PDM_LOCK */
51	# define PIC_LOCK(pThis, rc) do { } while (0)
52	# define PIC_UNLOCK(pThis) do { } while (0)
53	#endif /* !VBOX_WITH_PDM_LOCK */
54
55
56	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
57	/*******************************************************************************
58	* Internal Functions *
59	*******************************************************************************/
60	__BEGIN_DECLS
61
62	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
63	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
64	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
65	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
66	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
67	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
68
69	__END_DECLS
70	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
71
72
73	/*
74	* QEMU 8259 interrupt controller emulation
75	*
76	* Copyright (c) 2003-2004 Fabrice Bellard
77	*
78	* Permission is hereby granted, free of charge, to any person obtaining a copy
79	* of this software and associated documentation files (the "Software"), to deal
80	* in the Software without restriction, including without limitation the rights
81	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
82	* copies of the Software, and to permit persons to whom the Software is
83	* furnished to do so, subject to the following conditions:
84	*
85	* The above copyright notice and this permission notice shall be included in
86	* all copies or substantial portions of the Software.
87	*
88	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
89	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
90	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
91	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
92	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
93	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
94	* THE SOFTWARE.
95	*/
96
97	/* debug PIC */
98	#define DEBUG_PIC
99
100	/#define DEBUG_IRQ_COUNT/
101
102	typedef struct PicState {
103	uint8_t last_irr; /* edge detection */
104	uint8_t irr; /* interrupt request register */
105	uint8_t imr; /* interrupt mask register */
106	uint8_t isr; /* interrupt service register */
107	uint8_t priority_add; /* highest irq priority */
108	uint8_t irq_base;
109	uint8_t read_reg_select;
110	uint8_t poll;
111	uint8_t special_mask;
112	uint8_t init_state;
113	uint8_t auto_eoi;
114	uint8_t rotate_on_auto_eoi;
115	uint8_t special_fully_nested_mode;
116	uint8_t init4; /* true if 4 byte init */
117	uint8_t elcr; /* PIIX edge/trigger selection*/
118	uint8_t elcr_mask;
119	/** Pointer to the device instance, HCPtr. */
120	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
121	/** Pointer to the device instance, GCPtr. */
122	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
123	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS != 64
124	RTGCPTR Alignment0;
125	#endif
126	} PicState;
127
128	/**
129	* A PIC device instance data.
130	*/
131	typedef struct DEVPIC
132	{
133	/** The two interrupt controllers. */
134	PicState aPics[2];
135	/** Pointer to the PIC R3 helpers. */
136	PCPDMPICHLPR3 pPicHlpR3;
137	/** Pointer to the PIC R0 helpers. */
138	PCPDMPICHLPR0 pPicHlpR0;
139	/** Pointer to the PIC GC helpers. */
140	PCPDMPICHLPGC pPicHlpGC;
141	/** Pointer to the device instance - GC Ptr. */
142	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
143	/** Pointer to the device instance - GC Ptr. */
144	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
145	#if HC_ARCH_BITS == 32
146	uint32_t Alignmnet0;
147	#endif
148	#ifdef VBOX_WITH_STATISTICS
149	STAMCOUNTER StatSetIrqGC;
150	STAMCOUNTER StatSetIrqHC;
151	STAMCOUNTER StatClearedActiveIRQ2;
152	STAMCOUNTER StatClearedActiveMasterIRQ;
153	STAMCOUNTER StatClearedActiveSlaveIRQ;
154	#endif
155	} DEVPIC, *PDEVPIC;
156
157
158	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
159	#ifdef LOG_ENABLED
160	static inline void DumpPICState(PicState s, char szFn)
161	{
162	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
163
164	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
165	szFn, (&pData->aPics[0] == s) ? 0 : 1,
166	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
167	}
168	#else
169	# define DumpPICState(pData, szFn) do { } while (0)
170	#endif
171
172	/* set irq level. If an edge is detected, then the IRR is set to 1 */
173	static inline void pic_set_irq1(PicState *s, int irq, int level)
174	{
175	int mask;
176	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
177	mask = 1 << irq;
178	if (s->elcr & mask) {
179	/* level triggered */
180	if (level) {
181	s->irr \|= mask;
182	s->last_irr \|= mask;
183	} else {
184	s->irr &= ~mask;
185	s->last_irr &= ~mask;
186	}
187	} else {
188	/* edge triggered */
189	if (level) {
190	if ((s->last_irr & mask) == 0)
191	{
192	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
193	s->irr \|= mask;
194	}
195	s->last_irr \|= mask;
196	} else {
197	s->last_irr &= ~mask;
198	}
199	}
200	DumpPICState(s, "pic_set_irq1");
201	}
202
203	/* return the highest priority found in mask (highest = smallest
204	number). Return 8 if no irq */
205	static inline int get_priority(PicState *s, int mask)
206	{
207	int priority;
208	if (mask == 0)
209	return 8;
210	priority = 0;
211	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
212	priority++;
213	return priority;
214	}
215
216	/* return the pic wanted interrupt. return -1 if none */
217	static int pic_get_irq(PicState *s)
218	{
219	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
220	int mask, cur_priority, priority;
221	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
222	DumpPICState(s, "pic_get_irq");
223
224	mask = s->irr & ~s->imr;
225	priority = get_priority(s, mask);
226	Log(("pic_get_irq: priority=%x\n", priority));
227	if (priority == 8)
228	return -1;
229	/* compute current priority. If special fully nested mode on the
230	master, the IRQ coming from the slave is not taken into account
231	for the priority computation. */
232	mask = s->isr;
233	if (s->special_fully_nested_mode && s == &pics[0])
234	mask &= ~(1 << 2);
235	cur_priority = get_priority(s, mask);
236	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
237	if (priority < cur_priority) {
238	/* higher priority found: an irq should be generated */
239	return (priority + s->priority_add) & 7;
240	} else {
241	return -1;
242	}
243	}
244
245	/* raise irq to CPU if necessary. must be called every time the active
246	irq may change */
247	static int pic_update_irq(PDEVPIC pData)
248	{
249	PicState *pics = &pData->aPics[0];
250	int irq2, irq;
251
252	/* first look at slave pic */
253	irq2 = pic_get_irq(&pics[1]);
254	Log(("pic_update_irq irq2=%d\n", irq2));
255	if (irq2 >= 0) {
256	/* if irq request by slave pic, signal master PIC */
257	pic_set_irq1(&pics[0], 2, 1);
258	pic_set_irq1(&pics[0], 2, 0);
259	}
260	/* look at requested irq */
261	irq = pic_get_irq(&pics[0]);
262	if (irq >= 0)
263	{
264	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
265	* spurious slave interrupts in picGetInterrupt.
266	*/
267	if (irq != 2 \|\| irq2 != -1)
268	{
269	#if defined(DEBUG_PIC)
270	int i;
271	for(i = 0; i < 2; i++) {
272	Log(("pic%d: imr=%x irr=%x padd=%d\n",
273	i, pics[i].imr, pics[i].irr,
274	pics[i].priority_add));
275	}
276	Log(("pic: cpu_interrupt\n"));
277	#endif
278	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
279	}
280	else
281	{
282	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
283	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
284	/* Clear it here, so lower priority interrupts can still be dispatched. */
285	/** @note Is this correct? */
286	pics[0].irr &= ~(1 << 2);
287	}
288	}
289	return VINF_SUCCESS;
290	}
291
292	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
293	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
294	{
295	int irq, intno;
296	PicState *pActivePIC;
297
298	/* Query the current pending irq, if any. */
299	pActivePIC = &pData->aPics[0];
300	intno = irq = pic_get_irq(pActivePIC);
301	if (irq == 2)
302	{
303	pActivePIC = &pData->aPics[1];
304	irq = pic_get_irq(pActivePIC);
305	intno = irq + 8;
306	}
307
308	/* Update IMR */
309	s->imr = val;
310
311	/* If an interrupt is pending and now masked, then clear the FF flag. */
312	if ( irq >= 0
313	&& ((1 << irq) & ~pActivePIC->imr) == 0)
314	{
315	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
316	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
317	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
318	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
319
320	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
321	/** @todo Is this correct? */
322	if (intno > 7)
323	{
324	pData->aPics[0].irr &= ~(1 << 2);
325	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
326	}
327	else
328	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
329
330	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
331	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
332	}
333	}
334
335
336	/**
337	* Set the an IRQ.
338	*
339	* @param pDevIns Device instance of the PICs.
340	* @param iIrq IRQ number to set.
341	* @param iLevel IRQ level.
342	*/
343	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
344	{
345	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
346	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
347	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
348	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
349	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
350
351	Log(("picSetIrq %d %d\n", iIrq, iLevel));
352	DumpPICState(&pData->aPics[0], "picSetIrq");
353	DumpPICState(&pData->aPics[1], "picSetIrq");
354	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
355	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
356	pic_update_irq(pData);
357	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
358	{
359	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, 0);
360	pic_update_irq(pData);
361	}
362	}
363
364
365	/* acknowledge interrupt 'irq' */
366	static inline void pic_intack(PicState *s, int irq)
367	{
368	if (s->auto_eoi) {
369	if (s->rotate_on_auto_eoi)
370	s->priority_add = (irq + 1) & 7;
371	} else {
372	s->isr \|= (1 << irq);
373	}
374	/* We don't clear a level sensitive interrupt here */
375	if (!(s->elcr & (1 << irq)))
376	s->irr &= ~(1 << irq);
377	}
378
379
380	/**
381	* Get a pending interrupt.
382	*
383	* @returns Pending interrupt number.
384	* @param pDevIns Device instance of the PICs.
385	*/
386	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
387	{
388	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
389	int irq;
390	int irq2;
391	int intno;
392
393	/* read the irq from the PIC */
394	DumpPICState(&pData->aPics[0], "picGetInterrupt");
395	DumpPICState(&pData->aPics[1], "picGetInterrupt");
396
397	irq = pic_get_irq(&pData->aPics[0]);
398	if (irq >= 0)
399	{
400	pic_intack(&pData->aPics[0], irq);
401	if (irq == 2)
402	{
403	irq2 = pic_get_irq(&pData->aPics[1]);
404	if (irq2 >= 0) {
405	pic_intack(&pData->aPics[1], irq2);
406	}
407	else
408	{
409	/* spurious IRQ on slave controller (impossible) */
410	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
411	irq2 = 7;
412	}
413	intno = pData->aPics[1].irq_base + irq2;
414	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
415	irq = irq2 + 8;
416	}
417	else {
418	intno = pData->aPics[0].irq_base + irq;
419	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
420	}
421	}
422	else
423	{
424	/* spurious IRQ on host controller (impossible) */
425	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
426	irq = 7;
427	intno = pData->aPics[0].irq_base + irq;
428	}
429	pic_update_irq(pData);
430
431	Log(("picGetInterrupt: pending 0:%d 1:%d\n", pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
432
433	return intno;
434	}
435
436	static void pic_reset(PicState *s)
437	{
438	HCPTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
439	GCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
440	int tmp, tmp2;
441
442	tmp = s->elcr_mask;
443	tmp2 = s->elcr;
444	memset(s, 0, sizeof(PicState));
445	s->elcr_mask = tmp;
446	s->elcr = tmp2;
447	s->pDevInsHC = pDevInsHC;
448	s->pDevInsGC = pDevInsGC;
449	}
450
451
452	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
453	{
454	PicState s = (PicState)opaque;
455	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
456	int rc = VINF_SUCCESS;
457	int priority, cmd, irq;
458
459	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
460	addr &= 1;
461	if (addr == 0) {
462	if (val & 0x10) {
463	/* init */
464	pic_reset(s);
465	/* deassert a pending interrupt */
466	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
467
468	s->init_state = 1;
469	s->init4 = val & 1;
470	if (val & 0x02)
471	AssertReleaseMsgFailed(("single mode not supported"));
472	if (val & 0x08)
473	AssertReleaseMsgFailed(("level sensitive irq not supported"));
474	} else if (val & 0x08) {
475	if (val & 0x04)
476	s->poll = 1;
477	if (val & 0x02)
478	s->read_reg_select = val & 1;
479	if (val & 0x40)
480	s->special_mask = (val >> 5) & 1;
481	} else {
482	cmd = val >> 5;
483	switch(cmd) {
484	case 0:
485	case 4:
486	s->rotate_on_auto_eoi = cmd >> 2;
487	break;
488	case 1: /* end of interrupt */
489	case 5:
490	{
491	priority = get_priority(s, s->isr);
492	if (priority != 8) {
493	irq = (priority + s->priority_add) & 7;
494	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
495	s->isr &= ~(1 << irq);
496	if (cmd == 5)
497	s->priority_add = (irq + 1) & 7;
498	rc = pic_update_irq(pData);
499	Assert(rc == VINF_SUCCESS);
500	}
501	break;
502	}
503	case 3:
504	{
505	irq = val & 7;
506	Log(("pic_write: EOI2 for irq %d\n", irq));
507	s->isr &= ~(1 << irq);
508	rc = pic_update_irq(pData);
509	Assert(rc == VINF_SUCCESS);
510	break;
511	}
512	case 6:
513	{
514	s->priority_add = (val + 1) & 7;
515	rc = pic_update_irq(pData);
516	Assert(rc == VINF_SUCCESS);
517	break;
518	}
519	case 7:
520	{
521	irq = val & 7;
522	Log(("pic_write: EOI3 for irq %d\n", irq));
523	s->isr &= ~(1 << irq);
524	s->priority_add = (irq + 1) & 7;
525	rc = pic_update_irq(pData);
526	Assert(rc == VINF_SUCCESS);
527	break;
528	}
529	default:
530	/* no operation */
531	break;
532	}
533	}
534	} else {
535	switch(s->init_state) {
536	case 0:
537	{
538	/* normal mode */
539	pic_update_imr(pData, s, val);
540
541	rc = pic_update_irq(pData);
542	Assert(rc == VINF_SUCCESS);
543	break;
544	}
545	case 1:
546	s->irq_base = val & 0xf8;
547	s->init_state = 2;
548	Log(("pic_write: set irq base to %x\n", s->irq_base));
549	break;
550	case 2:
551	if (s->init4) {
552	s->init_state = 3;
553	} else {
554	s->init_state = 0;
555	}
556	break;
557	case 3:
558	s->special_fully_nested_mode = (val >> 4) & 1;
559	s->auto_eoi = (val >> 1) & 1;
560	s->init_state = 0;
561	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
562	break;
563	}
564	}
565	return rc;
566	}
567
568
569	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
570	{
571	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
572	PicState *pics = &pData->aPics[0];
573	int ret;
574
575	ret = pic_get_irq(s);
576	if (ret >= 0) {
577	if (addr1 >> 7) {
578	Log2(("pic_poll_read: clear slave irq (isr)\n"));
579	pics[0].isr &= ~(1 << 2);
580	pics[0].irr &= ~(1 << 2);
581	}
582	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
583	s->irr &= ~(1 << ret);
584	s->isr &= ~(1 << ret);
585	if (addr1 >> 7 \|\| ret != 2)
586	pic_update_irq(pData);
587	} else {
588	ret = 0x07;
589	pic_update_irq(pData);
590	}
591
592	return ret;
593	}
594
595
596	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
597	{
598	PicState s = (PicState)opaque;
599	unsigned int addr;
600	int ret;
601
602	*pRC = VINF_SUCCESS;
603
604	addr = addr1;
605	addr &= 1;
606	if (s->poll) {
607	ret = pic_poll_read(s, addr1);
608	s->poll = 0;
609	} else {
610	if (addr == 0) {
611	if (s->read_reg_select)
612	ret = s->isr;
613	else
614	ret = s->irr;
615	} else {
616	ret = s->imr;
617	}
618	}
619	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
620	return ret;
621	}
622
623
624
625	#ifdef IN_RING3
626
627	static void pic_save(QEMUFile f, void opaque)
628	{
629	PicState s = (PicState)opaque;
630
631	qemu_put_8s(f, &s->last_irr);
632	qemu_put_8s(f, &s->irr);
633	qemu_put_8s(f, &s->imr);
634	qemu_put_8s(f, &s->isr);
635	qemu_put_8s(f, &s->priority_add);
636	qemu_put_8s(f, &s->irq_base);
637	qemu_put_8s(f, &s->read_reg_select);
638	qemu_put_8s(f, &s->poll);
639	qemu_put_8s(f, &s->special_mask);
640	qemu_put_8s(f, &s->init_state);
641	qemu_put_8s(f, &s->auto_eoi);
642	qemu_put_8s(f, &s->rotate_on_auto_eoi);
643	qemu_put_8s(f, &s->special_fully_nested_mode);
644	qemu_put_8s(f, &s->init4);
645	qemu_put_8s(f, &s->elcr);
646	}
647
648	static int pic_load(QEMUFile f, void opaque, int version_id)
649	{
650	PicState s = (PicState)opaque;
651
652	if (version_id != 1)
653	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
654
655	qemu_get_8s(f, &s->last_irr);
656	qemu_get_8s(f, &s->irr);
657	qemu_get_8s(f, &s->imr);
658	qemu_get_8s(f, &s->isr);
659	qemu_get_8s(f, &s->priority_add);
660	qemu_get_8s(f, &s->irq_base);
661	qemu_get_8s(f, &s->read_reg_select);
662	qemu_get_8s(f, &s->poll);
663	qemu_get_8s(f, &s->special_mask);
664	qemu_get_8s(f, &s->init_state);
665	qemu_get_8s(f, &s->auto_eoi);
666	qemu_get_8s(f, &s->rotate_on_auto_eoi);
667	qemu_get_8s(f, &s->special_fully_nested_mode);
668	qemu_get_8s(f, &s->init4);
669	qemu_get_8s(f, &s->elcr);
670	return 0;
671	}
672	#endif /* IN_RING3 */
673
674
675	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
676
677	/**
678	* Port I/O Handler for IN operations.
679	*
680	* @returns VBox status code.
681	*
682	* @param pDevIns The device instance.
683	* @param pvUser User argument - pointer to the PIC in question.
684	* @param uPort Port number used for the IN operation.
685	* @param pu32 Where to store the result.
686	* @param cb Number of bytes read.
687	*/
688	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
689	{
690	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
691	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
692
693	Assert(iPic == 0 \|\| iPic == 1);
694	if (cb == 1)
695	{
696	int rc;
697	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
698	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
699	PIC_UNLOCK(pData);
700	return rc;
701	}
702	return VERR_IOM_IOPORT_UNUSED;
703	}
704
705	/**
706	* Port I/O Handler for OUT operations.
707	*
708	* @returns VBox status code.
709	*
710	* @param pDevIns The device instance.
711	* @param pvUser User argument - pointer to the PIC in question.
712	* @param uPort Port number used for the IN operation.
713	* @param u32 The value to output.
714	* @param cb The value size in bytes.
715	*/
716	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
717	{
718	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
719	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
720
721	Assert(iPic == 0 \|\| iPic == 1);
722
723	if (cb == 1)
724	{
725	int rc;
726	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
727	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
728	PIC_UNLOCK(pData);
729	return rc;
730	}
731	return VINF_SUCCESS;
732	}
733
734
735	/**
736	* Port I/O Handler for IN operations.
737	*
738	* @returns VBox status code.
739	*
740	* @param pDevIns The device instance.
741	* @param pvUser User argument - pointer to the PIC in question.
742	* @param uPort Port number used for the IN operation.
743	* @param pu32 Where to store the result.
744	* @param cb Number of bytes read.
745	*/
746	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
747	{
748	if (cb == 1)
749	{
750	PicState s = (PicState)pvUser;
751	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
752	*pu32 = s->elcr;
753	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
754	return VINF_SUCCESS;
755	}
756	return VERR_IOM_IOPORT_UNUSED;
757	}
758
759	/**
760	* Port I/O Handler for OUT operations.
761	*
762	* @returns VBox status code.
763	*
764	* @param pDevIns The device instance.
765	* @param pvUser User argument - pointer to the PIC in question.
766	* @param uPort Port number used for the IN operation.
767	* @param u32 The value to output.
768	* @param cb The value size in bytes.
769	*/
770	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
771	{
772	if (cb == 1)
773	{
774	PicState s = (PicState)pvUser;
775	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
776	s->elcr = u32 & s->elcr_mask;
777	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
778	}
779	return VINF_SUCCESS;
780	}
781
782
783	#ifdef IN_RING3
784
785	#ifdef DEBUG
786	/**
787	* PIC status info callback.
788	*
789	* @param pDevIns The device instance.
790	* @param pHlp The output helpers.
791	* @param pszArgs The arguments.
792	*/
793	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
794	{
795	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
796
797	/*
798	* Show info.
799	*/
800	for (int i=0;i<2;i++)
801	{
802	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
803	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
804	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
805	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
806	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
807	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
808	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
809	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
810	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
811	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
812	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
813	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
814	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
815	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
816	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
817	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
818	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
819	}
820	}
821	#endif /* DEBUG */
822
823	/**
824	* Saves a state of the programmable interrupt controller device.
825	*
826	* @returns VBox status code.
827	* @param pDevIns The device instance.
828	* @param pSSMHandle The handle to save the state to.
829	*/
830	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
831	{
832	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
833	pic_save(pSSMHandle, &pData->aPics[0]);
834	pic_save(pSSMHandle, &pData->aPics[1]);
835	return VINF_SUCCESS;
836	}
837
838
839	/**
840	* Loads a saved programmable interrupt controller device state.
841	*
842	* @returns VBox status code.
843	* @param pDevIns The device instance.
844	* @param pSSMHandle The handle to the saved state.
845	* @param u32Version The data unit version number.
846	*/
847	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
848	{
849	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
850	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
851	if (VBOX_SUCCESS(rc))
852	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
853	return rc;
854	}
855
856
857	/* -=-=-=-=-=- real code -=-=-=-=-=- */
858
859	/**
860	* Reset notification.
861	*
862	* @returns VBox status.
863	* @param pDevIns The device instance data.
864	*/
865	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
866	{
867	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
868	unsigned i;
869	LogFlow(("picReset:\n"));
870	#ifdef VBOX_WITH_PDM_LOCK
871	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
872	#endif
873
874	for (i = 0; i < ELEMENTS(pData->aPics); i++)
875	pic_reset(&pData->aPics[i]);
876
877	PIC_UNLOCK(pData);
878	}
879
880
881	/**
882	* @copydoc FNPDMDEVRELOCATE
883	*/
884	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
885	{
886	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
887	unsigned i;
888
889	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
890	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
891	for (i = 0; i < ELEMENTS(pData->aPics); i++)
892	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
893	}
894
895
896	/**
897	* @copydoc FNPDMDEVCONSTRUCT
898	*/
899	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
900	{
901	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
902	PDMPICREG PicReg;
903	int rc;
904	bool fGCEnabled;
905	bool fR0Enabled;
906	Assert(iInstance == 0);
907
908	/*
909	* Validate and read configuration.
910	*/
911	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
912	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
913
914	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
915	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
916	fGCEnabled = true;
917	else if (VBOX_FAILURE(rc))
918	return PDMDEV_SET_ERROR(pDevIns, rc,
919	N_("Configuration error: failed to read GCEnabled as boolean"));
920
921	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
922	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
923	fR0Enabled = true;
924	else if (VBOX_FAILURE(rc))
925	return PDMDEV_SET_ERROR(pDevIns, rc,
926	N_("Configuration error: failed to read R0Enabled as boolean"));
927
928	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
929
930	/*
931	* Init the data.
932	*/
933	Assert(ELEMENTS(pData->aPics) == 2);
934	pData->pDevInsHC = pDevIns;
935	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
936	pData->aPics[0].elcr_mask = 0xf8;
937	pData->aPics[1].elcr_mask = 0xde;
938	pData->aPics[0].pDevInsHC = pDevIns;
939	pData->aPics[1].pDevInsHC = pDevIns;
940	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
941	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
942
943	/*
944	* Register PIC, I/O ports and save state.
945	*/
946	PicReg.u32Version = PDM_PICREG_VERSION;
947	PicReg.pfnSetIrqHC = picSetIrq;
948	PicReg.pfnGetInterruptHC = picGetInterrupt;
949	if (fGCEnabled)
950	{
951	PicReg.pszSetIrqGC = "picSetIrq";
952	PicReg.pszGetInterruptGC = "picGetInterrupt";
953	}
954	else
955	{
956	PicReg.pszSetIrqGC = NULL;
957	PicReg.pszGetInterruptGC = NULL;
958	}
959
960	if (fR0Enabled)
961	{
962	PicReg.pszSetIrqR0 = "picSetIrq";
963	PicReg.pszGetInterruptR0 = "picGetInterrupt";
964	}
965	else
966	{
967	PicReg.pszSetIrqR0 = NULL;
968	PicReg.pszGetInterruptR0 = NULL;
969	}
970
971	Assert(pDevIns->pDevHlp->pfnPICRegister);
972	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
973	if (VBOX_FAILURE(rc))
974	{
975	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
976	return rc;
977	}
978	if (fGCEnabled)
979	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
980	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
981	if (VBOX_FAILURE(rc))
982	return rc;
983	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
984	if (VBOX_FAILURE(rc))
985	return rc;
986	if (fGCEnabled)
987	{
988	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
989	if (VBOX_FAILURE(rc))
990	return rc;
991	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
992	if (VBOX_FAILURE(rc))
993	return rc;
994	}
995	if (fR0Enabled)
996	{
997	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
998
999	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1000	if (VBOX_FAILURE(rc))
1001	return rc;
1002	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1003	if (VBOX_FAILURE(rc))
1004	return rc;
1005	}
1006
1007	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
1008	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1009	if (VBOX_FAILURE(rc))
1010	return rc;
1011	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
1012	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1013	if (VBOX_FAILURE(rc))
1014	return rc;
1015	if (fGCEnabled)
1016	{
1017	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1018	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1019	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1020	if (VBOX_FAILURE(rc))
1021	return rc;
1022	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1023	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1024	if (VBOX_FAILURE(rc))
1025	return rc;
1026	}
1027	if (fR0Enabled)
1028	{
1029	RTR0PTR pDataR0 = PDMINS2DATA_R0PTR(pDevIns);
1030	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1031	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1032	if (VBOX_FAILURE(rc))
1033	return rc;
1034	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1035	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1036	if (VBOX_FAILURE(rc))
1037	return rc;
1038	}
1039
1040	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1041	NULL, picSaveExec, NULL,
1042	NULL, picLoadExec, NULL);
1043	if (VBOX_FAILURE(rc))
1044	return rc;
1045
1046
1047	#ifdef DEBUG
1048	/*
1049	* Register the info item.
1050	*/
1051	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1052	#endif
1053
1054	/*
1055	* Initialize the device state.
1056	*/
1057	picReset(pDevIns);
1058
1059	#ifdef VBOX_WITH_STATISTICS
1060	/*
1061	* Statistics.
1062	*/
1063	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1064	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1065
1066	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1067	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1068	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1069	#endif
1070
1071	return VINF_SUCCESS;
1072	}
1073
1074
1075	/**
1076	* The device registration structure.
1077	*/
1078	const PDMDEVREG g_DeviceI8259 =
1079	{
1080	/* u32Version */
1081	PDM_DEVREG_VERSION,
1082	/* szDeviceName */
1083	"i8259",
1084	/* szGCMod */
1085	"VBoxDDGC.gc",
1086	/* szR0Mod */
1087	"VBoxDDR0.r0",
1088	/* pszDescription */
1089	"i8259 Programmable Interrupt Controller",
1090	/* fFlags */
1091	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1092	/* fClass */
1093	PDM_DEVREG_CLASS_PIC,
1094	/* cMaxInstances */
1095	1,
1096	/* cbInstance */
1097	sizeof(DEVPIC),
1098	/* pfnConstruct */
1099	picConstruct,
1100	/* pfnDestruct */
1101	NULL,
1102	/* pfnRelocate */
1103	picRelocate,
1104	/* pfnIOCtl */
1105	NULL,
1106	/* pfnPowerOn */
1107	NULL,
1108	/* pfnReset */
1109	picReset,
1110	/* pfnSuspend */
1111	NULL,
1112	/* pfnResume */
1113	NULL,
1114	/* pfnAttach */
1115	NULL,
1116	/* pfnDetach */
1117	NULL,
1118	/* pfnQueryInterface. */
1119	NULL
1120	};
1121
1122	#endif /* IN_RING3 */
1123	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1124

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 2564

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