DevPIC.cpp@ 33595

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1	/* $Id: DevPIC.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PIC
22	#include <VBox/pdmdev.h>
23	#include <VBox/log.h>
24	#include <iprt/assert.h>
25	#include <iprt/string.h>
26
27	#include "../Builtins.h"
28
29
30	/*******************************************************************************
31	* Defined Constants And Macros *
32	*******************************************************************************/
33	/** @def PIC_LOCK
34	* Acquires the PDM lock. This is a NOP if locking is disabled. */
35	/** @def PIC_UNLOCK
36	* Releases the PDM lock. This is a NOP if locking is disabled. */
37	#define PIC_LOCK(pThis, rc) \
38	do { \
39	int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
40	if (rc2 != VINF_SUCCESS) \
41	return rc2; \
42	} while (0)
43	#define PIC_UNLOCK(pThis) \
44	(pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
45
46
47	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	RT_C_DECLS_BEGIN
52
53	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
54	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
55	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
56	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
57	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
58	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
59
60	RT_C_DECLS_END
61	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
62
63
64	/*
65	* QEMU 8259 interrupt controller emulation
66	*
67	* Copyright (c) 2003-2004 Fabrice Bellard
68	*
69	* Permission is hereby granted, free of charge, to any person obtaining a copy
70	* of this software and associated documentation files (the "Software"), to deal
71	* in the Software without restriction, including without limitation the rights
72	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
73	* copies of the Software, and to permit persons to whom the Software is
74	* furnished to do so, subject to the following conditions:
75	*
76	* The above copyright notice and this permission notice shall be included in
77	* all copies or substantial portions of the Software.
78	*
79	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
80	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
81	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
82	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
83	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
84	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
85	* THE SOFTWARE.
86	*/
87
88	/* debug PIC */
89	#define DEBUG_PIC
90
91	/#define DEBUG_IRQ_COUNT/
92
93	typedef struct PicState {
94	uint8_t last_irr; /* edge detection */
95	uint8_t irr; /* interrupt request register */
96	uint8_t imr; /* interrupt mask register */
97	uint8_t isr; /* interrupt service register */
98	uint8_t priority_add; /* highest irq priority */
99	uint8_t irq_base;
100	uint8_t read_reg_select;
101	uint8_t poll;
102	uint8_t special_mask;
103	uint8_t init_state;
104	uint8_t auto_eoi;
105	uint8_t rotate_on_auto_eoi;
106	uint8_t special_fully_nested_mode;
107	uint8_t init4; /* true if 4 byte init */
108	uint8_t elcr; /* PIIX edge/trigger selection*/
109	uint8_t elcr_mask;
110	/** Pointer to the device instance, R3 Ptr. */
111	PPDMDEVINSR3 pDevInsR3;
112	/** Pointer to the device instance, R0 Ptr. */
113	PPDMDEVINSR0 pDevInsR0;
114	/** Pointer to the device instance, RC Ptr. */
115	PPDMDEVINSRC pDevInsRC;
116	RTRCPTR Alignment0; /*< Structure size alignment. /
117	} PicState;
118
119	/**
120	* A PIC device instance data.
121	*/
122	typedef struct DEVPIC
123	{
124	/** The two interrupt controllers. */
125	PicState aPics[2];
126	/** Pointer to the device instance - R3 Ptr. */
127	PPDMDEVINSR3 pDevInsR3;
128	/** Pointer to the PIC R3 helpers. */
129	PCPDMPICHLPR3 pPicHlpR3;
130	/** Pointer to the device instance - R0 Ptr. */
131	PPDMDEVINSR0 pDevInsR0;
132	/** Pointer to the PIC R0 helpers. */
133	PCPDMPICHLPR0 pPicHlpR0;
134	/** Pointer to the device instance - RC Ptr. */
135	PPDMDEVINSRC pDevInsRC;
136	/** Pointer to the PIC RC helpers. */
137	PCPDMPICHLPRC pPicHlpRC;
138	#ifdef VBOX_WITH_STATISTICS
139	STAMCOUNTER StatSetIrqGC;
140	STAMCOUNTER StatSetIrqHC;
141	STAMCOUNTER StatClearedActiveIRQ2;
142	STAMCOUNTER StatClearedActiveMasterIRQ;
143	STAMCOUNTER StatClearedActiveSlaveIRQ;
144	#endif
145	} DEVPIC, *PDEVPIC;
146
147
148	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
149	#ifdef LOG_ENABLED
150	static inline void DumpPICState(PicState s, const char szFn)
151	{
152	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
153
154	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
155	szFn, (&pThis->aPics[0] == s) ? 0 : 1,
156	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
157	}
158	#else
159	# define DumpPICState(pThis, szFn) do { } while (0)
160	#endif
161
162	/* set irq level. If an edge is detected, then the IRR is set to 1 */
163	static inline void pic_set_irq1(PicState *s, int irq, int level)
164	{
165	int mask;
166	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
167	mask = 1 << irq;
168	if (s->elcr & mask) {
169	/* level triggered */
170	if (level) {
171	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", s->irr, s->irr \| mask));
172	s->irr \|= mask;
173	s->last_irr \|= mask;
174	} else {
175	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", s->irr, s->irr & ~mask));
176	s->irr &= ~mask;
177	s->last_irr &= ~mask;
178	}
179	} else {
180	/* edge triggered */
181	if (level) {
182	if ((s->last_irr & mask) == 0)
183	{
184	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
185	s->irr \|= mask;
186	}
187	s->last_irr \|= mask;
188	} else {
189	s->last_irr &= ~mask;
190	}
191	}
192	DumpPICState(s, "pic_set_irq1");
193	}
194
195	/* return the highest priority found in mask (highest = smallest
196	number). Return 8 if no irq */
197	static inline int get_priority(PicState *s, int mask)
198	{
199	int priority;
200	if (mask == 0)
201	return 8;
202	priority = 0;
203	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
204	priority++;
205	return priority;
206	}
207
208	/* return the pic wanted interrupt. return -1 if none */
209	static int pic_get_irq(PicState *s)
210	{
211	PicState *pics = &(PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC))->aPics[0];
212	int mask, cur_priority, priority;
213	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
214	DumpPICState(s, "pic_get_irq");
215
216	mask = s->irr & ~s->imr;
217	priority = get_priority(s, mask);
218	Log(("pic_get_irq: priority=%x\n", priority));
219	if (priority == 8)
220	return -1;
221	/* compute current priority. If special fully nested mode on the
222	master, the IRQ coming from the slave is not taken into account
223	for the priority computation. */
224	mask = s->isr;
225	if (s->special_fully_nested_mode && s == &pics[0])
226	mask &= ~(1 << 2);
227	cur_priority = get_priority(s, mask);
228	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
229	if (priority < cur_priority) {
230	/* higher priority found: an irq should be generated */
231	return (priority + s->priority_add) & 7;
232	} else {
233	return -1;
234	}
235	}
236
237	/* raise irq to CPU if necessary. must be called every time the active
238	irq may change */
239	static int pic_update_irq(PDEVPIC pThis)
240	{
241	PicState *pics = &pThis->aPics[0];
242	int irq2, irq;
243
244	/* first look at slave pic */
245	irq2 = pic_get_irq(&pics[1]);
246	Log(("pic_update_irq irq2=%d\n", irq2));
247	if (irq2 >= 0) {
248	/* if irq request by slave pic, signal master PIC */
249	pic_set_irq1(&pics[0], 2, 1);
250	pic_set_irq1(&pics[0], 2, 0);
251	}
252	/* look at requested irq */
253	irq = pic_get_irq(&pics[0]);
254	if (irq >= 0)
255	{
256	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
257	* spurious slave interrupts in picGetInterrupt.
258	*/
259	if (irq != 2 \|\| irq2 != -1)
260	{
261	#if defined(DEBUG_PIC)
262	int i;
263	for(i = 0; i < 2; i++) {
264	Log(("pic%d: imr=%x irr=%x padd=%d\n",
265	i, pics[i].imr, pics[i].irr,
266	pics[i].priority_add));
267	}
268	Log(("pic: cpu_interrupt\n"));
269	#endif
270	pThis->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pThis->CTX_SUFF(pDevIns));
271	}
272	else
273	{
274	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
275	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
276	/* Clear it here, so lower priority interrupts can still be dispatched. */
277
278	/* if this was the only pending irq, then we must clear the interrupt ff flag */
279	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
280
281	/** @note Is this correct? */
282	pics[0].irr &= ~(1 << 2);
283
284	/* Call ourselves again just in case other interrupts are pending */
285	return pic_update_irq(pThis);
286	}
287	}
288	else
289	{
290	Log(("pic_update_irq: no interrupt is pending!!\n"));
291
292	/* we must clear the interrupt ff flag */
293	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
294	}
295	return VINF_SUCCESS;
296	}
297
298	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
299	static void pic_update_imr(PDEVPIC pThis, PicState *s, uint8_t val)
300	{
301	int irq, intno;
302	PicState *pActivePIC;
303
304	/* Query the current pending irq, if any. */
305	pActivePIC = &pThis->aPics[0];
306	intno = irq = pic_get_irq(pActivePIC);
307	if (irq == 2)
308	{
309	pActivePIC = &pThis->aPics[1];
310	irq = pic_get_irq(pActivePIC);
311	intno = irq + 8;
312	}
313
314	/* Update IMR */
315	s->imr = val;
316
317	/* If an interrupt is pending and now masked, then clear the FF flag. */
318	if ( irq >= 0
319	&& ((1 << irq) & ~pActivePIC->imr) == 0)
320	{
321	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
322	pThis->aPics[0].elcr, pThis->aPics[0].last_irr, pThis->aPics[0].irr, pThis->aPics[0].imr, pThis->aPics[0].isr, pThis->aPics[0].irq_base));
323	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
324	pThis->aPics[1].elcr, pThis->aPics[1].last_irr, pThis->aPics[1].irr, pThis->aPics[1].imr, pThis->aPics[1].isr, pThis->aPics[1].irq_base));
325
326	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
327	/** @todo Is this correct? */
328	if (intno > 7)
329	{
330	pThis->aPics[0].irr &= ~(1 << 2);
331	STAM_COUNTER_INC(&pThis->StatClearedActiveSlaveIRQ);
332	}
333	else
334	STAM_COUNTER_INC(&pThis->StatClearedActiveMasterIRQ);
335
336	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
337	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
338	}
339	}
340
341
342	/**
343	* Set the an IRQ.
344	*
345	* @param pDevIns Device instance of the PICs.
346	* @param iIrq IRQ number to set.
347	* @param iLevel IRQ level.
348	*/
349	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
350	{
351	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
352	Assert(pThis->CTX_SUFF(pDevIns) == pDevIns);
353	Assert(pThis->aPics[0].CTX_SUFF(pDevIns) == pDevIns);
354	Assert(pThis->aPics[1].CTX_SUFF(pDevIns) == pDevIns);
355	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
356
357	Log(("picSetIrq %d %d\n", iIrq, iLevel));
358	DumpPICState(&pThis->aPics[0], "picSetIrq");
359	DumpPICState(&pThis->aPics[1], "picSetIrq");
360	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
361	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
362	pic_update_irq(pThis);
363	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
364	{
365	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0);
366	pic_update_irq(pThis);
367	}
368	}
369
370
371	/* acknowledge interrupt 'irq' */
372	static inline void pic_intack(PicState *s, int irq)
373	{
374	if (s->auto_eoi) {
375	if (s->rotate_on_auto_eoi)
376	s->priority_add = (irq + 1) & 7;
377	} else {
378	s->isr \|= (1 << irq);
379	}
380	/* We don't clear a level sensitive interrupt here */
381	if (!(s->elcr & (1 << irq)))
382	{
383	Log2(("pic_intack: irr=%x irrnew=%x\n", s->irr, s->irr & ~(1 << irq)));
384	s->irr &= ~(1 << irq);
385	}
386	}
387
388
389	/**
390	* Get a pending interrupt.
391	*
392	* @returns Pending interrupt number.
393	* @param pDevIns Device instance of the PICs.
394	*/
395	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
396	{
397	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
398	int irq;
399	int irq2;
400	int intno;
401
402	/* read the irq from the PIC */
403	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
404	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
405
406	irq = pic_get_irq(&pThis->aPics[0]);
407	if (irq >= 0)
408	{
409	pic_intack(&pThis->aPics[0], irq);
410	if (irq == 2)
411	{
412	irq2 = pic_get_irq(&pThis->aPics[1]);
413	if (irq2 >= 0) {
414	pic_intack(&pThis->aPics[1], irq2);
415	}
416	else
417	{
418	/* spurious IRQ on slave controller (impossible) */
419	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
420	irq2 = 7;
421	}
422	intno = pThis->aPics[1].irq_base + irq2;
423	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pThis->aPics[1].irq_base, irq2));
424	irq = irq2 + 8;
425	}
426	else {
427	intno = pThis->aPics[0].irq_base + irq;
428	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pThis->aPics[0].irq_base, irq));
429	}
430	}
431	else
432	{
433	/* spurious IRQ on host controller (impossible) */
434	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
435	irq = 7;
436	intno = pThis->aPics[0].irq_base + irq;
437	}
438	pic_update_irq(pThis);
439
440	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
441
442	return intno;
443	}
444
445	static void pic_reset(PicState *s)
446	{
447	PPDMDEVINSR3 pDevInsR3 = s->pDevInsR3;
448	PPDMDEVINSR0 pDevInsR0 = s->pDevInsR0;
449	PPDMDEVINSRC pDevInsRC = s->pDevInsRC;
450	int elcr_mask = s->elcr_mask;
451	int elcr = s->elcr;
452
453	memset(s, 0, sizeof(PicState));
454
455	s->elcr = elcr;
456	s->elcr_mask = elcr_mask;
457	s->pDevInsRC = pDevInsRC;
458	s->pDevInsR0 = pDevInsR0;
459	s->pDevInsR3 = pDevInsR3;
460	}
461
462
463	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
464	{
465	PicState s = (PicState)opaque;
466	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
467	int rc = VINF_SUCCESS;
468	int priority, cmd, irq;
469
470	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
471	addr &= 1;
472	if (addr == 0) {
473	if (val & 0x10) {
474	/* init */
475	pic_reset(s);
476	/* deassert a pending interrupt */
477	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
478
479	s->init_state = 1;
480	s->init4 = val & 1;
481	if (val & 0x02)
482	AssertReleaseMsgFailed(("single mode not supported"));
483	if (val & 0x08)
484	AssertReleaseMsgFailed(("level sensitive irq not supported"));
485	} else if (val & 0x08) {
486	if (val & 0x04)
487	s->poll = 1;
488	if (val & 0x02)
489	s->read_reg_select = val & 1;
490	if (val & 0x40)
491	s->special_mask = (val >> 5) & 1;
492	} else {
493	cmd = val >> 5;
494	switch(cmd) {
495	case 0:
496	case 4:
497	s->rotate_on_auto_eoi = cmd >> 2;
498	break;
499	case 1: /* end of interrupt */
500	case 5:
501	{
502	priority = get_priority(s, s->isr);
503	if (priority != 8) {
504	irq = (priority + s->priority_add) & 7;
505	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
506	s->isr &= ~(1 << irq);
507	if (cmd == 5)
508	s->priority_add = (irq + 1) & 7;
509	rc = pic_update_irq(pThis);
510	Assert(rc == VINF_SUCCESS);
511	DumpPICState(s, "eoi");
512	}
513	break;
514	}
515	case 3:
516	{
517	irq = val & 7;
518	Log(("pic_write: EOI2 for irq %d\n", irq));
519	s->isr &= ~(1 << irq);
520	rc = pic_update_irq(pThis);
521	Assert(rc == VINF_SUCCESS);
522	DumpPICState(s, "eoi2");
523	break;
524	}
525	case 6:
526	{
527	s->priority_add = (val + 1) & 7;
528	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, s->priority_add));
529	rc = pic_update_irq(pThis);
530	Assert(rc == VINF_SUCCESS);
531	break;
532	}
533	case 7:
534	{
535	irq = val & 7;
536	Log(("pic_write: EOI3 for irq %d\n", irq));
537	s->isr &= ~(1 << irq);
538	s->priority_add = (irq + 1) & 7;
539	rc = pic_update_irq(pThis);
540	Assert(rc == VINF_SUCCESS);
541	DumpPICState(s, "eoi3");
542	break;
543	}
544	default:
545	/* no operation */
546	break;
547	}
548	}
549	} else {
550	switch(s->init_state) {
551	case 0:
552	{
553	/* normal mode */
554	pic_update_imr(pThis, s, val);
555
556	rc = pic_update_irq(pThis);
557	Assert(rc == VINF_SUCCESS);
558	break;
559	}
560	case 1:
561	s->irq_base = val & 0xf8;
562	s->init_state = 2;
563	Log(("pic_write: set irq base to %x\n", s->irq_base));
564	break;
565	case 2:
566	if (s->init4) {
567	s->init_state = 3;
568	} else {
569	s->init_state = 0;
570	}
571	break;
572	case 3:
573	s->special_fully_nested_mode = (val >> 4) & 1;
574	s->auto_eoi = (val >> 1) & 1;
575	s->init_state = 0;
576	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
577	break;
578	}
579	}
580	return rc;
581	}
582
583
584	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
585	{
586	PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
587	PicState *pics = &pThis->aPics[0];
588	int ret;
589
590	ret = pic_get_irq(s);
591	if (ret >= 0) {
592	if (addr1 >> 7) {
593	Log2(("pic_poll_read: clear slave irq (isr)\n"));
594	pics[0].isr &= ~(1 << 2);
595	pics[0].irr &= ~(1 << 2);
596	}
597	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
598	s->irr &= ~(1 << ret);
599	s->isr &= ~(1 << ret);
600	if (addr1 >> 7 \|\| ret != 2)
601	pic_update_irq(pThis);
602	} else {
603	ret = 0x07;
604	pic_update_irq(pThis);
605	}
606
607	return ret;
608	}
609
610
611	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
612	{
613	PicState s = (PicState)opaque;
614	unsigned int addr;
615	int ret;
616
617	*pRC = VINF_SUCCESS;
618
619	addr = addr1;
620	addr &= 1;
621	if (s->poll) {
622	ret = pic_poll_read(s, addr1);
623	s->poll = 0;
624	} else {
625	if (addr == 0) {
626	if (s->read_reg_select)
627	ret = s->isr;
628	else
629	ret = s->irr;
630	} else {
631	ret = s->imr;
632	}
633	}
634	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
635	return ret;
636	}
637
638
639
640	/* -=-=-=-=-=- wrappers / stuff -=-=-=-=-=- */
641
642	/**
643	* Port I/O Handler for IN operations.
644	*
645	* @returns VBox status code.
646	*
647	* @param pDevIns The device instance.
648	* @param pvUser User argument - pointer to the PIC in question.
649	* @param uPort Port number used for the IN operation.
650	* @param pu32 Where to store the result.
651	* @param cb Number of bytes read.
652	*/
653	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
654	{
655	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
656	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
657
658	Assert(iPic == 0 \|\| iPic == 1);
659	if (cb == 1)
660	{
661	int rc;
662	PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_READ);
663	*pu32 = pic_ioport_read(&pThis->aPics[iPic], Port, &rc);
664	PIC_UNLOCK(pThis);
665	return rc;
666	}
667	return VERR_IOM_IOPORT_UNUSED;
668	}
669
670	/**
671	* Port I/O Handler for OUT operations.
672	*
673	* @returns VBox status code.
674	*
675	* @param pDevIns The device instance.
676	* @param pvUser User argument - pointer to the PIC in question.
677	* @param uPort Port number used for the IN operation.
678	* @param u32 The value to output.
679	* @param cb The value size in bytes.
680	*/
681	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
682	{
683	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
684	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
685
686	Assert(iPic == 0 \|\| iPic == 1);
687
688	if (cb == 1)
689	{
690	int rc;
691	PIC_LOCK(pThis, VINF_IOM_HC_IOPORT_WRITE);
692	rc = pic_ioport_write(&pThis->aPics[iPic], Port, u32);
693	PIC_UNLOCK(pThis);
694	return rc;
695	}
696	return VINF_SUCCESS;
697	}
698
699
700	/**
701	* Port I/O Handler for IN operations.
702	*
703	* @returns VBox status code.
704	*
705	* @param pDevIns The device instance.
706	* @param pvUser User argument - pointer to the PIC in question.
707	* @param uPort Port number used for the IN operation.
708	* @param pu32 Where to store the result.
709	* @param cb Number of bytes read.
710	*/
711	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
712	{
713	if (cb == 1)
714	{
715	PicState s = (PicState)pvUser;
716	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
717	*pu32 = s->elcr;
718	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
719	return VINF_SUCCESS;
720	}
721	return VERR_IOM_IOPORT_UNUSED;
722	}
723
724	/**
725	* Port I/O Handler for OUT operations.
726	*
727	* @returns VBox status code.
728	*
729	* @param pDevIns The device instance.
730	* @param pvUser User argument - pointer to the PIC in question.
731	* @param uPort Port number used for the IN operation.
732	* @param u32 The value to output.
733	* @param cb The value size in bytes.
734	*/
735	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
736	{
737	if (cb == 1)
738	{
739	PicState s = (PicState)pvUser;
740	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
741	s->elcr = u32 & s->elcr_mask;
742	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
743	}
744	return VINF_SUCCESS;
745	}
746
747
748	#ifdef IN_RING3
749
750	/**
751	* PIC status info callback.
752	*
753	* @param pDevIns The device instance.
754	* @param pHlp The output helpers.
755	* @param pszArgs The arguments.
756	*/
757	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
758	{
759	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
760
761	/*
762	* Show info.
763	*/
764	for (int i=0;i<2;i++)
765	{
766	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
767	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pThis->aPics[i].last_irr);
768	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pThis->aPics[i].irr);
769	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pThis->aPics[i].imr);
770	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pThis->aPics[i].isr);
771	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pThis->aPics[i].priority_add);
772	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pThis->aPics[i].irq_base);
773	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pThis->aPics[i].read_reg_select);
774	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pThis->aPics[i].poll);
775	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pThis->aPics[i].special_mask);
776	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pThis->aPics[i].init_state);
777	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pThis->aPics[i].auto_eoi);
778	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pThis->aPics[i].rotate_on_auto_eoi);
779	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pThis->aPics[i].special_fully_nested_mode);
780	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pThis->aPics[i].init4);
781	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pThis->aPics[i].elcr);
782	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pThis->aPics[i].elcr_mask);
783	}
784	}
785
786	/**
787	* Saves a state of the programmable interrupt controller device.
788	*
789	* @returns VBox status code.
790	* @param pDevIns The device instance.
791	* @param pSSMHandle The handle to save the state to.
792	*/
793	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
794	{
795	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
796	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
797	{
798	SSMR3PutU8(pSSMHandle, pThis->aPics[i].last_irr);
799	SSMR3PutU8(pSSMHandle, pThis->aPics[i].irr);
800	SSMR3PutU8(pSSMHandle, pThis->aPics[i].imr);
801	SSMR3PutU8(pSSMHandle, pThis->aPics[i].isr);
802	SSMR3PutU8(pSSMHandle, pThis->aPics[i].priority_add);
803	SSMR3PutU8(pSSMHandle, pThis->aPics[i].irq_base);
804	SSMR3PutU8(pSSMHandle, pThis->aPics[i].read_reg_select);
805	SSMR3PutU8(pSSMHandle, pThis->aPics[i].poll);
806	SSMR3PutU8(pSSMHandle, pThis->aPics[i].special_mask);
807	SSMR3PutU8(pSSMHandle, pThis->aPics[i].init_state);
808	SSMR3PutU8(pSSMHandle, pThis->aPics[i].auto_eoi);
809	SSMR3PutU8(pSSMHandle, pThis->aPics[i].rotate_on_auto_eoi);
810	SSMR3PutU8(pSSMHandle, pThis->aPics[i].special_fully_nested_mode);
811	SSMR3PutU8(pSSMHandle, pThis->aPics[i].init4);
812	SSMR3PutU8(pSSMHandle, pThis->aPics[i].elcr);
813	}
814	return VINF_SUCCESS;
815	}
816
817
818	/**
819	* Loads a saved programmable interrupt controller device state.
820	*
821	* @returns VBox status code.
822	* @param pDevIns The device instance.
823	* @param pSSMHandle The handle to the saved state.
824	* @param uVersion The data unit version number.
825	* @param uPass The data pass.
826	*/
827	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
828	{
829	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
830
831	if (uVersion != 1)
832	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
833	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
834
835	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
836	{
837	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].last_irr);
838	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].irr);
839	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].imr);
840	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].isr);
841	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].priority_add);
842	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].irq_base);
843	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].read_reg_select);
844	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].poll);
845	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].special_mask);
846	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].init_state);
847	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].auto_eoi);
848	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].rotate_on_auto_eoi);
849	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].special_fully_nested_mode);
850	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].init4);
851	SSMR3GetU8(pSSMHandle, &pThis->aPics[i].elcr);
852	}
853	return VINF_SUCCESS;
854	}
855
856
857	/* -=-=-=-=-=- real code -=-=-=-=-=- */
858
859	/**
860	* Reset notification.
861	*
862	* @returns VBox status.
863	* @param pDevIns The device instance data.
864	*/
865	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
866	{
867	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
868	unsigned i;
869	LogFlow(("picReset:\n"));
870	pThis->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
871
872	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
873	pic_reset(&pThis->aPics[i]);
874
875	PIC_UNLOCK(pThis);
876	}
877
878
879	/**
880	* @copydoc FNPDMDEVRELOCATE
881	*/
882	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
883	{
884	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
885	unsigned i;
886
887	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
888	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
889	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
890	pThis->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
891	}
892
893
894	/**
895	* @copydoc FNPDMDEVCONSTRUCT
896	*/
897	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
898	{
899	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
900	PDMPICREG PicReg;
901	int rc;
902	bool fGCEnabled;
903	bool fR0Enabled;
904	Assert(iInstance == 0);
905
906	/*
907	* Validate and read configuration.
908	*/
909	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
910	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
911
912	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
913	if (RT_FAILURE(rc))
914	return PDMDEV_SET_ERROR(pDevIns, rc,
915	N_("Configuration error: failed to read GCEnabled as boolean"));
916
917	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
918	if (RT_FAILURE(rc))
919	return PDMDEV_SET_ERROR(pDevIns, rc,
920	N_("Configuration error: failed to read R0Enabled as boolean"));
921
922	Log(("DevPIC: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
923
924	/*
925	* Init the data.
926	*/
927	Assert(RT_ELEMENTS(pThis->aPics) == 2);
928	pThis->pDevInsR3 = pDevIns;
929	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
930	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
931	pThis->aPics[0].elcr_mask = 0xf8;
932	pThis->aPics[1].elcr_mask = 0xde;
933	pThis->aPics[0].pDevInsR3 = pDevIns;
934	pThis->aPics[1].pDevInsR3 = pDevIns;
935	pThis->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
936	pThis->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
937	pThis->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
938	pThis->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
939
940	/*
941	* Register us as the PIC with PDM.
942	*/
943	PicReg.u32Version = PDM_PICREG_VERSION;
944	PicReg.pfnSetIrqR3 = picSetIrq;
945	PicReg.pfnGetInterruptR3 = picGetInterrupt;
946
947	if (fGCEnabled)
948	{
949	PicReg.pszSetIrqRC = "picSetIrq";
950	PicReg.pszGetInterruptRC = "picGetInterrupt";
951	}
952	else
953	{
954	PicReg.pszSetIrqRC = NULL;
955	PicReg.pszGetInterruptRC = NULL;
956	}
957
958	if (fR0Enabled)
959	{
960	PicReg.pszSetIrqR0 = "picSetIrq";
961	PicReg.pszGetInterruptR0 = "picGetInterrupt";
962	}
963	else
964	{
965	PicReg.pszSetIrqR0 = NULL;
966	PicReg.pszGetInterruptR0 = NULL;
967	}
968
969	rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThis->pPicHlpR3);
970	AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Rrc\n", rc), rc);
971	if (fGCEnabled)
972	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
973	if (fR0Enabled)
974	pThis->pPicHlpR0 = pThis->pPicHlpR3->pfnGetR0Helpers(pDevIns);
975
976
977	/*
978	* Register I/O ports and save state.
979	*/
980	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
981	if (RT_FAILURE(rc))
982	return rc;
983	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
984	if (RT_FAILURE(rc))
985	return rc;
986	if (fGCEnabled)
987	{
988	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
989	if (RT_FAILURE(rc))
990	return rc;
991	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
992	if (RT_FAILURE(rc))
993	return rc;
994	}
995	if (fR0Enabled)
996	{
997	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
998	if (RT_FAILURE(rc))
999	return rc;
1000	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1001	if (RT_FAILURE(rc))
1002	return rc;
1003	}
1004
1005	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pThis->aPics[0],
1006	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1007	if (RT_FAILURE(rc))
1008	return rc;
1009	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pThis->aPics[1],
1010	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1011	if (RT_FAILURE(rc))
1012	return rc;
1013	if (fGCEnabled)
1014	{
1015	RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns);
1016	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),
1017	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1018	if (RT_FAILURE(rc))
1019	return rc;
1020	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),
1021	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1022	if (RT_FAILURE(rc))
1023	return rc;
1024	}
1025	if (fR0Enabled)
1026	{
1027	RTR0PTR pDataR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1028	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1029	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1030	if (RT_FAILURE(rc))
1031	return rc;
1032	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1033	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1034	if (RT_FAILURE(rc))
1035	return rc;
1036	}
1037
1038	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion /, sizeof(pThis), picSaveExec, picLoadExec);
1039	if (RT_FAILURE(rc))
1040	return rc;
1041
1042
1043	/*
1044	* Register the info item.
1045	*/
1046	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1047
1048	/*
1049	* Initialize the device state.
1050	*/
1051	picReset(pDevIns);
1052
1053	#ifdef VBOX_WITH_STATISTICS
1054	/*
1055	* Statistics.
1056	*/
1057	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1058	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1059
1060	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1061	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1062	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1063	#endif
1064
1065	return VINF_SUCCESS;
1066	}
1067
1068
1069	/**
1070	* The device registration structure.
1071	*/
1072	const PDMDEVREG g_DeviceI8259 =
1073	{
1074	/* u32Version */
1075	PDM_DEVREG_VERSION,
1076	/* szName */
1077	"i8259",
1078	/* szRCMod */
1079	"VBoxDDGC.gc",
1080	/* szR0Mod */
1081	"VBoxDDR0.r0",
1082	/* pszDescription */
1083	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1084	/* fFlags */
1085	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1086	/* fClass */
1087	PDM_DEVREG_CLASS_PIC,
1088	/* cMaxInstances */
1089	1,
1090	/* cbInstance */
1091	sizeof(DEVPIC),
1092	/* pfnConstruct */
1093	picConstruct,
1094	/* pfnDestruct */
1095	NULL,
1096	/* pfnRelocate */
1097	picRelocate,
1098	/* pfnIOCtl */
1099	NULL,
1100	/* pfnPowerOn */
1101	NULL,
1102	/* pfnReset */
1103	picReset,
1104	/* pfnSuspend */
1105	NULL,
1106	/* pfnResume */
1107	NULL,
1108	/* pfnAttach */
1109	NULL,
1110	/* pfnDetach */
1111	NULL,
1112	/* pfnQueryInterface. */
1113	NULL,
1114	/* pfnInitComplete */
1115	NULL,
1116	/* pfnPowerOff */
1117	NULL,
1118	/* pfnSoftReset */
1119	NULL,
1120	/* u32VersionEnd */
1121	PDM_DEVREG_VERSION
1122	};
1123
1124	#endif /* IN_RING3 */
1125	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1126

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 33595

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