DevPIC.cpp@ 3867

Last change on this file since 3867 was 3489, checked in by vboxsync, 18 years ago
Clear interrupt action flag when a spurious interrupt situation is detected. (-> dangerous change)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 36.7 KB

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1	/* $Id: DevPIC.cpp 3489 2007-07-06 11:15:52Z vboxsync $ */
2	/** @file
3	* Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PIC
26	#include <VBox/pdm.h>
27	#include <VBox/log.h>
28	#include <iprt/assert.h>
29
30	#include "vl_vbox.h"
31
32
33	/*******************************************************************************
34	* Defined Constants And Macros *
35	*******************************************************************************/
36	/** @def PIC_LOCK
37	* Acquires the PDM lock. This is a NOP if locking is disabled. */
38	/** @def PIC_UNLOCK
39	* Releases the PDM lock. This is a NOP if locking is disabled. */
40	#ifdef VBOX_WITH_PDM_LOCK
41	# define PIC_LOCK(pThis, rc) \
42	do { \
43	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
44	if (rc2 != VINF_SUCCESS) \
45	return rc2; \
46	} while (0)
47	# define PIC_UNLOCK(pThis) \
48	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
49	#else /* !VBOX_WITH_PDM_LOCK */
50	# define PIC_LOCK(pThis, rc) do { } while (0)
51	# define PIC_UNLOCK(pThis) do { } while (0)
52	#endif /* !VBOX_WITH_PDM_LOCK */
53
54
55	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
56	/*******************************************************************************
57	* Internal Functions *
58	*******************************************************************************/
59	__BEGIN_DECLS
60
61	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
62	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
63	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
64	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
65	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
66	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
67
68	__END_DECLS
69	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
70
71
72	/*
73	* QEMU 8259 interrupt controller emulation
74	*
75	* Copyright (c) 2003-2004 Fabrice Bellard
76	*
77	* Permission is hereby granted, free of charge, to any person obtaining a copy
78	* of this software and associated documentation files (the "Software"), to deal
79	* in the Software without restriction, including without limitation the rights
80	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
81	* copies of the Software, and to permit persons to whom the Software is
82	* furnished to do so, subject to the following conditions:
83	*
84	* The above copyright notice and this permission notice shall be included in
85	* all copies or substantial portions of the Software.
86	*
87	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
88	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
89	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
90	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
91	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
92	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
93	* THE SOFTWARE.
94	*/
95
96	/* debug PIC */
97	#define DEBUG_PIC
98
99	/#define DEBUG_IRQ_COUNT/
100
101	typedef struct PicState {
102	uint8_t last_irr; /* edge detection */
103	uint8_t irr; /* interrupt request register */
104	uint8_t imr; /* interrupt mask register */
105	uint8_t isr; /* interrupt service register */
106	uint8_t priority_add; /* highest irq priority */
107	uint8_t irq_base;
108	uint8_t read_reg_select;
109	uint8_t poll;
110	uint8_t special_mask;
111	uint8_t init_state;
112	uint8_t auto_eoi;
113	uint8_t rotate_on_auto_eoi;
114	uint8_t special_fully_nested_mode;
115	uint8_t init4; /* true if 4 byte init */
116	uint8_t elcr; /* PIIX edge/trigger selection*/
117	uint8_t elcr_mask;
118	/** Pointer to the device instance, HCPtr. */
119	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
120	/** Pointer to the device instance, GCPtr. */
121	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
122	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS != 64
123	RTGCPTR Alignment0;
124	#endif
125	} PicState;
126
127	/**
128	* A PIC device instance data.
129	*/
130	typedef struct DEVPIC
131	{
132	/** The two interrupt controllers. */
133	PicState aPics[2];
134	/** Pointer to the PIC R3 helpers. */
135	PCPDMPICHLPR3 pPicHlpR3;
136	/** Pointer to the PIC R0 helpers. */
137	PCPDMPICHLPR0 pPicHlpR0;
138	/** Pointer to the PIC GC helpers. */
139	PCPDMPICHLPGC pPicHlpGC;
140	/** Pointer to the device instance - GC Ptr. */
141	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
142	/** Pointer to the device instance - GC Ptr. */
143	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
144	#if HC_ARCH_BITS == 32
145	uint32_t Alignmnet0;
146	#endif
147	#ifdef VBOX_WITH_STATISTICS
148	STAMCOUNTER StatSetIrqGC;
149	STAMCOUNTER StatSetIrqHC;
150	STAMCOUNTER StatClearedActiveIRQ2;
151	STAMCOUNTER StatClearedActiveMasterIRQ;
152	STAMCOUNTER StatClearedActiveSlaveIRQ;
153	#endif
154	} DEVPIC, *PDEVPIC;
155
156
157	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
158	#ifdef LOG_ENABLED
159	static inline void DumpPICState(PicState s, const char szFn)
160	{
161	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
162
163	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
164	szFn, (&pData->aPics[0] == s) ? 0 : 1,
165	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
166	}
167	#else
168	# define DumpPICState(pData, szFn) do { } while (0)
169	#endif
170
171	/* set irq level. If an edge is detected, then the IRR is set to 1 */
172	static inline void pic_set_irq1(PicState *s, int irq, int level)
173	{
174	int mask;
175	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
176	mask = 1 << irq;
177	if (s->elcr & mask) {
178	/* level triggered */
179	if (level) {
180	s->irr \|= mask;
181	s->last_irr \|= mask;
182	} else {
183	s->irr &= ~mask;
184	s->last_irr &= ~mask;
185	}
186	} else {
187	/* edge triggered */
188	if (level) {
189	if ((s->last_irr & mask) == 0)
190	{
191	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
192	s->irr \|= mask;
193	}
194	s->last_irr \|= mask;
195	} else {
196	s->last_irr &= ~mask;
197	}
198	}
199	DumpPICState(s, "pic_set_irq1");
200	}
201
202	/* return the highest priority found in mask (highest = smallest
203	number). Return 8 if no irq */
204	static inline int get_priority(PicState *s, int mask)
205	{
206	int priority;
207	if (mask == 0)
208	return 8;
209	priority = 0;
210	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
211	priority++;
212	return priority;
213	}
214
215	/* return the pic wanted interrupt. return -1 if none */
216	static int pic_get_irq(PicState *s)
217	{
218	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
219	int mask, cur_priority, priority;
220	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
221	DumpPICState(s, "pic_get_irq");
222
223	mask = s->irr & ~s->imr;
224	priority = get_priority(s, mask);
225	Log(("pic_get_irq: priority=%x\n", priority));
226	if (priority == 8)
227	return -1;
228	/* compute current priority. If special fully nested mode on the
229	master, the IRQ coming from the slave is not taken into account
230	for the priority computation. */
231	mask = s->isr;
232	if (s->special_fully_nested_mode && s == &pics[0])
233	mask &= ~(1 << 2);
234	cur_priority = get_priority(s, mask);
235	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
236	if (priority < cur_priority) {
237	/* higher priority found: an irq should be generated */
238	return (priority + s->priority_add) & 7;
239	} else {
240	return -1;
241	}
242	}
243
244	/* raise irq to CPU if necessary. must be called every time the active
245	irq may change */
246	static int pic_update_irq(PDEVPIC pData)
247	{
248	PicState *pics = &pData->aPics[0];
249	int irq2, irq;
250
251	/* first look at slave pic */
252	irq2 = pic_get_irq(&pics[1]);
253	Log(("pic_update_irq irq2=%d\n", irq2));
254	if (irq2 >= 0) {
255	/* if irq request by slave pic, signal master PIC */
256	pic_set_irq1(&pics[0], 2, 1);
257	pic_set_irq1(&pics[0], 2, 0);
258	}
259	/* look at requested irq */
260	irq = pic_get_irq(&pics[0]);
261	if (irq >= 0)
262	{
263	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
264	* spurious slave interrupts in picGetInterrupt.
265	*/
266	if (irq != 2 \|\| irq2 != -1)
267	{
268	#if defined(DEBUG_PIC)
269	int i;
270	for(i = 0; i < 2; i++) {
271	Log(("pic%d: imr=%x irr=%x padd=%d\n",
272	i, pics[i].imr, pics[i].irr,
273	pics[i].priority_add));
274	}
275	Log(("pic: cpu_interrupt\n"));
276	#endif
277	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
278	}
279	else
280	{
281	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
282	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
283	/* Clear it here, so lower priority interrupts can still be dispatched. */
284
285	/* if this was the only pending irq, then we must clear the interrupt ff flag */
286	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
287
288	/** @note Is this correct? */
289	pics[0].irr &= ~(1 << 2);
290
291	/* Call ourselves again just in case other interrupts are pending */
292	return pic_update_irq(pData);
293	}
294	}
295	return VINF_SUCCESS;
296	}
297
298	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
299	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
300	{
301	int irq, intno;
302	PicState *pActivePIC;
303
304	/* Query the current pending irq, if any. */
305	pActivePIC = &pData->aPics[0];
306	intno = irq = pic_get_irq(pActivePIC);
307	if (irq == 2)
308	{
309	pActivePIC = &pData->aPics[1];
310	irq = pic_get_irq(pActivePIC);
311	intno = irq + 8;
312	}
313
314	/* Update IMR */
315	s->imr = val;
316
317	/* If an interrupt is pending and now masked, then clear the FF flag. */
318	if ( irq >= 0
319	&& ((1 << irq) & ~pActivePIC->imr) == 0)
320	{
321	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
322	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
323	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
324	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
325
326	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
327	/** @todo Is this correct? */
328	if (intno > 7)
329	{
330	pData->aPics[0].irr &= ~(1 << 2);
331	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
332	}
333	else
334	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
335
336	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
337	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
338	}
339	}
340
341
342	/**
343	* Set the an IRQ.
344	*
345	* @param pDevIns Device instance of the PICs.
346	* @param iIrq IRQ number to set.
347	* @param iLevel IRQ level.
348	*/
349	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
350	{
351	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
352	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
353	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
354	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
355	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
356
357	Log(("picSetIrq %d %d\n", iIrq, iLevel));
358	DumpPICState(&pData->aPics[0], "picSetIrq");
359	DumpPICState(&pData->aPics[1], "picSetIrq");
360	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
361	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
362	pic_update_irq(pData);
363	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
364	{
365	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, 0);
366	pic_update_irq(pData);
367	}
368	}
369
370
371	/* acknowledge interrupt 'irq' */
372	static inline void pic_intack(PicState *s, int irq)
373	{
374	if (s->auto_eoi) {
375	if (s->rotate_on_auto_eoi)
376	s->priority_add = (irq + 1) & 7;
377	} else {
378	s->isr \|= (1 << irq);
379	}
380	/* We don't clear a level sensitive interrupt here */
381	if (!(s->elcr & (1 << irq)))
382	s->irr &= ~(1 << irq);
383	}
384
385
386	/**
387	* Get a pending interrupt.
388	*
389	* @returns Pending interrupt number.
390	* @param pDevIns Device instance of the PICs.
391	*/
392	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
393	{
394	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
395	int irq;
396	int irq2;
397	int intno;
398
399	/* read the irq from the PIC */
400	DumpPICState(&pData->aPics[0], "picGetInterrupt");
401	DumpPICState(&pData->aPics[1], "picGetInterrupt");
402
403	irq = pic_get_irq(&pData->aPics[0]);
404	if (irq >= 0)
405	{
406	pic_intack(&pData->aPics[0], irq);
407	if (irq == 2)
408	{
409	irq2 = pic_get_irq(&pData->aPics[1]);
410	if (irq2 >= 0) {
411	pic_intack(&pData->aPics[1], irq2);
412	}
413	else
414	{
415	/* spurious IRQ on slave controller (impossible) */
416	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
417	irq2 = 7;
418	}
419	intno = pData->aPics[1].irq_base + irq2;
420	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
421	irq = irq2 + 8;
422	}
423	else {
424	intno = pData->aPics[0].irq_base + irq;
425	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
426	}
427	}
428	else
429	{
430	/* spurious IRQ on host controller (impossible) */
431	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
432	irq = 7;
433	intno = pData->aPics[0].irq_base + irq;
434	}
435	pic_update_irq(pData);
436
437	Log(("picGetInterrupt: pending 0:%d 1:%d\n", pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
438
439	return intno;
440	}
441
442	static void pic_reset(PicState *s)
443	{
444	HCPTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
445	GCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
446	int tmp, tmp2;
447
448	tmp = s->elcr_mask;
449	tmp2 = s->elcr;
450	memset(s, 0, sizeof(PicState));
451	s->elcr_mask = tmp;
452	s->elcr = tmp2;
453	s->pDevInsHC = pDevInsHC;
454	s->pDevInsGC = pDevInsGC;
455	}
456
457
458	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
459	{
460	PicState s = (PicState)opaque;
461	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
462	int rc = VINF_SUCCESS;
463	int priority, cmd, irq;
464
465	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
466	addr &= 1;
467	if (addr == 0) {
468	if (val & 0x10) {
469	/* init */
470	pic_reset(s);
471	/* deassert a pending interrupt */
472	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
473
474	s->init_state = 1;
475	s->init4 = val & 1;
476	if (val & 0x02)
477	AssertReleaseMsgFailed(("single mode not supported"));
478	if (val & 0x08)
479	AssertReleaseMsgFailed(("level sensitive irq not supported"));
480	} else if (val & 0x08) {
481	if (val & 0x04)
482	s->poll = 1;
483	if (val & 0x02)
484	s->read_reg_select = val & 1;
485	if (val & 0x40)
486	s->special_mask = (val >> 5) & 1;
487	} else {
488	cmd = val >> 5;
489	switch(cmd) {
490	case 0:
491	case 4:
492	s->rotate_on_auto_eoi = cmd >> 2;
493	break;
494	case 1: /* end of interrupt */
495	case 5:
496	{
497	priority = get_priority(s, s->isr);
498	if (priority != 8) {
499	irq = (priority + s->priority_add) & 7;
500	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
501	s->isr &= ~(1 << irq);
502	if (cmd == 5)
503	s->priority_add = (irq + 1) & 7;
504	rc = pic_update_irq(pData);
505	Assert(rc == VINF_SUCCESS);
506	}
507	break;
508	}
509	case 3:
510	{
511	irq = val & 7;
512	Log(("pic_write: EOI2 for irq %d\n", irq));
513	s->isr &= ~(1 << irq);
514	rc = pic_update_irq(pData);
515	Assert(rc == VINF_SUCCESS);
516	break;
517	}
518	case 6:
519	{
520	s->priority_add = (val + 1) & 7;
521	rc = pic_update_irq(pData);
522	Assert(rc == VINF_SUCCESS);
523	break;
524	}
525	case 7:
526	{
527	irq = val & 7;
528	Log(("pic_write: EOI3 for irq %d\n", irq));
529	s->isr &= ~(1 << irq);
530	s->priority_add = (irq + 1) & 7;
531	rc = pic_update_irq(pData);
532	Assert(rc == VINF_SUCCESS);
533	break;
534	}
535	default:
536	/* no operation */
537	break;
538	}
539	}
540	} else {
541	switch(s->init_state) {
542	case 0:
543	{
544	/* normal mode */
545	pic_update_imr(pData, s, val);
546
547	rc = pic_update_irq(pData);
548	Assert(rc == VINF_SUCCESS);
549	break;
550	}
551	case 1:
552	s->irq_base = val & 0xf8;
553	s->init_state = 2;
554	Log(("pic_write: set irq base to %x\n", s->irq_base));
555	break;
556	case 2:
557	if (s->init4) {
558	s->init_state = 3;
559	} else {
560	s->init_state = 0;
561	}
562	break;
563	case 3:
564	s->special_fully_nested_mode = (val >> 4) & 1;
565	s->auto_eoi = (val >> 1) & 1;
566	s->init_state = 0;
567	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
568	break;
569	}
570	}
571	return rc;
572	}
573
574
575	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
576	{
577	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
578	PicState *pics = &pData->aPics[0];
579	int ret;
580
581	ret = pic_get_irq(s);
582	if (ret >= 0) {
583	if (addr1 >> 7) {
584	Log2(("pic_poll_read: clear slave irq (isr)\n"));
585	pics[0].isr &= ~(1 << 2);
586	pics[0].irr &= ~(1 << 2);
587	}
588	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
589	s->irr &= ~(1 << ret);
590	s->isr &= ~(1 << ret);
591	if (addr1 >> 7 \|\| ret != 2)
592	pic_update_irq(pData);
593	} else {
594	ret = 0x07;
595	pic_update_irq(pData);
596	}
597
598	return ret;
599	}
600
601
602	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
603	{
604	PicState s = (PicState)opaque;
605	unsigned int addr;
606	int ret;
607
608	*pRC = VINF_SUCCESS;
609
610	addr = addr1;
611	addr &= 1;
612	if (s->poll) {
613	ret = pic_poll_read(s, addr1);
614	s->poll = 0;
615	} else {
616	if (addr == 0) {
617	if (s->read_reg_select)
618	ret = s->isr;
619	else
620	ret = s->irr;
621	} else {
622	ret = s->imr;
623	}
624	}
625	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
626	return ret;
627	}
628
629
630
631	#ifdef IN_RING3
632
633	static void pic_save(QEMUFile f, void opaque)
634	{
635	PicState s = (PicState)opaque;
636
637	qemu_put_8s(f, &s->last_irr);
638	qemu_put_8s(f, &s->irr);
639	qemu_put_8s(f, &s->imr);
640	qemu_put_8s(f, &s->isr);
641	qemu_put_8s(f, &s->priority_add);
642	qemu_put_8s(f, &s->irq_base);
643	qemu_put_8s(f, &s->read_reg_select);
644	qemu_put_8s(f, &s->poll);
645	qemu_put_8s(f, &s->special_mask);
646	qemu_put_8s(f, &s->init_state);
647	qemu_put_8s(f, &s->auto_eoi);
648	qemu_put_8s(f, &s->rotate_on_auto_eoi);
649	qemu_put_8s(f, &s->special_fully_nested_mode);
650	qemu_put_8s(f, &s->init4);
651	qemu_put_8s(f, &s->elcr);
652	}
653
654	static int pic_load(QEMUFile f, void opaque, int version_id)
655	{
656	PicState s = (PicState)opaque;
657
658	if (version_id != 1)
659	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
660
661	qemu_get_8s(f, &s->last_irr);
662	qemu_get_8s(f, &s->irr);
663	qemu_get_8s(f, &s->imr);
664	qemu_get_8s(f, &s->isr);
665	qemu_get_8s(f, &s->priority_add);
666	qemu_get_8s(f, &s->irq_base);
667	qemu_get_8s(f, &s->read_reg_select);
668	qemu_get_8s(f, &s->poll);
669	qemu_get_8s(f, &s->special_mask);
670	qemu_get_8s(f, &s->init_state);
671	qemu_get_8s(f, &s->auto_eoi);
672	qemu_get_8s(f, &s->rotate_on_auto_eoi);
673	qemu_get_8s(f, &s->special_fully_nested_mode);
674	qemu_get_8s(f, &s->init4);
675	qemu_get_8s(f, &s->elcr);
676	return 0;
677	}
678	#endif /* IN_RING3 */
679
680
681	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
682
683	/**
684	* Port I/O Handler for IN operations.
685	*
686	* @returns VBox status code.
687	*
688	* @param pDevIns The device instance.
689	* @param pvUser User argument - pointer to the PIC in question.
690	* @param uPort Port number used for the IN operation.
691	* @param pu32 Where to store the result.
692	* @param cb Number of bytes read.
693	*/
694	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
695	{
696	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
697	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
698
699	Assert(iPic == 0 \|\| iPic == 1);
700	if (cb == 1)
701	{
702	int rc;
703	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
704	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
705	PIC_UNLOCK(pData);
706	return rc;
707	}
708	return VERR_IOM_IOPORT_UNUSED;
709	}
710
711	/**
712	* Port I/O Handler for OUT operations.
713	*
714	* @returns VBox status code.
715	*
716	* @param pDevIns The device instance.
717	* @param pvUser User argument - pointer to the PIC in question.
718	* @param uPort Port number used for the IN operation.
719	* @param u32 The value to output.
720	* @param cb The value size in bytes.
721	*/
722	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
723	{
724	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
725	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
726
727	Assert(iPic == 0 \|\| iPic == 1);
728
729	if (cb == 1)
730	{
731	int rc;
732	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
733	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
734	PIC_UNLOCK(pData);
735	return rc;
736	}
737	return VINF_SUCCESS;
738	}
739
740
741	/**
742	* Port I/O Handler for IN operations.
743	*
744	* @returns VBox status code.
745	*
746	* @param pDevIns The device instance.
747	* @param pvUser User argument - pointer to the PIC in question.
748	* @param uPort Port number used for the IN operation.
749	* @param pu32 Where to store the result.
750	* @param cb Number of bytes read.
751	*/
752	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
753	{
754	if (cb == 1)
755	{
756	PicState s = (PicState)pvUser;
757	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
758	*pu32 = s->elcr;
759	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
760	return VINF_SUCCESS;
761	}
762	return VERR_IOM_IOPORT_UNUSED;
763	}
764
765	/**
766	* Port I/O Handler for OUT operations.
767	*
768	* @returns VBox status code.
769	*
770	* @param pDevIns The device instance.
771	* @param pvUser User argument - pointer to the PIC in question.
772	* @param uPort Port number used for the IN operation.
773	* @param u32 The value to output.
774	* @param cb The value size in bytes.
775	*/
776	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
777	{
778	if (cb == 1)
779	{
780	PicState s = (PicState)pvUser;
781	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
782	s->elcr = u32 & s->elcr_mask;
783	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
784	}
785	return VINF_SUCCESS;
786	}
787
788
789	#ifdef IN_RING3
790
791	#ifdef DEBUG
792	/**
793	* PIC status info callback.
794	*
795	* @param pDevIns The device instance.
796	* @param pHlp The output helpers.
797	* @param pszArgs The arguments.
798	*/
799	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
800	{
801	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
802
803	/*
804	* Show info.
805	*/
806	for (int i=0;i<2;i++)
807	{
808	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
809	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
810	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
811	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
812	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
813	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
814	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
815	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
816	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
817	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
818	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
819	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
820	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
821	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
822	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
823	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
824	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
825	}
826	}
827	#endif /* DEBUG */
828
829	/**
830	* Saves a state of the programmable interrupt controller device.
831	*
832	* @returns VBox status code.
833	* @param pDevIns The device instance.
834	* @param pSSMHandle The handle to save the state to.
835	*/
836	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
837	{
838	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
839	pic_save(pSSMHandle, &pData->aPics[0]);
840	pic_save(pSSMHandle, &pData->aPics[1]);
841	return VINF_SUCCESS;
842	}
843
844
845	/**
846	* Loads a saved programmable interrupt controller device state.
847	*
848	* @returns VBox status code.
849	* @param pDevIns The device instance.
850	* @param pSSMHandle The handle to the saved state.
851	* @param u32Version The data unit version number.
852	*/
853	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
854	{
855	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
856	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
857	if (VBOX_SUCCESS(rc))
858	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
859	return rc;
860	}
861
862
863	/* -=-=-=-=-=- real code -=-=-=-=-=- */
864
865	/**
866	* Reset notification.
867	*
868	* @returns VBox status.
869	* @param pDevIns The device instance data.
870	*/
871	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
872	{
873	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
874	unsigned i;
875	LogFlow(("picReset:\n"));
876	#ifdef VBOX_WITH_PDM_LOCK
877	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
878	#endif
879
880	for (i = 0; i < ELEMENTS(pData->aPics); i++)
881	pic_reset(&pData->aPics[i]);
882
883	PIC_UNLOCK(pData);
884	}
885
886
887	/**
888	* @copydoc FNPDMDEVRELOCATE
889	*/
890	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
891	{
892	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
893	unsigned i;
894
895	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
896	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
897	for (i = 0; i < ELEMENTS(pData->aPics); i++)
898	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
899	}
900
901
902	/**
903	* @copydoc FNPDMDEVCONSTRUCT
904	*/
905	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
906	{
907	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
908	PDMPICREG PicReg;
909	int rc;
910	bool fGCEnabled;
911	bool fR0Enabled;
912	Assert(iInstance == 0);
913
914	/*
915	* Validate and read configuration.
916	*/
917	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
918	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
919
920	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
921	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
922	fGCEnabled = true;
923	else if (VBOX_FAILURE(rc))
924	return PDMDEV_SET_ERROR(pDevIns, rc,
925	N_("Configuration error: failed to read GCEnabled as boolean"));
926
927	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
928	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
929	fR0Enabled = true;
930	else if (VBOX_FAILURE(rc))
931	return PDMDEV_SET_ERROR(pDevIns, rc,
932	N_("Configuration error: failed to read R0Enabled as boolean"));
933
934	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
935
936	/*
937	* Init the data.
938	*/
939	Assert(ELEMENTS(pData->aPics) == 2);
940	pData->pDevInsHC = pDevIns;
941	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
942	pData->aPics[0].elcr_mask = 0xf8;
943	pData->aPics[1].elcr_mask = 0xde;
944	pData->aPics[0].pDevInsHC = pDevIns;
945	pData->aPics[1].pDevInsHC = pDevIns;
946	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
947	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
948
949	/*
950	* Register PIC, I/O ports and save state.
951	*/
952	PicReg.u32Version = PDM_PICREG_VERSION;
953	PicReg.pfnSetIrqHC = picSetIrq;
954	PicReg.pfnGetInterruptHC = picGetInterrupt;
955	if (fGCEnabled)
956	{
957	PicReg.pszSetIrqGC = "picSetIrq";
958	PicReg.pszGetInterruptGC = "picGetInterrupt";
959	}
960	else
961	{
962	PicReg.pszSetIrqGC = NULL;
963	PicReg.pszGetInterruptGC = NULL;
964	}
965
966	if (fR0Enabled)
967	{
968	PicReg.pszSetIrqR0 = "picSetIrq";
969	PicReg.pszGetInterruptR0 = "picGetInterrupt";
970	}
971	else
972	{
973	PicReg.pszSetIrqR0 = NULL;
974	PicReg.pszGetInterruptR0 = NULL;
975	}
976
977	Assert(pDevIns->pDevHlp->pfnPICRegister);
978	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
979	if (VBOX_FAILURE(rc))
980	{
981	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
982	return rc;
983	}
984	if (fGCEnabled)
985	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
986	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
987	if (VBOX_FAILURE(rc))
988	return rc;
989	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
990	if (VBOX_FAILURE(rc))
991	return rc;
992	if (fGCEnabled)
993	{
994	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
995	if (VBOX_FAILURE(rc))
996	return rc;
997	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
998	if (VBOX_FAILURE(rc))
999	return rc;
1000	}
1001	if (fR0Enabled)
1002	{
1003	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
1004
1005	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1006	if (VBOX_FAILURE(rc))
1007	return rc;
1008	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1009	if (VBOX_FAILURE(rc))
1010	return rc;
1011	}
1012
1013	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
1014	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1015	if (VBOX_FAILURE(rc))
1016	return rc;
1017	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
1018	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1019	if (VBOX_FAILURE(rc))
1020	return rc;
1021	if (fGCEnabled)
1022	{
1023	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1024	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1025	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1026	if (VBOX_FAILURE(rc))
1027	return rc;
1028	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1029	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1030	if (VBOX_FAILURE(rc))
1031	return rc;
1032	}
1033	if (fR0Enabled)
1034	{
1035	RTR0PTR pDataR0 = PDMINS2DATA_R0PTR(pDevIns);
1036	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1037	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1038	if (VBOX_FAILURE(rc))
1039	return rc;
1040	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1041	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1042	if (VBOX_FAILURE(rc))
1043	return rc;
1044	}
1045
1046	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1047	NULL, picSaveExec, NULL,
1048	NULL, picLoadExec, NULL);
1049	if (VBOX_FAILURE(rc))
1050	return rc;
1051
1052
1053	#ifdef DEBUG
1054	/*
1055	* Register the info item.
1056	*/
1057	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1058	#endif
1059
1060	/*
1061	* Initialize the device state.
1062	*/
1063	picReset(pDevIns);
1064
1065	#ifdef VBOX_WITH_STATISTICS
1066	/*
1067	* Statistics.
1068	*/
1069	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1070	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1071
1072	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1073	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1074	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1075	#endif
1076
1077	return VINF_SUCCESS;
1078	}
1079
1080
1081	/**
1082	* The device registration structure.
1083	*/
1084	const PDMDEVREG g_DeviceI8259 =
1085	{
1086	/* u32Version */
1087	PDM_DEVREG_VERSION,
1088	/* szDeviceName */
1089	"i8259",
1090	/* szGCMod */
1091	"VBoxDDGC.gc",
1092	/* szR0Mod */
1093	"VBoxDDR0.r0",
1094	/* pszDescription */
1095	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1096	/* fFlags */
1097	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1098	/* fClass */
1099	PDM_DEVREG_CLASS_PIC,
1100	/* cMaxInstances */
1101	1,
1102	/* cbInstance */
1103	sizeof(DEVPIC),
1104	/* pfnConstruct */
1105	picConstruct,
1106	/* pfnDestruct */
1107	NULL,
1108	/* pfnRelocate */
1109	picRelocate,
1110	/* pfnIOCtl */
1111	NULL,
1112	/* pfnPowerOn */
1113	NULL,
1114	/* pfnReset */
1115	picReset,
1116	/* pfnSuspend */
1117	NULL,
1118	/* pfnResume */
1119	NULL,
1120	/* pfnAttach */
1121	NULL,
1122	/* pfnDetach */
1123	NULL,
1124	/* pfnQueryInterface. */
1125	NULL
1126	};
1127
1128	#endif /* IN_RING3 */
1129	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1130

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 3867

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