DevPIC.cpp@ 584

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1	/** @file
2	*
3	* VBox basic PC devices:
4	* Intel 8259 Programmable Interrupt Controller.
5	*/
6
7	/*
8	* Copyright (C) 2006 InnoTek Systemberatung GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* If you received this file as part of a commercial VirtualBox
19	* distribution, then only the terms of your commercial VirtualBox
20	* license agreement apply instead of the previous paragraph.
21	*/
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_PIC
27	#include <VBox/pdm.h>
28	#include <VBox/log.h>
29	#include <iprt/assert.h>
30
31	#include "vl_vbox.h"
32
33
34	/*******************************************************************************
35	* Defined Constants And Macros *
36	*******************************************************************************/
37	/** @def PIC_LOCK
38	* Acquires the PDM lock. This is a NOP if locking is disabled. */
39	/** @def PIC_UNLOCK
40	* Releases the PDM lock. This is a NOP if locking is disabled. */
41	#ifdef VBOX_WITH_PDM_LOCK
42	# define PIC_LOCK(pThis, rc) \
43	do { \
44	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
45	if (rc2 != VINF_SUCCESS) \
46	return rc2; \
47	} while (0)
48	# define PIC_UNLOCK(pThis) \
49	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
50	#else /* !VBOX_WITH_PDM_LOCK */
51	# define PIC_LOCK(pThis, rc) do { } while (0)
52	# define PIC_UNLOCK(pThis) do { } while (0)
53	#endif /* !VBOX_WITH_PDM_LOCK */
54
55
56	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
57	/*******************************************************************************
58	* Internal Functions *
59	*******************************************************************************/
60	__BEGIN_DECLS
61
62	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
63	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
64	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
65	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
66	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
67	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
68
69	__END_DECLS
70	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
71
72
73	/*
74	* QEMU 8259 interrupt controller emulation
75	*
76	* Copyright (c) 2003-2004 Fabrice Bellard
77	*
78	* Permission is hereby granted, free of charge, to any person obtaining a copy
79	* of this software and associated documentation files (the "Software"), to deal
80	* in the Software without restriction, including without limitation the rights
81	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
82	* copies of the Software, and to permit persons to whom the Software is
83	* furnished to do so, subject to the following conditions:
84	*
85	* The above copyright notice and this permission notice shall be included in
86	* all copies or substantial portions of the Software.
87	*
88	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
89	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
90	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
91	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
92	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
93	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
94	* THE SOFTWARE.
95	*/
96
97	/* debug PIC */
98	#define DEBUG_PIC
99
100	/#define DEBUG_IRQ_COUNT/
101
102	typedef struct PicState {
103	uint8_t last_irr; /* edge detection */
104	uint8_t irr; /* interrupt request register */
105	uint8_t imr; /* interrupt mask register */
106	uint8_t isr; /* interrupt service register */
107	uint8_t priority_add; /* highest irq priority */
108	uint8_t irq_base;
109	uint8_t read_reg_select;
110	uint8_t poll;
111	uint8_t special_mask;
112	uint8_t init_state;
113	uint8_t auto_eoi;
114	uint8_t rotate_on_auto_eoi;
115	uint8_t special_fully_nested_mode;
116	uint8_t init4; /* true if 4 byte init */
117	uint8_t elcr; /* PIIX edge/trigger selection*/
118	uint8_t elcr_mask;
119	/** Pointer to the device instance, HCPtr. */
120	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
121	/** Pointer to the device instance, GCPtr. */
122	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
123	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS != 64
124	RTGCPTR Alignment0;
125	#endif
126	} PicState;
127
128	/**
129	* A PIC device instance data.
130	*/
131	typedef struct DEVPIC
132	{
133	/** The two interrupt controllers. */
134	PicState aPics[2];
135	/** Pointer to the PIC R3 helpers. */
136	PCPDMPICHLPR3 pPicHlpR3;
137	/** Pointer to the PIC R0 helpers. */
138	PCPDMPICHLPR0 pPicHlpR0;
139	/** Pointer to the PIC GC helpers. */
140	PCPDMPICHLPGC pPicHlpGC;
141	/** Pointer to the device instance - GC Ptr. */
142	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
143	/** Pointer to the device instance - GC Ptr. */
144	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
145	#if HC_ARCH_BITS == 32
146	uint32_t Alignmnet0;
147	#endif
148	#ifdef VBOX_WITH_STATISTICS
149	STAMCOUNTER StatSetIrqGC;
150	STAMCOUNTER StatSetIrqHC;
151	STAMCOUNTER StatClearedActiveIRQ2;
152	STAMCOUNTER StatClearedActiveMasterIRQ;
153	STAMCOUNTER StatClearedActiveSlaveIRQ;
154	#endif
155	} DEVPIC, *PDEVPIC;
156
157
158	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
159	#ifdef LOG_ENABLED
160	static inline void DumpPICState(PicState s, char szFn)
161	{
162	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
163
164	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
165	szFn, (&pData->aPics[0] == s) ? 0 : 1,
166	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
167	}
168	#else
169	# define DumpPICState(pData, szFn) do { } while (0)
170	#endif
171
172	/* set irq level. If an edge is detected, then the IRR is set to 1 */
173	static inline void pic_set_irq1(PicState *s, int irq, int level)
174	{
175	int mask;
176	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
177	mask = 1 << irq;
178	if (s->elcr & mask) {
179	/* level triggered */
180	if (level) {
181	s->irr \|= mask;
182	s->last_irr \|= mask;
183	} else {
184	s->irr &= ~mask;
185	s->last_irr &= ~mask;
186	}
187	} else {
188	/* edge triggered */
189	if (level) {
190	if ((s->last_irr & mask) == 0)
191	{
192	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
193	s->irr \|= mask;
194	}
195	s->last_irr \|= mask;
196	} else {
197	s->last_irr &= ~mask;
198	}
199	}
200	DumpPICState(s, "pic_set_irq1");
201	}
202
203	/* return the highest priority found in mask (highest = smallest
204	number). Return 8 if no irq */
205	static inline int get_priority(PicState *s, int mask)
206	{
207	int priority;
208	if (mask == 0)
209	return 8;
210	priority = 0;
211	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
212	priority++;
213	return priority;
214	}
215
216	/* return the pic wanted interrupt. return -1 if none */
217	static int pic_get_irq(PicState *s)
218	{
219	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
220	int mask, cur_priority, priority;
221	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
222	DumpPICState(s, "pic_get_irq");
223
224	mask = s->irr & ~s->imr;
225	priority = get_priority(s, mask);
226	Log(("pic_get_irq: priority=%x\n", priority));
227	if (priority == 8)
228	return -1;
229	/* compute current priority. If special fully nested mode on the
230	master, the IRQ coming from the slave is not taken into account
231	for the priority computation. */
232	mask = s->isr;
233	if (s->special_fully_nested_mode && s == &pics[0])
234	mask &= ~(1 << 2);
235	cur_priority = get_priority(s, mask);
236	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
237	if (priority < cur_priority) {
238	/* higher priority found: an irq should be generated */
239	return (priority + s->priority_add) & 7;
240	} else {
241	return -1;
242	}
243	}
244
245	/* raise irq to CPU if necessary. must be called every time the active
246	irq may change */
247	static int pic_update_irq(PDEVPIC pData)
248	{
249	PicState *pics = &pData->aPics[0];
250	int irq2, irq;
251
252	/* first look at slave pic */
253	irq2 = pic_get_irq(&pics[1]);
254	Log(("pic_update_irq irq2=%d\n", irq2));
255	if (irq2 >= 0) {
256	/* if irq request by slave pic, signal master PIC */
257	pic_set_irq1(&pics[0], 2, 1);
258	pic_set_irq1(&pics[0], 2, 0);
259	}
260	/* look at requested irq */
261	irq = pic_get_irq(&pics[0]);
262	if (irq >= 0)
263	{
264	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
265	* spurious slave interrupts in picGetInterrupt.
266	*/
267	if (irq != 2 \|\| irq2 != -1)
268	{
269	#if defined(DEBUG_PIC)
270	int i;
271	for(i = 0; i < 2; i++) {
272	Log(("pic%d: imr=%x irr=%x padd=%d\n",
273	i, pics[i].imr, pics[i].irr,
274	pics[i].priority_add));
275	}
276	Log(("pic: cpu_interrupt\n"));
277	#endif
278	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
279	}
280	else
281	{
282	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
283	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
284	/* Clear it here, so lower priority interrupts can still be dispatched. */
285	/** @note Is this correct? */
286	pics[0].irr &= ~(1 << 2);
287	}
288	}
289	return VINF_SUCCESS;
290	}
291
292	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
293	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
294	{
295	int irq, intno;
296	PicState *pActivePIC;
297
298	/* Query the current pending irq, if any. */
299	pActivePIC = &pData->aPics[0];
300	intno = irq = pic_get_irq(pActivePIC);
301	if (irq == 2)
302	{
303	pActivePIC = &pData->aPics[1];
304	irq = pic_get_irq(pActivePIC);
305	intno = irq + 8;
306	}
307
308	/* Update IMR */
309	s->imr = val;
310
311	/* If an interrupt is pending and now masked, then clear the FF flag. */
312	if ( irq >= 0
313	&& ((1 << irq) & ~pActivePIC->imr) == 0)
314	{
315	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
316	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
317	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
318	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
319
320	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
321	/** @todo Is this correct? */
322	if (intno > 7)
323	{
324	pData->aPics[0].irr &= ~(1 << 2);
325	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
326	}
327	else
328	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
329
330	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
331	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
332	}
333	}
334
335
336	/**
337	* Set the an IRQ.
338	*
339	* @param pDevIns Device instance of the PICs.
340	* @param iIrq IRQ number to set.
341	* @param iLevel IRQ level.
342	*/
343	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
344	{
345	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
346	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
347	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
348	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
349	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
350
351	Log(("picSetIrq %d %d\n", iIrq, iLevel));
352	DumpPICState(&pData->aPics[0], "picSetIrq");
353	DumpPICState(&pData->aPics[1], "picSetIrq");
354	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
355	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel);
356	pic_update_irq(pData);
357	}
358
359
360	/* acknowledge interrupt 'irq' */
361	static inline void pic_intack(PicState *s, int irq)
362	{
363	if (s->auto_eoi) {
364	if (s->rotate_on_auto_eoi)
365	s->priority_add = (irq + 1) & 7;
366	} else {
367	s->isr \|= (1 << irq);
368	}
369	/* We don't clear a level sensitive interrupt here */
370	if (!(s->elcr & (1 << irq)))
371	s->irr &= ~(1 << irq);
372	}
373
374
375	/**
376	* Get a pending interrupt.
377	*
378	* @returns Pending interrupt number.
379	* @param pDevIns Device instance of the PICs.
380	*/
381	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
382	{
383	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
384	int irq;
385	int irq2;
386	int intno;
387
388	/* read the irq from the PIC */
389	DumpPICState(&pData->aPics[0], "picGetInterrupt");
390	DumpPICState(&pData->aPics[1], "picGetInterrupt");
391
392	irq = pic_get_irq(&pData->aPics[0]);
393	if (irq >= 0)
394	{
395	pic_intack(&pData->aPics[0], irq);
396	if (irq == 2)
397	{
398	irq2 = pic_get_irq(&pData->aPics[1]);
399	if (irq2 >= 0) {
400	pic_intack(&pData->aPics[1], irq2);
401	}
402	else
403	{
404	/* spurious IRQ on slave controller (impossible) */
405	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
406	irq2 = 7;
407	}
408	intno = pData->aPics[1].irq_base + irq2;
409	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
410	irq = irq2 + 8;
411	}
412	else {
413	intno = pData->aPics[0].irq_base + irq;
414	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
415	}
416	}
417	else
418	{
419	/* spurious IRQ on host controller (impossible) */
420	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
421	irq = 7;
422	intno = pData->aPics[0].irq_base + irq;
423	}
424	pic_update_irq(pData);
425
426	Log(("picGetInterrupt: pending 0:%d 1:%d\n", pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
427
428	return intno;
429	}
430
431	static void pic_reset(PicState *s)
432	{
433	HCPTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
434	GCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
435	int tmp, tmp2;
436
437	tmp = s->elcr_mask;
438	tmp2 = s->elcr;
439	memset(s, 0, sizeof(PicState));
440	s->elcr_mask = tmp;
441	s->elcr = tmp2;
442	s->pDevInsHC = pDevInsHC;
443	s->pDevInsGC = pDevInsGC;
444	}
445
446
447	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
448	{
449	PicState s = (PicState)opaque;
450	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
451	int rc = VINF_SUCCESS;
452	int priority, cmd, irq;
453
454	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
455	addr &= 1;
456	if (addr == 0) {
457	if (val & 0x10) {
458	/* init */
459	pic_reset(s);
460	/* deassert a pending interrupt */
461	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
462
463	s->init_state = 1;
464	s->init4 = val & 1;
465	if (val & 0x02)
466	AssertReleaseMsgFailed(("single mode not supported"));
467	if (val & 0x08)
468	AssertReleaseMsgFailed(("level sensitive irq not supported"));
469	} else if (val & 0x08) {
470	if (val & 0x04)
471	s->poll = 1;
472	if (val & 0x02)
473	s->read_reg_select = val & 1;
474	if (val & 0x40)
475	s->special_mask = (val >> 5) & 1;
476	} else {
477	cmd = val >> 5;
478	switch(cmd) {
479	case 0:
480	case 4:
481	s->rotate_on_auto_eoi = cmd >> 2;
482	break;
483	case 1: /* end of interrupt */
484	case 5:
485	{
486	priority = get_priority(s, s->isr);
487	if (priority != 8) {
488	irq = (priority + s->priority_add) & 7;
489	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
490	s->isr &= ~(1 << irq);
491	if (cmd == 5)
492	s->priority_add = (irq + 1) & 7;
493	rc = pic_update_irq(pData);
494	Assert(rc == VINF_SUCCESS);
495	}
496	break;
497	}
498	case 3:
499	{
500	irq = val & 7;
501	Log(("pic_write: EOI2 for irq %d\n", irq));
502	s->isr &= ~(1 << irq);
503	rc = pic_update_irq(pData);
504	Assert(rc == VINF_SUCCESS);
505	break;
506	}
507	case 6:
508	{
509	s->priority_add = (val + 1) & 7;
510	rc = pic_update_irq(pData);
511	Assert(rc == VINF_SUCCESS);
512	break;
513	}
514	case 7:
515	{
516	irq = val & 7;
517	Log(("pic_write: EOI3 for irq %d\n", irq));
518	s->isr &= ~(1 << irq);
519	s->priority_add = (irq + 1) & 7;
520	rc = pic_update_irq(pData);
521	Assert(rc == VINF_SUCCESS);
522	break;
523	}
524	default:
525	/* no operation */
526	break;
527	}
528	}
529	} else {
530	switch(s->init_state) {
531	case 0:
532	{
533	/* normal mode */
534	pic_update_imr(pData, s, val);
535
536	rc = pic_update_irq(pData);
537	Assert(rc == VINF_SUCCESS);
538	break;
539	}
540	case 1:
541	s->irq_base = val & 0xf8;
542	s->init_state = 2;
543	Log(("pic_write: set irq base to %x\n", s->irq_base));
544	break;
545	case 2:
546	if (s->init4) {
547	s->init_state = 3;
548	} else {
549	s->init_state = 0;
550	}
551	break;
552	case 3:
553	s->special_fully_nested_mode = (val >> 4) & 1;
554	s->auto_eoi = (val >> 1) & 1;
555	s->init_state = 0;
556	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
557	break;
558	}
559	}
560	return rc;
561	}
562
563
564	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
565	{
566	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
567	PicState *pics = &pData->aPics[0];
568	int ret;
569
570	ret = pic_get_irq(s);
571	if (ret >= 0) {
572	if (addr1 >> 7) {
573	Log2(("pic_poll_read: clear slave irq (isr)\n"));
574	pics[0].isr &= ~(1 << 2);
575	pics[0].irr &= ~(1 << 2);
576	}
577	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
578	s->irr &= ~(1 << ret);
579	s->isr &= ~(1 << ret);
580	if (addr1 >> 7 \|\| ret != 2)
581	pic_update_irq(pData);
582	} else {
583	ret = 0x07;
584	pic_update_irq(pData);
585	}
586
587	return ret;
588	}
589
590
591	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
592	{
593	PicState s = (PicState)opaque;
594	unsigned int addr;
595	int ret;
596
597	*pRC = VINF_SUCCESS;
598
599	addr = addr1;
600	addr &= 1;
601	if (s->poll) {
602	ret = pic_poll_read(s, addr1);
603	s->poll = 0;
604	} else {
605	if (addr == 0) {
606	if (s->read_reg_select)
607	ret = s->isr;
608	else
609	ret = s->irr;
610	} else {
611	ret = s->imr;
612	}
613	}
614	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
615	return ret;
616	}
617
618
619
620	#ifdef IN_RING3
621
622	static void pic_save(QEMUFile f, void opaque)
623	{
624	PicState s = (PicState)opaque;
625
626	qemu_put_8s(f, &s->last_irr);
627	qemu_put_8s(f, &s->irr);
628	qemu_put_8s(f, &s->imr);
629	qemu_put_8s(f, &s->isr);
630	qemu_put_8s(f, &s->priority_add);
631	qemu_put_8s(f, &s->irq_base);
632	qemu_put_8s(f, &s->read_reg_select);
633	qemu_put_8s(f, &s->poll);
634	qemu_put_8s(f, &s->special_mask);
635	qemu_put_8s(f, &s->init_state);
636	qemu_put_8s(f, &s->auto_eoi);
637	qemu_put_8s(f, &s->rotate_on_auto_eoi);
638	qemu_put_8s(f, &s->special_fully_nested_mode);
639	qemu_put_8s(f, &s->init4);
640	qemu_put_8s(f, &s->elcr);
641	}
642
643	static int pic_load(QEMUFile f, void opaque, int version_id)
644	{
645	PicState s = (PicState)opaque;
646
647	if (version_id != 1)
648	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
649
650	qemu_get_8s(f, &s->last_irr);
651	qemu_get_8s(f, &s->irr);
652	qemu_get_8s(f, &s->imr);
653	qemu_get_8s(f, &s->isr);
654	qemu_get_8s(f, &s->priority_add);
655	qemu_get_8s(f, &s->irq_base);
656	qemu_get_8s(f, &s->read_reg_select);
657	qemu_get_8s(f, &s->poll);
658	qemu_get_8s(f, &s->special_mask);
659	qemu_get_8s(f, &s->init_state);
660	qemu_get_8s(f, &s->auto_eoi);
661	qemu_get_8s(f, &s->rotate_on_auto_eoi);
662	qemu_get_8s(f, &s->special_fully_nested_mode);
663	qemu_get_8s(f, &s->init4);
664	qemu_get_8s(f, &s->elcr);
665	return 0;
666	}
667	#endif /* IN_RING3 */
668
669
670	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
671
672	/**
673	* Port I/O Handler for IN operations.
674	*
675	* @returns VBox status code.
676	*
677	* @param pDevIns The device instance.
678	* @param pvUser User argument - pointer to the PIC in question.
679	* @param uPort Port number used for the IN operation.
680	* @param pu32 Where to store the result.
681	* @param cb Number of bytes read.
682	*/
683	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
684	{
685	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
686	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
687
688	Assert(iPic == 0 \|\| iPic == 1);
689	if (cb == 1)
690	{
691	int rc;
692	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
693	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
694	PIC_UNLOCK(pData);
695	return rc;
696	}
697	return VERR_IOM_IOPORT_UNUSED;
698	}
699
700	/**
701	* Port I/O Handler for OUT operations.
702	*
703	* @returns VBox status code.
704	*
705	* @param pDevIns The device instance.
706	* @param pvUser User argument - pointer to the PIC in question.
707	* @param uPort Port number used for the IN operation.
708	* @param u32 The value to output.
709	* @param cb The value size in bytes.
710	*/
711	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
712	{
713	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
714	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
715
716	Assert(iPic == 0 \|\| iPic == 1);
717
718	if (cb == 1)
719	{
720	int rc;
721	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
722	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
723	PIC_UNLOCK(pData);
724	return rc;
725	}
726	return VINF_SUCCESS;
727	}
728
729
730	/**
731	* Port I/O Handler for IN operations.
732	*
733	* @returns VBox status code.
734	*
735	* @param pDevIns The device instance.
736	* @param pvUser User argument - pointer to the PIC in question.
737	* @param uPort Port number used for the IN operation.
738	* @param pu32 Where to store the result.
739	* @param cb Number of bytes read.
740	*/
741	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
742	{
743	if (cb == 1)
744	{
745	PicState s = (PicState)pvUser;
746	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
747	*pu32 = s->elcr;
748	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
749	return VINF_SUCCESS;
750	}
751	return VERR_IOM_IOPORT_UNUSED;
752	}
753
754	/**
755	* Port I/O Handler for OUT operations.
756	*
757	* @returns VBox status code.
758	*
759	* @param pDevIns The device instance.
760	* @param pvUser User argument - pointer to the PIC in question.
761	* @param uPort Port number used for the IN operation.
762	* @param u32 The value to output.
763	* @param cb The value size in bytes.
764	*/
765	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
766	{
767	if (cb == 1)
768	{
769	PicState s = (PicState)pvUser;
770	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
771	s->elcr = u32 & s->elcr_mask;
772	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
773	}
774	return VINF_SUCCESS;
775	}
776
777
778	#ifdef IN_RING3
779
780	#ifdef DEBUG
781	/**
782	* PIC status info callback.
783	*
784	* @param pDevIns The device instance.
785	* @param pHlp The output helpers.
786	* @param pszArgs The arguments.
787	*/
788	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
789	{
790	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
791
792	/*
793	* Show info.
794	*/
795	for (int i=0;i<2;i++)
796	{
797	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
798	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
799	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
800	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
801	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
802	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
803	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
804	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
805	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
806	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
807	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
808	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
809	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
810	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
811	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
812	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
813	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
814	}
815	}
816	#endif /* DEBUG */
817
818	/**
819	* Saves a state of the programmable interrupt controller device.
820	*
821	* @returns VBox status code.
822	* @param pDevIns The device instance.
823	* @param pSSMHandle The handle to save the state to.
824	*/
825	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
826	{
827	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
828	pic_save(pSSMHandle, &pData->aPics[0]);
829	pic_save(pSSMHandle, &pData->aPics[1]);
830	return VINF_SUCCESS;
831	}
832
833
834	/**
835	* Loads a saved programmable interrupt controller device state.
836	*
837	* @returns VBox status code.
838	* @param pDevIns The device instance.
839	* @param pSSMHandle The handle to the saved state.
840	* @param u32Version The data unit version number.
841	*/
842	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
843	{
844	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
845	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
846	if (VBOX_SUCCESS(rc))
847	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
848	return rc;
849	}
850
851
852	/* -=-=-=-=-=- real code -=-=-=-=-=- */
853
854	/**
855	* Reset notification.
856	*
857	* @returns VBox status.
858	* @param pDevIns The device instance data.
859	*/
860	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
861	{
862	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
863	unsigned i;
864	LogFlow(("picReset:\n"));
865	#ifdef VBOX_WITH_PDM_LOCK
866	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
867	#endif
868
869	for (i = 0; i < ELEMENTS(pData->aPics); i++)
870	pic_reset(&pData->aPics[i]);
871
872	PIC_UNLOCK(pData);
873	}
874
875
876	/**
877	* @copydoc FNPDMDEVRELOCATE
878	*/
879	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
880	{
881	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
882	unsigned i;
883
884	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
885	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
886	for (i = 0; i < ELEMENTS(pData->aPics); i++)
887	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
888	}
889
890
891	/**
892	* @copydoc FNPDMDEVCONSTRUCT
893	*/
894	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
895	{
896	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
897	PDMPICREG PicReg;
898	int rc;
899	bool fGCEnabled;
900	bool fR0Enabled;
901	Assert(iInstance == 0);
902
903	/*
904	* Validate and read configuration.
905	*/
906	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
907	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
908
909	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
910	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
911	fGCEnabled = true;
912	else if (VBOX_FAILURE(rc))
913	return PDMDEV_SET_ERROR(pDevIns, rc,
914	N_("Configuration error: failed to read GCEnabled as boolean"));
915
916	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
917	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
918	fR0Enabled = true;
919	else if (VBOX_FAILURE(rc))
920	return PDMDEV_SET_ERROR(pDevIns, rc,
921	N_("Configuration error: failed to read R0Enabled as boolean"));
922
923	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
924
925	/*
926	* Init the data.
927	*/
928	Assert(ELEMENTS(pData->aPics) == 2);
929	pData->pDevInsHC = pDevIns;
930	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
931	pData->aPics[0].elcr_mask = 0xf8;
932	pData->aPics[1].elcr_mask = 0xde;
933	pData->aPics[0].pDevInsHC = pDevIns;
934	pData->aPics[1].pDevInsHC = pDevIns;
935	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
936	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
937
938	/*
939	* Register PIC, I/O ports and save state.
940	*/
941	PicReg.u32Version = PDM_PICREG_VERSION;
942	PicReg.pfnSetIrqHC = picSetIrq;
943	PicReg.pfnGetInterruptHC = picGetInterrupt;
944	if (fGCEnabled)
945	{
946	PicReg.pszSetIrqGC = "picSetIrq";
947	PicReg.pszGetInterruptGC = "picGetInterrupt";
948	}
949	else
950	{
951	PicReg.pszSetIrqGC = NULL;
952	PicReg.pszGetInterruptGC = NULL;
953	}
954
955	if (fR0Enabled)
956	{
957	PicReg.pszSetIrqR0 = "picSetIrq";
958	PicReg.pszGetInterruptR0 = "picGetInterrupt";
959	}
960	else
961	{
962	PicReg.pszSetIrqR0 = NULL;
963	PicReg.pszGetInterruptR0 = NULL;
964	}
965
966	Assert(pDevIns->pDevHlp->pfnPICRegister);
967	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
968	if (VBOX_FAILURE(rc))
969	{
970	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
971	return rc;
972	}
973	if (fGCEnabled)
974	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
975	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
976	if (VBOX_FAILURE(rc))
977	return rc;
978	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
979	if (VBOX_FAILURE(rc))
980	return rc;
981	if (fGCEnabled)
982	{
983	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
984	if (VBOX_FAILURE(rc))
985	return rc;
986	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
987	if (VBOX_FAILURE(rc))
988	return rc;
989	}
990	if (fR0Enabled)
991	{
992	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
993
994	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, (void *)0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
995	if (VBOX_FAILURE(rc))
996	return rc;
997	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, (void *)1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
998	if (VBOX_FAILURE(rc))
999	return rc;
1000	}
1001
1002	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
1003	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1004	if (VBOX_FAILURE(rc))
1005	return rc;
1006	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
1007	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1008	if (VBOX_FAILURE(rc))
1009	return rc;
1010	if (fGCEnabled)
1011	{
1012	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1013	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1014	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1015	if (VBOX_FAILURE(rc))
1016	return rc;
1017	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1018	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1019	if (VBOX_FAILURE(rc))
1020	return rc;
1021	}
1022	if (fR0Enabled)
1023	{
1024	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, &pData->aPics[0],
1025	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1026	if (VBOX_FAILURE(rc))
1027	return rc;
1028	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, &pData->aPics[1],
1029	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1030	if (VBOX_FAILURE(rc))
1031	return rc;
1032	}
1033
1034	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1035	NULL, picSaveExec, NULL,
1036	NULL, picLoadExec, NULL);
1037	if (VBOX_FAILURE(rc))
1038	return rc;
1039
1040
1041	#ifdef DEBUG
1042	/*
1043	* Register the info item.
1044	*/
1045	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1046	#endif
1047
1048	/*
1049	* Initialize the device state.
1050	*/
1051	picReset(pDevIns);
1052
1053	#ifdef VBOX_WITH_STATISTICS
1054	/*
1055	* Statistics.
1056	*/
1057	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1058	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1059
1060	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1061	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1062	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1063	#endif
1064
1065	return VINF_SUCCESS;
1066	}
1067
1068
1069	/**
1070	* The device registration structure.
1071	*/
1072	const PDMDEVREG g_DeviceI8259 =
1073	{
1074	/* u32Version */
1075	PDM_DEVREG_VERSION,
1076	/* szDeviceName */
1077	"i8259",
1078	/* szGCMod */
1079	"VBoxDDGC.gc",
1080	/* szR0Mod */
1081	"VBoxDDR0.r0",
1082	/* pszDescription */
1083	"i8259 Programmable Interrupt Controller",
1084	/* fFlags */
1085	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1086	/* fClass */
1087	PDM_DEVREG_CLASS_PIC,
1088	/* cMaxInstances */
1089	1,
1090	/* cbInstance */
1091	sizeof(DEVPIC),
1092	/* pfnConstruct */
1093	picConstruct,
1094	/* pfnDestruct */
1095	NULL,
1096	/* pfnRelocate */
1097	picRelocate,
1098	/* pfnIOCtl */
1099	NULL,
1100	/* pfnPowerOn */
1101	NULL,
1102	/* pfnReset */
1103	picReset,
1104	/* pfnSuspend */
1105	NULL,
1106	/* pfnResume */
1107	NULL,
1108	/* pfnAttach */
1109	NULL,
1110	/* pfnDetach */
1111	NULL,
1112	/* pfnQueryInterface. */
1113	NULL
1114	};
1115
1116	#endif /* IN_RING3 */
1117	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1118

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 584

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