DevPIC.cpp@ 81914

Last change on this file since 81914 was 81914, checked in by vboxsync, 5 years ago
DevPIC: Split up the structure and marked the device as new-style. bugref:9218
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
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1	/* $Id: DevPIC.cpp 81914 2019-11-17 20:29:52Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* -------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8259 interrupt controller emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*
42	*/
43
44
45	/*********************************************************************************************************************************
46	* Header Files *
47	*********************************************************************************************************************************/
48	#define LOG_GROUP LOG_GROUP_DEV_PIC
49	#include <VBox/vmm/pdmdev.h>
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include "VBoxDD.h"
55
56
57	/*********************************************************************************************************************************
58	* Defined Constants And Macros *
59	*********************************************************************************************************************************/
60	/** @def PIC_LOCK
61	* Acquires the PDM lock. This is a NOP if locking is disabled. */
62	/** @def PIC_UNLOCK
63	* Releases the PDM lock. This is a NOP if locking is disabled. */
64	#define PIC_LOCK(a_pDevIns, a_pThisCC, rc) \
65	do { \
66	int rc2 = (a_pThisCC)->pPicHlp->pfnLock((a_pDevIns), rc); \
67	if (rc2 != VINF_SUCCESS) \
68	return rc2; \
69	} while (0)
70	#define PIC_UNLOCK(a_pDevIns, a_pThisCC) \
71	(a_pThisCC)->pPicHlp->pfnUnlock((a_pDevIns))
72
73
74	/*********************************************************************************************************************************
75	* Structures and Typedefs *
76	*********************************************************************************************************************************/
77	/**
78	* The instance data of one (1) PIC.
79	*/
80	typedef struct PICSTATE
81	{
82	uint8_t last_irr; /*< edge detection /
83	uint8_t irr; /*< interrupt request register /
84	uint8_t imr; /*< interrupt mask register /
85	uint8_t isr; /*< interrupt service register /
86	uint8_t priority_add; /*< highest irq priority /
87	uint8_t irq_base;
88	uint8_t read_reg_select;
89	uint8_t poll;
90	uint8_t special_mask;
91	uint8_t init_state;
92	uint8_t auto_eoi;
93	uint8_t rotate_on_auto_eoi;
94	uint8_t special_fully_nested_mode;
95	uint8_t init4; /*< true if 4 byte init /
96	uint8_t elcr; /*< PIIX edge/trigger selection/
97	uint8_t elcr_mask;
98	/** The IRQ tags and source IDs for each (tracing purposes). */
99	uint32_t auTags[8];
100	/** The PIC index (0 or 1). */
101	uint8_t idxPic;
102	uint8_t abAlignment0[7]; /*< Alignment padding. /
103	/** The two I/O ports at 0x20 or 0xa0. */
104	IOMIOPORTHANDLE hIoPorts0;
105	/** The ELCR I/O port at 0x4d0 or 0x4d1. */
106	IOMIOPORTHANDLE hIoPorts1;
107	} PICSTATE;
108	AssertCompileMemberAlignment(PICSTATE, hIoPorts0, 8);
109	/** Pointer to the state of one PIC. */
110	typedef PICSTATE *PPICSTATE;
111
112
113	/**
114	* The shared PIC device instance data.
115	*/
116	typedef struct DEVPIC
117	{
118	/** The two interrupt controllers. */
119	PICSTATE aPics[2];
120	/** Number of release log entries. Used to prevent flooding. */
121	uint32_t cRelLogEntries;
122	uint32_t u32Padding;
123	#ifdef VBOX_WITH_STATISTICS
124	STAMCOUNTER StatSetIrqRZ;
125	STAMCOUNTER StatSetIrqR3;
126	STAMCOUNTER StatClearedActiveIRQ2;
127	STAMCOUNTER StatClearedActiveMasterIRQ;
128	STAMCOUNTER StatClearedActiveSlaveIRQ;
129	#endif
130	} DEVPIC;
131	/** Pointer to the shared PIC instance data. */
132	typedef DEVPIC *PDEVPIC;
133
134
135	/**
136	* The PIC device instance data for ring-3.
137	*/
138	typedef struct DEVPICR3
139	{
140	/** Pointer to the PIC ring-3 helpers. */
141	R3PTRTYPE(PCPDMPICHLP) pPicHlp;
142	} DEVPICR3;
143	/** Pointer to the ring-3 PIC instance data. */
144	typedef DEVPICR3 *PDEVPICR3;
145
146
147	/**
148	* The PIC device instance data for ring-0.
149	*/
150	typedef struct DEVPICR0
151	{
152	/** Pointer to the PIC ring-0 helpers. */
153	R0PTRTYPE(PCPDMPICHLP) pPicHlp;
154	} DEVPICR0;
155	/** Pointer to the ring-0 PIC instance data. */
156	typedef DEVPICR0 *PDEVPICR0;
157
158
159	/**
160	* The PIC device instance data for raw-mode.
161	*/
162	typedef struct DEVPICRC
163	{
164	/** Pointer to the PIC raw-mode helpers. */
165	RCPTRTYPE(PCPDMPICHLP) pPicHlp;
166	} DEVPICRC;
167	/** Pointer to the raw-mode PIC instance data. */
168	typedef DEVPICRC *PDEVPICRC;
169
170
171	/** The PIC instance data for the current context. */
172	typedef CTX_SUFF(DEVPIC) DEVPICCC;
173	/** Pointer to the PIC instance data for the current context. */
174	typedef CTX_SUFF(PDEVPIC) PDEVPICCC;
175
176
177
178	#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* The rest of the file! */
179
180	#ifdef LOG_ENABLED
181	DECLINLINE(void) DumpPICState(PPICSTATE pPic, const char *pszFn)
182	{
183	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
184	pszFn, pPic->idxPic, pPic->elcr, pPic->last_irr, pPic->irr, pPic->imr, pPic->isr, pPic->irq_base));
185	}
186	#else
187	# define DumpPICState(pThis, szFn) do { } while (0)
188	#endif
189
190	/* set irq level. If an edge is detected, then the IRR is set to 1 */
191	DECLINLINE(void) pic_set_irq1(PPICSTATE pPic, int irq, int level, uint32_t uTagSrc)
192	{
193	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
194	int mask = 1 << irq;
195	if (pPic->elcr & mask)
196	{
197	/* level triggered */
198	if (level)
199	{
200	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", pPic->irr, pPic->irr \| mask));
201	pPic->irr \|= mask;
202	pPic->last_irr \|= mask;
203	}
204	else
205	{
206	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", pPic->irr, pPic->irr & ~mask));
207	pPic->irr &= ~mask;
208	pPic->last_irr &= ~mask;
209	}
210	}
211	else
212	{
213	/* edge triggered */
214	if (level)
215	{
216	if ((pPic->last_irr & mask) == 0)
217	{
218	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", pPic->irr \| mask, pPic->last_irr));
219	pPic->irr \|= mask;
220	}
221	pPic->last_irr \|= mask;
222	}
223	else
224	{
225	pPic->irr &= ~mask;
226	pPic->last_irr &= ~mask;
227	}
228	}
229
230	/* Save the tag. */
231	if (level)
232	{
233	if (!pPic->auTags[irq])
234	pPic->auTags[irq] = uTagSrc;
235	else
236	pPic->auTags[irq] \|= RT_BIT_32(31);
237	}
238
239	DumpPICState(pPic, "pic_set_irq1");
240	}
241
242	/* return the highest priority found in mask (highest = smallest
243	number). Return 8 if no irq */
244	DECLINLINE(int) get_priority(PPICSTATE pPic, int mask)
245	{
246	int priority;
247	if (mask == 0)
248	return 8;
249	priority = 0;
250	while ((mask & (1 << ((priority + pPic->priority_add) & 7))) == 0)
251	priority++;
252	return priority;
253	}
254
255	/* return the pic wanted interrupt. return -1 if none */
256	static int pic_get_irq(PPICSTATE pPic)
257	{
258	int mask, cur_priority, priority;
259	Log(("pic_get_irq%d: mask=%x\n", pPic->idxPic, pPic->irr & ~pPic->imr));
260	DumpPICState(pPic, "pic_get_irq");
261
262	mask = pPic->irr & ~pPic->imr;
263	priority = get_priority(pPic, mask);
264	Log(("pic_get_irq: priority=%x\n", priority));
265	if (priority == 8)
266	return -1;
267	/* compute current priority. If special fully nested mode on the
268	master, the IRQ coming from the slave is not taken into account
269	for the priority computation. */
270	mask = pPic->isr;
271	if (pPic->special_mask)
272	mask &= ~pPic->imr;
273	if (pPic->special_fully_nested_mode && pPic->idxPic == 0)
274	mask &= ~(1 << 2);
275	cur_priority = get_priority(pPic, mask);
276	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", pPic->idxPic,
277	cur_priority, (priority == 8) ? -1 : (priority + pPic->priority_add) & 7));
278	if (priority < cur_priority)
279	{
280	/* higher priority found: an irq should be generated */
281	return (priority + pPic->priority_add) & 7;
282	}
283	return -1;
284	}
285
286	/* raise irq to CPU if necessary. must be called every time the active
287	irq may change */
288	static int pic_update_irq(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC)
289	{
290	int irq2, irq;
291
292	/* first look at slave pic */
293	irq2 = pic_get_irq(&pThis->aPics[1]);
294	Log(("pic_update_irq irq2=%d\n", irq2));
295	if (irq2 >= 0)
296	{
297	/* if irq request by slave pic, signal master PIC */
298	pic_set_irq1(&pThis->aPics[0], 2, 1, pThis->aPics[1].auTags[irq2]);
299	}
300	else
301	{
302	/* If not, clear the IR on the master PIC. */
303	pic_set_irq1(&pThis->aPics[0], 2, 0, 0 /uTagSrc/);
304	}
305	/* look at requested irq */
306	irq = pic_get_irq(&pThis->aPics[0]);
307	if (irq >= 0)
308	{
309	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
310	* spurious slave interrupts in picGetInterrupt.
311	*/
312	if (irq != 2 \|\| irq2 != -1)
313	{
314	for (int i = 0; i < 2; i++)
315	Log(("pic%d: imr=%x irr=%x padd=%d\n", i, pThis->aPics[i].imr, pThis->aPics[i].irr, pThis->aPics[i].priority_add));
316	Log(("pic: cpu_interrupt\n"));
317	pThisCC->pPicHlp->pfnSetInterruptFF(pDevIns);
318	}
319	else
320	{
321	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
322	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
323	/* Clear it here, so lower priority interrupts can still be dispatched. */
324
325	/* if this was the only pending irq, then we must clear the interrupt ff flag */
326	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
327
328	/** @todo Is this correct? */
329	pThis->aPics[0].irr &= ~(1 << 2);
330
331	/* Call ourselves again just in case other interrupts are pending */
332	return pic_update_irq(pDevIns, pThis, pThisCC);
333	}
334	}
335	else
336	{
337	Log(("pic_update_irq: no interrupt is pending!!\n"));
338
339	/* we must clear the interrupt ff flag */
340	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
341	}
342	return VINF_SUCCESS;
343	}
344
345	/**
346	* Set the an IRQ.
347	*
348	* @param pDevIns Device instance of the PICs.
349	* @param pDevIns
350	* @param iIrq IRQ number to set.
351	* @param iLevel IRQ level.
352	* @param uTagSrc The IRQ tag and source ID (for tracing).
353	*/
354	static DECLCALLBACK(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
355	{
356	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
357	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
358	AssertMsgReturnVoid(iIrq < 16, ("iIrq=%d\n", iIrq));
359
360	Log(("picSetIrq %d %d\n", iIrq, iLevel));
361	DumpPICState(&pThis->aPics[0], "picSetIrq");
362	DumpPICState(&pThis->aPics[1], "picSetIrq");
363	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
364	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
365	{
366	/* A flip-flop lowers the IRQ line and immediately raises it, so
367	* that a rising edge is guaranteed to occur. Note that the IRQ
368	* line must be held high for a while to avoid spurious interrupts.
369	*/
370	pic_set_irq1(&RT_SAFE_SUBSCRIPT(pThis->aPics, iIrq >> 3), iIrq & 7, 0, uTagSrc);
371	pic_update_irq(pDevIns, pThis, pThisCC);
372	}
373	pic_set_irq1(&RT_SAFE_SUBSCRIPT(pThis->aPics, iIrq >> 3), iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc);
374	pic_update_irq(pDevIns, pThis, pThisCC);
375	}
376
377
378	/* acknowledge interrupt 'irq' */
379	DECLINLINE(void) pic_intack(PPICSTATE pPic, int irq)
380	{
381	if (pPic->auto_eoi)
382	{
383	if (pPic->rotate_on_auto_eoi)
384	pPic->priority_add = (irq + 1) & 7;
385	}
386	else
387	pPic->isr \|= (1 << irq);
388
389	/* We don't clear a level sensitive interrupt here */
390	if (!(pPic->elcr & (1 << irq)))
391	{
392	Log2(("pic_intack: irr=%x irrnew=%x\n", pPic->irr, pPic->irr & ~(1 << irq)));
393	pPic->irr &= ~(1 << irq);
394	}
395	}
396
397
398	/**
399	* Get a pending interrupt.
400	*
401	* @returns Pending interrupt number.
402	* @param pDevIns Device instance of the PICs.
403	* @param puTagSrc Where to return the IRQ tag and source ID.
404	*/
405	static DECLCALLBACK(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
406	{
407	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
408	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
409	int irq;
410	int irq2;
411	int intno;
412
413	/* read the irq from the PIC */
414	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
415	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
416
417	irq = pic_get_irq(&pThis->aPics[0]);
418	if (irq >= 0)
419	{
420	pic_intack(&pThis->aPics[0], irq);
421	if (irq == 2)
422	{
423	irq2 = pic_get_irq(&pThis->aPics[1]);
424	if (irq2 >= 0)
425	pic_intack(&pThis->aPics[1], irq2);
426	else
427	{
428	/* Interrupt went away or is now masked. */
429	Log(("picGetInterrupt: spurious IRQ on slave controller, converted to IRQ15\n"));
430	irq2 = 7;
431	}
432	intno = pThis->aPics[1].irq_base + irq2;
433	*puTagSrc = pThis->aPics[0].auTags[irq2];
434	pThis->aPics[0].auTags[irq2] = 0;
435	Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc));
436	irq = irq2 + 8;
437	}
438	else
439	{
440	intno = pThis->aPics[0].irq_base + irq;
441	*puTagSrc = pThis->aPics[0].auTags[irq];
442	pThis->aPics[0].auTags[irq] = 0;
443	Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc));
444	}
445	}
446	else
447	{
448	/* Interrupt went away or is now masked. */
449	Log(("picGetInterrupt: spurious IRQ on master controller, converted to IRQ7\n"));
450	irq = 7;
451	intno = pThis->aPics[0].irq_base + irq;
452	*puTagSrc = 0;
453	}
454	pic_update_irq(pDevIns, pThis, pThisCC);
455
456	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
457
458	return intno;
459	}
460
461	static void pic_reset(PPICSTATE pPic)
462	{
463	pPic->last_irr = 0;
464	pPic->irr = 0;
465	pPic->imr = 0;
466	pPic->isr = 0;
467	pPic->priority_add = 0;
468	pPic->irq_base = 0;
469	pPic->read_reg_select = 0;
470	pPic->poll = 0;
471	pPic->special_mask = 0;
472	pPic->init_state = 0;
473	pPic->auto_eoi = 0;
474	pPic->rotate_on_auto_eoi = 0;
475	pPic->special_fully_nested_mode = 0;
476	pPic->init4 = 0;
477	//pPic->elcr - not cleared;
478	//pPic->elcr_mask - not cleared;
479	RT_ZERO(pPic->auTags);
480	}
481
482
483	static VBOXSTRICTRC pic_ioport_write(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic,
484	uint32_t addr, uint32_t val)
485	{
486	VBOXSTRICTRC rc = VINF_SUCCESS;
487	int irq;
488
489	Log(("pic_write/%zu: addr=0x%02x val=0x%02x\n", pPic - pThis->aPics, addr, val));
490	addr &= 1;
491	if (addr == 0)
492	{
493	if (val & 0x10)
494	{
495	/* init */
496	pic_reset(pPic);
497	/* deassert a pending interrupt */
498	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
499
500	pPic->init_state = 1;
501	pPic->init4 = val & 1;
502	if (val & 0x02)
503	AssertReleaseMsgFailed(("single mode not supported"));
504	if (val & 0x08)
505	if (pThis->cRelLogEntries++ < 64)
506	LogRel(("pic_write: Level sensitive IRQ setting ignored.\n"));
507	}
508	else if (val & 0x08)
509	{
510	if (val & 0x04)
511	pPic->poll = 1;
512	if (val & 0x02)
513	pPic->read_reg_select = val & 1;
514	if (val & 0x40)
515	pPic->special_mask = (val >> 5) & 1;
516	}
517	else
518	{
519	int cmd = val >> 5;
520	switch (cmd)
521	{
522	case 0:
523	case 4:
524	pPic->rotate_on_auto_eoi = cmd >> 2;
525	break;
526	case 1: /* end of interrupt */
527	case 5:
528	{
529	int priority = get_priority(pPic, pPic->isr);
530	if (priority != 8) {
531	irq = (priority + pPic->priority_add) & 7;
532	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
533	pPic->isr &= ~(1 << irq);
534	if (cmd == 5)
535	pPic->priority_add = (irq + 1) & 7;
536	rc = pic_update_irq(pDevIns, pThis, pThisCC);
537	Assert(rc == VINF_SUCCESS);
538	DumpPICState(pPic, "eoi");
539	}
540	break;
541	}
542	case 3:
543	{
544	irq = val & 7;
545	Log(("pic_write: EOI2 for irq %d\n", irq));
546	pPic->isr &= ~(1 << irq);
547	rc = pic_update_irq(pDevIns, pThis, pThisCC);
548	Assert(rc == VINF_SUCCESS);
549	DumpPICState(pPic, "eoi2");
550	break;
551	}
552	case 6:
553	{
554	pPic->priority_add = (val + 1) & 7;
555	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, pPic->priority_add));
556	rc = pic_update_irq(pDevIns, pThis, pThisCC);
557	Assert(rc == VINF_SUCCESS);
558	break;
559	}
560	case 7:
561	{
562	irq = val & 7;
563	Log(("pic_write: EOI3 for irq %d\n", irq));
564	pPic->isr &= ~(1 << irq);
565	pPic->priority_add = (irq + 1) & 7;
566	rc = pic_update_irq(pDevIns, pThis, pThisCC);
567	Assert(rc == VINF_SUCCESS);
568	DumpPICState(pPic, "eoi3");
569	break;
570	}
571	default:
572	/* no operation */
573	break;
574	}
575	}
576	}
577	else
578	{
579	switch (pPic->init_state)
580	{
581	case 0:
582	/* normal mode */
583	pPic->imr = val;
584	rc = pic_update_irq(pDevIns, pThis, pThisCC);
585	Assert(rc == VINF_SUCCESS);
586	break;
587	case 1:
588	pPic->irq_base = val & 0xf8;
589	pPic->init_state = 2;
590	Log(("pic_write: set irq base to %x\n", pPic->irq_base));
591	break;
592	case 2:
593	if (pPic->init4)
594	pPic->init_state = 3;
595	else
596	pPic->init_state = 0;
597	break;
598	case 3:
599	pPic->special_fully_nested_mode = (val >> 4) & 1;
600	pPic->auto_eoi = (val >> 1) & 1;
601	pPic->init_state = 0;
602	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", pPic->special_fully_nested_mode, pPic->auto_eoi));
603	break;
604	}
605	}
606	return rc;
607	}
608
609
610	static uint32_t pic_poll_read(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic, uint32_t addr1)
611	{
612	int ret = pic_get_irq(pPic);
613	if (ret >= 0)
614	{
615	if (addr1 >> 7)
616	{
617	Log2(("pic_poll_read: clear slave irq (isr)\n"));
618	pThis->aPics[0].isr &= ~(1 << 2);
619	pThis->aPics[0].irr &= ~(1 << 2);
620	}
621	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
622	pPic->irr &= ~(1 << ret);
623	pPic->isr &= ~(1 << ret);
624	if (addr1 >> 7 \|\| ret != 2)
625	pic_update_irq(pDevIns, pThis, pThisCC);
626	}
627	else
628	{
629	ret = 0;
630	pic_update_irq(pDevIns, pThis, pThisCC);
631	}
632
633	return ret;
634	}
635
636
637	static uint32_t pic_ioport_read(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic, uint32_t addr1, int *pRC)
638	{
639	unsigned int addr;
640	int ret;
641
642	*pRC = VINF_SUCCESS;
643
644	addr = addr1;
645	addr &= 1;
646	if (pPic->poll)
647	{
648	ret = pic_poll_read(pDevIns, pThis, pThisCC, pPic, addr1);
649	pPic->poll = 0;
650	}
651	else
652	{
653	if (addr == 0)
654	{
655	if (pPic->read_reg_select)
656	ret = pPic->isr;
657	else
658	ret = pPic->irr;
659	}
660	else
661	ret = pPic->imr;
662	}
663	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
664	return ret;
665	}
666
667
668
669	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
670
671	/**
672	* @callback_method_impl{FNIOMIOPORTIN}
673	*/
674	static DECLCALLBACK(VBOXSTRICTRC) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
675	{
676	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
677	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
678	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
679
680	Assert(iPic == 0 \|\| iPic == 1);
681	if (cb == 1)
682	{
683	int rc;
684	PIC_LOCK(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
685	*pu32 = pic_ioport_read(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, &rc);
686	PIC_UNLOCK(pDevIns, pThisCC);
687	return rc;
688	}
689	return VERR_IOM_IOPORT_UNUSED;
690	}
691
692
693	/**
694	* @callback_method_impl{FNIOMIOPORTNEWOUT}
695	*/
696	static DECLCALLBACK(VBOXSTRICTRC) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
697	{
698	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
699	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
700	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
701
702	Assert(iPic == 0 \|\| iPic == 1);
703
704	if (cb == 1)
705	{
706	VBOXSTRICTRC rc;
707	PIC_LOCK(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
708	rc = pic_ioport_write(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, u32);
709	PIC_UNLOCK(pDevIns, pThisCC);
710	return rc;
711	}
712	return VINF_SUCCESS;
713	}
714
715
716	/**
717	* @callback_method_impl{FNIOMIOPORTNEWIN, ELCR}
718	*/
719	static DECLCALLBACK(VBOXSTRICTRC) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
720	{
721	if (cb == 1)
722	{
723	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
724	PPICSTATE pPic = (PPICSTATE)pvUser;
725	PIC_LOCK(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
726	*pu32 = pPic->elcr;
727	PIC_UNLOCK(pDevIns, pThisCC);
728	return VINF_SUCCESS;
729	}
730	RT_NOREF(offPort);
731	return VERR_IOM_IOPORT_UNUSED;
732	}
733
734
735	/**
736	* @callback_method_impl{FNIOMIOPORTNEWOUT, ELCR}
737	*/
738	static DECLCALLBACK(VBOXSTRICTRC) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
739	{
740	if (cb == 1)
741	{
742	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
743	PPICSTATE pPic = (PPICSTATE)pvUser;
744	PIC_LOCK(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
745	pPic->elcr = u32 & pPic->elcr_mask;
746	PIC_UNLOCK(pDevIns, pThisCC);
747	}
748	RT_NOREF(offPort);
749	return VINF_SUCCESS;
750	}
751
752
753	#ifdef IN_RING3
754
755	/**
756	* @callback_method_impl{FNDBGFHANDLERDEV}
757	*/
758	static DECLCALLBACK(void) picIR3nfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
759	{
760	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
761	NOREF(pszArgs);
762
763	/*
764	* Show info.
765	*/
766	for (int i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
767	{
768	PPICSTATE pPic = &pThis->aPics[i];
769
770	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
771	pHlp->pfnPrintf(pHlp, " IMR :%02x ISR :%02x IRR :%02x LIRR:%02x\n",
772	pPic->imr, pPic->isr, pPic->irr, pPic->last_irr);
773	pHlp->pfnPrintf(pHlp, " Base:%02x PriAdd:%02x RegSel:%02x\n",
774	pPic->irq_base, pPic->priority_add, pPic->read_reg_select);
775	pHlp->pfnPrintf(pHlp, " Poll:%02x SpMask:%02x IState:%02x\n",
776	pPic->poll, pPic->special_mask, pPic->init_state);
777	pHlp->pfnPrintf(pHlp, " AEOI:%02x Rotate:%02x FNest :%02x Ini4:%02x\n",
778	pPic->auto_eoi, pPic->rotate_on_auto_eoi,
779	pPic->special_fully_nested_mode, pPic->init4);
780	pHlp->pfnPrintf(pHlp, " ELCR:%02x ELMask:%02x\n", pPic->elcr, pPic->elcr_mask);
781	}
782	}
783
784
785	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
786
787	/**
788	* @callback_method_impl{FNSSMDEVSAVEEXEC}
789	*/
790	static DECLCALLBACK(int) picR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
791	{
792	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
793	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
794
795	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
796	{
797	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].last_irr);
798	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].irr);
799	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].imr);
800	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].isr);
801	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].priority_add);
802	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].irq_base);
803	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].read_reg_select);
804	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].poll);
805	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].special_mask);
806	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].init_state);
807	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].auto_eoi);
808	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].rotate_on_auto_eoi);
809	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].special_fully_nested_mode);
810	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].init4);
811	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].elcr);
812	}
813	return VINF_SUCCESS;
814	}
815
816
817	/**
818	* @callback_method_impl{FNSSMDEVLOADEXEC}
819	*/
820	static DECLCALLBACK(int) picR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
821	{
822	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
823	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
824
825	if (uVersion != 1)
826	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
827	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
828
829	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
830	{
831	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].last_irr);
832	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].irr);
833	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].imr);
834	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].isr);
835	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].priority_add);
836	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].irq_base);
837	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].read_reg_select);
838	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].poll);
839	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].special_mask);
840	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].init_state);
841	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].auto_eoi);
842	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].rotate_on_auto_eoi);
843	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].special_fully_nested_mode);
844	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].init4);
845	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].elcr);
846	}
847
848	/* Note! PDM will restore the VMCPU_FF_INTERRUPT_PIC state. */
849	return VINF_SUCCESS;
850	}
851
852
853	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
854
855	/**
856	* @interface_method_impl{PDMDEVREG,pfnReset}
857	*/
858	static DECLCALLBACK(void) picR3Reset(PPDMDEVINS pDevIns)
859	{
860	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
861	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
862	unsigned i;
863	LogFlow(("picR3Reset:\n"));
864	pThisCC->pPicHlp->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
865
866	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
867	pic_reset(&pThis->aPics[i]);
868
869	PIC_UNLOCK(pDevIns, pThisCC);
870	}
871
872
873	/**
874	* @interface_method_impl{PDMDEVREG,pfnRelocate}
875	*/
876	static DECLCALLBACK(void) picR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
877	{
878	PDEVPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PDEVPICRC);
879	pThisRC->pPicHlp += offDelta;
880	}
881
882
883	/**
884	* @interface_method_impl{PDMDEVREG,pfnConstruct}
885	*/
886	static DECLCALLBACK(int) picR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
887	{
888	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
889	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
890	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
891	int rc;
892	RT_NOREF(iInstance, pCfg);
893
894	Assert(iInstance == 0);
895
896	/*
897	* Validate and read configuration.
898	*/
899	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
900	Log(("DevPIC: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
901
902	/*
903	* Init the data.
904	*/
905	Assert(RT_ELEMENTS(pThis->aPics) == 2);
906	pThis->aPics[0].elcr_mask = 0xf8;
907	pThis->aPics[1].elcr_mask = 0xde;
908	pThis->aPics[0].idxPic = 0;
909	pThis->aPics[1].idxPic = 1;
910	pThis->cRelLogEntries = 0;
911
912	/*
913	* Register us as the PIC with PDM.
914	*/
915	PDMPICREG PicReg;
916	PicReg.u32Version = PDM_PICREG_VERSION;
917	PicReg.pfnSetIrq = picSetIrq;
918	PicReg.pfnGetInterrupt = picGetInterrupt;
919	PicReg.u32TheEnd = PDM_PICREG_VERSION;
920	rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThisCC->pPicHlp);
921	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpPICRegister -> %Rrc\n", rc), rc);
922	AssertReturn(pThisCC->pPicHlp->u32Version == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
923	AssertReturn(pThisCC->pPicHlp->u32TheEnd == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
924
925	/*
926	* Since the PIC helper interface provides access to the PDM lock,
927	* we need no device level critical section.
928	*/
929	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
930	AssertRCReturn(rc, rc);
931
932	/*
933	* Register I/O ports and save state.
934	*/
935	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x20 /uPort/, 2 /cPorts/, picIOPortWrite, picIOPortRead, (void *)0,
936	"i8259 PIC #0", NULL /paExtDesc/, &pThis->aPics[0].hIoPorts0);
937	AssertRCReturn(rc, rc);
938	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xa0 /uPort/, 2 /cPorts/, picIOPortWrite, picIOPortRead, (void *)1,
939	"i8259 PIC #1", NULL /paExtDesc/, &pThis->aPics[1].hIoPorts0);
940	AssertRCReturn(rc, rc);
941
942
943	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x4d0 /uPort/, 1 /cPorts/, picIOPortElcrWrite, picIOPortElcrRead,
944	&pThis->aPics[0], "i8259 PIC #0 - elcr", NULL /paExtDesc/, &pThis->aPics[0].hIoPorts1);
945	AssertRCReturn(rc, rc);
946	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x4d1 /uPort/, 1 /cPorts/, picIOPortElcrWrite, picIOPortElcrRead,
947	&pThis->aPics[1], "i8259 PIC #1 - elcr", NULL /paExtDesc/, &pThis->aPics[1].hIoPorts1);
948	AssertRCReturn(rc, rc);
949
950	/*
951	* Saved state.
952	*/
953	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion /, sizeof(pThis), picR3SaveExec, picR3LoadExec);
954	AssertRCReturn(rc, rc);
955
956	/*
957	* Register the info item.
958	*/
959	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picIR3nfo);
960
961	/*
962	* Initialize the device state.
963	*/
964	picR3Reset(pDevIns);
965
966	# ifdef VBOX_WITH_STATISTICS
967	/*
968	* Statistics.
969	*/
970	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "SetIrqRZ", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in ring-0/raw-mode.");
971	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "SetIrqR3", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in ring-3.");
972
973	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
974	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
975	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
976	# endif
977
978	return VINF_SUCCESS;
979	}
980
981	#else /* !IN_RING3 */
982
983	/**
984	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
985	*/
986	static DECLCALLBACK(int) picRZConstruct(PPDMDEVINS pDevIns)
987	{
988	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
989	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
990	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
991
992	/* NOP the critsect: */
993	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
994	AssertRCReturn(rc, rc);
995
996	/* Set up the PIC callbacks: */
997	PDMPICREG PicReg;
998	PicReg.u32Version = PDM_PICREG_VERSION;
999	PicReg.pfnSetIrq = picSetIrq;
1000	PicReg.pfnGetInterrupt = picGetInterrupt;
1001	PicReg.u32TheEnd = PDM_PICREG_VERSION;
1002	rc = PDMDevHlpPICSetUpContext(pDevIns, &PicReg, &pThisCC->pPicHlp);
1003	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpPICSetUpContext -> %Rrc\n", rc), rc);
1004	AssertPtrReturn(pThisCC->pPicHlp, VERR_INTERNAL_ERROR_3);
1005	AssertReturn(pThisCC->pPicHlp->u32Version == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
1006	AssertReturn(pThisCC->pPicHlp->u32TheEnd == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
1007
1008	/* I/O port callbacks: */
1009	Assert(RT_ELEMENTS(pThis->aPics) == 2);
1010	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[0].hIoPorts0, picIOPortWrite, picIOPortRead, (void *)0);
1011	AssertRCReturn(rc, rc);
1012	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[1].hIoPorts0, picIOPortWrite, picIOPortRead, (void *)1);
1013	AssertRCReturn(rc, rc);
1014
1015	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[0].hIoPorts1, picIOPortElcrWrite, picIOPortElcrRead, &pThis->aPics[0]);
1016	AssertRCReturn(rc, rc);
1017	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[1].hIoPorts1, picIOPortElcrWrite, picIOPortElcrRead, &pThis->aPics[1]);
1018	AssertRCReturn(rc, rc);
1019
1020	return VINF_SUCCESS;
1021	}
1022
1023	#endif /* !IN_RING3 */
1024
1025	/**
1026	* The device registration structure.
1027	*/
1028	const PDMDEVREG g_DeviceI8259 =
1029	{
1030	/* .u32Version = */ PDM_DEVREG_VERSION,
1031	/* .uReserved0 = */ 0,
1032	/* .szName = */ "i8259",
1033	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1034	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1035	/* .cMaxInstances = */ 1,
1036	/* .uSharedVersion = */ 42,
1037	/* .cbInstanceShared = */ sizeof(DEVPIC),
1038	/* .cbInstanceCC = */ sizeof(DEVPICCC),
1039	/* .cbInstanceRC = */ sizeof(DEVPICRC),
1040	/* .cMaxPciDevices = */ 0,
1041	/* .cMaxMsixVectors = */ 0,
1042	/* .pszDescription = */ "Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1043	#if defined(IN_RING3)
1044	/* .pszRCMod = */ "VBoxDDRC.rc",
1045	/* .pszR0Mod = */ "VBoxDDR0.r0",
1046	/* .pfnConstruct = */ picR3Construct,
1047	/* .pfnDestruct = */ NULL,
1048	/* .pfnRelocate = */ picR3Relocate,
1049	/* .pfnMemSetup = */ NULL,
1050	/* .pfnPowerOn = */ NULL,
1051	/* .pfnReset = */ picR3Reset,
1052	/* .pfnSuspend = */ NULL,
1053	/* .pfnResume = */ NULL,
1054	/* .pfnAttach = */ NULL,
1055	/* .pfnDetach = */ NULL,
1056	/* .pfnQueryInterface = */ NULL,
1057	/* .pfnInitComplete = */ NULL,
1058	/* .pfnPowerOff = */ NULL,
1059	/* .pfnSoftReset = */ NULL,
1060	/* .pfnReserved0 = */ NULL,
1061	/* .pfnReserved1 = */ NULL,
1062	/* .pfnReserved2 = */ NULL,
1063	/* .pfnReserved3 = */ NULL,
1064	/* .pfnReserved4 = */ NULL,
1065	/* .pfnReserved5 = */ NULL,
1066	/* .pfnReserved6 = */ NULL,
1067	/* .pfnReserved7 = */ NULL,
1068	#elif defined(IN_RING0)
1069	/* .pfnEarlyConstruct = */ NULL,
1070	/* .pfnConstruct = */ picRZConstruct,
1071	/* .pfnDestruct = */ NULL,
1072	/* .pfnFinalDestruct = */ NULL,
1073	/* .pfnRequest = */ NULL,
1074	/* .pfnReserved0 = */ NULL,
1075	/* .pfnReserved1 = */ NULL,
1076	/* .pfnReserved2 = */ NULL,
1077	/* .pfnReserved3 = */ NULL,
1078	/* .pfnReserved4 = */ NULL,
1079	/* .pfnReserved5 = */ NULL,
1080	/* .pfnReserved6 = */ NULL,
1081	/* .pfnReserved7 = */ NULL,
1082	#elif defined(IN_RC)
1083	/* .pfnConstruct = */ picRZConstruct,
1084	/* .pfnReserved0 = */ NULL,
1085	/* .pfnReserved1 = */ NULL,
1086	/* .pfnReserved2 = */ NULL,
1087	/* .pfnReserved3 = */ NULL,
1088	/* .pfnReserved4 = */ NULL,
1089	/* .pfnReserved5 = */ NULL,
1090	/* .pfnReserved6 = */ NULL,
1091	/* .pfnReserved7 = */ NULL,
1092	#else
1093	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1094	#endif
1095	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1096	};
1097
1098	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1099

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 81914

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