DevPIC.cpp@ 91575

Last change on this file since 91575 was 90436, checked in by vboxsync, 3 years ago
VMM,Dev*: Handle PDMCritSectEnter failures in relation to the PDM critsect. bugref:6695
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1	/* $Id: DevPIC.cpp 90436 2021-07-30 16:03:48Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* -------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8259 interrupt controller emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*
42	*/
43
44
45	/*********************************************************************************************************************************
46	* Header Files *
47	*********************************************************************************************************************************/
48	#define LOG_GROUP LOG_GROUP_DEV_PIC
49	#include <VBox/vmm/pdmdev.h>
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include "VBoxDD.h"
55
56
57	/*********************************************************************************************************************************
58	* Defined Constants And Macros *
59	*********************************************************************************************************************************/
60	/** @def PIC_LOCK_RET
61	* Acquires the PDM lock. This is a NOP if locking is disabled. */
62	#define PIC_LOCK_RET(a_pDevIns, a_pThisCC, rcBusy) \
63	do { \
64	int const rcLock = (a_pThisCC)->pPicHlp->pfnLock((a_pDevIns), rcBusy); \
65	if (rcLock == VINF_SUCCESS) \
66	{ /* likely */ } \
67	else \
68	return rcLock; \
69	} while (0)
70	/** @def PIC_UNLOCK
71	* Releases the PDM lock. This is a NOP if locking is disabled. */
72	#define PIC_UNLOCK(a_pDevIns, a_pThisCC) \
73	(a_pThisCC)->pPicHlp->pfnUnlock((a_pDevIns))
74
75
76	/*********************************************************************************************************************************
77	* Structures and Typedefs *
78	*********************************************************************************************************************************/
79	/**
80	* The instance data of one (1) PIC.
81	*/
82	typedef struct PICSTATE
83	{
84	uint8_t last_irr; /*< edge detection /
85	uint8_t irr; /*< interrupt request register /
86	uint8_t imr; /*< interrupt mask register /
87	uint8_t isr; /*< interrupt service register /
88	uint8_t priority_add; /*< highest irq priority /
89	uint8_t irq_base;
90	uint8_t read_reg_select;
91	uint8_t poll;
92	uint8_t special_mask;
93	uint8_t init_state;
94	uint8_t auto_eoi;
95	uint8_t rotate_on_auto_eoi;
96	uint8_t special_fully_nested_mode;
97	uint8_t init4; /*< true if 4 byte init /
98	uint8_t elcr; /*< PIIX edge/trigger selection/
99	uint8_t elcr_mask;
100	/** The IRQ tags and source IDs for each (tracing purposes). */
101	uint32_t auTags[8];
102	/** The PIC index (0 or 1). */
103	uint8_t idxPic;
104	uint8_t abAlignment0[7]; /*< Alignment padding. /
105	/** The two I/O ports at 0x20 or 0xa0. */
106	IOMIOPORTHANDLE hIoPorts0;
107	/** The ELCR I/O port at 0x4d0 or 0x4d1. */
108	IOMIOPORTHANDLE hIoPorts1;
109	} PICSTATE;
110	AssertCompileMemberAlignment(PICSTATE, hIoPorts0, 8);
111	/** Pointer to the state of one PIC. */
112	typedef PICSTATE *PPICSTATE;
113
114
115	/**
116	* The shared PIC device instance data.
117	*/
118	typedef struct DEVPIC
119	{
120	/** The two interrupt controllers. */
121	PICSTATE aPics[2];
122	/** Number of release log entries. Used to prevent flooding. */
123	uint32_t cRelLogEntries;
124	uint32_t u32Padding;
125	#ifdef VBOX_WITH_STATISTICS
126	STAMCOUNTER StatSetIrqRZ;
127	STAMCOUNTER StatSetIrqR3;
128	STAMCOUNTER StatClearedActiveIRQ2;
129	STAMCOUNTER StatClearedActiveMasterIRQ;
130	STAMCOUNTER StatClearedActiveSlaveIRQ;
131	#endif
132	} DEVPIC;
133	/** Pointer to the shared PIC instance data. */
134	typedef DEVPIC *PDEVPIC;
135
136
137	/**
138	* The PIC device instance data for ring-3.
139	*/
140	typedef struct DEVPICR3
141	{
142	/** Pointer to the PIC ring-3 helpers. */
143	R3PTRTYPE(PCPDMPICHLP) pPicHlp;
144	} DEVPICR3;
145	/** Pointer to the ring-3 PIC instance data. */
146	typedef DEVPICR3 *PDEVPICR3;
147
148
149	/**
150	* The PIC device instance data for ring-0.
151	*/
152	typedef struct DEVPICR0
153	{
154	/** Pointer to the PIC ring-0 helpers. */
155	R0PTRTYPE(PCPDMPICHLP) pPicHlp;
156	} DEVPICR0;
157	/** Pointer to the ring-0 PIC instance data. */
158	typedef DEVPICR0 *PDEVPICR0;
159
160
161	/**
162	* The PIC device instance data for raw-mode.
163	*/
164	typedef struct DEVPICRC
165	{
166	/** Pointer to the PIC raw-mode helpers. */
167	RCPTRTYPE(PCPDMPICHLP) pPicHlp;
168	} DEVPICRC;
169	/** Pointer to the raw-mode PIC instance data. */
170	typedef DEVPICRC *PDEVPICRC;
171
172
173	/** The PIC instance data for the current context. */
174	typedef CTX_SUFF(DEVPIC) DEVPICCC;
175	/** Pointer to the PIC instance data for the current context. */
176	typedef CTX_SUFF(PDEVPIC) PDEVPICCC;
177
178
179
180	#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* The rest of the file! */
181
182	#ifdef LOG_ENABLED
183	DECLINLINE(void) DumpPICState(PPICSTATE pPic, const char *pszFn)
184	{
185	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
186	pszFn, pPic->idxPic, pPic->elcr, pPic->last_irr, pPic->irr, pPic->imr, pPic->isr, pPic->irq_base));
187	}
188	#else
189	# define DumpPICState(pThis, szFn) do { } while (0)
190	#endif
191
192	/* set irq level. If an edge is detected, then the IRR is set to 1 */
193	DECLINLINE(void) pic_set_irq1(PPICSTATE pPic, int irq, int level, uint32_t uTagSrc)
194	{
195	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
196	int mask = 1 << irq;
197	if (pPic->elcr & mask)
198	{
199	/* level triggered */
200	if (level)
201	{
202	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", pPic->irr, pPic->irr \| mask));
203	pPic->irr \|= mask;
204	pPic->last_irr \|= mask;
205	}
206	else
207	{
208	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", pPic->irr, pPic->irr & ~mask));
209	pPic->irr &= ~mask;
210	pPic->last_irr &= ~mask;
211	}
212	}
213	else
214	{
215	/* edge triggered */
216	if (level)
217	{
218	if ((pPic->last_irr & mask) == 0)
219	{
220	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", pPic->irr \| mask, pPic->last_irr));
221	pPic->irr \|= mask;
222	}
223	pPic->last_irr \|= mask;
224	}
225	else
226	{
227	pPic->irr &= ~mask;
228	pPic->last_irr &= ~mask;
229	}
230	}
231
232	/* Save the tag. */
233	if (level)
234	{
235	if (!pPic->auTags[irq])
236	pPic->auTags[irq] = uTagSrc;
237	else
238	pPic->auTags[irq] \|= RT_BIT_32(31);
239	}
240
241	DumpPICState(pPic, "pic_set_irq1");
242	}
243
244	/* return the highest priority found in mask (highest = smallest
245	number). Return 8 if no irq */
246	DECLINLINE(int) get_priority(PPICSTATE pPic, int mask)
247	{
248	int priority;
249	if (mask == 0)
250	return 8;
251	priority = 0;
252	while ((mask & (1 << ((priority + pPic->priority_add) & 7))) == 0)
253	priority++;
254	return priority;
255	}
256
257	/* return the pic wanted interrupt. return -1 if none */
258	static int pic_get_irq(PPICSTATE pPic)
259	{
260	int mask, cur_priority, priority;
261	Log(("pic_get_irq%d: mask=%x\n", pPic->idxPic, pPic->irr & ~pPic->imr));
262	DumpPICState(pPic, "pic_get_irq");
263
264	mask = pPic->irr & ~pPic->imr;
265	priority = get_priority(pPic, mask);
266	Log(("pic_get_irq: priority=%x\n", priority));
267	if (priority == 8)
268	return -1;
269	/* compute current priority. If special fully nested mode on the
270	master, the IRQ coming from the slave is not taken into account
271	for the priority computation. */
272	mask = pPic->isr;
273	if (pPic->special_mask)
274	mask &= ~pPic->imr;
275	if (pPic->special_fully_nested_mode && pPic->idxPic == 0)
276	mask &= ~(1 << 2);
277	cur_priority = get_priority(pPic, mask);
278	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", pPic->idxPic,
279	cur_priority, (priority == 8) ? -1 : (priority + pPic->priority_add) & 7));
280	if (priority < cur_priority)
281	{
282	/* higher priority found: an irq should be generated */
283	return (priority + pPic->priority_add) & 7;
284	}
285	return -1;
286	}
287
288	/* raise irq to CPU if necessary. must be called every time the active
289	irq may change */
290	static int pic_update_irq(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC)
291	{
292	int irq2, irq;
293
294	/* first look at slave pic */
295	irq2 = pic_get_irq(&pThis->aPics[1]);
296	Log(("pic_update_irq irq2=%d\n", irq2));
297	if (irq2 >= 0)
298	{
299	/* if irq request by slave pic, signal master PIC */
300	pic_set_irq1(&pThis->aPics[0], 2, 1, pThis->aPics[1].auTags[irq2]);
301	}
302	else
303	{
304	/* If not, clear the IR on the master PIC. */
305	pic_set_irq1(&pThis->aPics[0], 2, 0, 0 /uTagSrc/);
306	}
307	/* look at requested irq */
308	irq = pic_get_irq(&pThis->aPics[0]);
309	if (irq >= 0)
310	{
311	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
312	* spurious slave interrupts in picGetInterrupt.
313	*/
314	if (irq != 2 \|\| irq2 != -1)
315	{
316	for (int i = 0; i < 2; i++)
317	Log(("pic%d: imr=%x irr=%x padd=%d\n", i, pThis->aPics[i].imr, pThis->aPics[i].irr, pThis->aPics[i].priority_add));
318	Log(("pic: cpu_interrupt\n"));
319	pThisCC->pPicHlp->pfnSetInterruptFF(pDevIns);
320	}
321	else
322	{
323	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
324	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
325	/* Clear it here, so lower priority interrupts can still be dispatched. */
326
327	/* if this was the only pending irq, then we must clear the interrupt ff flag */
328	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
329
330	/** @todo Is this correct? */
331	pThis->aPics[0].irr &= ~(1 << 2);
332
333	/* Call ourselves again just in case other interrupts are pending */
334	return pic_update_irq(pDevIns, pThis, pThisCC);
335	}
336	}
337	else
338	{
339	Log(("pic_update_irq: no interrupt is pending!!\n"));
340
341	/* we must clear the interrupt ff flag */
342	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
343	}
344	return VINF_SUCCESS;
345	}
346
347	/**
348	* Set the an IRQ.
349	*
350	* @param pDevIns Device instance of the PICs.
351	* @param iIrq IRQ number to set.
352	* @param iLevel IRQ level.
353	* @param uTagSrc The IRQ tag and source ID (for tracing).
354	*/
355	static DECLCALLBACK(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
356	{
357	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
358	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
359	AssertMsgReturnVoid(iIrq < 16, ("iIrq=%d\n", iIrq));
360
361	Log(("picSetIrq %d %d\n", iIrq, iLevel));
362	DumpPICState(&pThis->aPics[0], "picSetIrq");
363	DumpPICState(&pThis->aPics[1], "picSetIrq");
364	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
365	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
366	{
367	/* A flip-flop lowers the IRQ line and immediately raises it, so
368	* that a rising edge is guaranteed to occur. Note that the IRQ
369	* line must be held high for a while to avoid spurious interrupts.
370	*/
371	pic_set_irq1(&RT_SAFE_SUBSCRIPT(pThis->aPics, iIrq >> 3), iIrq & 7, 0, uTagSrc);
372	pic_update_irq(pDevIns, pThis, pThisCC);
373	}
374	pic_set_irq1(&RT_SAFE_SUBSCRIPT(pThis->aPics, iIrq >> 3), iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc);
375	pic_update_irq(pDevIns, pThis, pThisCC);
376	}
377
378
379	/* acknowledge interrupt 'irq' */
380	DECLINLINE(void) pic_intack(PPICSTATE pPic, int irq)
381	{
382	if (pPic->auto_eoi)
383	{
384	if (pPic->rotate_on_auto_eoi)
385	pPic->priority_add = (irq + 1) & 7;
386	}
387	else
388	pPic->isr \|= (1 << irq);
389
390	/* We don't clear a level sensitive interrupt here */
391	if (!(pPic->elcr & (1 << irq)))
392	{
393	Log2(("pic_intack: irr=%x irrnew=%x\n", pPic->irr, pPic->irr & ~(1 << irq)));
394	pPic->irr &= ~(1 << irq);
395	}
396	}
397
398
399	/**
400	* Get a pending interrupt.
401	*
402	* @returns Pending interrupt number.
403	* @param pDevIns Device instance of the PICs.
404	* @param puTagSrc Where to return the IRQ tag and source ID.
405	*/
406	static DECLCALLBACK(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
407	{
408	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
409	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
410	int irq;
411	int irq2;
412	int intno;
413
414	/* read the irq from the PIC */
415	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
416	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
417
418	irq = pic_get_irq(&pThis->aPics[0]);
419	if (irq >= 0)
420	{
421	pic_intack(&pThis->aPics[0], irq);
422	if (irq == 2)
423	{
424	irq2 = pic_get_irq(&pThis->aPics[1]);
425	if (irq2 >= 0)
426	pic_intack(&pThis->aPics[1], irq2);
427	else
428	{
429	/* Interrupt went away or is now masked. */
430	Log(("picGetInterrupt: spurious IRQ on slave controller, converted to IRQ15\n"));
431	irq2 = 7;
432	}
433	intno = pThis->aPics[1].irq_base + irq2;
434	*puTagSrc = pThis->aPics[0].auTags[irq2];
435	pThis->aPics[0].auTags[irq2] = 0;
436	Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc));
437	irq = irq2 + 8;
438	}
439	else
440	{
441	intno = pThis->aPics[0].irq_base + irq;
442	*puTagSrc = pThis->aPics[0].auTags[irq];
443	pThis->aPics[0].auTags[irq] = 0;
444	Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc));
445	}
446	}
447	else
448	{
449	/* Interrupt went away or is now masked. */
450	Log(("picGetInterrupt: spurious IRQ on master controller, converted to IRQ7\n"));
451	irq = 7;
452	intno = pThis->aPics[0].irq_base + irq;
453	*puTagSrc = 0;
454	}
455	pic_update_irq(pDevIns, pThis, pThisCC);
456
457	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
458
459	return intno;
460	}
461
462	static void pic_reset(PPICSTATE pPic)
463	{
464	pPic->last_irr = 0;
465	pPic->irr = 0;
466	pPic->imr = 0;
467	pPic->isr = 0;
468	pPic->priority_add = 0;
469	pPic->irq_base = 0;
470	pPic->read_reg_select = 0;
471	pPic->poll = 0;
472	pPic->special_mask = 0;
473	pPic->init_state = 0;
474	pPic->auto_eoi = 0;
475	pPic->rotate_on_auto_eoi = 0;
476	pPic->special_fully_nested_mode = 0;
477	pPic->init4 = 0;
478	//pPic->elcr - not cleared;
479	//pPic->elcr_mask - not cleared;
480	RT_ZERO(pPic->auTags);
481	}
482
483
484	static VBOXSTRICTRC pic_ioport_write(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic,
485	uint32_t addr, uint32_t val)
486	{
487	VBOXSTRICTRC rc = VINF_SUCCESS;
488	int irq;
489
490	Log(("pic_write/%zu: addr=0x%02x val=0x%02x\n", pPic - pThis->aPics, addr, val));
491	addr &= 1;
492	if (addr == 0)
493	{
494	if (val & 0x10)
495	{
496	/* init */
497	pic_reset(pPic);
498	/* deassert a pending interrupt */
499	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
500
501	pPic->init_state = 1;
502	pPic->init4 = val & 1;
503	if (val & 0x02)
504	AssertReleaseMsgFailed(("single mode not supported"));
505	if (val & 0x08)
506	if (pThis->cRelLogEntries++ < 64)
507	LogRel(("pic_write: Level sensitive IRQ setting ignored.\n"));
508	}
509	else if (val & 0x08)
510	{
511	if (val & 0x04)
512	pPic->poll = 1;
513	if (val & 0x02)
514	pPic->read_reg_select = val & 1;
515	if (val & 0x40)
516	pPic->special_mask = (val >> 5) & 1;
517	}
518	else
519	{
520	int cmd = val >> 5;
521	switch (cmd)
522	{
523	case 0:
524	case 4:
525	pPic->rotate_on_auto_eoi = cmd >> 2;
526	break;
527	case 1: /* end of interrupt */
528	case 5:
529	{
530	int priority = get_priority(pPic, pPic->isr);
531	if (priority != 8) {
532	irq = (priority + pPic->priority_add) & 7;
533	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
534	pPic->isr &= ~(1 << irq);
535	if (cmd == 5)
536	pPic->priority_add = (irq + 1) & 7;
537	rc = pic_update_irq(pDevIns, pThis, pThisCC);
538	Assert(rc == VINF_SUCCESS);
539	DumpPICState(pPic, "eoi");
540	}
541	break;
542	}
543	case 3:
544	{
545	irq = val & 7;
546	Log(("pic_write: EOI2 for irq %d\n", irq));
547	pPic->isr &= ~(1 << irq);
548	rc = pic_update_irq(pDevIns, pThis, pThisCC);
549	Assert(rc == VINF_SUCCESS);
550	DumpPICState(pPic, "eoi2");
551	break;
552	}
553	case 6:
554	{
555	pPic->priority_add = (val + 1) & 7;
556	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, pPic->priority_add));
557	rc = pic_update_irq(pDevIns, pThis, pThisCC);
558	Assert(rc == VINF_SUCCESS);
559	break;
560	}
561	case 7:
562	{
563	irq = val & 7;
564	Log(("pic_write: EOI3 for irq %d\n", irq));
565	pPic->isr &= ~(1 << irq);
566	pPic->priority_add = (irq + 1) & 7;
567	rc = pic_update_irq(pDevIns, pThis, pThisCC);
568	Assert(rc == VINF_SUCCESS);
569	DumpPICState(pPic, "eoi3");
570	break;
571	}
572	default:
573	/* no operation */
574	break;
575	}
576	}
577	}
578	else
579	{
580	switch (pPic->init_state)
581	{
582	case 0:
583	/* normal mode */
584	pPic->imr = val;
585	rc = pic_update_irq(pDevIns, pThis, pThisCC);
586	Assert(rc == VINF_SUCCESS);
587	break;
588	case 1:
589	pPic->irq_base = val & 0xf8;
590	pPic->init_state = 2;
591	Log(("pic_write: set irq base to %x\n", pPic->irq_base));
592	break;
593	case 2:
594	if (pPic->init4)
595	pPic->init_state = 3;
596	else
597	pPic->init_state = 0;
598	break;
599	case 3:
600	pPic->special_fully_nested_mode = (val >> 4) & 1;
601	pPic->auto_eoi = (val >> 1) & 1;
602	pPic->init_state = 0;
603	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", pPic->special_fully_nested_mode, pPic->auto_eoi));
604	break;
605	}
606	}
607	return rc;
608	}
609
610
611	static uint32_t pic_poll_read(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic, uint32_t addr1)
612	{
613	int ret = pic_get_irq(pPic);
614	if (ret >= 0)
615	{
616	if (addr1 >> 7)
617	{
618	Log2(("pic_poll_read: clear slave irq (isr)\n"));
619	pThis->aPics[0].isr &= ~(1 << 2);
620	pThis->aPics[0].irr &= ~(1 << 2);
621	}
622	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
623	pPic->irr &= ~(1 << ret);
624	pPic->isr &= ~(1 << ret);
625	if (addr1 >> 7 \|\| ret != 2)
626	pic_update_irq(pDevIns, pThis, pThisCC);
627	}
628	else
629	{
630	ret = 0;
631	pic_update_irq(pDevIns, pThis, pThisCC);
632	}
633
634	return ret;
635	}
636
637
638	static uint32_t pic_ioport_read(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic, uint32_t addr1, int *pRC)
639	{
640	unsigned int addr;
641	int ret;
642
643	*pRC = VINF_SUCCESS;
644
645	addr = addr1;
646	addr &= 1;
647	if (pPic->poll)
648	{
649	ret = pic_poll_read(pDevIns, pThis, pThisCC, pPic, addr1);
650	pPic->poll = 0;
651	}
652	else
653	{
654	if (addr == 0)
655	{
656	if (pPic->read_reg_select)
657	ret = pPic->isr;
658	else
659	ret = pPic->irr;
660	}
661	else
662	ret = pPic->imr;
663	}
664	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
665	return ret;
666	}
667
668
669
670	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
671
672	/**
673	* @callback_method_impl{FNIOMIOPORTNEWIN}
674	*/
675	static DECLCALLBACK(VBOXSTRICTRC) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
676	{
677	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
678	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
679	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
680
681	Assert(iPic == 0 \|\| iPic == 1);
682	if (cb == 1)
683	{
684	int rc;
685	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
686	*pu32 = pic_ioport_read(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, &rc);
687	PIC_UNLOCK(pDevIns, pThisCC);
688	return rc;
689	}
690	return VERR_IOM_IOPORT_UNUSED;
691	}
692
693
694	/**
695	* @callback_method_impl{FNIOMIOPORTNEWOUT}
696	*/
697	static DECLCALLBACK(VBOXSTRICTRC) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
698	{
699	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
700	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
701	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
702
703	Assert(iPic == 0 \|\| iPic == 1);
704
705	if (cb == 1)
706	{
707	VBOXSTRICTRC rc;
708	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
709	rc = pic_ioport_write(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, u32);
710	PIC_UNLOCK(pDevIns, pThisCC);
711	return rc;
712	}
713	return VINF_SUCCESS;
714	}
715
716
717	/**
718	* @callback_method_impl{FNIOMIOPORTNEWIN, ELCR}
719	*/
720	static DECLCALLBACK(VBOXSTRICTRC) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
721	{
722	if (cb == 1)
723	{
724	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
725	PPICSTATE pPic = (PPICSTATE)pvUser;
726	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
727	*pu32 = pPic->elcr;
728	PIC_UNLOCK(pDevIns, pThisCC);
729	return VINF_SUCCESS;
730	}
731	RT_NOREF(offPort);
732	return VERR_IOM_IOPORT_UNUSED;
733	}
734
735
736	/**
737	* @callback_method_impl{FNIOMIOPORTNEWOUT, ELCR}
738	*/
739	static DECLCALLBACK(VBOXSTRICTRC) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
740	{
741	if (cb == 1)
742	{
743	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
744	PPICSTATE pPic = (PPICSTATE)pvUser;
745	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
746	pPic->elcr = u32 & pPic->elcr_mask;
747	PIC_UNLOCK(pDevIns, pThisCC);
748	}
749	RT_NOREF(offPort);
750	return VINF_SUCCESS;
751	}
752
753
754	#ifdef IN_RING3
755
756	/**
757	* @callback_method_impl{FNDBGFHANDLERDEV}
758	*/
759	static DECLCALLBACK(void) picR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
760	{
761	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
762	NOREF(pszArgs);
763
764	/*
765	* Show info.
766	*/
767	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
768	{
769	PPICSTATE pPic = &pThis->aPics[i];
770
771	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
772	pHlp->pfnPrintf(pHlp, " IMR :%02x ISR :%02x IRR :%02x LIRR:%02x\n",
773	pPic->imr, pPic->isr, pPic->irr, pPic->last_irr);
774	pHlp->pfnPrintf(pHlp, " Base:%02x PriAdd:%02x RegSel:%02x\n",
775	pPic->irq_base, pPic->priority_add, pPic->read_reg_select);
776	pHlp->pfnPrintf(pHlp, " Poll:%02x SpMask:%02x IState:%02x\n",
777	pPic->poll, pPic->special_mask, pPic->init_state);
778	pHlp->pfnPrintf(pHlp, " AEOI:%02x Rotate:%02x FNest :%02x Ini4:%02x\n",
779	pPic->auto_eoi, pPic->rotate_on_auto_eoi,
780	pPic->special_fully_nested_mode, pPic->init4);
781	pHlp->pfnPrintf(pHlp, " ELCR:%02x ELMask:%02x\n", pPic->elcr, pPic->elcr_mask);
782	}
783	}
784
785
786	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
787
788	/**
789	* @callback_method_impl{FNSSMDEVSAVEEXEC}
790	*/
791	static DECLCALLBACK(int) picR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
792	{
793	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
794	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
795
796	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
797	{
798	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].last_irr);
799	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].irr);
800	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].imr);
801	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].isr);
802	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].priority_add);
803	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].irq_base);
804	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].read_reg_select);
805	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].poll);
806	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].special_mask);
807	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].init_state);
808	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].auto_eoi);
809	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].rotate_on_auto_eoi);
810	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].special_fully_nested_mode);
811	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].init4);
812	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].elcr);
813	}
814	return VINF_SUCCESS;
815	}
816
817
818	/**
819	* @callback_method_impl{FNSSMDEVLOADEXEC}
820	*/
821	static DECLCALLBACK(int) picR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
822	{
823	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
824	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
825
826	if (uVersion != 1)
827	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
828	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
829
830	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
831	{
832	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].last_irr);
833	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].irr);
834	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].imr);
835	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].isr);
836	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].priority_add);
837	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].irq_base);
838	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].read_reg_select);
839	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].poll);
840	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].special_mask);
841	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].init_state);
842	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].auto_eoi);
843	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].rotate_on_auto_eoi);
844	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].special_fully_nested_mode);
845	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].init4);
846	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].elcr);
847	}
848
849	/* Note! PDM will restore the VMCPU_FF_INTERRUPT_PIC state. */
850	return VINF_SUCCESS;
851	}
852
853
854	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
855
856	/**
857	* @interface_method_impl{PDMDEVREG,pfnReset}
858	*/
859	static DECLCALLBACK(void) picR3Reset(PPDMDEVINS pDevIns)
860	{
861	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
862	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
863	unsigned i;
864	LogFlow(("picR3Reset:\n"));
865	pThisCC->pPicHlp->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
866
867	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
868	pic_reset(&pThis->aPics[i]);
869
870	PIC_UNLOCK(pDevIns, pThisCC);
871	}
872
873
874	/**
875	* @interface_method_impl{PDMDEVREG,pfnRelocate}
876	*/
877	static DECLCALLBACK(void) picR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
878	{
879	PDEVPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PDEVPICRC);
880	pThisRC->pPicHlp += offDelta;
881	}
882
883
884	/**
885	* @interface_method_impl{PDMDEVREG,pfnConstruct}
886	*/
887	static DECLCALLBACK(int) picR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
888	{
889	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
890	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
891	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
892	int rc;
893	RT_NOREF(iInstance, pCfg);
894
895	Assert(iInstance == 0);
896
897	/*
898	* Validate and read configuration.
899	*/
900	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
901	Log(("DevPIC: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
902
903	/*
904	* Init the data.
905	*/
906	Assert(RT_ELEMENTS(pThis->aPics) == 2);
907	pThis->aPics[0].elcr_mask = 0xf8;
908	pThis->aPics[1].elcr_mask = 0xde;
909	pThis->aPics[0].idxPic = 0;
910	pThis->aPics[1].idxPic = 1;
911	pThis->cRelLogEntries = 0;
912
913	/*
914	* Register us as the PIC with PDM.
915	*/
916	PDMPICREG PicReg;
917	PicReg.u32Version = PDM_PICREG_VERSION;
918	PicReg.pfnSetIrq = picSetIrq;
919	PicReg.pfnGetInterrupt = picGetInterrupt;
920	PicReg.u32TheEnd = PDM_PICREG_VERSION;
921	rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThisCC->pPicHlp);
922	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpPICRegister -> %Rrc\n", rc), rc);
923	AssertReturn(pThisCC->pPicHlp->u32Version == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
924	AssertReturn(pThisCC->pPicHlp->u32TheEnd == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
925
926	/*
927	* Since the PIC helper interface provides access to the PDM lock,
928	* we need no device level critical section.
929	*/
930	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
931	AssertRCReturn(rc, rc);
932
933	/*
934	* Register I/O ports and save state.
935	*/
936	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x20 /uPort/, 2 /cPorts/, picIOPortWrite, picIOPortRead, (void *)0,
937	"i8259 PIC #0", NULL /paExtDesc/, &pThis->aPics[0].hIoPorts0);
938	AssertRCReturn(rc, rc);
939	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xa0 /uPort/, 2 /cPorts/, picIOPortWrite, picIOPortRead, (void *)1,
940	"i8259 PIC #1", NULL /paExtDesc/, &pThis->aPics[1].hIoPorts0);
941	AssertRCReturn(rc, rc);
942
943
944	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x4d0 /uPort/, 1 /cPorts/, picIOPortElcrWrite, picIOPortElcrRead,
945	&pThis->aPics[0], "i8259 PIC #0 - elcr", NULL /paExtDesc/, &pThis->aPics[0].hIoPorts1);
946	AssertRCReturn(rc, rc);
947	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x4d1 /uPort/, 1 /cPorts/, picIOPortElcrWrite, picIOPortElcrRead,
948	&pThis->aPics[1], "i8259 PIC #1 - elcr", NULL /paExtDesc/, &pThis->aPics[1].hIoPorts1);
949	AssertRCReturn(rc, rc);
950
951	/*
952	* Saved state.
953	*/
954	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion /, sizeof(pThis), picR3SaveExec, picR3LoadExec);
955	AssertRCReturn(rc, rc);
956
957	/*
958	* Register the info item.
959	*/
960	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picR3Info);
961
962	/*
963	* Initialize the device state.
964	*/
965	picR3Reset(pDevIns);
966
967	# ifdef VBOX_WITH_STATISTICS
968	/*
969	* Statistics.
970	*/
971	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "SetIrqRZ", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in ring-0/raw-mode.");
972	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "SetIrqR3", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in ring-3.");
973
974	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
975	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
976	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
977	# endif
978
979	return VINF_SUCCESS;
980	}
981
982	#else /* !IN_RING3 */
983
984	/**
985	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
986	*/
987	static DECLCALLBACK(int) picRZConstruct(PPDMDEVINS pDevIns)
988	{
989	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
990	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
991	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
992
993	/* NOP the critsect: */
994	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
995	AssertRCReturn(rc, rc);
996
997	/* Set up the PIC callbacks: */
998	PDMPICREG PicReg;
999	PicReg.u32Version = PDM_PICREG_VERSION;
1000	PicReg.pfnSetIrq = picSetIrq;
1001	PicReg.pfnGetInterrupt = picGetInterrupt;
1002	PicReg.u32TheEnd = PDM_PICREG_VERSION;
1003	rc = PDMDevHlpPICSetUpContext(pDevIns, &PicReg, &pThisCC->pPicHlp);
1004	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpPICSetUpContext -> %Rrc\n", rc), rc);
1005	AssertPtrReturn(pThisCC->pPicHlp, VERR_INTERNAL_ERROR_3);
1006	AssertReturn(pThisCC->pPicHlp->u32Version == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
1007	AssertReturn(pThisCC->pPicHlp->u32TheEnd == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
1008
1009	/* I/O port callbacks: */
1010	Assert(RT_ELEMENTS(pThis->aPics) == 2);
1011	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[0].hIoPorts0, picIOPortWrite, picIOPortRead, (void *)0);
1012	AssertRCReturn(rc, rc);
1013	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[1].hIoPorts0, picIOPortWrite, picIOPortRead, (void *)1);
1014	AssertRCReturn(rc, rc);
1015
1016	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[0].hIoPorts1, picIOPortElcrWrite, picIOPortElcrRead, &pThis->aPics[0]);
1017	AssertRCReturn(rc, rc);
1018	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[1].hIoPorts1, picIOPortElcrWrite, picIOPortElcrRead, &pThis->aPics[1]);
1019	AssertRCReturn(rc, rc);
1020
1021	return VINF_SUCCESS;
1022	}
1023
1024	#endif /* !IN_RING3 */
1025
1026	/**
1027	* The device registration structure.
1028	*/
1029	const PDMDEVREG g_DeviceI8259 =
1030	{
1031	/* .u32Version = */ PDM_DEVREG_VERSION,
1032	/* .uReserved0 = */ 0,
1033	/* .szName = */ "i8259",
1034	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1035	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1036	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1037	/* .cMaxInstances = */ 1,
1038	/* .uSharedVersion = */ 42,
1039	/* .cbInstanceShared = */ sizeof(DEVPIC),
1040	/* .cbInstanceCC = */ sizeof(DEVPICCC),
1041	/* .cbInstanceRC = */ sizeof(DEVPICRC),
1042	/* .cMaxPciDevices = */ 0,
1043	/* .cMaxMsixVectors = */ 0,
1044	/* .pszDescription = */ "Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1045	#if defined(IN_RING3)
1046	/* .pszRCMod = */ "VBoxDDRC.rc",
1047	/* .pszR0Mod = */ "VBoxDDR0.r0",
1048	/* .pfnConstruct = */ picR3Construct,
1049	/* .pfnDestruct = */ NULL,
1050	/* .pfnRelocate = */ picR3Relocate,
1051	/* .pfnMemSetup = */ NULL,
1052	/* .pfnPowerOn = */ NULL,
1053	/* .pfnReset = */ picR3Reset,
1054	/* .pfnSuspend = */ NULL,
1055	/* .pfnResume = */ NULL,
1056	/* .pfnAttach = */ NULL,
1057	/* .pfnDetach = */ NULL,
1058	/* .pfnQueryInterface = */ NULL,
1059	/* .pfnInitComplete = */ NULL,
1060	/* .pfnPowerOff = */ NULL,
1061	/* .pfnSoftReset = */ NULL,
1062	/* .pfnReserved0 = */ NULL,
1063	/* .pfnReserved1 = */ NULL,
1064	/* .pfnReserved2 = */ NULL,
1065	/* .pfnReserved3 = */ NULL,
1066	/* .pfnReserved4 = */ NULL,
1067	/* .pfnReserved5 = */ NULL,
1068	/* .pfnReserved6 = */ NULL,
1069	/* .pfnReserved7 = */ NULL,
1070	#elif defined(IN_RING0)
1071	/* .pfnEarlyConstruct = */ NULL,
1072	/* .pfnConstruct = */ picRZConstruct,
1073	/* .pfnDestruct = */ NULL,
1074	/* .pfnFinalDestruct = */ NULL,
1075	/* .pfnRequest = */ NULL,
1076	/* .pfnReserved0 = */ NULL,
1077	/* .pfnReserved1 = */ NULL,
1078	/* .pfnReserved2 = */ NULL,
1079	/* .pfnReserved3 = */ NULL,
1080	/* .pfnReserved4 = */ NULL,
1081	/* .pfnReserved5 = */ NULL,
1082	/* .pfnReserved6 = */ NULL,
1083	/* .pfnReserved7 = */ NULL,
1084	#elif defined(IN_RC)
1085	/* .pfnConstruct = */ picRZConstruct,
1086	/* .pfnReserved0 = */ NULL,
1087	/* .pfnReserved1 = */ NULL,
1088	/* .pfnReserved2 = */ NULL,
1089	/* .pfnReserved3 = */ NULL,
1090	/* .pfnReserved4 = */ NULL,
1091	/* .pfnReserved5 = */ NULL,
1092	/* .pfnReserved6 = */ NULL,
1093	/* .pfnReserved7 = */ NULL,
1094	#else
1095	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1096	#endif
1097	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1098	};
1099
1100	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1101

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 91575

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