DevPIC.cpp@ 9584

Last change on this file since 9584 was 9387, checked in by vboxsync, 17 years ago
64-bit GC alignment fixes
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 37.4 KB

Line
1	/* $Id: DevPIC.cpp 9387 2008-06-04 13:51:21Z vboxsync $ */
2	/** @file
3	* Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PIC
26	#include <VBox/pdmdev.h>
27	#include <VBox/log.h>
28	#include <iprt/assert.h>
29
30	#include "vl_vbox.h"
31
32
33	/*******************************************************************************
34	* Defined Constants And Macros *
35	*******************************************************************************/
36	/** @def PIC_LOCK
37	* Acquires the PDM lock. This is a NOP if locking is disabled. */
38	/** @def PIC_UNLOCK
39	* Releases the PDM lock. This is a NOP if locking is disabled. */
40	#ifdef VBOX_WITH_PDM_LOCK
41	# define PIC_LOCK(pThis, rc) \
42	do { \
43	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
44	if (rc2 != VINF_SUCCESS) \
45	return rc2; \
46	} while (0)
47	# define PIC_UNLOCK(pThis) \
48	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
49	#else /* !VBOX_WITH_PDM_LOCK */
50	# define PIC_LOCK(pThis, rc) do { } while (0)
51	# define PIC_UNLOCK(pThis) do { } while (0)
52	#endif /* !VBOX_WITH_PDM_LOCK */
53
54
55	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
56	/*******************************************************************************
57	* Internal Functions *
58	*******************************************************************************/
59	__BEGIN_DECLS
60
61	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
62	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
63	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
64	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
65	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
66	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
67
68	__END_DECLS
69	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
70
71
72	/*
73	* QEMU 8259 interrupt controller emulation
74	*
75	* Copyright (c) 2003-2004 Fabrice Bellard
76	*
77	* Permission is hereby granted, free of charge, to any person obtaining a copy
78	* of this software and associated documentation files (the "Software"), to deal
79	* in the Software without restriction, including without limitation the rights
80	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
81	* copies of the Software, and to permit persons to whom the Software is
82	* furnished to do so, subject to the following conditions:
83	*
84	* The above copyright notice and this permission notice shall be included in
85	* all copies or substantial portions of the Software.
86	*
87	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
88	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
89	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
90	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
91	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
92	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
93	* THE SOFTWARE.
94	*/
95
96	/* debug PIC */
97	#define DEBUG_PIC
98
99	/#define DEBUG_IRQ_COUNT/
100
101	typedef struct PicState {
102	uint8_t last_irr; /* edge detection */
103	uint8_t irr; /* interrupt request register */
104	uint8_t imr; /* interrupt mask register */
105	uint8_t isr; /* interrupt service register */
106	uint8_t priority_add; /* highest irq priority */
107	uint8_t irq_base;
108	uint8_t read_reg_select;
109	uint8_t poll;
110	uint8_t special_mask;
111	uint8_t init_state;
112	uint8_t auto_eoi;
113	uint8_t rotate_on_auto_eoi;
114	uint8_t special_fully_nested_mode;
115	uint8_t init4; /* true if 4 byte init */
116	uint8_t elcr; /* PIIX edge/trigger selection*/
117	uint8_t elcr_mask;
118	/** Pointer to the device instance, HCPtr. */
119	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;
120	/** Pointer to the device instance, GCPtr. */
121	RCPTRTYPE(PPDMDEVINS) pDevInsGC;
122	#if HC_ARCH_BITS == 64
123	RTRCPTR Alignment0;
124	#endif
125	} PicState;
126
127	/**
128	* A PIC device instance data.
129	*/
130	typedef struct DEVPIC
131	{
132	/** The two interrupt controllers. */
133	PicState aPics[2];
134	/** Pointer to the PIC R3 helpers. */
135	PCPDMPICHLPR3 pPicHlpR3;
136	/** Pointer to the PIC R0 helpers. */
137	PCPDMPICHLPR0 pPicHlpR0;
138	/** Pointer to the PIC GC helpers. */
139	PCPDMPICHLPGC pPicHlpGC;
140	#if HC_ARCH_BITS == 32
141	uint32_t Alignmnet1;
142	#endif
143	/** Pointer to the device instance - GC Ptr. */
144	RCPTRTYPE(PPDMDEVINS) pDevInsGC;
145	/** Pointer to the device instance - GC Ptr. */
146	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;
147	#ifdef VBOX_WITH_STATISTICS
148	STAMCOUNTER StatSetIrqGC;
149	STAMCOUNTER StatSetIrqHC;
150	STAMCOUNTER StatClearedActiveIRQ2;
151	STAMCOUNTER StatClearedActiveMasterIRQ;
152	STAMCOUNTER StatClearedActiveSlaveIRQ;
153	#endif
154	} DEVPIC, *PDEVPIC;
155
156
157	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
158	#ifdef LOG_ENABLED
159	static inline void DumpPICState(PicState s, const char szFn)
160	{
161	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
162
163	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
164	szFn, (&pData->aPics[0] == s) ? 0 : 1,
165	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
166	}
167	#else
168	# define DumpPICState(pData, szFn) do { } while (0)
169	#endif
170
171	/* set irq level. If an edge is detected, then the IRR is set to 1 */
172	static inline void pic_set_irq1(PicState *s, int irq, int level)
173	{
174	int mask;
175	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
176	mask = 1 << irq;
177	if (s->elcr & mask) {
178	/* level triggered */
179	if (level) {
180	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", s->irr, s->irr \| mask));
181	s->irr \|= mask;
182	s->last_irr \|= mask;
183	} else {
184	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", s->irr, s->irr & ~mask));
185	s->irr &= ~mask;
186	s->last_irr &= ~mask;
187	}
188	} else {
189	/* edge triggered */
190	if (level) {
191	if ((s->last_irr & mask) == 0)
192	{
193	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
194	s->irr \|= mask;
195	}
196	s->last_irr \|= mask;
197	} else {
198	s->last_irr &= ~mask;
199	}
200	}
201	DumpPICState(s, "pic_set_irq1");
202	}
203
204	/* return the highest priority found in mask (highest = smallest
205	number). Return 8 if no irq */
206	static inline int get_priority(PicState *s, int mask)
207	{
208	int priority;
209	if (mask == 0)
210	return 8;
211	priority = 0;
212	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
213	priority++;
214	return priority;
215	}
216
217	/* return the pic wanted interrupt. return -1 if none */
218	static int pic_get_irq(PicState *s)
219	{
220	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
221	int mask, cur_priority, priority;
222	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
223	DumpPICState(s, "pic_get_irq");
224
225	mask = s->irr & ~s->imr;
226	priority = get_priority(s, mask);
227	Log(("pic_get_irq: priority=%x\n", priority));
228	if (priority == 8)
229	return -1;
230	/* compute current priority. If special fully nested mode on the
231	master, the IRQ coming from the slave is not taken into account
232	for the priority computation. */
233	mask = s->isr;
234	if (s->special_fully_nested_mode && s == &pics[0])
235	mask &= ~(1 << 2);
236	cur_priority = get_priority(s, mask);
237	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
238	if (priority < cur_priority) {
239	/* higher priority found: an irq should be generated */
240	return (priority + s->priority_add) & 7;
241	} else {
242	return -1;
243	}
244	}
245
246	/* raise irq to CPU if necessary. must be called every time the active
247	irq may change */
248	static int pic_update_irq(PDEVPIC pData)
249	{
250	PicState *pics = &pData->aPics[0];
251	int irq2, irq;
252
253	/* first look at slave pic */
254	irq2 = pic_get_irq(&pics[1]);
255	Log(("pic_update_irq irq2=%d\n", irq2));
256	if (irq2 >= 0) {
257	/* if irq request by slave pic, signal master PIC */
258	pic_set_irq1(&pics[0], 2, 1);
259	pic_set_irq1(&pics[0], 2, 0);
260	}
261	/* look at requested irq */
262	irq = pic_get_irq(&pics[0]);
263	if (irq >= 0)
264	{
265	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
266	* spurious slave interrupts in picGetInterrupt.
267	*/
268	if (irq != 2 \|\| irq2 != -1)
269	{
270	#if defined(DEBUG_PIC)
271	int i;
272	for(i = 0; i < 2; i++) {
273	Log(("pic%d: imr=%x irr=%x padd=%d\n",
274	i, pics[i].imr, pics[i].irr,
275	pics[i].priority_add));
276	}
277	Log(("pic: cpu_interrupt\n"));
278	#endif
279	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
280	}
281	else
282	{
283	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
284	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
285	/* Clear it here, so lower priority interrupts can still be dispatched. */
286
287	/* if this was the only pending irq, then we must clear the interrupt ff flag */
288	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
289
290	/** @note Is this correct? */
291	pics[0].irr &= ~(1 << 2);
292
293	/* Call ourselves again just in case other interrupts are pending */
294	return pic_update_irq(pData);
295	}
296	}
297	else
298	{
299	Log(("pic_update_irq: no interrupt is pending!!\n"));
300
301	/* we must clear the interrupt ff flag */
302	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
303	}
304	return VINF_SUCCESS;
305	}
306
307	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
308	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
309	{
310	int irq, intno;
311	PicState *pActivePIC;
312
313	/* Query the current pending irq, if any. */
314	pActivePIC = &pData->aPics[0];
315	intno = irq = pic_get_irq(pActivePIC);
316	if (irq == 2)
317	{
318	pActivePIC = &pData->aPics[1];
319	irq = pic_get_irq(pActivePIC);
320	intno = irq + 8;
321	}
322
323	/* Update IMR */
324	s->imr = val;
325
326	/* If an interrupt is pending and now masked, then clear the FF flag. */
327	if ( irq >= 0
328	&& ((1 << irq) & ~pActivePIC->imr) == 0)
329	{
330	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
331	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
332	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
333	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
334
335	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
336	/** @todo Is this correct? */
337	if (intno > 7)
338	{
339	pData->aPics[0].irr &= ~(1 << 2);
340	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
341	}
342	else
343	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
344
345	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
346	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
347	}
348	}
349
350
351	/**
352	* Set the an IRQ.
353	*
354	* @param pDevIns Device instance of the PICs.
355	* @param iIrq IRQ number to set.
356	* @param iLevel IRQ level.
357	*/
358	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
359	{
360	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
361	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
362	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
363	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
364	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
365
366	Log(("picSetIrq %d %d\n", iIrq, iLevel));
367	DumpPICState(&pData->aPics[0], "picSetIrq");
368	DumpPICState(&pData->aPics[1], "picSetIrq");
369	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
370	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
371	pic_update_irq(pData);
372	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
373	{
374	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, 0);
375	pic_update_irq(pData);
376	}
377	}
378
379
380	/* acknowledge interrupt 'irq' */
381	static inline void pic_intack(PicState *s, int irq)
382	{
383	if (s->auto_eoi) {
384	if (s->rotate_on_auto_eoi)
385	s->priority_add = (irq + 1) & 7;
386	} else {
387	s->isr \|= (1 << irq);
388	}
389	/* We don't clear a level sensitive interrupt here */
390	if (!(s->elcr & (1 << irq)))
391	{
392	Log2(("pic_intack: irr=%x irrnew=%x\n", s->irr, s->irr & ~(1 << irq)));
393	s->irr &= ~(1 << irq);
394	}
395	}
396
397
398	/**
399	* Get a pending interrupt.
400	*
401	* @returns Pending interrupt number.
402	* @param pDevIns Device instance of the PICs.
403	*/
404	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
405	{
406	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
407	int irq;
408	int irq2;
409	int intno;
410
411	/* read the irq from the PIC */
412	DumpPICState(&pData->aPics[0], "picGetInterrupt");
413	DumpPICState(&pData->aPics[1], "picGetInterrupt");
414
415	irq = pic_get_irq(&pData->aPics[0]);
416	if (irq >= 0)
417	{
418	pic_intack(&pData->aPics[0], irq);
419	if (irq == 2)
420	{
421	irq2 = pic_get_irq(&pData->aPics[1]);
422	if (irq2 >= 0) {
423	pic_intack(&pData->aPics[1], irq2);
424	}
425	else
426	{
427	/* spurious IRQ on slave controller (impossible) */
428	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
429	irq2 = 7;
430	}
431	intno = pData->aPics[1].irq_base + irq2;
432	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
433	irq = irq2 + 8;
434	}
435	else {
436	intno = pData->aPics[0].irq_base + irq;
437	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
438	}
439	}
440	else
441	{
442	/* spurious IRQ on host controller (impossible) */
443	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
444	irq = 7;
445	intno = pData->aPics[0].irq_base + irq;
446	}
447	pic_update_irq(pData);
448
449	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
450
451	return intno;
452	}
453
454	static void pic_reset(PicState *s)
455	{
456	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
457	RCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
458	int tmp, tmp2;
459
460	tmp = s->elcr_mask;
461	tmp2 = s->elcr;
462	memset(s, 0, sizeof(PicState));
463	s->elcr_mask = tmp;
464	s->elcr = tmp2;
465	s->pDevInsHC = pDevInsHC;
466	s->pDevInsGC = pDevInsGC;
467	}
468
469
470	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
471	{
472	PicState s = (PicState)opaque;
473	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
474	int rc = VINF_SUCCESS;
475	int priority, cmd, irq;
476
477	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
478	addr &= 1;
479	if (addr == 0) {
480	if (val & 0x10) {
481	/* init */
482	pic_reset(s);
483	/* deassert a pending interrupt */
484	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
485
486	s->init_state = 1;
487	s->init4 = val & 1;
488	if (val & 0x02)
489	AssertReleaseMsgFailed(("single mode not supported"));
490	if (val & 0x08)
491	AssertReleaseMsgFailed(("level sensitive irq not supported"));
492	} else if (val & 0x08) {
493	if (val & 0x04)
494	s->poll = 1;
495	if (val & 0x02)
496	s->read_reg_select = val & 1;
497	if (val & 0x40)
498	s->special_mask = (val >> 5) & 1;
499	} else {
500	cmd = val >> 5;
501	switch(cmd) {
502	case 0:
503	case 4:
504	s->rotate_on_auto_eoi = cmd >> 2;
505	break;
506	case 1: /* end of interrupt */
507	case 5:
508	{
509	priority = get_priority(s, s->isr);
510	if (priority != 8) {
511	irq = (priority + s->priority_add) & 7;
512	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
513	s->isr &= ~(1 << irq);
514	if (cmd == 5)
515	s->priority_add = (irq + 1) & 7;
516	rc = pic_update_irq(pData);
517	Assert(rc == VINF_SUCCESS);
518	DumpPICState(s, "eoi");
519	}
520	break;
521	}
522	case 3:
523	{
524	irq = val & 7;
525	Log(("pic_write: EOI2 for irq %d\n", irq));
526	s->isr &= ~(1 << irq);
527	rc = pic_update_irq(pData);
528	Assert(rc == VINF_SUCCESS);
529	DumpPICState(s, "eoi2");
530	break;
531	}
532	case 6:
533	{
534	s->priority_add = (val + 1) & 7;
535	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, s->priority_add));
536	rc = pic_update_irq(pData);
537	Assert(rc == VINF_SUCCESS);
538	break;
539	}
540	case 7:
541	{
542	irq = val & 7;
543	Log(("pic_write: EOI3 for irq %d\n", irq));
544	s->isr &= ~(1 << irq);
545	s->priority_add = (irq + 1) & 7;
546	rc = pic_update_irq(pData);
547	Assert(rc == VINF_SUCCESS);
548	DumpPICState(s, "eoi3");
549	break;
550	}
551	default:
552	/* no operation */
553	break;
554	}
555	}
556	} else {
557	switch(s->init_state) {
558	case 0:
559	{
560	/* normal mode */
561	pic_update_imr(pData, s, val);
562
563	rc = pic_update_irq(pData);
564	Assert(rc == VINF_SUCCESS);
565	break;
566	}
567	case 1:
568	s->irq_base = val & 0xf8;
569	s->init_state = 2;
570	Log(("pic_write: set irq base to %x\n", s->irq_base));
571	break;
572	case 2:
573	if (s->init4) {
574	s->init_state = 3;
575	} else {
576	s->init_state = 0;
577	}
578	break;
579	case 3:
580	s->special_fully_nested_mode = (val >> 4) & 1;
581	s->auto_eoi = (val >> 1) & 1;
582	s->init_state = 0;
583	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
584	break;
585	}
586	}
587	return rc;
588	}
589
590
591	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
592	{
593	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
594	PicState *pics = &pData->aPics[0];
595	int ret;
596
597	ret = pic_get_irq(s);
598	if (ret >= 0) {
599	if (addr1 >> 7) {
600	Log2(("pic_poll_read: clear slave irq (isr)\n"));
601	pics[0].isr &= ~(1 << 2);
602	pics[0].irr &= ~(1 << 2);
603	}
604	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
605	s->irr &= ~(1 << ret);
606	s->isr &= ~(1 << ret);
607	if (addr1 >> 7 \|\| ret != 2)
608	pic_update_irq(pData);
609	} else {
610	ret = 0x07;
611	pic_update_irq(pData);
612	}
613
614	return ret;
615	}
616
617
618	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
619	{
620	PicState s = (PicState)opaque;
621	unsigned int addr;
622	int ret;
623
624	*pRC = VINF_SUCCESS;
625
626	addr = addr1;
627	addr &= 1;
628	if (s->poll) {
629	ret = pic_poll_read(s, addr1);
630	s->poll = 0;
631	} else {
632	if (addr == 0) {
633	if (s->read_reg_select)
634	ret = s->isr;
635	else
636	ret = s->irr;
637	} else {
638	ret = s->imr;
639	}
640	}
641	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
642	return ret;
643	}
644
645
646
647	#ifdef IN_RING3
648
649	static void pic_save(QEMUFile f, void opaque)
650	{
651	PicState s = (PicState)opaque;
652
653	qemu_put_8s(f, &s->last_irr);
654	qemu_put_8s(f, &s->irr);
655	qemu_put_8s(f, &s->imr);
656	qemu_put_8s(f, &s->isr);
657	qemu_put_8s(f, &s->priority_add);
658	qemu_put_8s(f, &s->irq_base);
659	qemu_put_8s(f, &s->read_reg_select);
660	qemu_put_8s(f, &s->poll);
661	qemu_put_8s(f, &s->special_mask);
662	qemu_put_8s(f, &s->init_state);
663	qemu_put_8s(f, &s->auto_eoi);
664	qemu_put_8s(f, &s->rotate_on_auto_eoi);
665	qemu_put_8s(f, &s->special_fully_nested_mode);
666	qemu_put_8s(f, &s->init4);
667	qemu_put_8s(f, &s->elcr);
668	}
669
670	static int pic_load(QEMUFile f, void opaque, int version_id)
671	{
672	PicState s = (PicState)opaque;
673
674	if (version_id != 1)
675	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
676
677	qemu_get_8s(f, &s->last_irr);
678	qemu_get_8s(f, &s->irr);
679	qemu_get_8s(f, &s->imr);
680	qemu_get_8s(f, &s->isr);
681	qemu_get_8s(f, &s->priority_add);
682	qemu_get_8s(f, &s->irq_base);
683	qemu_get_8s(f, &s->read_reg_select);
684	qemu_get_8s(f, &s->poll);
685	qemu_get_8s(f, &s->special_mask);
686	qemu_get_8s(f, &s->init_state);
687	qemu_get_8s(f, &s->auto_eoi);
688	qemu_get_8s(f, &s->rotate_on_auto_eoi);
689	qemu_get_8s(f, &s->special_fully_nested_mode);
690	qemu_get_8s(f, &s->init4);
691	qemu_get_8s(f, &s->elcr);
692	return 0;
693	}
694	#endif /* IN_RING3 */
695
696
697	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
698
699	/**
700	* Port I/O Handler for IN operations.
701	*
702	* @returns VBox status code.
703	*
704	* @param pDevIns The device instance.
705	* @param pvUser User argument - pointer to the PIC in question.
706	* @param uPort Port number used for the IN operation.
707	* @param pu32 Where to store the result.
708	* @param cb Number of bytes read.
709	*/
710	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
711	{
712	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
713	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
714
715	Assert(iPic == 0 \|\| iPic == 1);
716	if (cb == 1)
717	{
718	int rc;
719	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
720	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
721	PIC_UNLOCK(pData);
722	return rc;
723	}
724	return VERR_IOM_IOPORT_UNUSED;
725	}
726
727	/**
728	* Port I/O Handler for OUT operations.
729	*
730	* @returns VBox status code.
731	*
732	* @param pDevIns The device instance.
733	* @param pvUser User argument - pointer to the PIC in question.
734	* @param uPort Port number used for the IN operation.
735	* @param u32 The value to output.
736	* @param cb The value size in bytes.
737	*/
738	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
739	{
740	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
741	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
742
743	Assert(iPic == 0 \|\| iPic == 1);
744
745	if (cb == 1)
746	{
747	int rc;
748	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
749	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
750	PIC_UNLOCK(pData);
751	return rc;
752	}
753	return VINF_SUCCESS;
754	}
755
756
757	/**
758	* Port I/O Handler for IN operations.
759	*
760	* @returns VBox status code.
761	*
762	* @param pDevIns The device instance.
763	* @param pvUser User argument - pointer to the PIC in question.
764	* @param uPort Port number used for the IN operation.
765	* @param pu32 Where to store the result.
766	* @param cb Number of bytes read.
767	*/
768	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
769	{
770	if (cb == 1)
771	{
772	PicState s = (PicState)pvUser;
773	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
774	*pu32 = s->elcr;
775	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
776	return VINF_SUCCESS;
777	}
778	return VERR_IOM_IOPORT_UNUSED;
779	}
780
781	/**
782	* Port I/O Handler for OUT operations.
783	*
784	* @returns VBox status code.
785	*
786	* @param pDevIns The device instance.
787	* @param pvUser User argument - pointer to the PIC in question.
788	* @param uPort Port number used for the IN operation.
789	* @param u32 The value to output.
790	* @param cb The value size in bytes.
791	*/
792	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
793	{
794	if (cb == 1)
795	{
796	PicState s = (PicState)pvUser;
797	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
798	s->elcr = u32 & s->elcr_mask;
799	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
800	}
801	return VINF_SUCCESS;
802	}
803
804
805	#ifdef IN_RING3
806
807	#ifdef DEBUG
808	/**
809	* PIC status info callback.
810	*
811	* @param pDevIns The device instance.
812	* @param pHlp The output helpers.
813	* @param pszArgs The arguments.
814	*/
815	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
816	{
817	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
818
819	/*
820	* Show info.
821	*/
822	for (int i=0;i<2;i++)
823	{
824	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
825	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
826	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
827	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
828	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
829	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
830	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
831	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
832	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
833	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
834	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
835	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
836	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
837	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
838	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
839	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
840	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
841	}
842	}
843	#endif /* DEBUG */
844
845	/**
846	* Saves a state of the programmable interrupt controller device.
847	*
848	* @returns VBox status code.
849	* @param pDevIns The device instance.
850	* @param pSSMHandle The handle to save the state to.
851	*/
852	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
853	{
854	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
855	pic_save(pSSMHandle, &pData->aPics[0]);
856	pic_save(pSSMHandle, &pData->aPics[1]);
857	return VINF_SUCCESS;
858	}
859
860
861	/**
862	* Loads a saved programmable interrupt controller device state.
863	*
864	* @returns VBox status code.
865	* @param pDevIns The device instance.
866	* @param pSSMHandle The handle to the saved state.
867	* @param u32Version The data unit version number.
868	*/
869	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
870	{
871	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
872	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
873	if (VBOX_SUCCESS(rc))
874	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
875	return rc;
876	}
877
878
879	/* -=-=-=-=-=- real code -=-=-=-=-=- */
880
881	/**
882	* Reset notification.
883	*
884	* @returns VBox status.
885	* @param pDevIns The device instance data.
886	*/
887	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
888	{
889	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
890	unsigned i;
891	LogFlow(("picReset:\n"));
892	#ifdef VBOX_WITH_PDM_LOCK
893	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
894	#endif
895
896	for (i = 0; i < ELEMENTS(pData->aPics); i++)
897	pic_reset(&pData->aPics[i]);
898
899	PIC_UNLOCK(pData);
900	}
901
902
903	/**
904	* @copydoc FNPDMDEVRELOCATE
905	*/
906	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
907	{
908	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
909	unsigned i;
910
911	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
912	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
913	for (i = 0; i < ELEMENTS(pData->aPics); i++)
914	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
915	}
916
917
918	/**
919	* @copydoc FNPDMDEVCONSTRUCT
920	*/
921	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
922	{
923	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
924	PDMPICREG PicReg;
925	int rc;
926	bool fGCEnabled;
927	bool fR0Enabled;
928	Assert(iInstance == 0);
929
930	/*
931	* Validate and read configuration.
932	*/
933	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
934	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
935
936	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
937	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
938	fGCEnabled = true;
939	else if (VBOX_FAILURE(rc))
940	return PDMDEV_SET_ERROR(pDevIns, rc,
941	N_("Configuration error: failed to read GCEnabled as boolean"));
942
943	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
944	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
945	fR0Enabled = true;
946	else if (VBOX_FAILURE(rc))
947	return PDMDEV_SET_ERROR(pDevIns, rc,
948	N_("Configuration error: failed to read R0Enabled as boolean"));
949
950	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
951
952	/*
953	* Init the data.
954	*/
955	Assert(ELEMENTS(pData->aPics) == 2);
956	pData->pDevInsHC = pDevIns;
957	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
958	pData->aPics[0].elcr_mask = 0xf8;
959	pData->aPics[1].elcr_mask = 0xde;
960	pData->aPics[0].pDevInsHC = pDevIns;
961	pData->aPics[1].pDevInsHC = pDevIns;
962	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
963	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
964
965	/*
966	* Register PIC, I/O ports and save state.
967	*/
968	PicReg.u32Version = PDM_PICREG_VERSION;
969	PicReg.pfnSetIrqHC = picSetIrq;
970	PicReg.pfnGetInterruptHC = picGetInterrupt;
971	if (fGCEnabled)
972	{
973	PicReg.pszSetIrqGC = "picSetIrq";
974	PicReg.pszGetInterruptGC = "picGetInterrupt";
975	}
976	else
977	{
978	PicReg.pszSetIrqGC = NULL;
979	PicReg.pszGetInterruptGC = NULL;
980	}
981
982	if (fR0Enabled)
983	{
984	PicReg.pszSetIrqR0 = "picSetIrq";
985	PicReg.pszGetInterruptR0 = "picGetInterrupt";
986	}
987	else
988	{
989	PicReg.pszSetIrqR0 = NULL;
990	PicReg.pszGetInterruptR0 = NULL;
991	}
992
993	Assert(pDevIns->pDevHlp->pfnPICRegister);
994	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
995	if (VBOX_FAILURE(rc))
996	{
997	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
998	return rc;
999	}
1000	if (fGCEnabled)
1001	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
1002	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
1003	if (VBOX_FAILURE(rc))
1004	return rc;
1005	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
1006	if (VBOX_FAILURE(rc))
1007	return rc;
1008	if (fGCEnabled)
1009	{
1010	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1011	if (VBOX_FAILURE(rc))
1012	return rc;
1013	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1014	if (VBOX_FAILURE(rc))
1015	return rc;
1016	}
1017	if (fR0Enabled)
1018	{
1019	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
1020
1021	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1022	if (VBOX_FAILURE(rc))
1023	return rc;
1024	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1025	if (VBOX_FAILURE(rc))
1026	return rc;
1027	}
1028
1029	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
1030	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1031	if (VBOX_FAILURE(rc))
1032	return rc;
1033	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
1034	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1035	if (VBOX_FAILURE(rc))
1036	return rc;
1037	if (fGCEnabled)
1038	{
1039	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1040	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1041	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1042	if (VBOX_FAILURE(rc))
1043	return rc;
1044	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1045	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1046	if (VBOX_FAILURE(rc))
1047	return rc;
1048	}
1049	if (fR0Enabled)
1050	{
1051	RTR0PTR pDataR0 = PDMINS2DATA_R0PTR(pDevIns);
1052	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1053	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1054	if (VBOX_FAILURE(rc))
1055	return rc;
1056	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1057	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1058	if (VBOX_FAILURE(rc))
1059	return rc;
1060	}
1061
1062	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1063	NULL, picSaveExec, NULL,
1064	NULL, picLoadExec, NULL);
1065	if (VBOX_FAILURE(rc))
1066	return rc;
1067
1068
1069	#ifdef DEBUG
1070	/*
1071	* Register the info item.
1072	*/
1073	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1074	#endif
1075
1076	/*
1077	* Initialize the device state.
1078	*/
1079	picReset(pDevIns);
1080
1081	#ifdef VBOX_WITH_STATISTICS
1082	/*
1083	* Statistics.
1084	*/
1085	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1086	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1087
1088	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1089	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1090	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1091	#endif
1092
1093	return VINF_SUCCESS;
1094	}
1095
1096
1097	/**
1098	* The device registration structure.
1099	*/
1100	const PDMDEVREG g_DeviceI8259 =
1101	{
1102	/* u32Version */
1103	PDM_DEVREG_VERSION,
1104	/* szDeviceName */
1105	"i8259",
1106	/* szGCMod */
1107	"VBoxDDGC.gc",
1108	/* szR0Mod */
1109	"VBoxDDR0.r0",
1110	/* pszDescription */
1111	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1112	/* fFlags */
1113	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1114	/* fClass */
1115	PDM_DEVREG_CLASS_PIC,
1116	/* cMaxInstances */
1117	1,
1118	/* cbInstance */
1119	sizeof(DEVPIC),
1120	/* pfnConstruct */
1121	picConstruct,
1122	/* pfnDestruct */
1123	NULL,
1124	/* pfnRelocate */
1125	picRelocate,
1126	/* pfnIOCtl */
1127	NULL,
1128	/* pfnPowerOn */
1129	NULL,
1130	/* pfnReset */
1131	picReset,
1132	/* pfnSuspend */
1133	NULL,
1134	/* pfnResume */
1135	NULL,
1136	/* pfnAttach */
1137	NULL,
1138	/* pfnDetach */
1139	NULL,
1140	/* pfnQueryInterface. */
1141	NULL
1142	};
1143
1144	#endif /* IN_RING3 */
1145	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1146

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 9584

Download in other formats: