DevPit-i8254.cpp@ 2151

Last change on this file since 2151 was 1912, checked in by vboxsync, 18 years ago
muldiv64() => ASMMultU64ByU32DivByU32(); dma.c => DevDMA.cpp
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 38.0 KB

Line
1	/** @file
2	*
3	* VBox basic PC devices:
4	* Intel 8254 programmable interval timer
5	*/
6
7	/*
8	* Copyright (C) 2006 InnoTek Systemberatung GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* If you received this file as part of a commercial VirtualBox
19	* distribution, then only the terms of your commercial VirtualBox
20	* license agreement apply instead of the previous paragraph.
21	*
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU 8253/8254 interval timer emulation
27	*
28	* Copyright (c) 2003-2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*******************************************************************************
51	* Header Files *
52	*******************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PIT
54	#include <VBox/pdm.h>
55	#include <VBox/log.h>
56	#include <VBox/stam.h>
57	#include <iprt/assert.h>
58	#include <iprt/asm.h>
59
60	#include "Builtins.h"
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The version of the saved state. */
74	#define PIT_SAVED_STATE_VERSION 2
75
76
77	/*******************************************************************************
78	* Structures and Typedefs *
79	*******************************************************************************/
80	typedef struct PITChannelState
81	{
82	/** Pointer to the instance data - HCPtr. */
83	HCPTRTYPE(struct PITState *) pPitHC;
84	/** The timer - HCPtr. */
85	PTMTIMERHC pTimerHC;
86	/** Pointer to the instance data - GCPtr. */
87	GCPTRTYPE(struct PITState *) pPitGC;
88	/** The timer - HCPtr. */
89	PTMTIMERGC pTimerGC;
90	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
91	uint64_t u64ReloadTS;
92	/** The actual time of the next tick.
93	* As apposed to the next_transition_time which contains the correct time of the next tick. */
94	uint64_t u64NextTS;
95	/** When to give up catching up. (negative number) */
96	int64_t i64MaxCatchupTS;
97
98	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
99	uint64_t count_load_time;
100	/* irq handling */
101	int64_t next_transition_time;
102	int32_t irq;
103	uint32_t padding;
104
105	uint32_t count; /* can be 65536 */
106	uint16_t latched_count;
107	uint8_t count_latched;
108	uint8_t status_latched;
109
110	uint8_t status;
111	uint8_t read_state;
112	uint8_t write_state;
113	uint8_t write_latch;
114
115	uint8_t rw_mode;
116	uint8_t mode;
117	uint8_t bcd; /* not supported */
118	uint8_t gate; /* timer start */
119
120	} PITChannelState;
121
122	typedef struct PITState
123	{
124	PITChannelState channels[3];
125	/** Speaker data. */
126	int32_t speaker_data_on;
127	/** Speaker dummy. */
128	int32_t dummy_refresh_clock;
129	/** Pointer to the device instance. */
130	HCPTRTYPE(PPDMDEVINS) pDevIns;
131	#if HC_ARCH_BITS == 32
132	uint32_t Alignment0;
133	#endif
134	/** Number of IRQs that's been raised. */
135	STAMCOUNTER StatPITIrq;
136	/** Profiling the timer callback handler. */
137	STAMPROFILEADV StatPITHandler;
138	/** The number of times we've had to speed up the time because we lagged too far behind. */
139	STAMCOUNTER StatPITCatchup;
140	/** The number of times we've lagged too far behind for it to be worth trying to catch up. */
141	STAMCOUNTER StatPITGiveup;
142	} PITState;
143
144
145	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
146	/*******************************************************************************
147	* Internal Functions *
148	*******************************************************************************/
149	__BEGIN_DECLS
150	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
151	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
152	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
153	#ifdef IN_RING3
154	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
155	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
156	#endif
157	__END_DECLS
158
159
160
161
162	static int pit_get_count(PITChannelState *s)
163	{
164	uint64_t d;
165	int counter;
166	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
167
168	if (s->mode == 2) /** @todo Implement proper virtual time and get rid of this hack.. */
169	{
170	#if 0
171	d = TMTimerGet(pTimer);
172	d -= s->u64ReloadTS;
173	d = ASMMultU64ByU32DivByU32(d, PIT_FREQ, TMTimerGetFreq(pTimer));
174	#else /* variable time because of catch up */
175	if (s->u64NextTS == UINT64_MAX)
176	return 1; /** @todo check this value. */
177	d = TMTimerGet(pTimer);
178	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
179	#endif
180	if (d >= s->count)
181	return 1;
182	return s->count - d;
183	}
184	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
185	switch(s->mode) {
186	case 0:
187	case 1:
188	case 4:
189	case 5:
190	counter = (s->count - d) & 0xffff;
191	break;
192	case 3:
193	/* XXX: may be incorrect for odd counts */
194	counter = s->count - ((2 * d) % s->count);
195	break;
196	default:
197	counter = s->count - (d % s->count);
198	break;
199	}
200	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
201	return counter;
202	}
203
204	/* get pit output bit */
205	static int pit_get_out1(PITChannelState *s, int64_t current_time)
206	{
207	uint64_t d;
208	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
209	int out;
210
211	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
212	switch(s->mode) {
213	default:
214	case 0:
215	out = (d >= s->count);
216	break;
217	case 1:
218	out = (d < s->count);
219	break;
220	case 2:
221	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
222	if ((d % s->count) == 0 && d != 0)
223	out = 1;
224	else
225	out = 0;
226	break;
227	case 3:
228	out = (d % s->count) < ((s->count + 1) >> 1);
229	break;
230	case 4:
231	case 5:
232	out = (d == s->count);
233	break;
234	}
235	return out;
236	}
237
238
239	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
240	{
241	PITChannelState *s = &pit->channels[channel];
242	return pit_get_out1(s, current_time);
243	}
244
245
246	static int pit_get_gate(PITState *pit, int channel)
247	{
248	PITChannelState *s = &pit->channels[channel];
249	return s->gate;
250	}
251
252
253	/* if already latched, do not latch again */
254	static void pit_latch_count(PITChannelState *s)
255	{
256	if (!s->count_latched) {
257	s->latched_count = pit_get_count(s);
258	s->count_latched = s->rw_mode;
259	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
260	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
261	}
262	}
263
264	#ifdef IN_RING3
265
266	/* val must be 0 or 1 */
267	static void pit_set_gate(PITState *pit, int channel, int val)
268	{
269	PITChannelState *s = &pit->channels[channel];
270	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
271
272	switch(s->mode) {
273	default:
274	case 0:
275	case 4:
276	/* XXX: just disable/enable counting */
277	break;
278	case 1:
279	case 5:
280	if (s->gate < val) {
281	/* restart counting on rising edge */
282	s->count_load_time = TMTimerGet(pTimer);
283	pit_irq_timer_update(s, s->count_load_time);
284	}
285	break;
286	case 2:
287	case 3:
288	if (s->gate < val) {
289	/* restart counting on rising edge */
290	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
291	pit_irq_timer_update(s, s->count_load_time);
292	}
293	/* XXX: disable/enable counting */
294	break;
295	}
296	s->gate = val;
297	}
298
299	static inline void pit_load_count(PITChannelState *s, int val)
300	{
301	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
302	if (val == 0)
303	val = 0x10000;
304	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
305	s->count = val;
306	pit_irq_timer_update(s, s->count_load_time);
307	}
308
309	/* return -1 if no transition will occur. */
310	static int64_t pit_get_next_transition_time(PITChannelState *s,
311	uint64_t current_time)
312	{
313	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
314	uint64_t d, next_time, base;
315	uint32_t period2;
316
317	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
318	switch(s->mode) {
319	default:
320	case 0:
321	case 1:
322	if (d < s->count)
323	next_time = s->count;
324	else
325	return -1;
326	break;
327	/*
328	* Mode 2: The period is count + 1 PIT ticks.
329	* When the counter reaches 1 we sent the output low (for channel 0 that
330	* means raise an irq). On the next tick, where we should be decrementing
331	* from 1 to 0, the count is loaded and the output goes high (channel 0
332	* means clearing the irq).
333	*
334	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
335	* the irq. We also don't set it until we reach 0, which is a tick late - will
336	* try fix that later some day.
337	*/
338	case 2:
339	base = (d / s->count) * s->count;
340	#ifndef VBOX /* see above */
341	if ((d - base) == 0 && d != 0)
342	next_time = base + s->count;
343	else
344	#endif
345	next_time = base + s->count + 1;
346	break;
347	case 3:
348	base = (d / s->count) * s->count;
349	period2 = ((s->count + 1) >> 1);
350	if ((d - base) < period2)
351	next_time = base + period2;
352	else
353	next_time = base + s->count;
354	break;
355	case 4:
356	case 5:
357	if (d < s->count)
358	next_time = s->count;
359	else if (d == s->count)
360	next_time = s->count + 1;
361	else
362	return -1;
363	break;
364	}
365	/* convert to timer units */
366	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
367	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
368	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
369	/* fix potential rounding problems */
370	/* XXX: better solution: use a clock at PIT_FREQ Hz */
371	if (next_time <= current_time)
372	next_time = current_time + 1;
373	return next_time;
374	}
375
376	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
377	{
378	uint64_t now;
379	int64_t expire_time;
380	int irq_level;
381	PPDMDEVINS pDevIns;
382	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
383
384	if (!s->CTXSUFF(pTimer))
385	return;
386	expire_time = pit_get_next_transition_time(s, current_time);
387	irq_level = pit_get_out1(s, current_time);
388
389	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
390	pDevIns = s->CTXSUFF(pPit)->pDevIns;
391	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
392	if (irq_level)
393	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
394	now = TMTimerGet(pTimer);
395	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
396	if (irq_level)
397	{
398	s->u64ReloadTS = now;
399	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITIrq);
400	}
401
402	/* check if it expires too soon - move at 4x rate if it does. */
403	if (expire_time != -1)
404	{
405	int64_t delta = expire_time - now;
406	const int64_t quarter = (expire_time - s->next_transition_time) >> 2;
407	if (delta <= quarter && s->next_transition_time != -1)
408	{
409	if (delta >= s->i64MaxCatchupTS)
410	{
411	/* If we set the timer to 'expire_time' we could end up with flooding the guest
412	* with timer interrupts because the next interrupt(s) would probably raise
413	* immediately. Therefore we set the timer to 'now + quarter' with quarter>0.
414	* This delays the adaption a little bit. */
415	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITCatchup);
416	s->u64NextTS = now + quarter;
417	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64 delta=%9RI64\n",
418	s->mode, s->count, irq_level, quarter, s->u64NextTS, now, s->count_load_time,
419	ASMMultU64ByU32DivByU32(s->u64NextTS - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer)), delta));
420	}
421	else
422	{
423	/* We are too far away from the real time. Hard synchronize. */
424	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITGiveup);
425	s->u64NextTS = expire_time = pit_get_next_transition_time(s, now);
426	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64 delta=%9RI64 giving up!\n",
427	s->mode, s->count, irq_level, quarter, s->u64NextTS, now, s->count_load_time,
428	ASMMultU64ByU32DivByU32(s->u64NextTS - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer)), delta));
429	}
430	}
431	else
432	{
433	/* Everything is fine, just set the timer to the regular next expire_time. */
434	s->u64NextTS = expire_time;
435	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64\n",
436	s->mode, s->count, irq_level, expire_time - now, expire_time, now, s->count_load_time,
437	ASMMultU64ByU32DivByU32(expire_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer))));
438	}
439	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
440	}
441	else
442	{
443	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
444	TMTimerStop(s->CTXSUFF(pTimer));
445	s->u64NextTS = UINT64_MAX;
446	}
447	s->next_transition_time = expire_time;
448	}
449
450	#endif /* IN_RING3 */
451
452
453	/**
454	* Port I/O Handler for IN operations.
455	*
456	* @returns VBox status code.
457	*
458	* @param pDevIns The device instance.
459	* @param pvUser User argument - ignored.
460	* @param Port Port number used for the IN operation.
461	* @param pu32 Where to store the result.
462	* @param cb Number of bytes read.
463	*/
464	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
465	{
466	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
467	NOREF(pvUser);
468	Port &= 3;
469	if (cb != 1 \|\| Port == 3)
470	{
471	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
472	return VERR_IOM_IOPORT_UNUSED;
473	}
474
475	PITState pit = PDMINS2DATA(pDevIns, PITState );
476	int ret;
477	PITChannelState *s = &pit->channels[Port];
478	if (s->status_latched)
479	{
480	s->status_latched = 0;
481	ret = s->status;
482	}
483	else if (s->count_latched)
484	{
485	switch (s->count_latched)
486	{
487	default:
488	case RW_STATE_LSB:
489	ret = s->latched_count & 0xff;
490	s->count_latched = 0;
491	break;
492	case RW_STATE_MSB:
493	ret = s->latched_count >> 8;
494	s->count_latched = 0;
495	break;
496	case RW_STATE_WORD0:
497	ret = s->latched_count & 0xff;
498	s->count_latched = RW_STATE_MSB;
499	break;
500	}
501	}
502	else
503	{
504	int count;
505	switch (s->read_state)
506	{
507	default:
508	case RW_STATE_LSB:
509	count = pit_get_count(s);
510	ret = count & 0xff;
511	break;
512	case RW_STATE_MSB:
513	count = pit_get_count(s);
514	ret = (count >> 8) & 0xff;
515	break;
516	case RW_STATE_WORD0:
517	count = pit_get_count(s);
518	ret = count & 0xff;
519	s->read_state = RW_STATE_WORD1;
520	break;
521	case RW_STATE_WORD1:
522	count = pit_get_count(s);
523	ret = (count >> 8) & 0xff;
524	s->read_state = RW_STATE_WORD0;
525	break;
526	}
527	}
528
529	*pu32 = ret;
530	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
531	return VINF_SUCCESS;
532	}
533
534
535	/**
536	* Port I/O Handler for OUT operations.
537	*
538	* @returns VBox status code.
539	*
540	* @param pDevIns The device instance.
541	* @param pvUser User argument - ignored.
542	* @param Port Port number used for the IN operation.
543	* @param u32 The value to output.
544	* @param cb The value size in bytes.
545	*/
546	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
547	{
548	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
549	NOREF(pvUser);
550	if (cb != 1)
551	return VINF_SUCCESS;
552
553	PITState pit = PDMINS2DATA(pDevIns, PITState );
554	Port &= 3;
555	if (Port == 3)
556	{
557	/*
558	* Port 43h - Mode/Command Register.
559	* 7 6 5 4 3 2 1 0
560	* * * . . . . . . Select channel: 0 0 = Channel 0
561	* 0 1 = Channel 1
562	* 1 0 = Channel 2
563	* 1 1 = Read-back command (8254 only)
564	* (Illegal on 8253)
565	* (Illegal on PS/2 {JAM})
566	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
567	* 0 1 = Access mode: lobyte only
568	* 1 0 = Access mode: hibyte only
569	* 1 1 = Access mode: lobyte/hibyte
570	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
571	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
572	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
573	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
574	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
575	*/
576	unsigned channel = u32 >> 6;
577	if (channel == 3)
578	{
579	/* read-back command */
580	for (channel = 0; channel < ELEMENTS(pit->channels); channel++)
581	{
582	PITChannelState *s = &pit->channels[channel];
583	if (u32 & (2 << channel)) {
584	if (!(u32 & 0x20))
585	pit_latch_count(s);
586	if (!(u32 & 0x10) && !s->status_latched)
587	{
588	/* status latch */
589	/* XXX: add BCD and null count */
590	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
591	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
592	\| (s->rw_mode << 4)
593	\| (s->mode << 1)
594	\| s->bcd;
595	s->status_latched = 1;
596	}
597	}
598	}
599	}
600	else
601	{
602	PITChannelState *s = &pit->channels[channel];
603	unsigned access = (u32 >> 4) & 3;
604	if (access == 0)
605	pit_latch_count(s);
606	else
607	{
608	s->rw_mode = access;
609	s->read_state = access;
610	s->write_state = access;
611
612	s->mode = (u32 >> 1) & 7;
613	s->bcd = u32 & 1;
614	/* XXX: update irq timer ? */
615	}
616	}
617	}
618	else
619	{
620	#ifndef IN_RING3
621	return VINF_IOM_HC_IOPORT_WRITE;
622	#else /* IN_RING3 */
623	/*
624	* Port 40-42h - Channel Data Ports.
625	*/
626	PITChannelState *s = &pit->channels[Port];
627	switch(s->write_state)
628	{
629	default:
630	case RW_STATE_LSB:
631	pit_load_count(s, u32);
632	break;
633	case RW_STATE_MSB:
634	pit_load_count(s, u32 << 8);
635	break;
636	case RW_STATE_WORD0:
637	s->write_latch = u32;
638	s->write_state = RW_STATE_WORD1;
639	break;
640	case RW_STATE_WORD1:
641	pit_load_count(s, s->write_latch \| (u32 << 8));
642	s->write_state = RW_STATE_WORD0;
643	break;
644	}
645	#endif /* !IN_RING3 */
646	}
647	return VINF_SUCCESS;
648	}
649
650
651	/**
652	* Port I/O Handler for speaker IN operations.
653	*
654	* @returns VBox status code.
655	*
656	* @param pDevIns The device instance.
657	* @param pvUser User argument - ignored.
658	* @param Port Port number used for the IN operation.
659	* @param pu32 Where to store the result.
660	* @param cb Number of bytes read.
661	*/
662	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
663	{
664	NOREF(pvUser);
665	if (cb == 1)
666	{
667	PITState pData = PDMINS2DATA(pDevIns, PITState );
668	int out = pit_get_out(pData, 2, TMTimerGet(pData->channels[0].CTXSUFF(pTimer)));
669	pData->dummy_refresh_clock ^= 1;
670	*pu32 = (pData->speaker_data_on << 1) \| pit_get_gate(pData, 2) \| (out << 5) \| (pData->dummy_refresh_clock << 4);
671	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
672	return VINF_SUCCESS;
673	}
674	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
675	return VERR_IOM_IOPORT_UNUSED;
676	}
677
678	#ifdef IN_RING3
679
680	/**
681	* Port I/O Handler for speaker OUT operations.
682	*
683	* @returns VBox status code.
684	*
685	* @param pDevIns The device instance.
686	* @param pvUser User argument - ignored.
687	* @param Port Port number used for the IN operation.
688	* @param u32 The value to output.
689	* @param cb The value size in bytes.
690	*/
691	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
692	{
693	NOREF(pvUser);
694	if (cb == 1)
695	{
696	PITState pData = PDMINS2DATA(pDevIns, PITState );
697	pData->speaker_data_on = (u32 >> 1) & 1;
698	pit_set_gate(pData, 2, u32 & 1);
699	}
700	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
701	return VINF_SUCCESS;
702	}
703
704
705	/**
706	* Saves a state of the programmable interval timer device.
707	*
708	* @returns VBox status code.
709	* @param pDevIns The device instance.
710	* @param pSSMHandle The handle to save the state to.
711	*/
712	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
713	{
714	PITState pData = PDMINS2DATA(pDevIns, PITState );
715	unsigned i;
716
717	for (i = 0; i < ELEMENTS(pData->channels); i++)
718	{
719	PITChannelState *s = &pData->channels[i];
720	SSMR3PutU32(pSSMHandle, s->count);
721	SSMR3PutU16(pSSMHandle, s->latched_count);
722	SSMR3PutU8(pSSMHandle, s->count_latched);
723	SSMR3PutU8(pSSMHandle, s->status_latched);
724	SSMR3PutU8(pSSMHandle, s->status);
725	SSMR3PutU8(pSSMHandle, s->read_state);
726	SSMR3PutU8(pSSMHandle, s->write_state);
727	SSMR3PutU8(pSSMHandle, s->write_latch);
728	SSMR3PutU8(pSSMHandle, s->rw_mode);
729	SSMR3PutU8(pSSMHandle, s->mode);
730	SSMR3PutU8(pSSMHandle, s->bcd);
731	SSMR3PutU8(pSSMHandle, s->gate);
732	SSMR3PutU64(pSSMHandle, s->count_load_time);
733	SSMR3PutU64(pSSMHandle, s->u64NextTS);
734	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
735	SSMR3PutS64(pSSMHandle, s->next_transition_time);
736	if (s->CTXSUFF(pTimer))
737	TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
738	}
739
740	SSMR3PutS32(pSSMHandle, pData->speaker_data_on);
741	return SSMR3PutS32(pSSMHandle, pData->dummy_refresh_clock);
742	}
743
744
745	/**
746	* Loads a saved programmable interval timer device state.
747	*
748	* @returns VBox status code.
749	* @param pDevIns The device instance.
750	* @param pSSMHandle The handle to the saved state.
751	* @param u32Version The data unit version number.
752	*/
753	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
754	{
755	PITState pData = PDMINS2DATA(pDevIns, PITState );
756	unsigned i;
757
758	if (u32Version != PIT_SAVED_STATE_VERSION)
759	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
760
761	for (i = 0; i < ELEMENTS(pData->channels); i++)
762	{
763	PITChannelState *s = &pData->channels[i];
764	SSMR3GetU32(pSSMHandle, &s->count);
765	SSMR3GetU16(pSSMHandle, &s->latched_count);
766	SSMR3GetU8(pSSMHandle, &s->count_latched);
767	SSMR3GetU8(pSSMHandle, &s->status_latched);
768	SSMR3GetU8(pSSMHandle, &s->status);
769	SSMR3GetU8(pSSMHandle, &s->read_state);
770	SSMR3GetU8(pSSMHandle, &s->write_state);
771	SSMR3GetU8(pSSMHandle, &s->write_latch);
772	SSMR3GetU8(pSSMHandle, &s->rw_mode);
773	SSMR3GetU8(pSSMHandle, &s->mode);
774	SSMR3GetU8(pSSMHandle, &s->bcd);
775	SSMR3GetU8(pSSMHandle, &s->gate);
776	SSMR3GetU64(pSSMHandle, &s->count_load_time);
777	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
778	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
779	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
780	if (s->CTXSUFF(pTimer))
781	TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
782	}
783
784	SSMR3GetS32(pSSMHandle, &pData->speaker_data_on);
785	return SSMR3GetS32(pSSMHandle, &pData->dummy_refresh_clock);
786	}
787
788
789	/**
790	* Device timer callback function.
791	*
792	* @param pDevIns Device instance of the device which registered the timer.
793	* @param pTimer The timer handle.
794	*/
795	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
796	{
797	PITState pData = PDMINS2DATA(pDevIns, PITState );
798	PITChannelState *s = &pData->channels[0];
799	STAM_PROFILE_ADV_START(&s->CTXSUFF(pPit)->StatPITHandler, a);
800	pit_irq_timer_update(s, s->next_transition_time);
801	STAM_PROFILE_ADV_STOP(&s->CTXSUFF(pPit)->StatPITHandler, a);
802	}
803
804
805	/**
806	* Relocation notification.
807	*
808	* @returns VBox status.
809	* @param pDevIns The device instance data.
810	* @param offDelta The delta relative to the old address.
811	*/
812	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
813	{
814	PITState pData = PDMINS2DATA(pDevIns, PITState );
815	unsigned i;
816	LogFlow(("pitRelocate: \n"));
817
818	for (i = 0; i < ELEMENTS(pData->channels); i++)
819	{
820	PITChannelState *pCh = &pData->channels[i];
821	if (pCh->pTimerHC)
822	pCh->pTimerGC = TMTimerGCPtr(pCh->pTimerHC);
823	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
824	}
825	}
826
827	/** @todo remove this! */
828	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
829
830	/**
831	* Reset notification.
832	*
833	* @returns VBox status.
834	* @param pDevIns The device instance data.
835	*/
836	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
837	{
838	PITState pData = PDMINS2DATA(pDevIns, PITState );
839	unsigned i;
840	LogFlow(("pitReset: \n"));
841
842	for (i = 0; i < ELEMENTS(pData->channels); i++)
843	{
844	PITChannelState *s = &pData->channels[i];
845
846	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
847	s->latched_count = 0;
848	s->count_latched = 0;
849	s->status_latched = 0;
850	s->status = 0;
851	s->read_state = 0;
852	s->write_state = 0;
853	s->write_latch = 0;
854	s->rw_mode = 0;
855	s->bcd = 0;
856	#endif
857	s->mode = 3;
858	s->gate = (i != 2);
859	pit_load_count(s, 0);
860	}
861	/** @todo remove when #1589 is resolved. */
862	pitInfo(pDevIns, DBGFR3InfoLogRelHlp(), NULL);
863	}
864
865
866	/**
867	* Info handler, device version.
868	*
869	* @param pDevIns Device instance which registered the info.
870	* @param pHlp Callback functions for doing output.
871	* @param pszArgs Argument string. Optional and specific to the handler.
872	*/
873	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
874	{
875	PITState pData = PDMINS2DATA(pDevIns, PITState );
876	unsigned i;
877	for (i = 0; i < ELEMENTS(pData->channels); i++)
878	{
879	const PITChannelState *pCh = &pData->channels[i];
880
881	pHlp->pfnPrintf(pHlp,
882	"PIT (i8254) channel %d status: irq=%#x\n"
883	" count=%08x" " latched_count=%04x count_latched=%02x\n"
884	" status=%02x status_latched=%02x read_state=%02x\n"
885	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
886	" mode=%02x bcd=%02x gate=%02x\n"
887	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
888	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
889	,
890	i, pCh->irq,
891	pCh->count, pCh->latched_count, pCh->count_latched,
892	pCh->status, pCh->status_latched, pCh->read_state,
893	pCh->write_state, pCh->write_latch, pCh->rw_mode,
894	pCh->mode, pCh->bcd, pCh->gate,
895	pCh->count_load_time, pCh->next_transition_time,
896	pCh->u64ReloadTS, pCh->u64NextTS);
897	}
898	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
899	pData->speaker_data_on, pData->dummy_refresh_clock);
900	}
901
902
903	/**
904	* Construct a device instance for a VM.
905	*
906	* @returns VBox status.
907	* @param pDevIns The device instance data.
908	* If the registration structure is needed, pDevIns->pDevReg points to it.
909	* @param iInstance Instance number. Use this to figure out which registers and such to use.
910	* The device number is also found in pDevIns->iInstance, but since it's
911	* likely to be freqently used PDM passes it as parameter.
912	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
913	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
914	* iInstance it's expected to be used a bit in this function.
915	*/
916	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
917	{
918	PITState pData = PDMINS2DATA(pDevIns, PITState );
919	int rc;
920	uint8_t u8Irq;
921	uint16_t u16Base;
922	bool fSpeaker;
923	bool fGCEnabled;
924	bool fR0Enabled;
925	unsigned i;
926	Assert(iInstance == 0);
927
928	/*
929	* Validate configuration.
930	*/
931	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0Speaker\0GCEnabled\0R0Enabled"))
932	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
933
934	/*
935	* Init the data.
936	*/
937	rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
938	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
939	u8Irq = 0;
940	else if (VBOX_FAILURE(rc))
941	return PDMDEV_SET_ERROR(pDevIns, rc,
942	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
943
944	rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
945	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
946	u16Base = 0x40;
947	else if (VBOX_FAILURE(rc))
948	return PDMDEV_SET_ERROR(pDevIns, rc,
949	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
950
951	rc = CFGMR3QueryBool(pCfgHandle, "SpeakerEnabled", &fSpeaker);
952	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
953	fSpeaker = true;
954	else if (VBOX_FAILURE(rc))
955	return PDMDEV_SET_ERROR(pDevIns, rc,
956	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
957
958	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
959	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
960	fGCEnabled = true;
961	else if (VBOX_FAILURE(rc))
962	return PDMDEV_SET_ERROR(pDevIns, rc,
963	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
964
965	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
966	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
967	fR0Enabled = true;
968	else if (VBOX_FAILURE(rc))
969	return PDMDEV_SET_ERROR(pDevIns, rc,
970	N_("Configuration error: failed to read R0Enabled as boolean"));
971
972	pData->pDevIns = pDevIns;
973	pData->channels[0].irq = u8Irq;
974	for (i = 0; i < ELEMENTS(pData->channels); i++)
975	{
976	pData->channels[i].pPitHC = pData;
977	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
978	}
979
980	/*
981	* Create timer, register I/O Ports and save state.
982	*/
983	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pitTimer, "i8254 Programmable Interval Timer",
984	&pData->channels[0].CTXSUFF(pTimer));
985	if (VBOX_FAILURE(rc))
986	{
987	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
988	return rc;
989	}
990
991	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
992	if (VBOX_FAILURE(rc))
993	return rc;
994	if (fGCEnabled)
995	{
996	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
997	if (VBOX_FAILURE(rc))
998	return rc;
999	}
1000	if (fR0Enabled)
1001	{
1002	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1003	if (VBOX_FAILURE(rc))
1004	return rc;
1005	}
1006
1007	if (fSpeaker)
1008	{
1009	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1010	if (VBOX_FAILURE(rc))
1011	return rc;
1012	if (fGCEnabled)
1013	{
1014	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1015	if (VBOX_FAILURE(rc))
1016	return rc;
1017	}
1018	}
1019
1020	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pData),
1021	NULL, pitSaveExec, NULL,
1022	NULL, pitLoadExec, NULL);
1023	if (VBOX_FAILURE(rc))
1024	return rc;
1025
1026	/*
1027	* Calculate max catchup time.
1028	*/
1029	pData->channels[0].i64MaxCatchupTS = pData->channels[1].i64MaxCatchupTS
1030	= pData->channels[2].i64MaxCatchupTS = -TMTimerFromMilli(pData->channels[0].CTXSUFF(pTimer), 1000602); /* 2 min */
1031
1032	/*
1033	* Initialize the device state.
1034	*/
1035	pitReset(pDevIns);
1036
1037	/*
1038	* Register statistics and debug info.
1039	*/
1040	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1041	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1042	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITCatchup, STAMTYPE_COUNTER, "/TM/PIT/Catchup", STAMUNIT_OCCURENCES, "The number of times we lagged too far behind.");
1043	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITGiveup, STAMTYPE_COUNTER, "/TM/PIT/Giveup", STAMUNIT_OCCURENCES, "The number of times we lagged so far behind that we simply gave up.");
1044
1045	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1046
1047	return VINF_SUCCESS;
1048	}
1049
1050
1051	/**
1052	* The device registration structure.
1053	*/
1054	const PDMDEVREG g_DeviceI8254 =
1055	{
1056	/* u32Version */
1057	PDM_DEVREG_VERSION,
1058	/* szDeviceName */
1059	"i8254",
1060	/* szGCMod */
1061	"VBoxDDGC.gc",
1062	/* szR0Mod */
1063	"VBoxDDR0.r0",
1064	/* pszDescription */
1065	"i8254 Programmable Interval Timer And Dummy Speaker",
1066	/* fFlags */
1067	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1068	/* fClass */
1069	PDM_DEVREG_CLASS_PIT,
1070	/* cMaxInstances */
1071	1,
1072	/* cbInstance */
1073	sizeof(PITState),
1074	/* pfnConstruct */
1075	pitConstruct,
1076	/* pfnDestruct */
1077	NULL,
1078	/* pfnRelocate */
1079	pitRelocate,
1080	/* pfnIOCtl */
1081	NULL,
1082	/* pfnPowerOn */
1083	NULL,
1084	/* pfnReset */
1085	pitReset,
1086	/* pfnSuspend */
1087	NULL,
1088	/* pfnResume */
1089	NULL,
1090	/* pfnAttach */
1091	NULL,
1092	/* pfnDetach */
1093	NULL,
1094	/* pfnQueryInterface. */
1095	NULL
1096	};
1097
1098	#endif /* IN_RING3 */
1099	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1100

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 2151

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