DevPit-i8254.cpp@ 2685

Last change on this file since 2685 was 2569, checked in by vboxsync, 18 years ago
the string of valid CFG options in CFGMR3AreValuesValid() should be terminated with \0
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1	/** @file
2	*
3	* VBox basic PC devices:
4	* Intel 8254 programmable interval timer
5	*/
6
7	/*
8	* Copyright (C) 2006 InnoTek Systemberatung GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* If you received this file as part of a commercial VirtualBox
19	* distribution, then only the terms of your commercial VirtualBox
20	* license agreement apply instead of the previous paragraph.
21	*
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU 8253/8254 interval timer emulation
27	*
28	* Copyright (c) 2003-2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*******************************************************************************
51	* Header Files *
52	*******************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PIT
54	#include <VBox/pdm.h>
55	#include <VBox/log.h>
56	#include <VBox/stam.h>
57	#include <iprt/assert.h>
58	#include <iprt/asm.h>
59
60	#include "Builtins.h"
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The version of the saved state. */
74	#define PIT_SAVED_STATE_VERSION 2
75
76
77	/*******************************************************************************
78	* Structures and Typedefs *
79	*******************************************************************************/
80	typedef struct PITChannelState
81	{
82	/** Pointer to the instance data - HCPtr. */
83	HCPTRTYPE(struct PITState *) pPitHC;
84	/** The timer - HCPtr. */
85	PTMTIMERHC pTimerHC;
86	/** Pointer to the instance data - GCPtr. */
87	GCPTRTYPE(struct PITState *) pPitGC;
88	/** The timer - HCPtr. */
89	PTMTIMERGC pTimerGC;
90	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
91	uint64_t u64ReloadTS;
92	/** The actual time of the next tick.
93	* As apposed to the next_transition_time which contains the correct time of the next tick. */
94	uint64_t u64NextTS;
95
96	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
97	uint64_t count_load_time;
98	/* irq handling */
99	int64_t next_transition_time;
100	int32_t irq;
101	uint32_t padding;
102
103	uint32_t count; /* can be 65536 */
104	uint16_t latched_count;
105	uint8_t count_latched;
106	uint8_t status_latched;
107
108	uint8_t status;
109	uint8_t read_state;
110	uint8_t write_state;
111	uint8_t write_latch;
112
113	uint8_t rw_mode;
114	uint8_t mode;
115	uint8_t bcd; /* not supported */
116	uint8_t gate; /* timer start */
117
118	} PITChannelState;
119
120	typedef struct PITState
121	{
122	PITChannelState channels[3];
123	/** Speaker data. */
124	int32_t speaker_data_on;
125	/** Speaker dummy. */
126	int32_t dummy_refresh_clock;
127	/** Pointer to the device instance. */
128	HCPTRTYPE(PPDMDEVINS) pDevIns;
129	#if HC_ARCH_BITS == 32
130	uint32_t Alignment0;
131	#endif
132	/** Number of IRQs that's been raised. */
133	STAMCOUNTER StatPITIrq;
134	/** Profiling the timer callback handler. */
135	STAMPROFILEADV StatPITHandler;
136	} PITState;
137
138
139	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
140	/*******************************************************************************
141	* Internal Functions *
142	*******************************************************************************/
143	__BEGIN_DECLS
144	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
145	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
146	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
147	#ifdef IN_RING3
148	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
149	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
150	#endif
151	__END_DECLS
152
153
154
155
156	static int pit_get_count(PITChannelState *s)
157	{
158	uint64_t d;
159	int counter;
160	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
161
162	if (s->mode == 2) /** @todo Implement proper virtual time and get rid of this hack.. */
163	{
164	#if 0
165	d = TMTimerGet(pTimer);
166	d -= s->u64ReloadTS;
167	d = ASMMultU64ByU32DivByU32(d, PIT_FREQ, TMTimerGetFreq(pTimer));
168	#else /* variable time because of catch up */
169	if (s->u64NextTS == UINT64_MAX)
170	return 1; /** @todo check this value. */
171	d = TMTimerGet(pTimer);
172	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
173	#endif
174	if (d >= s->count)
175	return 1;
176	return s->count - d;
177	}
178	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
179	switch(s->mode) {
180	case 0:
181	case 1:
182	case 4:
183	case 5:
184	counter = (s->count - d) & 0xffff;
185	break;
186	case 3:
187	/* XXX: may be incorrect for odd counts */
188	counter = s->count - ((2 * d) % s->count);
189	break;
190	default:
191	counter = s->count - (d % s->count);
192	break;
193	}
194	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
195	return counter;
196	}
197
198	/* get pit output bit */
199	static int pit_get_out1(PITChannelState *s, int64_t current_time)
200	{
201	uint64_t d;
202	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
203	int out;
204
205	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
206	switch(s->mode) {
207	default:
208	case 0:
209	out = (d >= s->count);
210	break;
211	case 1:
212	out = (d < s->count);
213	break;
214	case 2:
215	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
216	if ((d % s->count) == 0 && d != 0)
217	out = 1;
218	else
219	out = 0;
220	break;
221	case 3:
222	out = (d % s->count) < ((s->count + 1) >> 1);
223	break;
224	case 4:
225	case 5:
226	out = (d == s->count);
227	break;
228	}
229	return out;
230	}
231
232
233	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
234	{
235	PITChannelState *s = &pit->channels[channel];
236	return pit_get_out1(s, current_time);
237	}
238
239
240	static int pit_get_gate(PITState *pit, int channel)
241	{
242	PITChannelState *s = &pit->channels[channel];
243	return s->gate;
244	}
245
246
247	/* if already latched, do not latch again */
248	static void pit_latch_count(PITChannelState *s)
249	{
250	if (!s->count_latched) {
251	s->latched_count = pit_get_count(s);
252	s->count_latched = s->rw_mode;
253	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
254	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
255	}
256	}
257
258	#ifdef IN_RING3
259
260	/* val must be 0 or 1 */
261	static void pit_set_gate(PITState *pit, int channel, int val)
262	{
263	PITChannelState *s = &pit->channels[channel];
264	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
265
266	switch(s->mode) {
267	default:
268	case 0:
269	case 4:
270	/* XXX: just disable/enable counting */
271	break;
272	case 1:
273	case 5:
274	if (s->gate < val) {
275	/* restart counting on rising edge */
276	s->count_load_time = TMTimerGet(pTimer);
277	pit_irq_timer_update(s, s->count_load_time);
278	}
279	break;
280	case 2:
281	case 3:
282	if (s->gate < val) {
283	/* restart counting on rising edge */
284	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
285	pit_irq_timer_update(s, s->count_load_time);
286	}
287	/* XXX: disable/enable counting */
288	break;
289	}
290	s->gate = val;
291	}
292
293	static inline void pit_load_count(PITChannelState *s, int val)
294	{
295	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
296	if (val == 0)
297	val = 0x10000;
298	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
299	s->count = val;
300	pit_irq_timer_update(s, s->count_load_time);
301	}
302
303	/* return -1 if no transition will occur. */
304	static int64_t pit_get_next_transition_time(PITChannelState *s,
305	uint64_t current_time)
306	{
307	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
308	uint64_t d, next_time, base;
309	uint32_t period2;
310
311	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
312	switch(s->mode) {
313	default:
314	case 0:
315	case 1:
316	if (d < s->count)
317	next_time = s->count;
318	else
319	return -1;
320	break;
321	/*
322	* Mode 2: The period is count + 1 PIT ticks.
323	* When the counter reaches 1 we sent the output low (for channel 0 that
324	* means raise an irq). On the next tick, where we should be decrementing
325	* from 1 to 0, the count is loaded and the output goes high (channel 0
326	* means clearing the irq).
327	*
328	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
329	* the irq. We also don't set it until we reach 0, which is a tick late - will
330	* try fix that later some day.
331	*/
332	case 2:
333	base = (d / s->count) * s->count;
334	#ifndef VBOX /* see above */
335	if ((d - base) == 0 && d != 0)
336	next_time = base + s->count;
337	else
338	#endif
339	next_time = base + s->count + 1;
340	break;
341	case 3:
342	base = (d / s->count) * s->count;
343	period2 = ((s->count + 1) >> 1);
344	if ((d - base) < period2)
345	next_time = base + period2;
346	else
347	next_time = base + s->count;
348	break;
349	case 4:
350	case 5:
351	if (d < s->count)
352	next_time = s->count;
353	else if (d == s->count)
354	next_time = s->count + 1;
355	else
356	return -1;
357	break;
358	}
359	/* convert to timer units */
360	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
361	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
362	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
363	/* fix potential rounding problems */
364	/* XXX: better solution: use a clock at PIT_FREQ Hz */
365	if (next_time <= current_time)
366	next_time = current_time + 1;
367	return next_time;
368	}
369
370	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
371	{
372	uint64_t now;
373	int64_t expire_time;
374	int irq_level;
375	PPDMDEVINS pDevIns;
376	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
377
378	if (!s->CTXSUFF(pTimer))
379	return;
380	expire_time = pit_get_next_transition_time(s, current_time);
381	irq_level = pit_get_out1(s, current_time);
382
383	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
384	pDevIns = s->CTXSUFF(pPit)->pDevIns;
385	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
386	if (irq_level)
387	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
388	now = TMTimerGet(pTimer);
389	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
390	if (irq_level)
391	{
392	s->u64ReloadTS = now;
393	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITIrq);
394	}
395
396	if (expire_time != -1)
397	{
398	s->u64NextTS = expire_time;
399	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
400	}
401	else
402	{
403	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
404	TMTimerStop(s->CTXSUFF(pTimer));
405	s->u64NextTS = UINT64_MAX;
406	}
407	s->next_transition_time = expire_time;
408	}
409
410	#endif /* IN_RING3 */
411
412
413	/**
414	* Port I/O Handler for IN operations.
415	*
416	* @returns VBox status code.
417	*
418	* @param pDevIns The device instance.
419	* @param pvUser User argument - ignored.
420	* @param Port Port number used for the IN operation.
421	* @param pu32 Where to store the result.
422	* @param cb Number of bytes read.
423	*/
424	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
425	{
426	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
427	NOREF(pvUser);
428	Port &= 3;
429	if (cb != 1 \|\| Port == 3)
430	{
431	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
432	return VERR_IOM_IOPORT_UNUSED;
433	}
434
435	PITState pit = PDMINS2DATA(pDevIns, PITState );
436	int ret;
437	PITChannelState *s = &pit->channels[Port];
438	if (s->status_latched)
439	{
440	s->status_latched = 0;
441	ret = s->status;
442	}
443	else if (s->count_latched)
444	{
445	switch (s->count_latched)
446	{
447	default:
448	case RW_STATE_LSB:
449	ret = s->latched_count & 0xff;
450	s->count_latched = 0;
451	break;
452	case RW_STATE_MSB:
453	ret = s->latched_count >> 8;
454	s->count_latched = 0;
455	break;
456	case RW_STATE_WORD0:
457	ret = s->latched_count & 0xff;
458	s->count_latched = RW_STATE_MSB;
459	break;
460	}
461	}
462	else
463	{
464	int count;
465	switch (s->read_state)
466	{
467	default:
468	case RW_STATE_LSB:
469	count = pit_get_count(s);
470	ret = count & 0xff;
471	break;
472	case RW_STATE_MSB:
473	count = pit_get_count(s);
474	ret = (count >> 8) & 0xff;
475	break;
476	case RW_STATE_WORD0:
477	count = pit_get_count(s);
478	ret = count & 0xff;
479	s->read_state = RW_STATE_WORD1;
480	break;
481	case RW_STATE_WORD1:
482	count = pit_get_count(s);
483	ret = (count >> 8) & 0xff;
484	s->read_state = RW_STATE_WORD0;
485	break;
486	}
487	}
488
489	*pu32 = ret;
490	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
491	return VINF_SUCCESS;
492	}
493
494
495	/**
496	* Port I/O Handler for OUT operations.
497	*
498	* @returns VBox status code.
499	*
500	* @param pDevIns The device instance.
501	* @param pvUser User argument - ignored.
502	* @param Port Port number used for the IN operation.
503	* @param u32 The value to output.
504	* @param cb The value size in bytes.
505	*/
506	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
507	{
508	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
509	NOREF(pvUser);
510	if (cb != 1)
511	return VINF_SUCCESS;
512
513	PITState pit = PDMINS2DATA(pDevIns, PITState );
514	Port &= 3;
515	if (Port == 3)
516	{
517	/*
518	* Port 43h - Mode/Command Register.
519	* 7 6 5 4 3 2 1 0
520	* * * . . . . . . Select channel: 0 0 = Channel 0
521	* 0 1 = Channel 1
522	* 1 0 = Channel 2
523	* 1 1 = Read-back command (8254 only)
524	* (Illegal on 8253)
525	* (Illegal on PS/2 {JAM})
526	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
527	* 0 1 = Access mode: lobyte only
528	* 1 0 = Access mode: hibyte only
529	* 1 1 = Access mode: lobyte/hibyte
530	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
531	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
532	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
533	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
534	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
535	*/
536	unsigned channel = u32 >> 6;
537	if (channel == 3)
538	{
539	/* read-back command */
540	for (channel = 0; channel < ELEMENTS(pit->channels); channel++)
541	{
542	PITChannelState *s = &pit->channels[channel];
543	if (u32 & (2 << channel)) {
544	if (!(u32 & 0x20))
545	pit_latch_count(s);
546	if (!(u32 & 0x10) && !s->status_latched)
547	{
548	/* status latch */
549	/* XXX: add BCD and null count */
550	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
551	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
552	\| (s->rw_mode << 4)
553	\| (s->mode << 1)
554	\| s->bcd;
555	s->status_latched = 1;
556	}
557	}
558	}
559	}
560	else
561	{
562	PITChannelState *s = &pit->channels[channel];
563	unsigned access = (u32 >> 4) & 3;
564	if (access == 0)
565	pit_latch_count(s);
566	else
567	{
568	s->rw_mode = access;
569	s->read_state = access;
570	s->write_state = access;
571
572	s->mode = (u32 >> 1) & 7;
573	s->bcd = u32 & 1;
574	/* XXX: update irq timer ? */
575	}
576	}
577	}
578	else
579	{
580	#ifndef IN_RING3
581	return VINF_IOM_HC_IOPORT_WRITE;
582	#else /* IN_RING3 */
583	/*
584	* Port 40-42h - Channel Data Ports.
585	*/
586	PITChannelState *s = &pit->channels[Port];
587	switch(s->write_state)
588	{
589	default:
590	case RW_STATE_LSB:
591	pit_load_count(s, u32);
592	break;
593	case RW_STATE_MSB:
594	pit_load_count(s, u32 << 8);
595	break;
596	case RW_STATE_WORD0:
597	s->write_latch = u32;
598	s->write_state = RW_STATE_WORD1;
599	break;
600	case RW_STATE_WORD1:
601	pit_load_count(s, s->write_latch \| (u32 << 8));
602	s->write_state = RW_STATE_WORD0;
603	break;
604	}
605	#endif /* !IN_RING3 */
606	}
607	return VINF_SUCCESS;
608	}
609
610
611	/**
612	* Port I/O Handler for speaker IN operations.
613	*
614	* @returns VBox status code.
615	*
616	* @param pDevIns The device instance.
617	* @param pvUser User argument - ignored.
618	* @param Port Port number used for the IN operation.
619	* @param pu32 Where to store the result.
620	* @param cb Number of bytes read.
621	*/
622	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
623	{
624	NOREF(pvUser);
625	if (cb == 1)
626	{
627	PITState pData = PDMINS2DATA(pDevIns, PITState );
628	int out = pit_get_out(pData, 2, TMTimerGet(pData->channels[0].CTXSUFF(pTimer)));
629	pData->dummy_refresh_clock ^= 1;
630	*pu32 = (pData->speaker_data_on << 1) \| pit_get_gate(pData, 2) \| (out << 5) \| (pData->dummy_refresh_clock << 4);
631	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
632	return VINF_SUCCESS;
633	}
634	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
635	return VERR_IOM_IOPORT_UNUSED;
636	}
637
638	#ifdef IN_RING3
639
640	/**
641	* Port I/O Handler for speaker OUT operations.
642	*
643	* @returns VBox status code.
644	*
645	* @param pDevIns The device instance.
646	* @param pvUser User argument - ignored.
647	* @param Port Port number used for the IN operation.
648	* @param u32 The value to output.
649	* @param cb The value size in bytes.
650	*/
651	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
652	{
653	NOREF(pvUser);
654	if (cb == 1)
655	{
656	PITState pData = PDMINS2DATA(pDevIns, PITState );
657	pData->speaker_data_on = (u32 >> 1) & 1;
658	pit_set_gate(pData, 2, u32 & 1);
659	}
660	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
661	return VINF_SUCCESS;
662	}
663
664
665	/**
666	* Saves a state of the programmable interval timer device.
667	*
668	* @returns VBox status code.
669	* @param pDevIns The device instance.
670	* @param pSSMHandle The handle to save the state to.
671	*/
672	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
673	{
674	PITState pData = PDMINS2DATA(pDevIns, PITState );
675	unsigned i;
676
677	for (i = 0; i < ELEMENTS(pData->channels); i++)
678	{
679	PITChannelState *s = &pData->channels[i];
680	SSMR3PutU32(pSSMHandle, s->count);
681	SSMR3PutU16(pSSMHandle, s->latched_count);
682	SSMR3PutU8(pSSMHandle, s->count_latched);
683	SSMR3PutU8(pSSMHandle, s->status_latched);
684	SSMR3PutU8(pSSMHandle, s->status);
685	SSMR3PutU8(pSSMHandle, s->read_state);
686	SSMR3PutU8(pSSMHandle, s->write_state);
687	SSMR3PutU8(pSSMHandle, s->write_latch);
688	SSMR3PutU8(pSSMHandle, s->rw_mode);
689	SSMR3PutU8(pSSMHandle, s->mode);
690	SSMR3PutU8(pSSMHandle, s->bcd);
691	SSMR3PutU8(pSSMHandle, s->gate);
692	SSMR3PutU64(pSSMHandle, s->count_load_time);
693	SSMR3PutU64(pSSMHandle, s->u64NextTS);
694	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
695	SSMR3PutS64(pSSMHandle, s->next_transition_time);
696	if (s->CTXSUFF(pTimer))
697	TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
698	}
699
700	SSMR3PutS32(pSSMHandle, pData->speaker_data_on);
701	return SSMR3PutS32(pSSMHandle, pData->dummy_refresh_clock);
702	}
703
704
705	/**
706	* Loads a saved programmable interval timer device state.
707	*
708	* @returns VBox status code.
709	* @param pDevIns The device instance.
710	* @param pSSMHandle The handle to the saved state.
711	* @param u32Version The data unit version number.
712	*/
713	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
714	{
715	PITState pData = PDMINS2DATA(pDevIns, PITState );
716	unsigned i;
717
718	if (u32Version != PIT_SAVED_STATE_VERSION)
719	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
720
721	for (i = 0; i < ELEMENTS(pData->channels); i++)
722	{
723	PITChannelState *s = &pData->channels[i];
724	SSMR3GetU32(pSSMHandle, &s->count);
725	SSMR3GetU16(pSSMHandle, &s->latched_count);
726	SSMR3GetU8(pSSMHandle, &s->count_latched);
727	SSMR3GetU8(pSSMHandle, &s->status_latched);
728	SSMR3GetU8(pSSMHandle, &s->status);
729	SSMR3GetU8(pSSMHandle, &s->read_state);
730	SSMR3GetU8(pSSMHandle, &s->write_state);
731	SSMR3GetU8(pSSMHandle, &s->write_latch);
732	SSMR3GetU8(pSSMHandle, &s->rw_mode);
733	SSMR3GetU8(pSSMHandle, &s->mode);
734	SSMR3GetU8(pSSMHandle, &s->bcd);
735	SSMR3GetU8(pSSMHandle, &s->gate);
736	SSMR3GetU64(pSSMHandle, &s->count_load_time);
737	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
738	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
739	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
740	if (s->CTXSUFF(pTimer))
741	TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
742	}
743
744	SSMR3GetS32(pSSMHandle, &pData->speaker_data_on);
745	return SSMR3GetS32(pSSMHandle, &pData->dummy_refresh_clock);
746	}
747
748
749	/**
750	* Device timer callback function.
751	*
752	* @param pDevIns Device instance of the device which registered the timer.
753	* @param pTimer The timer handle.
754	*/
755	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
756	{
757	PITState pData = PDMINS2DATA(pDevIns, PITState );
758	PITChannelState *s = &pData->channels[0];
759	STAM_PROFILE_ADV_START(&s->CTXSUFF(pPit)->StatPITHandler, a);
760	pit_irq_timer_update(s, s->next_transition_time);
761	STAM_PROFILE_ADV_STOP(&s->CTXSUFF(pPit)->StatPITHandler, a);
762	}
763
764
765	/**
766	* Relocation notification.
767	*
768	* @returns VBox status.
769	* @param pDevIns The device instance data.
770	* @param offDelta The delta relative to the old address.
771	*/
772	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
773	{
774	PITState pData = PDMINS2DATA(pDevIns, PITState );
775	unsigned i;
776	LogFlow(("pitRelocate: \n"));
777
778	for (i = 0; i < ELEMENTS(pData->channels); i++)
779	{
780	PITChannelState *pCh = &pData->channels[i];
781	if (pCh->pTimerHC)
782	pCh->pTimerGC = TMTimerGCPtr(pCh->pTimerHC);
783	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
784	}
785	}
786
787	/** @todo remove this! */
788	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
789
790	/**
791	* Reset notification.
792	*
793	* @returns VBox status.
794	* @param pDevIns The device instance data.
795	*/
796	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
797	{
798	PITState pData = PDMINS2DATA(pDevIns, PITState );
799	unsigned i;
800	LogFlow(("pitReset: \n"));
801
802	for (i = 0; i < ELEMENTS(pData->channels); i++)
803	{
804	PITChannelState *s = &pData->channels[i];
805
806	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
807	s->latched_count = 0;
808	s->count_latched = 0;
809	s->status_latched = 0;
810	s->status = 0;
811	s->read_state = 0;
812	s->write_state = 0;
813	s->write_latch = 0;
814	s->rw_mode = 0;
815	s->bcd = 0;
816	#endif
817	s->mode = 3;
818	s->gate = (i != 2);
819	pit_load_count(s, 0);
820	}
821	/** @todo remove when #1589 is resolved. */
822	pitInfo(pDevIns, DBGFR3InfoLogRelHlp(), NULL);
823	}
824
825
826	/**
827	* Info handler, device version.
828	*
829	* @param pDevIns Device instance which registered the info.
830	* @param pHlp Callback functions for doing output.
831	* @param pszArgs Argument string. Optional and specific to the handler.
832	*/
833	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
834	{
835	PITState pData = PDMINS2DATA(pDevIns, PITState );
836	unsigned i;
837	for (i = 0; i < ELEMENTS(pData->channels); i++)
838	{
839	const PITChannelState *pCh = &pData->channels[i];
840
841	pHlp->pfnPrintf(pHlp,
842	"PIT (i8254) channel %d status: irq=%#x\n"
843	" count=%08x" " latched_count=%04x count_latched=%02x\n"
844	" status=%02x status_latched=%02x read_state=%02x\n"
845	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
846	" mode=%02x bcd=%02x gate=%02x\n"
847	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
848	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
849	,
850	i, pCh->irq,
851	pCh->count, pCh->latched_count, pCh->count_latched,
852	pCh->status, pCh->status_latched, pCh->read_state,
853	pCh->write_state, pCh->write_latch, pCh->rw_mode,
854	pCh->mode, pCh->bcd, pCh->gate,
855	pCh->count_load_time, pCh->next_transition_time,
856	pCh->u64ReloadTS, pCh->u64NextTS);
857	}
858	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
859	pData->speaker_data_on, pData->dummy_refresh_clock);
860	}
861
862
863	/**
864	* Construct a device instance for a VM.
865	*
866	* @returns VBox status.
867	* @param pDevIns The device instance data.
868	* If the registration structure is needed, pDevIns->pDevReg points to it.
869	* @param iInstance Instance number. Use this to figure out which registers and such to use.
870	* The device number is also found in pDevIns->iInstance, but since it's
871	* likely to be freqently used PDM passes it as parameter.
872	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
873	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
874	* iInstance it's expected to be used a bit in this function.
875	*/
876	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
877	{
878	PITState pData = PDMINS2DATA(pDevIns, PITState );
879	int rc;
880	uint8_t u8Irq;
881	uint16_t u16Base;
882	bool fSpeaker;
883	bool fGCEnabled;
884	bool fR0Enabled;
885	unsigned i;
886	Assert(iInstance == 0);
887
888	/*
889	* Validate configuration.
890	*/
891	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0Speaker\0GCEnabled\0R0Enabled\0"))
892	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
893
894	/*
895	* Init the data.
896	*/
897	rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
898	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
899	u8Irq = 0;
900	else if (VBOX_FAILURE(rc))
901	return PDMDEV_SET_ERROR(pDevIns, rc,
902	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
903
904	rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
905	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
906	u16Base = 0x40;
907	else if (VBOX_FAILURE(rc))
908	return PDMDEV_SET_ERROR(pDevIns, rc,
909	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
910
911	rc = CFGMR3QueryBool(pCfgHandle, "SpeakerEnabled", &fSpeaker);
912	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
913	fSpeaker = true;
914	else if (VBOX_FAILURE(rc))
915	return PDMDEV_SET_ERROR(pDevIns, rc,
916	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
917
918	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
919	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
920	fGCEnabled = true;
921	else if (VBOX_FAILURE(rc))
922	return PDMDEV_SET_ERROR(pDevIns, rc,
923	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
924
925	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
926	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
927	fR0Enabled = true;
928	else if (VBOX_FAILURE(rc))
929	return PDMDEV_SET_ERROR(pDevIns, rc,
930	N_("Configuration error: failed to read R0Enabled as boolean"));
931
932	pData->pDevIns = pDevIns;
933	pData->channels[0].irq = u8Irq;
934	for (i = 0; i < ELEMENTS(pData->channels); i++)
935	{
936	pData->channels[i].pPitHC = pData;
937	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
938	}
939
940	/*
941	* Create timer, register I/O Ports and save state.
942	*/
943	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, "i8254 Programmable Interval Timer",
944	&pData->channels[0].CTXSUFF(pTimer));
945	if (VBOX_FAILURE(rc))
946	{
947	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
948	return rc;
949	}
950
951	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
952	if (VBOX_FAILURE(rc))
953	return rc;
954	if (fGCEnabled)
955	{
956	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
957	if (VBOX_FAILURE(rc))
958	return rc;
959	}
960	if (fR0Enabled)
961	{
962	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
963	if (VBOX_FAILURE(rc))
964	return rc;
965	}
966
967	if (fSpeaker)
968	{
969	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
970	if (VBOX_FAILURE(rc))
971	return rc;
972	if (fGCEnabled)
973	{
974	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
975	if (VBOX_FAILURE(rc))
976	return rc;
977	}
978	}
979
980	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pData),
981	NULL, pitSaveExec, NULL,
982	NULL, pitLoadExec, NULL);
983	if (VBOX_FAILURE(rc))
984	return rc;
985
986	/*
987	* Initialize the device state.
988	*/
989	pitReset(pDevIns);
990
991	/*
992	* Register statistics and debug info.
993	*/
994	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
995	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
996
997	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
998
999	return VINF_SUCCESS;
1000	}
1001
1002
1003	/**
1004	* The device registration structure.
1005	*/
1006	const PDMDEVREG g_DeviceI8254 =
1007	{
1008	/* u32Version */
1009	PDM_DEVREG_VERSION,
1010	/* szDeviceName */
1011	"i8254",
1012	/* szGCMod */
1013	"VBoxDDGC.gc",
1014	/* szR0Mod */
1015	"VBoxDDR0.r0",
1016	/* pszDescription */
1017	"i8254 Programmable Interval Timer And Dummy Speaker",
1018	/* fFlags */
1019	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1020	/* fClass */
1021	PDM_DEVREG_CLASS_PIT,
1022	/* cMaxInstances */
1023	1,
1024	/* cbInstance */
1025	sizeof(PITState),
1026	/* pfnConstruct */
1027	pitConstruct,
1028	/* pfnDestruct */
1029	NULL,
1030	/* pfnRelocate */
1031	pitRelocate,
1032	/* pfnIOCtl */
1033	NULL,
1034	/* pfnPowerOn */
1035	NULL,
1036	/* pfnReset */
1037	pitReset,
1038	/* pfnSuspend */
1039	NULL,
1040	/* pfnResume */
1041	NULL,
1042	/* pfnAttach */
1043	NULL,
1044	/* pfnDetach */
1045	NULL,
1046	/* pfnQueryInterface. */
1047	NULL
1048	};
1049
1050	#endif /* IN_RING3 */
1051	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1052

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 2685

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