DevPit-i8254.cpp@ 2789

Last change on this file since 2789 was 2781, checked in by vboxsync, 18 years ago
made the file description correspond to the device/driver description.
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1	/** $Id: DevPit-i8254.cpp 2781 2007-05-22 22:56:27Z vboxsync $ */
2	/** @file
3	* Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*
21	* --------------------------------------------------------------------
22	*
23	* This code is based on:
24	*
25	* QEMU 8253/8254 interval timer emulation
26	*
27	* Copyright (c) 2003-2004 Fabrice Bellard
28	*
29	* Permission is hereby granted, free of charge, to any person obtaining a copy
30	* of this software and associated documentation files (the "Software"), to deal
31	* in the Software without restriction, including without limitation the rights
32	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
33	* copies of the Software, and to permit persons to whom the Software is
34	* furnished to do so, subject to the following conditions:
35	*
36	* The above copyright notice and this permission notice shall be included in
37	* all copies or substantial portions of the Software.
38	*
39	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
40	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
41	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
42	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
43	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
44	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
45	* THE SOFTWARE.
46	*/
47
48
49	/*******************************************************************************
50	* Header Files *
51	*******************************************************************************/
52	#define LOG_GROUP LOG_GROUP_DEV_PIT
53	#include <VBox/pdm.h>
54	#include <VBox/log.h>
55	#include <VBox/stam.h>
56	#include <iprt/assert.h>
57	#include <iprt/asm.h>
58
59	#include "Builtins.h"
60
61	/*******************************************************************************
62	* Defined Constants And Macros *
63	*******************************************************************************/
64	/** The PIT frequency. */
65	#define PIT_FREQ 1193182
66
67	#define RW_STATE_LSB 1
68	#define RW_STATE_MSB 2
69	#define RW_STATE_WORD0 3
70	#define RW_STATE_WORD1 4
71
72	/** The version of the saved state. */
73	#define PIT_SAVED_STATE_VERSION 2
74
75
76	/*******************************************************************************
77	* Structures and Typedefs *
78	*******************************************************************************/
79	typedef struct PITChannelState
80	{
81	/** Pointer to the instance data - HCPtr. */
82	HCPTRTYPE(struct PITState *) pPitHC;
83	/** The timer - HCPtr. */
84	PTMTIMERHC pTimerHC;
85	/** Pointer to the instance data - GCPtr. */
86	GCPTRTYPE(struct PITState *) pPitGC;
87	/** The timer - HCPtr. */
88	PTMTIMERGC pTimerGC;
89	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
90	uint64_t u64ReloadTS;
91	/** The actual time of the next tick.
92	* As apposed to the next_transition_time which contains the correct time of the next tick. */
93	uint64_t u64NextTS;
94
95	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
96	uint64_t count_load_time;
97	/* irq handling */
98	int64_t next_transition_time;
99	int32_t irq;
100	/** Number of release log entries. Used to prevent floading. */
101	uint32_t cRelLogEntries;
102
103	uint32_t count; /* can be 65536 */
104	uint16_t latched_count;
105	uint8_t count_latched;
106	uint8_t status_latched;
107
108	uint8_t status;
109	uint8_t read_state;
110	uint8_t write_state;
111	uint8_t write_latch;
112
113	uint8_t rw_mode;
114	uint8_t mode;
115	uint8_t bcd; /* not supported */
116	uint8_t gate; /* timer start */
117
118	} PITChannelState;
119
120	typedef struct PITState
121	{
122	PITChannelState channels[3];
123	/** Speaker data. */
124	int32_t speaker_data_on;
125	/** Speaker dummy. */
126	int32_t dummy_refresh_clock;
127	/** Pointer to the device instance. */
128	HCPTRTYPE(PPDMDEVINS) pDevIns;
129	#if HC_ARCH_BITS == 32
130	uint32_t Alignment0;
131	#endif
132	/** Number of IRQs that's been raised. */
133	STAMCOUNTER StatPITIrq;
134	/** Profiling the timer callback handler. */
135	STAMPROFILEADV StatPITHandler;
136	} PITState;
137
138
139	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
140	/*******************************************************************************
141	* Internal Functions *
142	*******************************************************************************/
143	__BEGIN_DECLS
144	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
145	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
146	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
147	#ifdef IN_RING3
148	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
149	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
150	#endif
151	__END_DECLS
152
153
154
155
156	static int pit_get_count(PITChannelState *s)
157	{
158	uint64_t d;
159	int counter;
160	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
161
162	if (s->mode == 2) /** @todo Implement proper virtual time and get rid of this hack.. */
163	{
164	#if 0
165	d = TMTimerGet(pTimer);
166	d -= s->u64ReloadTS;
167	d = ASMMultU64ByU32DivByU32(d, PIT_FREQ, TMTimerGetFreq(pTimer));
168	#else /* variable time because of catch up */
169	if (s->u64NextTS == UINT64_MAX)
170	return 1; /** @todo check this value. */
171	d = TMTimerGet(pTimer);
172	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
173	#endif
174	if (d >= s->count)
175	return 1;
176	return s->count - d;
177	}
178	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
179	switch(s->mode) {
180	case 0:
181	case 1:
182	case 4:
183	case 5:
184	counter = (s->count - d) & 0xffff;
185	break;
186	case 3:
187	/* XXX: may be incorrect for odd counts */
188	counter = s->count - ((2 * d) % s->count);
189	break;
190	default:
191	counter = s->count - (d % s->count);
192	break;
193	}
194	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
195	return counter;
196	}
197
198	/* get pit output bit */
199	static int pit_get_out1(PITChannelState *s, int64_t current_time)
200	{
201	uint64_t d;
202	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
203	int out;
204
205	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
206	switch(s->mode) {
207	default:
208	case 0:
209	out = (d >= s->count);
210	break;
211	case 1:
212	out = (d < s->count);
213	break;
214	case 2:
215	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
216	if ((d % s->count) == 0 && d != 0)
217	out = 1;
218	else
219	out = 0;
220	break;
221	case 3:
222	out = (d % s->count) < ((s->count + 1) >> 1);
223	break;
224	case 4:
225	case 5:
226	out = (d == s->count);
227	break;
228	}
229	return out;
230	}
231
232
233	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
234	{
235	PITChannelState *s = &pit->channels[channel];
236	return pit_get_out1(s, current_time);
237	}
238
239
240	static int pit_get_gate(PITState *pit, int channel)
241	{
242	PITChannelState *s = &pit->channels[channel];
243	return s->gate;
244	}
245
246
247	/* if already latched, do not latch again */
248	static void pit_latch_count(PITChannelState *s)
249	{
250	if (!s->count_latched) {
251	s->latched_count = pit_get_count(s);
252	s->count_latched = s->rw_mode;
253	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
254	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
255	}
256	}
257
258	#ifdef IN_RING3
259
260	/* val must be 0 or 1 */
261	static void pit_set_gate(PITState *pit, int channel, int val)
262	{
263	PITChannelState *s = &pit->channels[channel];
264	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
265
266	switch(s->mode) {
267	default:
268	case 0:
269	case 4:
270	/* XXX: just disable/enable counting */
271	break;
272	case 1:
273	case 5:
274	if (s->gate < val) {
275	/* restart counting on rising edge */
276	s->count_load_time = TMTimerGet(pTimer);
277	pit_irq_timer_update(s, s->count_load_time);
278	}
279	break;
280	case 2:
281	case 3:
282	if (s->gate < val) {
283	/* restart counting on rising edge */
284	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
285	pit_irq_timer_update(s, s->count_load_time);
286	}
287	/* XXX: disable/enable counting */
288	break;
289	}
290	s->gate = val;
291	}
292
293	static inline void pit_load_count(PITChannelState *s, int val)
294	{
295	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
296	if (val == 0)
297	val = 0x10000;
298	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
299	s->count = val;
300	pit_irq_timer_update(s, s->count_load_time);
301
302	/* log the new rate if it's high enough. */
303	if ( ( s->mode == 2
304	\|\| s->mode == 3)
305	&& s->count < 0x10000
306	&& s->cRelLogEntries++ < 32)
307	LogRel(("PIT: mode=%d count=%#x - %d.%02d Hz\n", s->mode, s->count,
308	PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
309	}
310
311	/* return -1 if no transition will occur. */
312	static int64_t pit_get_next_transition_time(PITChannelState *s,
313	uint64_t current_time)
314	{
315	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
316	uint64_t d, next_time, base;
317	uint32_t period2;
318
319	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
320	switch(s->mode) {
321	default:
322	case 0:
323	case 1:
324	if (d < s->count)
325	next_time = s->count;
326	else
327	return -1;
328	break;
329	/*
330	* Mode 2: The period is count + 1 PIT ticks.
331	* When the counter reaches 1 we sent the output low (for channel 0 that
332	* means raise an irq). On the next tick, where we should be decrementing
333	* from 1 to 0, the count is loaded and the output goes high (channel 0
334	* means clearing the irq).
335	*
336	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
337	* the irq. We also don't set it until we reach 0, which is a tick late - will
338	* try fix that later some day.
339	*/
340	case 2:
341	base = (d / s->count) * s->count;
342	#ifndef VBOX /* see above */
343	if ((d - base) == 0 && d != 0)
344	next_time = base + s->count;
345	else
346	#endif
347	next_time = base + s->count + 1;
348	break;
349	case 3:
350	base = (d / s->count) * s->count;
351	period2 = ((s->count + 1) >> 1);
352	if ((d - base) < period2)
353	next_time = base + period2;
354	else
355	next_time = base + s->count;
356	break;
357	case 4:
358	case 5:
359	if (d < s->count)
360	next_time = s->count;
361	else if (d == s->count)
362	next_time = s->count + 1;
363	else
364	return -1;
365	break;
366	}
367	/* convert to timer units */
368	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
369	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
370	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
371	/* fix potential rounding problems */
372	/* XXX: better solution: use a clock at PIT_FREQ Hz */
373	if (next_time <= current_time)
374	next_time = current_time + 1;
375	return next_time;
376	}
377
378	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
379	{
380	uint64_t now;
381	int64_t expire_time;
382	int irq_level;
383	PPDMDEVINS pDevIns;
384	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
385
386	if (!s->CTXSUFF(pTimer))
387	return;
388	expire_time = pit_get_next_transition_time(s, current_time);
389	irq_level = pit_get_out1(s, current_time);
390
391	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
392	pDevIns = s->CTXSUFF(pPit)->pDevIns;
393	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
394	if (irq_level)
395	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
396	now = TMTimerGet(pTimer);
397	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
398	if (irq_level)
399	{
400	s->u64ReloadTS = now;
401	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITIrq);
402	}
403
404	if (expire_time != -1)
405	{
406	s->u64NextTS = expire_time;
407	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
408	}
409	else
410	{
411	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
412	TMTimerStop(s->CTXSUFF(pTimer));
413	s->u64NextTS = UINT64_MAX;
414	}
415	s->next_transition_time = expire_time;
416	}
417
418	#endif /* IN_RING3 */
419
420
421	/**
422	* Port I/O Handler for IN operations.
423	*
424	* @returns VBox status code.
425	*
426	* @param pDevIns The device instance.
427	* @param pvUser User argument - ignored.
428	* @param Port Port number used for the IN operation.
429	* @param pu32 Where to store the result.
430	* @param cb Number of bytes read.
431	*/
432	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
433	{
434	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
435	NOREF(pvUser);
436	Port &= 3;
437	if (cb != 1 \|\| Port == 3)
438	{
439	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
440	return VERR_IOM_IOPORT_UNUSED;
441	}
442
443	PITState pit = PDMINS2DATA(pDevIns, PITState );
444	int ret;
445	PITChannelState *s = &pit->channels[Port];
446	if (s->status_latched)
447	{
448	s->status_latched = 0;
449	ret = s->status;
450	}
451	else if (s->count_latched)
452	{
453	switch (s->count_latched)
454	{
455	default:
456	case RW_STATE_LSB:
457	ret = s->latched_count & 0xff;
458	s->count_latched = 0;
459	break;
460	case RW_STATE_MSB:
461	ret = s->latched_count >> 8;
462	s->count_latched = 0;
463	break;
464	case RW_STATE_WORD0:
465	ret = s->latched_count & 0xff;
466	s->count_latched = RW_STATE_MSB;
467	break;
468	}
469	}
470	else
471	{
472	int count;
473	switch (s->read_state)
474	{
475	default:
476	case RW_STATE_LSB:
477	count = pit_get_count(s);
478	ret = count & 0xff;
479	break;
480	case RW_STATE_MSB:
481	count = pit_get_count(s);
482	ret = (count >> 8) & 0xff;
483	break;
484	case RW_STATE_WORD0:
485	count = pit_get_count(s);
486	ret = count & 0xff;
487	s->read_state = RW_STATE_WORD1;
488	break;
489	case RW_STATE_WORD1:
490	count = pit_get_count(s);
491	ret = (count >> 8) & 0xff;
492	s->read_state = RW_STATE_WORD0;
493	break;
494	}
495	}
496
497	*pu32 = ret;
498	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
499	return VINF_SUCCESS;
500	}
501
502
503	/**
504	* Port I/O Handler for OUT operations.
505	*
506	* @returns VBox status code.
507	*
508	* @param pDevIns The device instance.
509	* @param pvUser User argument - ignored.
510	* @param Port Port number used for the IN operation.
511	* @param u32 The value to output.
512	* @param cb The value size in bytes.
513	*/
514	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
515	{
516	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
517	NOREF(pvUser);
518	if (cb != 1)
519	return VINF_SUCCESS;
520
521	PITState pit = PDMINS2DATA(pDevIns, PITState );
522	Port &= 3;
523	if (Port == 3)
524	{
525	/*
526	* Port 43h - Mode/Command Register.
527	* 7 6 5 4 3 2 1 0
528	* * * . . . . . . Select channel: 0 0 = Channel 0
529	* 0 1 = Channel 1
530	* 1 0 = Channel 2
531	* 1 1 = Read-back command (8254 only)
532	* (Illegal on 8253)
533	* (Illegal on PS/2 {JAM})
534	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
535	* 0 1 = Access mode: lobyte only
536	* 1 0 = Access mode: hibyte only
537	* 1 1 = Access mode: lobyte/hibyte
538	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
539	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
540	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
541	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
542	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
543	*/
544	unsigned channel = u32 >> 6;
545	if (channel == 3)
546	{
547	/* read-back command */
548	for (channel = 0; channel < ELEMENTS(pit->channels); channel++)
549	{
550	PITChannelState *s = &pit->channels[channel];
551	if (u32 & (2 << channel)) {
552	if (!(u32 & 0x20))
553	pit_latch_count(s);
554	if (!(u32 & 0x10) && !s->status_latched)
555	{
556	/* status latch */
557	/* XXX: add BCD and null count */
558	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
559	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
560	\| (s->rw_mode << 4)
561	\| (s->mode << 1)
562	\| s->bcd;
563	s->status_latched = 1;
564	}
565	}
566	}
567	}
568	else
569	{
570	PITChannelState *s = &pit->channels[channel];
571	unsigned access = (u32 >> 4) & 3;
572	if (access == 0)
573	pit_latch_count(s);
574	else
575	{
576	s->rw_mode = access;
577	s->read_state = access;
578	s->write_state = access;
579
580	s->mode = (u32 >> 1) & 7;
581	s->bcd = u32 & 1;
582	/* XXX: update irq timer ? */
583	}
584	}
585	}
586	else
587	{
588	#ifndef IN_RING3
589	return VINF_IOM_HC_IOPORT_WRITE;
590	#else /* IN_RING3 */
591	/*
592	* Port 40-42h - Channel Data Ports.
593	*/
594	PITChannelState *s = &pit->channels[Port];
595	switch(s->write_state)
596	{
597	default:
598	case RW_STATE_LSB:
599	pit_load_count(s, u32);
600	break;
601	case RW_STATE_MSB:
602	pit_load_count(s, u32 << 8);
603	break;
604	case RW_STATE_WORD0:
605	s->write_latch = u32;
606	s->write_state = RW_STATE_WORD1;
607	break;
608	case RW_STATE_WORD1:
609	pit_load_count(s, s->write_latch \| (u32 << 8));
610	s->write_state = RW_STATE_WORD0;
611	break;
612	}
613	#endif /* !IN_RING3 */
614	}
615	return VINF_SUCCESS;
616	}
617
618
619	/**
620	* Port I/O Handler for speaker IN operations.
621	*
622	* @returns VBox status code.
623	*
624	* @param pDevIns The device instance.
625	* @param pvUser User argument - ignored.
626	* @param Port Port number used for the IN operation.
627	* @param pu32 Where to store the result.
628	* @param cb Number of bytes read.
629	*/
630	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
631	{
632	NOREF(pvUser);
633	if (cb == 1)
634	{
635	PITState pData = PDMINS2DATA(pDevIns, PITState );
636	int out = pit_get_out(pData, 2, TMTimerGet(pData->channels[0].CTXSUFF(pTimer)));
637	pData->dummy_refresh_clock ^= 1;
638	*pu32 = (pData->speaker_data_on << 1) \| pit_get_gate(pData, 2) \| (out << 5) \| (pData->dummy_refresh_clock << 4);
639	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
640	return VINF_SUCCESS;
641	}
642	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
643	return VERR_IOM_IOPORT_UNUSED;
644	}
645
646	#ifdef IN_RING3
647
648	/**
649	* Port I/O Handler for speaker OUT operations.
650	*
651	* @returns VBox status code.
652	*
653	* @param pDevIns The device instance.
654	* @param pvUser User argument - ignored.
655	* @param Port Port number used for the IN operation.
656	* @param u32 The value to output.
657	* @param cb The value size in bytes.
658	*/
659	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
660	{
661	NOREF(pvUser);
662	if (cb == 1)
663	{
664	PITState pData = PDMINS2DATA(pDevIns, PITState );
665	pData->speaker_data_on = (u32 >> 1) & 1;
666	pit_set_gate(pData, 2, u32 & 1);
667	}
668	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
669	return VINF_SUCCESS;
670	}
671
672
673	/**
674	* Saves a state of the programmable interval timer device.
675	*
676	* @returns VBox status code.
677	* @param pDevIns The device instance.
678	* @param pSSMHandle The handle to save the state to.
679	*/
680	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
681	{
682	PITState pData = PDMINS2DATA(pDevIns, PITState );
683	unsigned i;
684
685	for (i = 0; i < ELEMENTS(pData->channels); i++)
686	{
687	PITChannelState *s = &pData->channels[i];
688	SSMR3PutU32(pSSMHandle, s->count);
689	SSMR3PutU16(pSSMHandle, s->latched_count);
690	SSMR3PutU8(pSSMHandle, s->count_latched);
691	SSMR3PutU8(pSSMHandle, s->status_latched);
692	SSMR3PutU8(pSSMHandle, s->status);
693	SSMR3PutU8(pSSMHandle, s->read_state);
694	SSMR3PutU8(pSSMHandle, s->write_state);
695	SSMR3PutU8(pSSMHandle, s->write_latch);
696	SSMR3PutU8(pSSMHandle, s->rw_mode);
697	SSMR3PutU8(pSSMHandle, s->mode);
698	SSMR3PutU8(pSSMHandle, s->bcd);
699	SSMR3PutU8(pSSMHandle, s->gate);
700	SSMR3PutU64(pSSMHandle, s->count_load_time);
701	SSMR3PutU64(pSSMHandle, s->u64NextTS);
702	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
703	SSMR3PutS64(pSSMHandle, s->next_transition_time);
704	if (s->CTXSUFF(pTimer))
705	TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
706	}
707
708	SSMR3PutS32(pSSMHandle, pData->speaker_data_on);
709	return SSMR3PutS32(pSSMHandle, pData->dummy_refresh_clock);
710	}
711
712
713	/**
714	* Loads a saved programmable interval timer device state.
715	*
716	* @returns VBox status code.
717	* @param pDevIns The device instance.
718	* @param pSSMHandle The handle to the saved state.
719	* @param u32Version The data unit version number.
720	*/
721	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
722	{
723	PITState pData = PDMINS2DATA(pDevIns, PITState );
724	unsigned i;
725
726	if (u32Version != PIT_SAVED_STATE_VERSION)
727	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
728
729	for (i = 0; i < ELEMENTS(pData->channels); i++)
730	{
731	PITChannelState *s = &pData->channels[i];
732	SSMR3GetU32(pSSMHandle, &s->count);
733	SSMR3GetU16(pSSMHandle, &s->latched_count);
734	SSMR3GetU8(pSSMHandle, &s->count_latched);
735	SSMR3GetU8(pSSMHandle, &s->status_latched);
736	SSMR3GetU8(pSSMHandle, &s->status);
737	SSMR3GetU8(pSSMHandle, &s->read_state);
738	SSMR3GetU8(pSSMHandle, &s->write_state);
739	SSMR3GetU8(pSSMHandle, &s->write_latch);
740	SSMR3GetU8(pSSMHandle, &s->rw_mode);
741	SSMR3GetU8(pSSMHandle, &s->mode);
742	SSMR3GetU8(pSSMHandle, &s->bcd);
743	SSMR3GetU8(pSSMHandle, &s->gate);
744	SSMR3GetU64(pSSMHandle, &s->count_load_time);
745	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
746	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
747	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
748	if (s->CTXSUFF(pTimer))
749	TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
750	}
751
752	SSMR3GetS32(pSSMHandle, &pData->speaker_data_on);
753	return SSMR3GetS32(pSSMHandle, &pData->dummy_refresh_clock);
754	}
755
756
757	/**
758	* Device timer callback function.
759	*
760	* @param pDevIns Device instance of the device which registered the timer.
761	* @param pTimer The timer handle.
762	*/
763	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
764	{
765	PITState pData = PDMINS2DATA(pDevIns, PITState );
766	PITChannelState *s = &pData->channels[0];
767	STAM_PROFILE_ADV_START(&s->CTXSUFF(pPit)->StatPITHandler, a);
768	pit_irq_timer_update(s, s->next_transition_time);
769	STAM_PROFILE_ADV_STOP(&s->CTXSUFF(pPit)->StatPITHandler, a);
770	}
771
772
773	/**
774	* Relocation notification.
775	*
776	* @returns VBox status.
777	* @param pDevIns The device instance data.
778	* @param offDelta The delta relative to the old address.
779	*/
780	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
781	{
782	PITState pData = PDMINS2DATA(pDevIns, PITState );
783	unsigned i;
784	LogFlow(("pitRelocate: \n"));
785
786	for (i = 0; i < ELEMENTS(pData->channels); i++)
787	{
788	PITChannelState *pCh = &pData->channels[i];
789	if (pCh->pTimerHC)
790	pCh->pTimerGC = TMTimerGCPtr(pCh->pTimerHC);
791	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
792	}
793	}
794
795	/** @todo remove this! */
796	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
797
798	/**
799	* Reset notification.
800	*
801	* @returns VBox status.
802	* @param pDevIns The device instance data.
803	*/
804	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
805	{
806	PITState pData = PDMINS2DATA(pDevIns, PITState );
807	unsigned i;
808	LogFlow(("pitReset: \n"));
809
810	for (i = 0; i < ELEMENTS(pData->channels); i++)
811	{
812	PITChannelState *s = &pData->channels[i];
813
814	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
815	s->latched_count = 0;
816	s->count_latched = 0;
817	s->status_latched = 0;
818	s->status = 0;
819	s->read_state = 0;
820	s->write_state = 0;
821	s->write_latch = 0;
822	s->rw_mode = 0;
823	s->bcd = 0;
824	#endif
825	s->cRelLogEntries = 0;
826	s->mode = 3;
827	s->gate = (i != 2);
828	pit_load_count(s, 0);
829	}
830	/** @todo remove when #1589 is resolved. */
831	pitInfo(pDevIns, DBGFR3InfoLogRelHlp(), NULL);
832	}
833
834
835	/**
836	* Info handler, device version.
837	*
838	* @param pDevIns Device instance which registered the info.
839	* @param pHlp Callback functions for doing output.
840	* @param pszArgs Argument string. Optional and specific to the handler.
841	*/
842	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
843	{
844	PITState pData = PDMINS2DATA(pDevIns, PITState );
845	unsigned i;
846	for (i = 0; i < ELEMENTS(pData->channels); i++)
847	{
848	const PITChannelState *pCh = &pData->channels[i];
849
850	pHlp->pfnPrintf(pHlp,
851	"PIT (i8254) channel %d status: irq=%#x\n"
852	" count=%08x" " latched_count=%04x count_latched=%02x\n"
853	" status=%02x status_latched=%02x read_state=%02x\n"
854	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
855	" mode=%02x bcd=%02x gate=%02x\n"
856	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
857	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
858	,
859	i, pCh->irq,
860	pCh->count, pCh->latched_count, pCh->count_latched,
861	pCh->status, pCh->status_latched, pCh->read_state,
862	pCh->write_state, pCh->write_latch, pCh->rw_mode,
863	pCh->mode, pCh->bcd, pCh->gate,
864	pCh->count_load_time, pCh->next_transition_time,
865	pCh->u64ReloadTS, pCh->u64NextTS);
866	}
867	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
868	pData->speaker_data_on, pData->dummy_refresh_clock);
869	}
870
871
872	/**
873	* Construct a device instance for a VM.
874	*
875	* @returns VBox status.
876	* @param pDevIns The device instance data.
877	* If the registration structure is needed, pDevIns->pDevReg points to it.
878	* @param iInstance Instance number. Use this to figure out which registers and such to use.
879	* The device number is also found in pDevIns->iInstance, but since it's
880	* likely to be freqently used PDM passes it as parameter.
881	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
882	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
883	* iInstance it's expected to be used a bit in this function.
884	*/
885	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
886	{
887	PITState pData = PDMINS2DATA(pDevIns, PITState );
888	int rc;
889	uint8_t u8Irq;
890	uint16_t u16Base;
891	bool fSpeaker;
892	bool fGCEnabled;
893	bool fR0Enabled;
894	unsigned i;
895	Assert(iInstance == 0);
896
897	/*
898	* Validate configuration.
899	*/
900	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0Speaker\0GCEnabled\0R0Enabled\0"))
901	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
902
903	/*
904	* Init the data.
905	*/
906	rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
907	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
908	u8Irq = 0;
909	else if (VBOX_FAILURE(rc))
910	return PDMDEV_SET_ERROR(pDevIns, rc,
911	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
912
913	rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
914	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
915	u16Base = 0x40;
916	else if (VBOX_FAILURE(rc))
917	return PDMDEV_SET_ERROR(pDevIns, rc,
918	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
919
920	rc = CFGMR3QueryBool(pCfgHandle, "SpeakerEnabled", &fSpeaker);
921	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
922	fSpeaker = true;
923	else if (VBOX_FAILURE(rc))
924	return PDMDEV_SET_ERROR(pDevIns, rc,
925	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
926
927	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
928	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
929	fGCEnabled = true;
930	else if (VBOX_FAILURE(rc))
931	return PDMDEV_SET_ERROR(pDevIns, rc,
932	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
933
934	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
935	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
936	fR0Enabled = true;
937	else if (VBOX_FAILURE(rc))
938	return PDMDEV_SET_ERROR(pDevIns, rc,
939	N_("Configuration error: failed to read R0Enabled as boolean"));
940
941	pData->pDevIns = pDevIns;
942	pData->channels[0].irq = u8Irq;
943	for (i = 0; i < ELEMENTS(pData->channels); i++)
944	{
945	pData->channels[i].pPitHC = pData;
946	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
947	}
948
949	/*
950	* Create timer, register I/O Ports and save state.
951	*/
952	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, "i8254 Programmable Interval Timer",
953	&pData->channels[0].CTXSUFF(pTimer));
954	if (VBOX_FAILURE(rc))
955	{
956	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
957	return rc;
958	}
959
960	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
961	if (VBOX_FAILURE(rc))
962	return rc;
963	if (fGCEnabled)
964	{
965	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
966	if (VBOX_FAILURE(rc))
967	return rc;
968	}
969	if (fR0Enabled)
970	{
971	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
972	if (VBOX_FAILURE(rc))
973	return rc;
974	}
975
976	if (fSpeaker)
977	{
978	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
979	if (VBOX_FAILURE(rc))
980	return rc;
981	if (fGCEnabled)
982	{
983	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
984	if (VBOX_FAILURE(rc))
985	return rc;
986	}
987	}
988
989	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pData),
990	NULL, pitSaveExec, NULL,
991	NULL, pitLoadExec, NULL);
992	if (VBOX_FAILURE(rc))
993	return rc;
994
995	/*
996	* Initialize the device state.
997	*/
998	pitReset(pDevIns);
999
1000	/*
1001	* Register statistics and debug info.
1002	*/
1003	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1004	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1005
1006	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1007
1008	return VINF_SUCCESS;
1009	}
1010
1011
1012	/**
1013	* The device registration structure.
1014	*/
1015	const PDMDEVREG g_DeviceI8254 =
1016	{
1017	/* u32Version */
1018	PDM_DEVREG_VERSION,
1019	/* szDeviceName */
1020	"i8254",
1021	/* szGCMod */
1022	"VBoxDDGC.gc",
1023	/* szR0Mod */
1024	"VBoxDDR0.r0",
1025	/* pszDescription */
1026	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1027	/* fFlags */
1028	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1029	/* fClass */
1030	PDM_DEVREG_CLASS_PIT,
1031	/* cMaxInstances */
1032	1,
1033	/* cbInstance */
1034	sizeof(PITState),
1035	/* pfnConstruct */
1036	pitConstruct,
1037	/* pfnDestruct */
1038	NULL,
1039	/* pfnRelocate */
1040	pitRelocate,
1041	/* pfnIOCtl */
1042	NULL,
1043	/* pfnPowerOn */
1044	NULL,
1045	/* pfnReset */
1046	pitReset,
1047	/* pfnSuspend */
1048	NULL,
1049	/* pfnResume */
1050	NULL,
1051	/* pfnAttach */
1052	NULL,
1053	/* pfnDetach */
1054	NULL,
1055	/* pfnQueryInterface. */
1056	NULL
1057	};
1058
1059	#endif /* IN_RING3 */
1060	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1061

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 2789

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