DevPit-i8254.cpp@ 28346

Last change on this file since 28346 was 27126, checked in by vboxsync, 15 years ago
PIT,RTC,HPET,PDM: Combined and simplified the two interfaces PDM uses to inform PIT & RTC about HPET legacy mode changes. Moved the code to the right places in the files. Use bool, not uint8_t, when we mean boolean (no saved state difference).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 40.1 KB

Line
1	/* $Id: DevPit-i8254.cpp 27126 2010-03-05 19:40:43Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	* --------------------------------------------------------------------
21	*
22	* This code is based on:
23	*
24	* QEMU 8253/8254 interval timer emulation
25	*
26	* Copyright (c) 2003-2004 Fabrice Bellard
27	*
28	* Permission is hereby granted, free of charge, to any person obtaining a copy
29	* of this software and associated documentation files (the "Software"), to deal
30	* in the Software without restriction, including without limitation the rights
31	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32	* copies of the Software, and to permit persons to whom the Software is
33	* furnished to do so, subject to the following conditions:
34	*
35	* The above copyright notice and this permission notice shall be included in
36	* all copies or substantial portions of the Software.
37	*
38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44	* THE SOFTWARE.
45	*/
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_PIT
51	#include <VBox/pdmdev.h>
52	#include <VBox/log.h>
53	#include <VBox/stam.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm.h>
56
57	#ifdef IN_RING3
58	# include <iprt/alloc.h>
59	# include <iprt/string.h>
60	# include <iprt/uuid.h>
61	#endif /* IN_RING3 */
62
63	#include "../Builtins.h"
64
65
66	/*******************************************************************************
67	* Defined Constants And Macros *
68	*******************************************************************************/
69	/** The PIT frequency. */
70	#define PIT_FREQ 1193182
71
72	#define RW_STATE_LSB 1
73	#define RW_STATE_MSB 2
74	#define RW_STATE_WORD0 3
75	#define RW_STATE_WORD1 4
76
77	/** The current saved state version. */
78	#define PIT_SAVED_STATE_VERSION 4
79	/** The saved state version used by VirtualBox 3.1 and earlier.
80	* This did not include disable by HPET flag. */
81	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
82	/** The saved state version used by VirtualBox 3.0 and earlier.
83	* This did not include the config part. */
84	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
85
86	/** @def FAKE_REFRESH_CLOCK
87	* Define this to flip the 15usec refresh bit on every read.
88	* If not defined, it will be flipped correctly. */
89	/* #define FAKE_REFRESH_CLOCK */
90	#ifdef DOXYGEN_RUNNING
91	# define FAKE_REFRESH_CLOCK
92	#endif
93
94
95	/*******************************************************************************
96	* Structures and Typedefs *
97	*******************************************************************************/
98	typedef struct PITChannelState
99	{
100	/** Pointer to the instance data - R3 Ptr. */
101	R3PTRTYPE(struct PITState *) pPitR3;
102	/** The timer - R3 Ptr. */
103	PTMTIMERR3 pTimerR3;
104	/** Pointer to the instance data - R0 Ptr. */
105	R0PTRTYPE(struct PITState *) pPitR0;
106	/** The timer - R0 Ptr. */
107	PTMTIMERR0 pTimerR0;
108	/** Pointer to the instance data - RC Ptr. */
109	RCPTRTYPE(struct PITState *) pPitRC;
110	/** The timer - RC Ptr. */
111	PTMTIMERRC pTimerRC;
112	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
113	uint64_t u64ReloadTS;
114	/** The actual time of the next tick.
115	* As apposed to the next_transition_time which contains the correct time of the next tick. */
116	uint64_t u64NextTS;
117
118	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
119	uint64_t count_load_time;
120	/* irq handling */
121	int64_t next_transition_time;
122	int32_t irq;
123	/** Number of release log entries. Used to prevent floading. */
124	uint32_t cRelLogEntries;
125
126	uint32_t count; /* can be 65536 */
127	uint16_t latched_count;
128	uint8_t count_latched;
129	uint8_t status_latched;
130
131	uint8_t status;
132	uint8_t read_state;
133	uint8_t write_state;
134	uint8_t write_latch;
135
136	uint8_t rw_mode;
137	uint8_t mode;
138	uint8_t bcd; /* not supported */
139	uint8_t gate; /* timer start */
140
141	} PITChannelState;
142
143	typedef struct PITState
144	{
145	PITChannelState channels[3];
146	/** Speaker data. */
147	int32_t speaker_data_on;
148	#ifdef FAKE_REFRESH_CLOCK
149	/** Speaker dummy. */
150	int32_t dummy_refresh_clock;
151	#else
152	uint32_t Alignment1;
153	#endif
154	/** Config: I/O port base. */
155	RTIOPORT IOPortBaseCfg;
156	/** Config: Speaker enabled. */
157	bool fSpeakerCfg;
158	bool fDisabledByHpet;
159	bool afAlignment0[HC_ARCH_BITS == 32 ? 4 : 4];
160	/** PIT port interface. */
161	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
162	/** Pointer to the device instance. */
163	PPDMDEVINSR3 pDevIns;
164	/** Number of IRQs that's been raised. */
165	STAMCOUNTER StatPITIrq;
166	/** Profiling the timer callback handler. */
167	STAMPROFILEADV StatPITHandler;
168	} PITState;
169
170
171	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
172	/*******************************************************************************
173	* Internal Functions *
174	*******************************************************************************/
175	RT_C_DECLS_BEGIN
176	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
177	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
178	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
179	#ifdef IN_RING3
180	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
181	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now);
182	#endif
183	RT_C_DECLS_END
184
185
186
187
188	static int pit_get_count(PITChannelState *s)
189	{
190	uint64_t d;
191	int counter;
192	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
193
194	if (s->mode == 2)
195	{
196	if (s->u64NextTS == UINT64_MAX)
197	{
198	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
199	return s->count - (d % s->count); /** @todo check this value. */
200	}
201	uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
202	if (!Interval)
203	return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
204	d = TMTimerGet(pTimer);
205	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
206	if (d >= s->count)
207	return 1;
208	return s->count - d;
209	}
210	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
211	switch(s->mode) {
212	case 0:
213	case 1:
214	case 4:
215	case 5:
216	counter = (s->count - d) & 0xffff;
217	break;
218	case 3:
219	/* XXX: may be incorrect for odd counts */
220	counter = s->count - ((2 * d) % s->count);
221	break;
222	default:
223	counter = s->count - (d % s->count);
224	break;
225	}
226	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
227	return counter;
228	}
229
230	/* get pit output bit */
231	static int pit_get_out1(PITChannelState *s, int64_t current_time)
232	{
233	uint64_t d;
234	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
235	int out;
236
237	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
238	switch(s->mode) {
239	default:
240	case 0:
241	out = (d >= s->count);
242	break;
243	case 1:
244	out = (d < s->count);
245	break;
246	case 2:
247	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
248	if ((d % s->count) == 0 && d != 0)
249	out = 1;
250	else
251	out = 0;
252	break;
253	case 3:
254	out = (d % s->count) < ((s->count + 1) >> 1);
255	break;
256	case 4:
257	case 5:
258	out = (d == s->count);
259	break;
260	}
261	return out;
262	}
263
264
265	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
266	{
267	PITChannelState *s = &pit->channels[channel];
268	return pit_get_out1(s, current_time);
269	}
270
271
272	static int pit_get_gate(PITState *pit, int channel)
273	{
274	PITChannelState *s = &pit->channels[channel];
275	return s->gate;
276	}
277
278
279	/* if already latched, do not latch again */
280	static void pit_latch_count(PITChannelState *s)
281	{
282	if (!s->count_latched) {
283	s->latched_count = pit_get_count(s);
284	s->count_latched = s->rw_mode;
285	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
286	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
287	}
288	}
289
290	#ifdef IN_RING3
291
292	/* val must be 0 or 1 */
293	static void pit_set_gate(PITState *pit, int channel, int val)
294	{
295	PITChannelState *s = &pit->channels[channel];
296	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
297	Assert((val & 1) == val);
298
299	switch(s->mode) {
300	default:
301	case 0:
302	case 4:
303	/* XXX: just disable/enable counting */
304	break;
305	case 1:
306	case 5:
307	if (s->gate < val) {
308	/* restart counting on rising edge */
309	Log(("pit_set_gate: restarting mode %d\n", s->mode));
310	s->count_load_time = TMTimerGet(pTimer);
311	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
312	}
313	break;
314	case 2:
315	case 3:
316	if (s->gate < val) {
317	/* restart counting on rising edge */
318	Log(("pit_set_gate: restarting mode %d\n", s->mode));
319	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
320	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
321	}
322	/* XXX: disable/enable counting */
323	break;
324	}
325	s->gate = val;
326	}
327
328	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
329	{
330	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
331	if (val == 0)
332	val = 0x10000;
333	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
334	s->count = val;
335	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
336
337	/* log the new rate (ch 0 only). */
338	if ( s->pTimerR3 /* ch 0 */
339	&& s->cRelLogEntries++ < 32)
340	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
341	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
342	else
343	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
344	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
345	}
346
347	/* return -1 if no transition will occur. */
348	static int64_t pit_get_next_transition_time(PITChannelState *s,
349	uint64_t current_time)
350	{
351	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
352	uint64_t d, next_time, base;
353	uint32_t period2;
354
355	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
356	switch(s->mode) {
357	default:
358	case 0:
359	case 1:
360	if (d < s->count)
361	next_time = s->count;
362	else
363	return -1;
364	break;
365	/*
366	* Mode 2: The period is count + 1 PIT ticks.
367	* When the counter reaches 1 we sent the output low (for channel 0 that
368	* means raise an irq). On the next tick, where we should be decrementing
369	* from 1 to 0, the count is loaded and the output goes high (channel 0
370	* means clearing the irq).
371	*
372	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
373	* the irq. We also don't set it until we reach 0, which is a tick late - will
374	* try fix that later some day.
375	*/
376	case 2:
377	base = (d / s->count) * s->count;
378	#ifndef VBOX /* see above */
379	if ((d - base) == 0 && d != 0)
380	next_time = base + s->count;
381	else
382	#endif
383	next_time = base + s->count + 1;
384	break;
385	case 3:
386	base = (d / s->count) * s->count;
387	period2 = ((s->count + 1) >> 1);
388	if ((d - base) < period2)
389	next_time = base + period2;
390	else
391	next_time = base + s->count;
392	break;
393	case 4:
394	case 5:
395	if (d < s->count)
396	next_time = s->count;
397	else if (d == s->count)
398	next_time = s->count + 1;
399	else
400	return -1;
401	break;
402	}
403	/* convert to timer units */
404	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
405	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
406	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
407	/* fix potential rounding problems */
408	/* XXX: better solution: use a clock at PIT_FREQ Hz */
409	if (next_time <= current_time)
410	next_time = current_time + 1;
411	return next_time;
412	}
413
414	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now)
415	{
416	int64_t expire_time;
417	int irq_level;
418	PPDMDEVINS pDevIns;
419	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
420
421	if (!s->CTX_SUFF(pTimer))
422	return;
423	expire_time = pit_get_next_transition_time(s, current_time);
424	irq_level = pit_get_out1(s, current_time);
425
426	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
427	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
428
429	/* If PIT disabled by HPET - just disconnect ticks from interrupt controllers, and not modify
430	* other moments of device functioning.
431	* @todo: is it correct?
432	*/
433	if (!s->pPitR3->fDisabledByHpet)
434	{
435	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
436	if (irq_level)
437	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
438	}
439
440	if (irq_level)
441	{
442	s->u64ReloadTS = now;
443	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
444	}
445
446	if (expire_time != -1)
447	{
448	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
449	s->u64NextTS = expire_time;
450	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
451	}
452	else
453	{
454	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
455	TMTimerStop(s->CTX_SUFF(pTimer));
456	s->u64NextTS = UINT64_MAX;
457	}
458	s->next_transition_time = expire_time;
459	}
460
461	#endif /* IN_RING3 */
462
463
464	/**
465	* Port I/O Handler for IN operations.
466	*
467	* @returns VBox status code.
468	*
469	* @param pDevIns The device instance.
470	* @param pvUser User argument - ignored.
471	* @param Port Port number used for the IN operation.
472	* @param pu32 Where to store the result.
473	* @param cb Number of bytes read.
474	*/
475	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
476	{
477	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
478	NOREF(pvUser);
479	Port &= 3;
480	if (cb != 1 \|\| Port == 3)
481	{
482	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
483	return VERR_IOM_IOPORT_UNUSED;
484	}
485
486	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
487	int ret;
488	PITChannelState *s = &pit->channels[Port];
489	if (s->status_latched)
490	{
491	s->status_latched = 0;
492	ret = s->status;
493	}
494	else if (s->count_latched)
495	{
496	switch (s->count_latched)
497	{
498	default:
499	case RW_STATE_LSB:
500	ret = s->latched_count & 0xff;
501	s->count_latched = 0;
502	break;
503	case RW_STATE_MSB:
504	ret = s->latched_count >> 8;
505	s->count_latched = 0;
506	break;
507	case RW_STATE_WORD0:
508	ret = s->latched_count & 0xff;
509	s->count_latched = RW_STATE_MSB;
510	break;
511	}
512	}
513	else
514	{
515	int count;
516	switch (s->read_state)
517	{
518	default:
519	case RW_STATE_LSB:
520	count = pit_get_count(s);
521	ret = count & 0xff;
522	break;
523	case RW_STATE_MSB:
524	count = pit_get_count(s);
525	ret = (count >> 8) & 0xff;
526	break;
527	case RW_STATE_WORD0:
528	count = pit_get_count(s);
529	ret = count & 0xff;
530	s->read_state = RW_STATE_WORD1;
531	break;
532	case RW_STATE_WORD1:
533	count = pit_get_count(s);
534	ret = (count >> 8) & 0xff;
535	s->read_state = RW_STATE_WORD0;
536	break;
537	}
538	}
539
540	*pu32 = ret;
541	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
542	return VINF_SUCCESS;
543	}
544
545
546	/**
547	* Port I/O Handler for OUT operations.
548	*
549	* @returns VBox status code.
550	*
551	* @param pDevIns The device instance.
552	* @param pvUser User argument - ignored.
553	* @param Port Port number used for the IN operation.
554	* @param u32 The value to output.
555	* @param cb The value size in bytes.
556	*/
557	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
558	{
559	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
560	NOREF(pvUser);
561	if (cb != 1)
562	return VINF_SUCCESS;
563
564	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
565	Port &= 3;
566	if (Port == 3)
567	{
568	/*
569	* Port 43h - Mode/Command Register.
570	* 7 6 5 4 3 2 1 0
571	* * * . . . . . . Select channel: 0 0 = Channel 0
572	* 0 1 = Channel 1
573	* 1 0 = Channel 2
574	* 1 1 = Read-back command (8254 only)
575	* (Illegal on 8253)
576	* (Illegal on PS/2 {JAM})
577	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
578	* 0 1 = Access mode: lobyte only
579	* 1 0 = Access mode: hibyte only
580	* 1 1 = Access mode: lobyte/hibyte
581	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
582	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
583	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
584	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
585	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
586	*/
587	unsigned channel = u32 >> 6;
588	if (channel == 3)
589	{
590	/* read-back command */
591	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
592	{
593	PITChannelState *s = &pit->channels[channel];
594	if (u32 & (2 << channel)) {
595	if (!(u32 & 0x20))
596	pit_latch_count(s);
597	if (!(u32 & 0x10) && !s->status_latched)
598	{
599	/* status latch */
600	/* XXX: add BCD and null count */
601	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
602	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
603	\| (s->rw_mode << 4)
604	\| (s->mode << 1)
605	\| s->bcd;
606	s->status_latched = 1;
607	}
608	}
609	}
610	}
611	else
612	{
613	PITChannelState *s = &pit->channels[channel];
614	unsigned access = (u32 >> 4) & 3;
615	if (access == 0)
616	pit_latch_count(s);
617	else
618	{
619	s->rw_mode = access;
620	s->read_state = access;
621	s->write_state = access;
622
623	s->mode = (u32 >> 1) & 7;
624	s->bcd = u32 & 1;
625	/* XXX: update irq timer ? */
626	}
627	}
628	}
629	else
630	{
631	#ifndef IN_RING3
632	return VINF_IOM_HC_IOPORT_WRITE;
633	#else /* IN_RING3 */
634	/*
635	* Port 40-42h - Channel Data Ports.
636	*/
637	PITChannelState *s = &pit->channels[Port];
638	switch(s->write_state)
639	{
640	default:
641	case RW_STATE_LSB:
642	pit_load_count(s, u32);
643	break;
644	case RW_STATE_MSB:
645	pit_load_count(s, u32 << 8);
646	break;
647	case RW_STATE_WORD0:
648	s->write_latch = u32;
649	s->write_state = RW_STATE_WORD1;
650	break;
651	case RW_STATE_WORD1:
652	pit_load_count(s, s->write_latch \| (u32 << 8));
653	s->write_state = RW_STATE_WORD0;
654	break;
655	}
656	#endif /* !IN_RING3 */
657	}
658	return VINF_SUCCESS;
659	}
660
661
662	/**
663	* Port I/O Handler for speaker IN operations.
664	*
665	* @returns VBox status code.
666	*
667	* @param pDevIns The device instance.
668	* @param pvUser User argument - ignored.
669	* @param Port Port number used for the IN operation.
670	* @param pu32 Where to store the result.
671	* @param cb Number of bytes read.
672	*/
673	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
674	{
675	NOREF(pvUser);
676	if (cb == 1)
677	{
678	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
679	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
680	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
681
682	/* bit 6,7 Parity error stuff. */
683	/* bit 5 - mirrors timer 2 output condition. */
684	const int fOut = pit_get_out(pThis, 2, u64Now);
685	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
686	ASSUMES ns timer freq, see assertion above. */
687	#ifndef FAKE_REFRESH_CLOCK
688	const int fRefresh = (u64Now / 15085) & 1;
689	#else
690	pThis->dummy_refresh_clock ^= 1;
691	const int fRefresh = pThis->dummy_refresh_clock;
692	#endif
693	/* bit 2,3 NMI / parity status stuff. */
694	/* bit 1 - speaker data status */
695	const int fSpeakerStatus = pThis->speaker_data_on;
696	/* bit 0 - timer 2 clock gate to speaker status. */
697	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
698
699	*pu32 = fTimer2GateStatus
700	\| (fSpeakerStatus << 1)
701	\| (fRefresh << 4)
702	\| (fOut << 5);
703	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
704	return VINF_SUCCESS;
705	}
706	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
707	return VERR_IOM_IOPORT_UNUSED;
708	}
709
710	#ifdef IN_RING3
711
712	/**
713	* Port I/O Handler for speaker OUT operations.
714	*
715	* @returns VBox status code.
716	*
717	* @param pDevIns The device instance.
718	* @param pvUser User argument - ignored.
719	* @param Port Port number used for the IN operation.
720	* @param u32 The value to output.
721	* @param cb The value size in bytes.
722	*/
723	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
724	{
725	NOREF(pvUser);
726	if (cb == 1)
727	{
728	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
729	pThis->speaker_data_on = (u32 >> 1) & 1;
730	pit_set_gate(pThis, 2, u32 & 1);
731	}
732	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
733	return VINF_SUCCESS;
734	}
735
736
737	/**
738	* @copydoc FNSSMDEVLIVEEXEC
739	*/
740	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
741	{
742	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
743	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
744	SSMR3PutU8( pSSM, pThis->channels[0].irq);
745	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
746	return VINF_SSM_DONT_CALL_AGAIN;
747	}
748
749
750	/**
751	* @copydoc FNSSMDEVSAVEEXEC
752	*/
753	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
754	{
755	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
756	unsigned i;
757
758	/* The config. */
759	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
760
761	/* The state. */
762	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
763	{
764	PITChannelState *s = &pThis->channels[i];
765	SSMR3PutU32(pSSM, s->count);
766	SSMR3PutU16(pSSM, s->latched_count);
767	SSMR3PutU8(pSSM, s->count_latched);
768	SSMR3PutU8(pSSM, s->status_latched);
769	SSMR3PutU8(pSSM, s->status);
770	SSMR3PutU8(pSSM, s->read_state);
771	SSMR3PutU8(pSSM, s->write_state);
772	SSMR3PutU8(pSSM, s->write_latch);
773	SSMR3PutU8(pSSM, s->rw_mode);
774	SSMR3PutU8(pSSM, s->mode);
775	SSMR3PutU8(pSSM, s->bcd);
776	SSMR3PutU8(pSSM, s->gate);
777	SSMR3PutU64(pSSM, s->count_load_time);
778	SSMR3PutU64(pSSM, s->u64NextTS);
779	SSMR3PutU64(pSSM, s->u64ReloadTS);
780	SSMR3PutS64(pSSM, s->next_transition_time);
781	if (s->CTX_SUFF(pTimer))
782	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
783	}
784
785	SSMR3PutS32(pSSM, pThis->speaker_data_on);
786	#ifdef FAKE_REFRESH_CLOCK
787	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
788	#else
789	SSMR3PutS32(pSSM, 0);
790	#endif
791
792	return SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
793	}
794
795
796	/**
797	* @copydoc FNSSMDEVLOADEXEC
798	*/
799	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
800	{
801	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
802	int rc;
803
804	if ( uVersion != PIT_SAVED_STATE_VERSION
805	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
806	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
807	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
808
809	/* The config. */
810	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
811	{
812	RTIOPORT IOPortBaseCfg;
813	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
814	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
815	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
816	IOPortBaseCfg, pThis->IOPortBaseCfg);
817
818	uint8_t u8Irq;
819	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
820	if (u8Irq != pThis->channels[0].irq)
821	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
822	u8Irq, pThis->channels[0].irq);
823
824	bool fSpeakerCfg;
825	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
826	if (fSpeakerCfg != pThis->fSpeakerCfg)
827	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
828	fSpeakerCfg, pThis->fSpeakerCfg);
829	}
830
831	if (uPass != SSM_PASS_FINAL)
832	return VINF_SUCCESS;
833
834	/* The state. */
835	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
836	{
837	PITChannelState *s = &pThis->channels[i];
838	SSMR3GetU32(pSSM, &s->count);
839	SSMR3GetU16(pSSM, &s->latched_count);
840	SSMR3GetU8(pSSM, &s->count_latched);
841	SSMR3GetU8(pSSM, &s->status_latched);
842	SSMR3GetU8(pSSM, &s->status);
843	SSMR3GetU8(pSSM, &s->read_state);
844	SSMR3GetU8(pSSM, &s->write_state);
845	SSMR3GetU8(pSSM, &s->write_latch);
846	SSMR3GetU8(pSSM, &s->rw_mode);
847	SSMR3GetU8(pSSM, &s->mode);
848	SSMR3GetU8(pSSM, &s->bcd);
849	SSMR3GetU8(pSSM, &s->gate);
850	SSMR3GetU64(pSSM, &s->count_load_time);
851	SSMR3GetU64(pSSM, &s->u64NextTS);
852	SSMR3GetU64(pSSM, &s->u64ReloadTS);
853	SSMR3GetS64(pSSM, &s->next_transition_time);
854	if (s->CTX_SUFF(pTimer))
855	{
856	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
857	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
858	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
859	}
860	pThis->channels[0].cRelLogEntries = 0;
861	}
862
863	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
864	#ifdef FAKE_REFRESH_CLOCK
865	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
866	#else
867	int32_t u32Dummy;
868	SSMR3GetS32(pSSM, &u32Dummy);
869	#endif
870	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
871	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
872
873	return VINF_SUCCESS;
874	}
875
876
877	/**
878	* Device timer callback function.
879	*
880	* @param pDevIns Device instance of the device which registered the timer.
881	* @param pTimer The timer handle.
882	* @param pvUser Pointer to the PIT channel state.
883	*/
884	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
885	{
886	PITChannelState s = (PITChannelState )pvUser;
887	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
888	Log(("pitTimer\n"));
889	pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer));
890	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
891	}
892
893
894	/**
895	* Info handler, device version.
896	*
897	* @param pDevIns Device instance which registered the info.
898	* @param pHlp Callback functions for doing output.
899	* @param pszArgs Argument string. Optional and specific to the handler.
900	*/
901	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
902	{
903	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
904	unsigned i;
905	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
906	{
907	const PITChannelState *pCh = &pThis->channels[i];
908
909	pHlp->pfnPrintf(pHlp,
910	"PIT (i8254) channel %d status: irq=%#x\n"
911	" count=%08x" " latched_count=%04x count_latched=%02x\n"
912	" status=%02x status_latched=%02x read_state=%02x\n"
913	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
914	" mode=%02x bcd=%02x gate=%02x\n"
915	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
916	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
917	,
918	i, pCh->irq,
919	pCh->count, pCh->latched_count, pCh->count_latched,
920	pCh->status, pCh->status_latched, pCh->read_state,
921	pCh->write_state, pCh->write_latch, pCh->rw_mode,
922	pCh->mode, pCh->bcd, pCh->gate,
923	pCh->count_load_time, pCh->next_transition_time,
924	pCh->u64ReloadTS, pCh->u64NextTS);
925	}
926	#ifdef FAKE_REFRESH_CLOCK
927	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
928	pThis->speaker_data_on, pThis->dummy_refresh_clock);
929	#else
930	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
931	#endif
932	if (pThis->fDisabledByHpet)
933	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
934	}
935
936
937	/**
938	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
939	*/
940	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
941	{
942	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
943	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
944	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
945	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
946	return NULL;
947	}
948
949
950	/**
951	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
952	*/
953	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
954	{
955	PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IHpetLegacyNotify);
956	pThis->fDisabledByHpet = fActivated;
957	}
958
959
960	/**
961	* Relocation notification.
962	*
963	* @returns VBox status.
964	* @param pDevIns The device instance data.
965	* @param offDelta The delta relative to the old address.
966	*/
967	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
968	{
969	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
970	unsigned i;
971	LogFlow(("pitRelocate: \n"));
972
973	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
974	{
975	PITChannelState *pCh = &pThis->channels[i];
976	if (pCh->pTimerR3)
977	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
978	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
979	}
980	}
981
982
983	/**
984	* Reset notification.
985	*
986	* @returns VBox status.
987	* @param pDevIns The device instance data.
988	*/
989	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
990	{
991	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
992	unsigned i;
993	LogFlow(("pitReset: \n"));
994
995	pThis->fDisabledByHpet = false;
996
997	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
998	{
999	PITChannelState *s = &pThis->channels[i];
1000
1001	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1002	s->latched_count = 0;
1003	s->count_latched = 0;
1004	s->status_latched = 0;
1005	s->status = 0;
1006	s->read_state = 0;
1007	s->write_state = 0;
1008	s->write_latch = 0;
1009	s->rw_mode = 0;
1010	s->bcd = 0;
1011	#endif
1012	s->u64NextTS = UINT64_MAX;
1013	s->cRelLogEntries = 0;
1014	s->mode = 3;
1015	s->gate = (i != 2);
1016	pit_load_count(s, 0);
1017	}
1018	}
1019
1020
1021	/**
1022	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1023	*/
1024	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1025	{
1026	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1027	int rc;
1028	uint8_t u8Irq;
1029	uint16_t u16Base;
1030	bool fSpeaker;
1031	bool fGCEnabled;
1032	bool fR0Enabled;
1033	unsigned i;
1034	Assert(iInstance == 0);
1035
1036	/*
1037	* Validate configuration.
1038	*/
1039	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1040	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1041
1042	/*
1043	* Init the data.
1044	*/
1045	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1046	if (RT_FAILURE(rc))
1047	return PDMDEV_SET_ERROR(pDevIns, rc,
1048	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1049
1050	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1051	if (RT_FAILURE(rc))
1052	return PDMDEV_SET_ERROR(pDevIns, rc,
1053	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1054
1055	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1056	if (RT_FAILURE(rc))
1057	return PDMDEV_SET_ERROR(pDevIns, rc,
1058	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1059
1060	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1061	if (RT_FAILURE(rc))
1062	return PDMDEV_SET_ERROR(pDevIns, rc,
1063	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1064
1065	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1066	if (RT_FAILURE(rc))
1067	return PDMDEV_SET_ERROR(pDevIns, rc,
1068	N_("Configuration error: failed to read R0Enabled as boolean"));
1069
1070	pThis->pDevIns = pDevIns;
1071	pThis->IOPortBaseCfg = u16Base;
1072	pThis->fSpeakerCfg = fSpeaker;
1073	pThis->channels[0].irq = u8Irq;
1074	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1075	{
1076	pThis->channels[i].pPitR3 = pThis;
1077	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1078	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1079	}
1080
1081	/*
1082	* Interfaces
1083	*/
1084	/* IBase */
1085	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1086	/* IHpetLegacyNotify */
1087	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1088
1089	/*
1090	* Create timer, register I/O Ports and save state.
1091	*/
1092	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1093	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1094	&pThis->channels[0].pTimerR3);
1095	if (RT_FAILURE(rc))
1096	return rc;
1097	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1098	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1099
1100	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1101	if (RT_FAILURE(rc))
1102	return rc;
1103	if (fGCEnabled)
1104	{
1105	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1106	if (RT_FAILURE(rc))
1107	return rc;
1108	}
1109	if (fR0Enabled)
1110	{
1111	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1112	if (RT_FAILURE(rc))
1113	return rc;
1114	}
1115
1116	if (fSpeaker)
1117	{
1118	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1119	if (RT_FAILURE(rc))
1120	return rc;
1121	if (fGCEnabled)
1122	{
1123	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1124	if (RT_FAILURE(rc))
1125	return rc;
1126	}
1127	}
1128
1129	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1130	if (RT_FAILURE(rc))
1131	return rc;
1132
1133	/*
1134	* Initialize the device state.
1135	*/
1136	pitReset(pDevIns);
1137
1138	/*
1139	* Register statistics and debug info.
1140	*/
1141	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1142	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1143
1144	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1145
1146	return VINF_SUCCESS;
1147	}
1148
1149
1150	/**
1151	* The device registration structure.
1152	*/
1153	const PDMDEVREG g_DeviceI8254 =
1154	{
1155	/* u32Version */
1156	PDM_DEVREG_VERSION,
1157	/* szName */
1158	"i8254",
1159	/* szRCMod */
1160	"VBoxDDGC.gc",
1161	/* szR0Mod */
1162	"VBoxDDR0.r0",
1163	/* pszDescription */
1164	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1165	/* fFlags */
1166	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1167	/* fClass */
1168	PDM_DEVREG_CLASS_PIT,
1169	/* cMaxInstances */
1170	1,
1171	/* cbInstance */
1172	sizeof(PITState),
1173	/* pfnConstruct */
1174	pitConstruct,
1175	/* pfnDestruct */
1176	NULL,
1177	/* pfnRelocate */
1178	pitRelocate,
1179	/* pfnIOCtl */
1180	NULL,
1181	/* pfnPowerOn */
1182	NULL,
1183	/* pfnReset */
1184	pitReset,
1185	/* pfnSuspend */
1186	NULL,
1187	/* pfnResume */
1188	NULL,
1189	/* pfnAttach */
1190	NULL,
1191	/* pfnDetach */
1192	NULL,
1193	/* pfnQueryInterface */
1194	NULL,
1195	/* pfnInitComplete */
1196	NULL,
1197	/* pfnPowerOff */
1198	NULL,
1199	/* pfnSoftReset */
1200	NULL,
1201	/* u32VersionEnd */
1202	PDM_DEVREG_VERSION
1203	};
1204
1205	#endif /* IN_RING3 */
1206	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 28346

Download in other formats: