DevPit-i8254.cpp@ 34714

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1	/* $Id: DevPit-i8254.cpp 34692 2010-12-03 12:49:36Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PIT
47	#include <VBox/pdmdev.h>
48	#include <VBox/log.h>
49	#include <VBox/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm-math.h>
52
53	#ifdef IN_RING3
54	# include <iprt/alloc.h>
55	# include <iprt/string.h>
56	# include <iprt/uuid.h>
57	#endif /* IN_RING3 */
58
59	#include "../Builtins.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The current saved state version. */
74	#define PIT_SAVED_STATE_VERSION 4
75	/** The saved state version used by VirtualBox 3.1 and earlier.
76	* This did not include disable by HPET flag. */
77	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
78	/** The saved state version used by VirtualBox 3.0 and earlier.
79	* This did not include the config part. */
80	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
81
82	/** @def FAKE_REFRESH_CLOCK
83	* Define this to flip the 15usec refresh bit on every read.
84	* If not defined, it will be flipped correctly. */
85	/* #define FAKE_REFRESH_CLOCK */
86	#ifdef DOXYGEN_RUNNING
87	# define FAKE_REFRESH_CLOCK
88	#endif
89
90
91	/*******************************************************************************
92	* Structures and Typedefs *
93	*******************************************************************************/
94	typedef struct PITChannelState
95	{
96	/** Pointer to the instance data - R3 Ptr. */
97	R3PTRTYPE(struct PITState *) pPitR3;
98	/** The timer - R3 Ptr. */
99	PTMTIMERR3 pTimerR3;
100	/** Pointer to the instance data - R0 Ptr. */
101	R0PTRTYPE(struct PITState *) pPitR0;
102	/** The timer - R0 Ptr. */
103	PTMTIMERR0 pTimerR0;
104	/** Pointer to the instance data - RC Ptr. */
105	RCPTRTYPE(struct PITState *) pPitRC;
106	/** The timer - RC Ptr. */
107	PTMTIMERRC pTimerRC;
108	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
109	uint64_t u64ReloadTS;
110	/** The actual time of the next tick.
111	* As apposed to the next_transition_time which contains the correct time of the next tick. */
112	uint64_t u64NextTS;
113
114	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
115	uint64_t count_load_time;
116	/* irq handling */
117	int64_t next_transition_time;
118	int32_t irq;
119	/** Number of release log entries. Used to prevent flooding. */
120	uint32_t cRelLogEntries;
121
122	uint32_t count; /* can be 65536 */
123	uint16_t latched_count;
124	uint8_t count_latched;
125	uint8_t status_latched;
126
127	uint8_t status;
128	uint8_t read_state;
129	uint8_t write_state;
130	uint8_t write_latch;
131
132	uint8_t rw_mode;
133	uint8_t mode;
134	uint8_t bcd; /* not supported */
135	uint8_t gate; /* timer start */
136
137	} PITChannelState;
138
139	typedef struct PITState
140	{
141	PITChannelState channels[3];
142	/** Speaker data. */
143	int32_t speaker_data_on;
144	#ifdef FAKE_REFRESH_CLOCK
145	/** Speaker dummy. */
146	int32_t dummy_refresh_clock;
147	#else
148	uint32_t Alignment1;
149	#endif
150	/** Config: I/O port base. */
151	RTIOPORT IOPortBaseCfg;
152	/** Config: Speaker enabled. */
153	bool fSpeakerCfg;
154	bool fDisabledByHpet;
155	bool afAlignment0[HC_ARCH_BITS == 32 ? 4 : 4];
156	/** PIT port interface. */
157	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
158	/** Pointer to the device instance. */
159	PPDMDEVINSR3 pDevIns;
160	/** Number of IRQs that's been raised. */
161	STAMCOUNTER StatPITIrq;
162	/** Profiling the timer callback handler. */
163	STAMPROFILEADV StatPITHandler;
164	} PITState;
165
166
167	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
168	/*******************************************************************************
169	* Internal Functions *
170	*******************************************************************************/
171	RT_C_DECLS_BEGIN
172	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
173	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
174	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
175	#ifdef IN_RING3
176	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
177	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now);
178	#endif
179	RT_C_DECLS_END
180
181
182
183
184	static int pit_get_count(PITChannelState *s)
185	{
186	uint64_t d;
187	int counter;
188	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
189
190	if (s->mode == 2)
191	{
192	if (s->u64NextTS == UINT64_MAX)
193	{
194	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
195	return s->count - (d % s->count); /** @todo check this value. */
196	}
197	uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
198	if (!Interval)
199	return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
200	d = TMTimerGet(pTimer);
201	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
202	if (d >= s->count)
203	return 1;
204	return s->count - d;
205	}
206	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
207	switch(s->mode) {
208	case 0:
209	case 1:
210	case 4:
211	case 5:
212	counter = (s->count - d) & 0xffff;
213	break;
214	case 3:
215	/* XXX: may be incorrect for odd counts */
216	counter = s->count - ((2 * d) % s->count);
217	break;
218	default:
219	counter = s->count - (d % s->count);
220	break;
221	}
222	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
223	return counter;
224	}
225
226	/* get pit output bit */
227	static int pit_get_out1(PITChannelState *s, int64_t current_time)
228	{
229	uint64_t d;
230	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
231	int out;
232
233	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
234	switch(s->mode) {
235	default:
236	case 0:
237	out = (d >= s->count);
238	break;
239	case 1:
240	out = (d < s->count);
241	break;
242	case 2:
243	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
244	if ((d % s->count) == 0 && d != 0)
245	out = 1;
246	else
247	out = 0;
248	break;
249	case 3:
250	out = (d % s->count) < ((s->count + 1) >> 1);
251	break;
252	case 4:
253	case 5:
254	out = (d == s->count);
255	break;
256	}
257	return out;
258	}
259
260
261	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
262	{
263	PITChannelState *s = &pit->channels[channel];
264	return pit_get_out1(s, current_time);
265	}
266
267
268	static int pit_get_gate(PITState *pit, int channel)
269	{
270	PITChannelState *s = &pit->channels[channel];
271	return s->gate;
272	}
273
274
275	/* if already latched, do not latch again */
276	static void pit_latch_count(PITChannelState *s)
277	{
278	if (!s->count_latched) {
279	s->latched_count = pit_get_count(s);
280	s->count_latched = s->rw_mode;
281	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
282	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
283	}
284	}
285
286	#ifdef IN_RING3
287
288	/* val must be 0 or 1 */
289	static void pit_set_gate(PITState *pit, int channel, int val)
290	{
291	PITChannelState *s = &pit->channels[channel];
292	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
293	Assert((val & 1) == val);
294
295	switch(s->mode) {
296	default:
297	case 0:
298	case 4:
299	/* XXX: just disable/enable counting */
300	break;
301	case 1:
302	case 5:
303	if (s->gate < val) {
304	/* restart counting on rising edge */
305	Log(("pit_set_gate: restarting mode %d\n", s->mode));
306	s->count_load_time = TMTimerGet(pTimer);
307	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
308	}
309	break;
310	case 2:
311	case 3:
312	if (s->gate < val) {
313	/* restart counting on rising edge */
314	Log(("pit_set_gate: restarting mode %d\n", s->mode));
315	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
316	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
317	}
318	/* XXX: disable/enable counting */
319	break;
320	}
321	s->gate = val;
322	}
323
324	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
325	{
326	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
327	if (val == 0)
328	val = 0x10000;
329	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
330	s->count = val;
331	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
332
333	/* log the new rate (ch 0 only). */
334	if (s->pTimerR3 /* ch 0 */)
335	{
336	if (s->cRelLogEntries++ < 32)
337	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
338	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
339	else
340	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
341	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
342	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
343	}
344	else
345	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
346	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100,
347	s - &s->CTX_SUFF(pPit)->channels[0]));
348	}
349
350	/* return -1 if no transition will occur. */
351	static int64_t pit_get_next_transition_time(PITChannelState *s,
352	uint64_t current_time)
353	{
354	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
355	uint64_t d, next_time, base;
356	uint32_t period2;
357
358	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
359	switch(s->mode) {
360	default:
361	case 0:
362	case 1:
363	if (d < s->count)
364	next_time = s->count;
365	else
366	return -1;
367	break;
368	/*
369	* Mode 2: The period is count + 1 PIT ticks.
370	* When the counter reaches 1 we set the output low (for channel 0 that
371	* means lowering IRQ0). On the next tick, where we should be decrementing
372	* from 1 to 0, the count is loaded and the output goes high (channel 0
373	* means raising IRQ0 again and triggering timer interrupt).
374	*
375	* In VBox we simplify the tick cycle between 1 and 0 and immediately trigger
376	* the interrupt. We also don't set it until we reach 0, which is a tick late
377	* - will try to fix that later some day.
378	*/
379	case 2:
380	base = (d / s->count) * s->count;
381	#ifndef VBOX /* see above */
382	if ((d - base) == 0 && d != 0)
383	next_time = base + s->count;
384	else
385	#endif
386	next_time = base + s->count + 1;
387	break;
388	case 3:
389	base = (d / s->count) * s->count;
390	period2 = ((s->count + 1) >> 1);
391	if ((d - base) < period2)
392	next_time = base + period2;
393	else
394	next_time = base + s->count;
395	break;
396	case 4:
397	case 5:
398	if (d < s->count)
399	next_time = s->count;
400	else if (d == s->count)
401	next_time = s->count + 1;
402	else
403	return -1;
404	break;
405	}
406	/* convert to timer units */
407	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
408	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
409	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
410	/* fix potential rounding problems */
411	/* XXX: better solution: use a clock at PIT_FREQ Hz */
412	if (next_time <= current_time)
413	next_time = current_time + 1;
414	return next_time;
415	}
416
417	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now)
418	{
419	int64_t expire_time;
420	int irq_level;
421	PPDMDEVINS pDevIns;
422	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
423
424	if (!s->CTX_SUFF(pTimer))
425	return;
426	expire_time = pit_get_next_transition_time(s, current_time);
427	irq_level = pit_get_out1(s, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
428
429	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
430	* but do not modify other aspects of device operation.
431	*/
432	if (!s->pPitR3->fDisabledByHpet)
433	{
434	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
435
436	if (s->mode == 2)
437	{
438	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for years). */
439	PDMDevHlpISASetIrq(pDevIns, s->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
440	} else
441	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
442	}
443
444	if (irq_level)
445	{
446	s->u64ReloadTS = now;
447	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
448	}
449
450	if (expire_time != -1)
451	{
452	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
453	s->u64NextTS = expire_time;
454	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
455	}
456	else
457	{
458	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
459	TMTimerStop(s->CTX_SUFF(pTimer));
460	s->u64NextTS = UINT64_MAX;
461	}
462	s->next_transition_time = expire_time;
463	}
464
465	#endif /* IN_RING3 */
466
467
468	/**
469	* Port I/O Handler for IN operations.
470	*
471	* @returns VBox status code.
472	*
473	* @param pDevIns The device instance.
474	* @param pvUser User argument - ignored.
475	* @param Port Port number used for the IN operation.
476	* @param pu32 Where to store the result.
477	* @param cb Number of bytes read.
478	*/
479	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
480	{
481	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
482	NOREF(pvUser);
483	Port &= 3;
484	if (cb != 1 \|\| Port == 3)
485	{
486	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
487	return VERR_IOM_IOPORT_UNUSED;
488	}
489
490	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
491	int ret;
492	PITChannelState *s = &pit->channels[Port];
493	if (s->status_latched)
494	{
495	s->status_latched = 0;
496	ret = s->status;
497	}
498	else if (s->count_latched)
499	{
500	switch (s->count_latched)
501	{
502	default:
503	case RW_STATE_LSB:
504	ret = s->latched_count & 0xff;
505	s->count_latched = 0;
506	break;
507	case RW_STATE_MSB:
508	ret = s->latched_count >> 8;
509	s->count_latched = 0;
510	break;
511	case RW_STATE_WORD0:
512	ret = s->latched_count & 0xff;
513	s->count_latched = RW_STATE_MSB;
514	break;
515	}
516	}
517	else
518	{
519	int count;
520	switch (s->read_state)
521	{
522	default:
523	case RW_STATE_LSB:
524	count = pit_get_count(s);
525	ret = count & 0xff;
526	break;
527	case RW_STATE_MSB:
528	count = pit_get_count(s);
529	ret = (count >> 8) & 0xff;
530	break;
531	case RW_STATE_WORD0:
532	count = pit_get_count(s);
533	ret = count & 0xff;
534	s->read_state = RW_STATE_WORD1;
535	break;
536	case RW_STATE_WORD1:
537	count = pit_get_count(s);
538	ret = (count >> 8) & 0xff;
539	s->read_state = RW_STATE_WORD0;
540	break;
541	}
542	}
543
544	*pu32 = ret;
545	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
546	return VINF_SUCCESS;
547	}
548
549
550	/**
551	* Port I/O Handler for OUT operations.
552	*
553	* @returns VBox status code.
554	*
555	* @param pDevIns The device instance.
556	* @param pvUser User argument - ignored.
557	* @param Port Port number used for the IN operation.
558	* @param u32 The value to output.
559	* @param cb The value size in bytes.
560	*/
561	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
562	{
563	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
564	NOREF(pvUser);
565	if (cb != 1)
566	return VINF_SUCCESS;
567
568	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
569	Port &= 3;
570	if (Port == 3)
571	{
572	/*
573	* Port 43h - Mode/Command Register.
574	* 7 6 5 4 3 2 1 0
575	* * * . . . . . . Select channel: 0 0 = Channel 0
576	* 0 1 = Channel 1
577	* 1 0 = Channel 2
578	* 1 1 = Read-back command (8254 only)
579	* (Illegal on 8253)
580	* (Illegal on PS/2 {JAM})
581	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
582	* 0 1 = Access mode: lobyte only
583	* 1 0 = Access mode: hibyte only
584	* 1 1 = Access mode: lobyte/hibyte
585	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
586	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
587	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
588	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
589	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
590	*/
591	unsigned channel = u32 >> 6;
592	if (channel == 3)
593	{
594	/* read-back command */
595	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
596	{
597	PITChannelState *s = &pit->channels[channel];
598	if (u32 & (2 << channel)) {
599	if (!(u32 & 0x20))
600	pit_latch_count(s);
601	if (!(u32 & 0x10) && !s->status_latched)
602	{
603	/* status latch */
604	/* XXX: add BCD and null count */
605	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
606	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
607	\| (s->rw_mode << 4)
608	\| (s->mode << 1)
609	\| s->bcd;
610	s->status_latched = 1;
611	}
612	}
613	}
614	}
615	else
616	{
617	PITChannelState *s = &pit->channels[channel];
618	unsigned access = (u32 >> 4) & 3;
619	if (access == 0)
620	pit_latch_count(s);
621	else
622	{
623	s->rw_mode = access;
624	s->read_state = access;
625	s->write_state = access;
626
627	s->mode = (u32 >> 1) & 7;
628	s->bcd = u32 & 1;
629	/* XXX: update irq timer ? */
630	}
631	}
632	}
633	else
634	{
635	#ifndef IN_RING3
636	return VINF_IOM_HC_IOPORT_WRITE;
637	#else /* IN_RING3 */
638	/*
639	* Port 40-42h - Channel Data Ports.
640	*/
641	PITChannelState *s = &pit->channels[Port];
642	switch(s->write_state)
643	{
644	default:
645	case RW_STATE_LSB:
646	pit_load_count(s, u32);
647	break;
648	case RW_STATE_MSB:
649	pit_load_count(s, u32 << 8);
650	break;
651	case RW_STATE_WORD0:
652	s->write_latch = u32;
653	s->write_state = RW_STATE_WORD1;
654	break;
655	case RW_STATE_WORD1:
656	pit_load_count(s, s->write_latch \| (u32 << 8));
657	s->write_state = RW_STATE_WORD0;
658	break;
659	}
660	#endif /* !IN_RING3 */
661	}
662	return VINF_SUCCESS;
663	}
664
665
666	/**
667	* Port I/O Handler for speaker IN operations.
668	*
669	* @returns VBox status code.
670	*
671	* @param pDevIns The device instance.
672	* @param pvUser User argument - ignored.
673	* @param Port Port number used for the IN operation.
674	* @param pu32 Where to store the result.
675	* @param cb Number of bytes read.
676	*/
677	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
678	{
679	NOREF(pvUser);
680	if (cb == 1)
681	{
682	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
683	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
684	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
685
686	/* bit 6,7 Parity error stuff. */
687	/* bit 5 - mirrors timer 2 output condition. */
688	const int fOut = pit_get_out(pThis, 2, u64Now);
689	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
690	ASSUMES ns timer freq, see assertion above. */
691	#ifndef FAKE_REFRESH_CLOCK
692	const int fRefresh = (u64Now / 15085) & 1;
693	#else
694	pThis->dummy_refresh_clock ^= 1;
695	const int fRefresh = pThis->dummy_refresh_clock;
696	#endif
697	/* bit 2,3 NMI / parity status stuff. */
698	/* bit 1 - speaker data status */
699	const int fSpeakerStatus = pThis->speaker_data_on;
700	/* bit 0 - timer 2 clock gate to speaker status. */
701	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
702
703	*pu32 = fTimer2GateStatus
704	\| (fSpeakerStatus << 1)
705	\| (fRefresh << 4)
706	\| (fOut << 5);
707	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
708	return VINF_SUCCESS;
709	}
710	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
711	return VERR_IOM_IOPORT_UNUSED;
712	}
713
714	#ifdef IN_RING3
715
716	/**
717	* Port I/O Handler for speaker OUT operations.
718	*
719	* @returns VBox status code.
720	*
721	* @param pDevIns The device instance.
722	* @param pvUser User argument - ignored.
723	* @param Port Port number used for the IN operation.
724	* @param u32 The value to output.
725	* @param cb The value size in bytes.
726	*/
727	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
728	{
729	NOREF(pvUser);
730	if (cb == 1)
731	{
732	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
733	pThis->speaker_data_on = (u32 >> 1) & 1;
734	pit_set_gate(pThis, 2, u32 & 1);
735	}
736	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
737	return VINF_SUCCESS;
738	}
739
740
741	/**
742	* @copydoc FNSSMDEVLIVEEXEC
743	*/
744	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
745	{
746	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
747	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
748	SSMR3PutU8( pSSM, pThis->channels[0].irq);
749	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
750	return VINF_SSM_DONT_CALL_AGAIN;
751	}
752
753
754	/**
755	* @copydoc FNSSMDEVSAVEEXEC
756	*/
757	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
758	{
759	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
760	unsigned i;
761
762	/* The config. */
763	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
764
765	/* The state. */
766	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
767	{
768	PITChannelState *s = &pThis->channels[i];
769	SSMR3PutU32(pSSM, s->count);
770	SSMR3PutU16(pSSM, s->latched_count);
771	SSMR3PutU8(pSSM, s->count_latched);
772	SSMR3PutU8(pSSM, s->status_latched);
773	SSMR3PutU8(pSSM, s->status);
774	SSMR3PutU8(pSSM, s->read_state);
775	SSMR3PutU8(pSSM, s->write_state);
776	SSMR3PutU8(pSSM, s->write_latch);
777	SSMR3PutU8(pSSM, s->rw_mode);
778	SSMR3PutU8(pSSM, s->mode);
779	SSMR3PutU8(pSSM, s->bcd);
780	SSMR3PutU8(pSSM, s->gate);
781	SSMR3PutU64(pSSM, s->count_load_time);
782	SSMR3PutU64(pSSM, s->u64NextTS);
783	SSMR3PutU64(pSSM, s->u64ReloadTS);
784	SSMR3PutS64(pSSM, s->next_transition_time);
785	if (s->CTX_SUFF(pTimer))
786	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
787	}
788
789	SSMR3PutS32(pSSM, pThis->speaker_data_on);
790	#ifdef FAKE_REFRESH_CLOCK
791	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
792	#else
793	SSMR3PutS32(pSSM, 0);
794	#endif
795
796	return SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
797	}
798
799
800	/**
801	* @copydoc FNSSMDEVLOADEXEC
802	*/
803	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
804	{
805	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
806	int rc;
807
808	if ( uVersion != PIT_SAVED_STATE_VERSION
809	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
810	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
811	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
812
813	/* The config. */
814	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
815	{
816	RTIOPORT IOPortBaseCfg;
817	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
818	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
819	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
820	IOPortBaseCfg, pThis->IOPortBaseCfg);
821
822	uint8_t u8Irq;
823	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
824	if (u8Irq != pThis->channels[0].irq)
825	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
826	u8Irq, pThis->channels[0].irq);
827
828	bool fSpeakerCfg;
829	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
830	if (fSpeakerCfg != pThis->fSpeakerCfg)
831	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
832	fSpeakerCfg, pThis->fSpeakerCfg);
833	}
834
835	if (uPass != SSM_PASS_FINAL)
836	return VINF_SUCCESS;
837
838	/* The state. */
839	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
840	{
841	PITChannelState *s = &pThis->channels[i];
842	SSMR3GetU32(pSSM, &s->count);
843	SSMR3GetU16(pSSM, &s->latched_count);
844	SSMR3GetU8(pSSM, &s->count_latched);
845	SSMR3GetU8(pSSM, &s->status_latched);
846	SSMR3GetU8(pSSM, &s->status);
847	SSMR3GetU8(pSSM, &s->read_state);
848	SSMR3GetU8(pSSM, &s->write_state);
849	SSMR3GetU8(pSSM, &s->write_latch);
850	SSMR3GetU8(pSSM, &s->rw_mode);
851	SSMR3GetU8(pSSM, &s->mode);
852	SSMR3GetU8(pSSM, &s->bcd);
853	SSMR3GetU8(pSSM, &s->gate);
854	SSMR3GetU64(pSSM, &s->count_load_time);
855	SSMR3GetU64(pSSM, &s->u64NextTS);
856	SSMR3GetU64(pSSM, &s->u64ReloadTS);
857	SSMR3GetS64(pSSM, &s->next_transition_time);
858	if (s->CTX_SUFF(pTimer))
859	{
860	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
861	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
862	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
863	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
864	}
865	pThis->channels[i].cRelLogEntries = 0;
866	}
867
868	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
869	#ifdef FAKE_REFRESH_CLOCK
870	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
871	#else
872	int32_t u32Dummy;
873	SSMR3GetS32(pSSM, &u32Dummy);
874	#endif
875	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
876	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
877
878	return VINF_SUCCESS;
879	}
880
881
882	/**
883	* Device timer callback function.
884	*
885	* @param pDevIns Device instance of the device which registered the timer.
886	* @param pTimer The timer handle.
887	* @param pvUser Pointer to the PIT channel state.
888	*/
889	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
890	{
891	PITChannelState s = (PITChannelState )pvUser;
892	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
893	Log(("pitTimer\n"));
894	pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer));
895	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
896	}
897
898
899	/**
900	* Info handler, device version.
901	*
902	* @param pDevIns Device instance which registered the info.
903	* @param pHlp Callback functions for doing output.
904	* @param pszArgs Argument string. Optional and specific to the handler.
905	*/
906	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
907	{
908	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
909	unsigned i;
910	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
911	{
912	const PITChannelState *pCh = &pThis->channels[i];
913
914	pHlp->pfnPrintf(pHlp,
915	"PIT (i8254) channel %d status: irq=%#x\n"
916	" count=%08x" " latched_count=%04x count_latched=%02x\n"
917	" status=%02x status_latched=%02x read_state=%02x\n"
918	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
919	" mode=%02x bcd=%02x gate=%02x\n"
920	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
921	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
922	,
923	i, pCh->irq,
924	pCh->count, pCh->latched_count, pCh->count_latched,
925	pCh->status, pCh->status_latched, pCh->read_state,
926	pCh->write_state, pCh->write_latch, pCh->rw_mode,
927	pCh->mode, pCh->bcd, pCh->gate,
928	pCh->count_load_time, pCh->next_transition_time,
929	pCh->u64ReloadTS, pCh->u64NextTS);
930	}
931	#ifdef FAKE_REFRESH_CLOCK
932	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
933	pThis->speaker_data_on, pThis->dummy_refresh_clock);
934	#else
935	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
936	#endif
937	if (pThis->fDisabledByHpet)
938	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
939	}
940
941
942	/**
943	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
944	*/
945	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
946	{
947	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
948	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
949	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
950	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
951	return NULL;
952	}
953
954
955	/**
956	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
957	*/
958	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
959	{
960	PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IHpetLegacyNotify);
961	pThis->fDisabledByHpet = fActivated;
962	}
963
964
965	/**
966	* Relocation notification.
967	*
968	* @returns VBox status.
969	* @param pDevIns The device instance data.
970	* @param offDelta The delta relative to the old address.
971	*/
972	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
973	{
974	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
975	unsigned i;
976	LogFlow(("pitRelocate: \n"));
977
978	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
979	{
980	PITChannelState *pCh = &pThis->channels[i];
981	if (pCh->pTimerR3)
982	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
983	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
984	}
985	}
986
987
988	/**
989	* Reset notification.
990	*
991	* @returns VBox status.
992	* @param pDevIns The device instance data.
993	*/
994	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
995	{
996	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
997	unsigned i;
998	LogFlow(("pitReset: \n"));
999
1000	pThis->fDisabledByHpet = false;
1001
1002	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1003	{
1004	PITChannelState *s = &pThis->channels[i];
1005
1006	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1007	s->latched_count = 0;
1008	s->count_latched = 0;
1009	s->status_latched = 0;
1010	s->status = 0;
1011	s->read_state = 0;
1012	s->write_state = 0;
1013	s->write_latch = 0;
1014	s->rw_mode = 0;
1015	s->bcd = 0;
1016	#endif
1017	s->u64NextTS = UINT64_MAX;
1018	s->cRelLogEntries = 0;
1019	s->mode = 3;
1020	s->gate = (i != 2);
1021	pit_load_count(s, 0);
1022	}
1023	}
1024
1025
1026	/**
1027	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1028	*/
1029	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1030	{
1031	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1032	int rc;
1033	uint8_t u8Irq;
1034	uint16_t u16Base;
1035	bool fSpeaker;
1036	bool fGCEnabled;
1037	bool fR0Enabled;
1038	unsigned i;
1039	Assert(iInstance == 0);
1040
1041	/*
1042	* Validate configuration.
1043	*/
1044	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1045	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1046
1047	/*
1048	* Init the data.
1049	*/
1050	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1051	if (RT_FAILURE(rc))
1052	return PDMDEV_SET_ERROR(pDevIns, rc,
1053	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1054
1055	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1056	if (RT_FAILURE(rc))
1057	return PDMDEV_SET_ERROR(pDevIns, rc,
1058	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1059
1060	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1061	if (RT_FAILURE(rc))
1062	return PDMDEV_SET_ERROR(pDevIns, rc,
1063	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1064
1065	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1066	if (RT_FAILURE(rc))
1067	return PDMDEV_SET_ERROR(pDevIns, rc,
1068	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1069
1070	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1071	if (RT_FAILURE(rc))
1072	return PDMDEV_SET_ERROR(pDevIns, rc,
1073	N_("Configuration error: failed to read R0Enabled as boolean"));
1074
1075	pThis->pDevIns = pDevIns;
1076	pThis->IOPortBaseCfg = u16Base;
1077	pThis->fSpeakerCfg = fSpeaker;
1078	pThis->channels[0].irq = u8Irq;
1079	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1080	{
1081	pThis->channels[i].pPitR3 = pThis;
1082	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1083	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1084	}
1085
1086	/*
1087	* Interfaces
1088	*/
1089	/* IBase */
1090	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1091	/* IHpetLegacyNotify */
1092	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1093
1094	/*
1095	* Create timer, register I/O Ports and save state.
1096	*/
1097	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1098	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1099	&pThis->channels[0].pTimerR3);
1100	if (RT_FAILURE(rc))
1101	return rc;
1102	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1103	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1104
1105	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1106	if (RT_FAILURE(rc))
1107	return rc;
1108	if (fGCEnabled)
1109	{
1110	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1111	if (RT_FAILURE(rc))
1112	return rc;
1113	}
1114	if (fR0Enabled)
1115	{
1116	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1117	if (RT_FAILURE(rc))
1118	return rc;
1119	}
1120
1121	if (fSpeaker)
1122	{
1123	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1124	if (RT_FAILURE(rc))
1125	return rc;
1126	if (fGCEnabled)
1127	{
1128	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1129	if (RT_FAILURE(rc))
1130	return rc;
1131	}
1132	}
1133
1134	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1135	if (RT_FAILURE(rc))
1136	return rc;
1137
1138	/*
1139	* Initialize the device state.
1140	*/
1141	pitReset(pDevIns);
1142
1143	/*
1144	* Register statistics and debug info.
1145	*/
1146	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1147	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1148
1149	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1150
1151	return VINF_SUCCESS;
1152	}
1153
1154
1155	/**
1156	* The device registration structure.
1157	*/
1158	const PDMDEVREG g_DeviceI8254 =
1159	{
1160	/* u32Version */
1161	PDM_DEVREG_VERSION,
1162	/* szName */
1163	"i8254",
1164	/* szRCMod */
1165	"VBoxDDGC.gc",
1166	/* szR0Mod */
1167	"VBoxDDR0.r0",
1168	/* pszDescription */
1169	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1170	/* fFlags */
1171	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1172	/* fClass */
1173	PDM_DEVREG_CLASS_PIT,
1174	/* cMaxInstances */
1175	1,
1176	/* cbInstance */
1177	sizeof(PITState),
1178	/* pfnConstruct */
1179	pitConstruct,
1180	/* pfnDestruct */
1181	NULL,
1182	/* pfnRelocate */
1183	pitRelocate,
1184	/* pfnIOCtl */
1185	NULL,
1186	/* pfnPowerOn */
1187	NULL,
1188	/* pfnReset */
1189	pitReset,
1190	/* pfnSuspend */
1191	NULL,
1192	/* pfnResume */
1193	NULL,
1194	/* pfnAttach */
1195	NULL,
1196	/* pfnDetach */
1197	NULL,
1198	/* pfnQueryInterface */
1199	NULL,
1200	/* pfnInitComplete */
1201	NULL,
1202	/* pfnPowerOff */
1203	NULL,
1204	/* pfnSoftReset */
1205	NULL,
1206	/* u32VersionEnd */
1207	PDM_DEVREG_VERSION
1208	};
1209
1210	#endif /* IN_RING3 */
1211	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 34714

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