DevPit-i8254.cpp@ 35351

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1	/* $Id: DevPit-i8254.cpp 35346 2010-12-27 16:13:13Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PIT
47	#include <VBox/vmm/pdmdev.h>
48	#include <VBox/log.h>
49	#include <VBox/vmm/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm-math.h>
52
53	#ifdef IN_RING3
54	# include <iprt/alloc.h>
55	# include <iprt/string.h>
56	# include <iprt/uuid.h>
57	#endif /* IN_RING3 */
58
59	#include "../Builtins.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The current saved state version. */
74	#define PIT_SAVED_STATE_VERSION 4
75	/** The saved state version used by VirtualBox 3.1 and earlier.
76	* This did not include disable by HPET flag. */
77	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
78	/** The saved state version used by VirtualBox 3.0 and earlier.
79	* This did not include the config part. */
80	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
81
82	/** @def FAKE_REFRESH_CLOCK
83	* Define this to flip the 15usec refresh bit on every read.
84	* If not defined, it will be flipped correctly. */
85	/* #define FAKE_REFRESH_CLOCK */
86	#ifdef DOXYGEN_RUNNING
87	# define FAKE_REFRESH_CLOCK
88	#endif
89
90	/** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
91	#define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
92
93	/*******************************************************************************
94	* Structures and Typedefs *
95	*******************************************************************************/
96	typedef struct PITChannelState
97	{
98	/** Pointer to the instance data - R3 Ptr. */
99	R3PTRTYPE(struct PITState *) pPitR3;
100	/** The timer - R3 Ptr. */
101	PTMTIMERR3 pTimerR3;
102	/** Pointer to the instance data - R0 Ptr. */
103	R0PTRTYPE(struct PITState *) pPitR0;
104	/** The timer - R0 Ptr. */
105	PTMTIMERR0 pTimerR0;
106	/** Pointer to the instance data - RC Ptr. */
107	RCPTRTYPE(struct PITState *) pPitRC;
108	/** The timer - RC Ptr. */
109	PTMTIMERRC pTimerRC;
110	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
111	uint64_t u64ReloadTS;
112	/** The actual time of the next tick.
113	* As apposed to the next_transition_time which contains the correct time of the next tick. */
114	uint64_t u64NextTS;
115
116	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
117	uint64_t count_load_time;
118	/* irq handling */
119	int64_t next_transition_time;
120	int32_t irq;
121	/** Number of release log entries. Used to prevent flooding. */
122	uint32_t cRelLogEntries;
123
124	uint32_t count; /* can be 65536 */
125	uint16_t latched_count;
126	uint8_t count_latched;
127	uint8_t status_latched;
128
129	uint8_t status;
130	uint8_t read_state;
131	uint8_t write_state;
132	uint8_t write_latch;
133
134	uint8_t rw_mode;
135	uint8_t mode;
136	uint8_t bcd; /* not supported */
137	uint8_t gate; /* timer start */
138
139	} PITChannelState;
140
141	typedef struct PITState
142	{
143	PITChannelState channels[3];
144	/** Speaker data. */
145	int32_t speaker_data_on;
146	#ifdef FAKE_REFRESH_CLOCK
147	/** Speaker dummy. */
148	int32_t dummy_refresh_clock;
149	#else
150	uint32_t Alignment1;
151	#endif
152	/** Config: I/O port base. */
153	RTIOPORT IOPortBaseCfg;
154	/** Config: Speaker enabled. */
155	bool fSpeakerCfg;
156	bool fDisabledByHpet;
157	bool afAlignment0[HC_ARCH_BITS == 32 ? 4 : 4];
158	/** PIT port interface. */
159	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
160	/** Pointer to the device instance. */
161	PPDMDEVINSR3 pDevIns;
162	/** Number of IRQs that's been raised. */
163	STAMCOUNTER StatPITIrq;
164	/** Profiling the timer callback handler. */
165	STAMPROFILEADV StatPITHandler;
166	} PITState;
167
168
169	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
170	/*******************************************************************************
171	* Internal Functions *
172	*******************************************************************************/
173	RT_C_DECLS_BEGIN
174	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
175	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
176	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
177	#ifdef IN_RING3
178	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
179	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now);
180	#endif
181	RT_C_DECLS_END
182
183
184
185
186	static int pit_get_count(PITChannelState *s)
187	{
188	uint64_t d;
189	int counter;
190	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
191
192	if (EFFECTIVE_MODE(s->mode) == 2)
193	{
194	if (s->u64NextTS == UINT64_MAX)
195	{
196	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
197	return s->count - (d % s->count); /** @todo check this value. */
198	}
199	uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
200	if (!Interval)
201	return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
202	d = TMTimerGet(pTimer);
203	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
204	if (d >= s->count)
205	return 1;
206	return s->count - d;
207	}
208	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
209	switch(EFFECTIVE_MODE(s->mode)) {
210	case 0:
211	case 1:
212	case 4:
213	case 5:
214	counter = (s->count - d) & 0xffff;
215	break;
216	case 3:
217	/* XXX: may be incorrect for odd counts */
218	counter = s->count - ((2 * d) % s->count);
219	break;
220	default:
221	counter = s->count - (d % s->count);
222	break;
223	}
224	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
225	return counter;
226	}
227
228	/* get pit output bit */
229	static int pit_get_out1(PITChannelState *s, int64_t current_time)
230	{
231	uint64_t d;
232	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
233	int out;
234
235	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
236	switch(EFFECTIVE_MODE(s->mode)) {
237	default:
238	case 0:
239	out = (d >= s->count);
240	break;
241	case 1:
242	out = (d < s->count);
243	break;
244	case 2:
245	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
246	if ((d % s->count) == 0 && d != 0)
247	out = 1;
248	else
249	out = 0;
250	break;
251	case 3:
252	out = (d % s->count) < ((s->count + 1) >> 1);
253	break;
254	case 4:
255	case 5:
256	out = (d == s->count);
257	break;
258	}
259	return out;
260	}
261
262
263	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
264	{
265	PITChannelState *s = &pit->channels[channel];
266	return pit_get_out1(s, current_time);
267	}
268
269
270	static int pit_get_gate(PITState *pit, int channel)
271	{
272	PITChannelState *s = &pit->channels[channel];
273	return s->gate;
274	}
275
276
277	/* if already latched, do not latch again */
278	static void pit_latch_count(PITChannelState *s)
279	{
280	if (!s->count_latched) {
281	s->latched_count = pit_get_count(s);
282	s->count_latched = s->rw_mode;
283	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
284	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
285	}
286	}
287
288	#ifdef IN_RING3
289
290	/* val must be 0 or 1 */
291	static void pit_set_gate(PITState *pit, int channel, int val)
292	{
293	PITChannelState *s = &pit->channels[channel];
294	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
295	Assert((val & 1) == val);
296
297	switch(EFFECTIVE_MODE(s->mode)) {
298	default:
299	case 0:
300	case 4:
301	/* XXX: just disable/enable counting */
302	break;
303	case 1:
304	case 5:
305	if (s->gate < val) {
306	/* restart counting on rising edge */
307	Log(("pit_set_gate: restarting mode %d\n", s->mode));
308	s->count_load_time = TMTimerGet(pTimer);
309	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
310	}
311	break;
312	case 2:
313	case 3:
314	if (s->gate < val) {
315	/* restart counting on rising edge */
316	Log(("pit_set_gate: restarting mode %d\n", s->mode));
317	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
318	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
319	}
320	/* XXX: disable/enable counting */
321	break;
322	}
323	s->gate = val;
324	}
325
326	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
327	{
328	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
329	if (val == 0)
330	val = 0x10000;
331	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
332	s->count = val;
333	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
334
335	/* log the new rate (ch 0 only). */
336	if (s->pTimerR3 /* ch 0 */)
337	{
338	if (s->cRelLogEntries++ < 32)
339	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
340	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
341	else
342	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
343	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
344	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
345	}
346	else
347	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
348	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100,
349	s - &s->CTX_SUFF(pPit)->channels[0]));
350	}
351
352	/* return -1 if no transition will occur. */
353	static int64_t pit_get_next_transition_time(PITChannelState *s,
354	uint64_t current_time)
355	{
356	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
357	uint64_t d, next_time, base;
358	uint32_t period2;
359
360	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
361	switch(EFFECTIVE_MODE(s->mode)) {
362	default:
363	case 0:
364	case 1:
365	if (d < s->count)
366	next_time = s->count;
367	else
368	return -1;
369	break;
370	/*
371	* Mode 2: The period is 'count' PIT ticks.
372	* When the counter reaches 1 we set the output low (for channel 0 that
373	* means lowering IRQ0). On the next tick, where we should be decrementing
374	* from 1 to 0, the count is loaded and the output goes high (channel 0
375	* means raising IRQ0 again and triggering timer interrupt).
376	*
377	* In VirtualBox we compress the pulse and flip-flop the IRQ line at the
378	* end of the period, which signals an interrupt at the exact same time.
379	*/
380	case 2:
381	base = (d / s->count) * s->count;
382	#ifndef VBOX /* see above */
383	if ((d - base) == 0 && d != 0)
384	next_time = base + s->count - 1;
385	else
386	#endif
387	next_time = base + s->count;
388	break;
389	case 3:
390	base = (d / s->count) * s->count;
391	period2 = ((s->count + 1) >> 1);
392	if ((d - base) < period2)
393	next_time = base + period2;
394	else
395	next_time = base + s->count;
396	break;
397	case 4:
398	case 5:
399	if (d < s->count)
400	next_time = s->count;
401	else if (d == s->count)
402	next_time = s->count + 1;
403	else
404	return -1;
405	break;
406	}
407	/* convert to timer units */
408	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
409	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
410	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
411	/* fix potential rounding problems */
412	if (next_time <= current_time)
413	next_time = current_time;
414	/* Add one to next_time; if we don't, integer truncation will cause
415	* the algorithm to think that at the end of each period, it's still
416	* within the first one instead of at the beginning of the next one.
417	*/
418	return next_time + 1;
419	}
420
421	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now)
422	{
423	int64_t expire_time;
424	int irq_level;
425	PPDMDEVINS pDevIns;
426	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
427
428	if (!s->CTX_SUFF(pTimer))
429	return;
430	expire_time = pit_get_next_transition_time(s, current_time);
431	irq_level = pit_get_out1(s, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
432
433	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
434	* but do not modify other aspects of device operation.
435	*/
436	if (!s->pPitR3->fDisabledByHpet)
437	{
438	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
439
440	if (EFFECTIVE_MODE(s->mode) == 2)
441	{
442	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for years). */
443	PDMDevHlpISASetIrq(pDevIns, s->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
444	} else
445	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
446	}
447
448	if (irq_level)
449	{
450	s->u64ReloadTS = now;
451	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
452	}
453
454	if (expire_time != -1)
455	{
456	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
457	s->u64NextTS = expire_time;
458	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
459	}
460	else
461	{
462	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
463	TMTimerStop(s->CTX_SUFF(pTimer));
464	s->u64NextTS = UINT64_MAX;
465	}
466	s->next_transition_time = expire_time;
467	}
468
469	#endif /* IN_RING3 */
470
471
472	/**
473	* Port I/O Handler for IN operations.
474	*
475	* @returns VBox status code.
476	*
477	* @param pDevIns The device instance.
478	* @param pvUser User argument - ignored.
479	* @param Port Port number used for the IN operation.
480	* @param pu32 Where to store the result.
481	* @param cb Number of bytes read.
482	*/
483	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
484	{
485	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
486	NOREF(pvUser);
487	Port &= 3;
488	if (cb != 1 \|\| Port == 3)
489	{
490	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
491	return VERR_IOM_IOPORT_UNUSED;
492	}
493
494	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
495	int ret;
496	PITChannelState *s = &pit->channels[Port];
497	if (s->status_latched)
498	{
499	s->status_latched = 0;
500	ret = s->status;
501	}
502	else if (s->count_latched)
503	{
504	switch (s->count_latched)
505	{
506	default:
507	case RW_STATE_LSB:
508	ret = s->latched_count & 0xff;
509	s->count_latched = 0;
510	break;
511	case RW_STATE_MSB:
512	ret = s->latched_count >> 8;
513	s->count_latched = 0;
514	break;
515	case RW_STATE_WORD0:
516	ret = s->latched_count & 0xff;
517	s->count_latched = RW_STATE_MSB;
518	break;
519	}
520	}
521	else
522	{
523	int count;
524	switch (s->read_state)
525	{
526	default:
527	case RW_STATE_LSB:
528	count = pit_get_count(s);
529	ret = count & 0xff;
530	break;
531	case RW_STATE_MSB:
532	count = pit_get_count(s);
533	ret = (count >> 8) & 0xff;
534	break;
535	case RW_STATE_WORD0:
536	count = pit_get_count(s);
537	ret = count & 0xff;
538	s->read_state = RW_STATE_WORD1;
539	break;
540	case RW_STATE_WORD1:
541	count = pit_get_count(s);
542	ret = (count >> 8) & 0xff;
543	s->read_state = RW_STATE_WORD0;
544	break;
545	}
546	}
547
548	*pu32 = ret;
549	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
550	return VINF_SUCCESS;
551	}
552
553
554	/**
555	* Port I/O Handler for OUT operations.
556	*
557	* @returns VBox status code.
558	*
559	* @param pDevIns The device instance.
560	* @param pvUser User argument - ignored.
561	* @param Port Port number used for the IN operation.
562	* @param u32 The value to output.
563	* @param cb The value size in bytes.
564	*/
565	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
566	{
567	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
568	NOREF(pvUser);
569	if (cb != 1)
570	return VINF_SUCCESS;
571
572	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
573	Port &= 3;
574	if (Port == 3)
575	{
576	/*
577	* Port 43h - Mode/Command Register.
578	* 7 6 5 4 3 2 1 0
579	* * * . . . . . . Select channel: 0 0 = Channel 0
580	* 0 1 = Channel 1
581	* 1 0 = Channel 2
582	* 1 1 = Read-back command (8254 only)
583	* (Illegal on 8253)
584	* (Illegal on PS/2 {JAM})
585	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
586	* 0 1 = Access mode: lobyte only
587	* 1 0 = Access mode: hibyte only
588	* 1 1 = Access mode: lobyte/hibyte
589	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
590	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
591	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
592	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
593	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
594	*/
595	unsigned channel = u32 >> 6;
596	if (channel == 3)
597	{
598	/* read-back command */
599	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
600	{
601	PITChannelState *s = &pit->channels[channel];
602	if (u32 & (2 << channel)) {
603	if (!(u32 & 0x20))
604	pit_latch_count(s);
605	if (!(u32 & 0x10) && !s->status_latched)
606	{
607	/* status latch */
608	/* XXX: add BCD and null count */
609	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
610	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
611	\| (s->rw_mode << 4)
612	\| (s->mode << 1)
613	\| s->bcd;
614	s->status_latched = 1;
615	}
616	}
617	}
618	}
619	else
620	{
621	PITChannelState *s = &pit->channels[channel];
622	unsigned access = (u32 >> 4) & 3;
623	if (access == 0)
624	pit_latch_count(s);
625	else
626	{
627	s->rw_mode = access;
628	s->read_state = access;
629	s->write_state = access;
630
631	s->mode = (u32 >> 1) & 7;
632	s->bcd = u32 & 1;
633	/* XXX: update irq timer ? */
634	}
635	}
636	}
637	else
638	{
639	#ifndef IN_RING3
640	return VINF_IOM_HC_IOPORT_WRITE;
641	#else /* IN_RING3 */
642	/*
643	* Port 40-42h - Channel Data Ports.
644	*/
645	PITChannelState *s = &pit->channels[Port];
646	switch(s->write_state)
647	{
648	default:
649	case RW_STATE_LSB:
650	pit_load_count(s, u32);
651	break;
652	case RW_STATE_MSB:
653	pit_load_count(s, u32 << 8);
654	break;
655	case RW_STATE_WORD0:
656	s->write_latch = u32;
657	s->write_state = RW_STATE_WORD1;
658	break;
659	case RW_STATE_WORD1:
660	pit_load_count(s, s->write_latch \| (u32 << 8));
661	s->write_state = RW_STATE_WORD0;
662	break;
663	}
664	#endif /* !IN_RING3 */
665	}
666	return VINF_SUCCESS;
667	}
668
669
670	/**
671	* Port I/O Handler for speaker IN operations.
672	*
673	* @returns VBox status code.
674	*
675	* @param pDevIns The device instance.
676	* @param pvUser User argument - ignored.
677	* @param Port Port number used for the IN operation.
678	* @param pu32 Where to store the result.
679	* @param cb Number of bytes read.
680	*/
681	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
682	{
683	NOREF(pvUser);
684	if (cb == 1)
685	{
686	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
687	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
688	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
689
690	/* bit 6,7 Parity error stuff. */
691	/* bit 5 - mirrors timer 2 output condition. */
692	const int fOut = pit_get_out(pThis, 2, u64Now);
693	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
694	ASSUMES ns timer freq, see assertion above. */
695	#ifndef FAKE_REFRESH_CLOCK
696	const int fRefresh = (u64Now / 15085) & 1;
697	#else
698	pThis->dummy_refresh_clock ^= 1;
699	const int fRefresh = pThis->dummy_refresh_clock;
700	#endif
701	/* bit 2,3 NMI / parity status stuff. */
702	/* bit 1 - speaker data status */
703	const int fSpeakerStatus = pThis->speaker_data_on;
704	/* bit 0 - timer 2 clock gate to speaker status. */
705	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
706
707	*pu32 = fTimer2GateStatus
708	\| (fSpeakerStatus << 1)
709	\| (fRefresh << 4)
710	\| (fOut << 5);
711	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
712	return VINF_SUCCESS;
713	}
714	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
715	return VERR_IOM_IOPORT_UNUSED;
716	}
717
718	#ifdef IN_RING3
719
720	/**
721	* Port I/O Handler for speaker OUT operations.
722	*
723	* @returns VBox status code.
724	*
725	* @param pDevIns The device instance.
726	* @param pvUser User argument - ignored.
727	* @param Port Port number used for the IN operation.
728	* @param u32 The value to output.
729	* @param cb The value size in bytes.
730	*/
731	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
732	{
733	NOREF(pvUser);
734	if (cb == 1)
735	{
736	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
737	pThis->speaker_data_on = (u32 >> 1) & 1;
738	pit_set_gate(pThis, 2, u32 & 1);
739	}
740	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
741	return VINF_SUCCESS;
742	}
743
744
745	/**
746	* @copydoc FNSSMDEVLIVEEXEC
747	*/
748	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
749	{
750	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
751	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
752	SSMR3PutU8( pSSM, pThis->channels[0].irq);
753	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
754	return VINF_SSM_DONT_CALL_AGAIN;
755	}
756
757
758	/**
759	* @copydoc FNSSMDEVSAVEEXEC
760	*/
761	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
762	{
763	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
764	unsigned i;
765
766	/* The config. */
767	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
768
769	/* The state. */
770	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
771	{
772	PITChannelState *s = &pThis->channels[i];
773	SSMR3PutU32(pSSM, s->count);
774	SSMR3PutU16(pSSM, s->latched_count);
775	SSMR3PutU8(pSSM, s->count_latched);
776	SSMR3PutU8(pSSM, s->status_latched);
777	SSMR3PutU8(pSSM, s->status);
778	SSMR3PutU8(pSSM, s->read_state);
779	SSMR3PutU8(pSSM, s->write_state);
780	SSMR3PutU8(pSSM, s->write_latch);
781	SSMR3PutU8(pSSM, s->rw_mode);
782	SSMR3PutU8(pSSM, s->mode);
783	SSMR3PutU8(pSSM, s->bcd);
784	SSMR3PutU8(pSSM, s->gate);
785	SSMR3PutU64(pSSM, s->count_load_time);
786	SSMR3PutU64(pSSM, s->u64NextTS);
787	SSMR3PutU64(pSSM, s->u64ReloadTS);
788	SSMR3PutS64(pSSM, s->next_transition_time);
789	if (s->CTX_SUFF(pTimer))
790	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
791	}
792
793	SSMR3PutS32(pSSM, pThis->speaker_data_on);
794	#ifdef FAKE_REFRESH_CLOCK
795	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
796	#else
797	SSMR3PutS32(pSSM, 0);
798	#endif
799
800	return SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
801	}
802
803
804	/**
805	* @copydoc FNSSMDEVLOADEXEC
806	*/
807	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
808	{
809	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
810	int rc;
811
812	if ( uVersion != PIT_SAVED_STATE_VERSION
813	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
814	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
815	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
816
817	/* The config. */
818	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
819	{
820	RTIOPORT IOPortBaseCfg;
821	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
822	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
823	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
824	IOPortBaseCfg, pThis->IOPortBaseCfg);
825
826	uint8_t u8Irq;
827	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
828	if (u8Irq != pThis->channels[0].irq)
829	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
830	u8Irq, pThis->channels[0].irq);
831
832	bool fSpeakerCfg;
833	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
834	if (fSpeakerCfg != pThis->fSpeakerCfg)
835	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
836	fSpeakerCfg, pThis->fSpeakerCfg);
837	}
838
839	if (uPass != SSM_PASS_FINAL)
840	return VINF_SUCCESS;
841
842	/* The state. */
843	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
844	{
845	PITChannelState *s = &pThis->channels[i];
846	SSMR3GetU32(pSSM, &s->count);
847	SSMR3GetU16(pSSM, &s->latched_count);
848	SSMR3GetU8(pSSM, &s->count_latched);
849	SSMR3GetU8(pSSM, &s->status_latched);
850	SSMR3GetU8(pSSM, &s->status);
851	SSMR3GetU8(pSSM, &s->read_state);
852	SSMR3GetU8(pSSM, &s->write_state);
853	SSMR3GetU8(pSSM, &s->write_latch);
854	SSMR3GetU8(pSSM, &s->rw_mode);
855	SSMR3GetU8(pSSM, &s->mode);
856	SSMR3GetU8(pSSM, &s->bcd);
857	SSMR3GetU8(pSSM, &s->gate);
858	SSMR3GetU64(pSSM, &s->count_load_time);
859	SSMR3GetU64(pSSM, &s->u64NextTS);
860	SSMR3GetU64(pSSM, &s->u64ReloadTS);
861	SSMR3GetS64(pSSM, &s->next_transition_time);
862	if (s->CTX_SUFF(pTimer))
863	{
864	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
865	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
866	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
867	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
868	}
869	pThis->channels[i].cRelLogEntries = 0;
870	}
871
872	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
873	#ifdef FAKE_REFRESH_CLOCK
874	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
875	#else
876	int32_t u32Dummy;
877	SSMR3GetS32(pSSM, &u32Dummy);
878	#endif
879	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
880	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
881
882	return VINF_SUCCESS;
883	}
884
885
886	/**
887	* Device timer callback function.
888	*
889	* @param pDevIns Device instance of the device which registered the timer.
890	* @param pTimer The timer handle.
891	* @param pvUser Pointer to the PIT channel state.
892	*/
893	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
894	{
895	PITChannelState s = (PITChannelState )pvUser;
896	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
897	Log(("pitTimer\n"));
898	pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer));
899	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
900	}
901
902
903	/**
904	* Info handler, device version.
905	*
906	* @param pDevIns Device instance which registered the info.
907	* @param pHlp Callback functions for doing output.
908	* @param pszArgs Argument string. Optional and specific to the handler.
909	*/
910	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
911	{
912	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
913	unsigned i;
914	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
915	{
916	const PITChannelState *pCh = &pThis->channels[i];
917
918	pHlp->pfnPrintf(pHlp,
919	"PIT (i8254) channel %d status: irq=%#x\n"
920	" count=%08x" " latched_count=%04x count_latched=%02x\n"
921	" status=%02x status_latched=%02x read_state=%02x\n"
922	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
923	" mode=%02x bcd=%02x gate=%02x\n"
924	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
925	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
926	,
927	i, pCh->irq,
928	pCh->count, pCh->latched_count, pCh->count_latched,
929	pCh->status, pCh->status_latched, pCh->read_state,
930	pCh->write_state, pCh->write_latch, pCh->rw_mode,
931	pCh->mode, pCh->bcd, pCh->gate,
932	pCh->count_load_time, pCh->next_transition_time,
933	pCh->u64ReloadTS, pCh->u64NextTS);
934	}
935	#ifdef FAKE_REFRESH_CLOCK
936	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
937	pThis->speaker_data_on, pThis->dummy_refresh_clock);
938	#else
939	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
940	#endif
941	if (pThis->fDisabledByHpet)
942	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
943	}
944
945
946	/**
947	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
948	*/
949	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
950	{
951	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
952	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
953	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
954	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
955	return NULL;
956	}
957
958
959	/**
960	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
961	*/
962	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
963	{
964	PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IHpetLegacyNotify);
965	pThis->fDisabledByHpet = fActivated;
966	}
967
968
969	/**
970	* Relocation notification.
971	*
972	* @returns VBox status.
973	* @param pDevIns The device instance data.
974	* @param offDelta The delta relative to the old address.
975	*/
976	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
977	{
978	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
979	unsigned i;
980	LogFlow(("pitRelocate: \n"));
981
982	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
983	{
984	PITChannelState *pCh = &pThis->channels[i];
985	if (pCh->pTimerR3)
986	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
987	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
988	}
989	}
990
991
992	/**
993	* Reset notification.
994	*
995	* @returns VBox status.
996	* @param pDevIns The device instance data.
997	*/
998	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
999	{
1000	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1001	unsigned i;
1002	LogFlow(("pitReset: \n"));
1003
1004	pThis->fDisabledByHpet = false;
1005
1006	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1007	{
1008	PITChannelState *s = &pThis->channels[i];
1009
1010	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1011	s->latched_count = 0;
1012	s->count_latched = 0;
1013	s->status_latched = 0;
1014	s->status = 0;
1015	s->read_state = 0;
1016	s->write_state = 0;
1017	s->write_latch = 0;
1018	s->rw_mode = 0;
1019	s->bcd = 0;
1020	#endif
1021	s->u64NextTS = UINT64_MAX;
1022	s->cRelLogEntries = 0;
1023	s->mode = 3;
1024	s->gate = (i != 2);
1025	pit_load_count(s, 0);
1026	}
1027	}
1028
1029
1030	/**
1031	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1032	*/
1033	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1034	{
1035	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1036	int rc;
1037	uint8_t u8Irq;
1038	uint16_t u16Base;
1039	bool fSpeaker;
1040	bool fGCEnabled;
1041	bool fR0Enabled;
1042	unsigned i;
1043	Assert(iInstance == 0);
1044
1045	/*
1046	* Validate configuration.
1047	*/
1048	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1049	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1050
1051	/*
1052	* Init the data.
1053	*/
1054	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1055	if (RT_FAILURE(rc))
1056	return PDMDEV_SET_ERROR(pDevIns, rc,
1057	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1058
1059	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1060	if (RT_FAILURE(rc))
1061	return PDMDEV_SET_ERROR(pDevIns, rc,
1062	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1063
1064	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1065	if (RT_FAILURE(rc))
1066	return PDMDEV_SET_ERROR(pDevIns, rc,
1067	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1068
1069	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1070	if (RT_FAILURE(rc))
1071	return PDMDEV_SET_ERROR(pDevIns, rc,
1072	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1073
1074	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1075	if (RT_FAILURE(rc))
1076	return PDMDEV_SET_ERROR(pDevIns, rc,
1077	N_("Configuration error: failed to read R0Enabled as boolean"));
1078
1079	pThis->pDevIns = pDevIns;
1080	pThis->IOPortBaseCfg = u16Base;
1081	pThis->fSpeakerCfg = fSpeaker;
1082	pThis->channels[0].irq = u8Irq;
1083	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1084	{
1085	pThis->channels[i].pPitR3 = pThis;
1086	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1087	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1088	}
1089
1090	/*
1091	* Interfaces
1092	*/
1093	/* IBase */
1094	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1095	/* IHpetLegacyNotify */
1096	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1097
1098	/*
1099	* Create timer, register I/O Ports and save state.
1100	*/
1101	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1102	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1103	&pThis->channels[0].pTimerR3);
1104	if (RT_FAILURE(rc))
1105	return rc;
1106	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1107	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1108
1109	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1110	if (RT_FAILURE(rc))
1111	return rc;
1112	if (fGCEnabled)
1113	{
1114	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1115	if (RT_FAILURE(rc))
1116	return rc;
1117	}
1118	if (fR0Enabled)
1119	{
1120	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1121	if (RT_FAILURE(rc))
1122	return rc;
1123	}
1124
1125	if (fSpeaker)
1126	{
1127	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1128	if (RT_FAILURE(rc))
1129	return rc;
1130	if (fGCEnabled)
1131	{
1132	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1133	if (RT_FAILURE(rc))
1134	return rc;
1135	}
1136	}
1137
1138	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1139	if (RT_FAILURE(rc))
1140	return rc;
1141
1142	/*
1143	* Initialize the device state.
1144	*/
1145	pitReset(pDevIns);
1146
1147	/*
1148	* Register statistics and debug info.
1149	*/
1150	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1151	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1152
1153	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1154
1155	return VINF_SUCCESS;
1156	}
1157
1158
1159	/**
1160	* The device registration structure.
1161	*/
1162	const PDMDEVREG g_DeviceI8254 =
1163	{
1164	/* u32Version */
1165	PDM_DEVREG_VERSION,
1166	/* szName */
1167	"i8254",
1168	/* szRCMod */
1169	"VBoxDDGC.gc",
1170	/* szR0Mod */
1171	"VBoxDDR0.r0",
1172	/* pszDescription */
1173	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1174	/* fFlags */
1175	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1176	/* fClass */
1177	PDM_DEVREG_CLASS_PIT,
1178	/* cMaxInstances */
1179	1,
1180	/* cbInstance */
1181	sizeof(PITState),
1182	/* pfnConstruct */
1183	pitConstruct,
1184	/* pfnDestruct */
1185	NULL,
1186	/* pfnRelocate */
1187	pitRelocate,
1188	/* pfnIOCtl */
1189	NULL,
1190	/* pfnPowerOn */
1191	NULL,
1192	/* pfnReset */
1193	pitReset,
1194	/* pfnSuspend */
1195	NULL,
1196	/* pfnResume */
1197	NULL,
1198	/* pfnAttach */
1199	NULL,
1200	/* pfnDetach */
1201	NULL,
1202	/* pfnQueryInterface */
1203	NULL,
1204	/* pfnInitComplete */
1205	NULL,
1206	/* pfnPowerOff */
1207	NULL,
1208	/* pfnSoftReset */
1209	NULL,
1210	/* u32VersionEnd */
1211	PDM_DEVREG_VERSION
1212	};
1213
1214	#endif /* IN_RING3 */
1215	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 35351

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