1 | /* $Id: DevPit-i8254.cpp 64369 2016-10-22 18:19:08Z vboxsync $ */
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2 | /** @file
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3 | * DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2016 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | * --------------------------------------------------------------------
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17 | *
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18 | * This code is based on:
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19 | *
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20 | * QEMU 8253/8254 interval timer emulation
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21 | *
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22 | * Copyright (c) 2003-2004 Fabrice Bellard
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23 | *
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24 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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25 | * of this software and associated documentation files (the "Software"), to deal
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26 | * in the Software without restriction, including without limitation the rights
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27 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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28 | * copies of the Software, and to permit persons to whom the Software is
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29 | * furnished to do so, subject to the following conditions:
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30 | *
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31 | * The above copyright notice and this permission notice shall be included in
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32 | * all copies or substantial portions of the Software.
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33 | *
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34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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35 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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36 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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37 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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38 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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39 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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40 | * THE SOFTWARE.
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41 | */
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42 |
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43 |
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44 | /*********************************************************************************************************************************
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45 | * Header Files *
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46 | *********************************************************************************************************************************/
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47 | #define LOG_GROUP LOG_GROUP_DEV_PIT
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48 | #include <VBox/vmm/pdmdev.h>
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49 | #include <VBox/log.h>
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50 | #include <VBox/vmm/stam.h>
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51 | #include <iprt/assert.h>
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52 | #include <iprt/asm-math.h>
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53 |
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54 | #ifdef IN_RING3
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55 | # ifdef RT_OS_LINUX
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56 | # include <fcntl.h>
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57 | # include <errno.h>
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58 | # include <unistd.h>
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59 | # include <stdio.h>
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60 | # include <linux/kd.h>
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61 | # include <linux/input.h>
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62 | # include <sys/ioctl.h>
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63 | # endif
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64 | # include <iprt/alloc.h>
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65 | # include <iprt/string.h>
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66 | # include <iprt/uuid.h>
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67 | #endif /* IN_RING3 */
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68 |
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69 | #include "VBoxDD.h"
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70 |
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71 |
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72 | /*********************************************************************************************************************************
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73 | * Defined Constants And Macros *
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74 | *********************************************************************************************************************************/
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75 | /** The PIT frequency. */
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76 | #define PIT_FREQ 1193182
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77 |
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78 | #define RW_STATE_LSB 1
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79 | #define RW_STATE_MSB 2
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80 | #define RW_STATE_WORD0 3
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81 | #define RW_STATE_WORD1 4
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82 |
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83 | /** The current saved state version. */
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84 | #define PIT_SAVED_STATE_VERSION 4
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85 | /** The saved state version used by VirtualBox 3.1 and earlier.
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86 | * This did not include disable by HPET flag. */
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87 | #define PIT_SAVED_STATE_VERSION_VBOX_31 3
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88 | /** The saved state version used by VirtualBox 3.0 and earlier.
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89 | * This did not include the config part. */
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90 | #define PIT_SAVED_STATE_VERSION_VBOX_30 2
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91 |
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92 | /** @def FAKE_REFRESH_CLOCK
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93 | * Define this to flip the 15usec refresh bit on every read.
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94 | * If not defined, it will be flipped correctly. */
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95 | /* #define FAKE_REFRESH_CLOCK */
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96 | #ifdef DOXYGEN_RUNNING
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97 | # define FAKE_REFRESH_CLOCK
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98 | #endif
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99 |
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100 | /** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
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101 | #define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
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102 |
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103 |
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104 | /**
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105 | * Acquires the PIT lock or returns.
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106 | */
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107 | #define DEVPIT_LOCK_RETURN(a_pThis, a_rcBusy) \
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108 | do { \
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109 | int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
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110 | if (rcLock != VINF_SUCCESS) \
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111 | return rcLock; \
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112 | } while (0)
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113 |
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114 | /**
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115 | * Releases the PIT lock.
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116 | */
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117 | #define DEVPIT_UNLOCK(a_pThis) \
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118 | do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
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119 |
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120 |
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121 | /**
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122 | * Acquires the TM lock and PIT lock, returns on failure.
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123 | */
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124 | #define DEVPIT_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
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125 | do { \
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126 | int rcLock = TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), (a_rcBusy)); \
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127 | if (rcLock != VINF_SUCCESS) \
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128 | return rcLock; \
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129 | rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
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130 | if (rcLock != VINF_SUCCESS) \
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131 | { \
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132 | TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
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133 | return rcLock; \
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134 | } \
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135 | } while (0)
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136 |
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137 | #ifdef IN_RING3
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138 | /**
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139 | * Acquires the TM lock and PIT lock, ignores failures.
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140 | */
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141 | # define DEVPIT_R3_LOCK_BOTH(a_pThis) \
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142 | do { \
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143 | TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), VERR_IGNORED); \
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144 | PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
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145 | } while (0)
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146 | #endif /* IN_RING3 */
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147 |
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148 | /**
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149 | * Releases the PIT lock and TM lock.
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150 | */
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151 | #define DEVPIT_UNLOCK_BOTH(a_pThis) \
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152 | do { \
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153 | PDMCritSectLeave(&(a_pThis)->CritSect); \
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154 | TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
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155 | } while (0)
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156 |
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157 |
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158 |
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159 | /*********************************************************************************************************************************
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160 | * Structures and Typedefs *
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161 | *********************************************************************************************************************************/
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162 | /**
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163 | * The state of one PIT channel.
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164 | */
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165 | typedef struct PITCHANNEL
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166 | {
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167 | /** Pointer to the instance data - R3 Ptr. */
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168 | R3PTRTYPE(struct PITSTATE *) pPitR3;
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169 | /** The timer - R3 Ptr.
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170 | * @note Only channel 0 has a timer. */
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171 | PTMTIMERR3 pTimerR3;
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172 | /** Pointer to the instance data - R0 Ptr. */
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173 | R0PTRTYPE(struct PITSTATE *) pPitR0;
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174 | /** The timer - R0 Ptr.
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175 | * @note Only channel 0 has a timer. */
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176 | PTMTIMERR0 pTimerR0;
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177 | /** Pointer to the instance data - RC Ptr. */
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178 | RCPTRTYPE(struct PITSTATE *) pPitRC;
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179 | /** The timer - RC Ptr.
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180 | * @note Only channel 0 has a timer. */
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181 | PTMTIMERRC pTimerRC;
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182 | /** The virtual time stamp at the last reload. (only used in mode 2 for now) */
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183 | uint64_t u64ReloadTS;
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184 | /** The actual time of the next tick.
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185 | * As apposed to the next_transition_time which contains the correct time of the next tick. */
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186 | uint64_t u64NextTS;
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187 |
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188 | /** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
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189 | uint64_t count_load_time;
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190 | /* irq handling */
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191 | int64_t next_transition_time;
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192 | int32_t irq;
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193 | /** Number of release log entries. Used to prevent flooding. */
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194 | uint32_t cRelLogEntries;
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195 |
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196 | uint32_t count; /* can be 65536 */
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197 | uint16_t latched_count;
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198 | uint8_t count_latched;
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199 | uint8_t status_latched;
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200 |
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201 | uint8_t status;
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202 | uint8_t read_state;
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203 | uint8_t write_state;
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204 | uint8_t write_latch;
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205 |
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206 | uint8_t rw_mode;
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207 | uint8_t mode;
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208 | uint8_t bcd; /* not supported */
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209 | uint8_t gate; /* timer start */
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210 |
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211 | } PITCHANNEL;
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212 | /** Pointer to the state of one PIT channel. */
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213 | typedef PITCHANNEL *PPITCHANNEL;
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214 |
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215 | /** Speaker emulation state. */
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216 | typedef enum PITSPEAKEREMU
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217 | {
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218 | PIT_SPEAKER_EMU_NONE = 0,
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219 | PIT_SPEAKER_EMU_CONSOLE,
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220 | PIT_SPEAKER_EMU_EVDEV,
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221 | PIT_SPEAKER_EMU_TTY
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222 | } PITSPEAKEREMU;
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223 |
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224 | /**
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225 | * The whole PIT state.
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226 | */
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227 | typedef struct PITSTATE
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228 | {
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229 | /** Channel state. Must come first? */
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230 | PITCHANNEL channels[3];
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231 | /** Speaker data. */
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232 | int32_t speaker_data_on;
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233 | #ifdef FAKE_REFRESH_CLOCK
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234 | /** Refresh dummy. */
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235 | int32_t dummy_refresh_clock;
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236 | #else
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237 | uint32_t Alignment1;
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238 | #endif
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239 | /** Config: I/O port base. */
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240 | RTIOPORT IOPortBaseCfg;
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241 | /** Config: Speaker enabled. */
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242 | bool fSpeakerCfg;
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243 | /** Disconnect PIT from the interrupt controllers if requested by HPET. */
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244 | bool fDisabledByHpet;
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245 | /** Config: What to do with speaker activity. */
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246 | PITSPEAKEREMU enmSpeakerEmu;
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247 | #ifdef RT_OS_LINUX
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248 | /** File handle for host speaker functionality. */
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249 | int hHostSpeaker;
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250 | int afAlignment2;
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251 | #endif
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252 | /** PIT port interface. */
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253 | PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
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254 | /** Pointer to the device instance. */
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255 | PPDMDEVINSR3 pDevIns;
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256 | /** Number of IRQs that's been raised. */
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257 | STAMCOUNTER StatPITIrq;
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258 | /** Profiling the timer callback handler. */
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259 | STAMPROFILEADV StatPITHandler;
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260 | /** Critical section protecting the state. */
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261 | PDMCRITSECT CritSect;
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262 | } PITSTATE;
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263 | /** Pointer to the PIT device state. */
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264 | typedef PITSTATE *PPITSTATE;
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265 |
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266 |
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267 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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268 |
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269 |
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270 | /*********************************************************************************************************************************
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271 | * Internal Functions *
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272 | *********************************************************************************************************************************/
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273 | #ifdef IN_RING3
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274 | static void pit_irq_timer_update(PPITCHANNEL pChan, uint64_t current_time, uint64_t now, bool in_timer);
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275 | #endif
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276 |
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277 |
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278 | #ifdef IN_RING3
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279 | # ifdef RT_OS_LINUX
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280 | static int pitTryDeviceOpen(const char *pszPath, int flags)
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281 | {
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282 | int fd = open(pszPath, flags);
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283 | if (fd == -1)
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284 | LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
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285 | else
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286 | LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
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287 | return fd;
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288 | }
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289 |
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290 | static int pitTryDeviceOpenSanitizeIoctl(const char *pszPath, int flags)
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291 | {
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292 | int fd = open(pszPath, flags);
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293 | if (fd == -1)
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294 | LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
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295 | else
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296 | {
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297 | int errno_eviocgsnd0 = 0;
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298 | int errno_kiocsound = 0;
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299 | if (ioctl(fd, EVIOCGSND(0)) == -1)
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300 | {
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301 | errno_eviocgsnd0 = errno;
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302 | if (ioctl(fd, KIOCSOUND, 1) == -1)
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303 | errno_kiocsound = errno;
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304 | else
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305 | ioctl(fd, KIOCSOUND, 0);
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306 | }
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307 | if (errno_eviocgsnd0 && errno_kiocsound)
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308 | {
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309 | LogRel(("PIT: speaker: cannot use \"%s\", ioctl failed errno=%d/errno=%d\n", pszPath, errno_eviocgsnd0, errno_kiocsound));
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310 | close(fd);
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311 | fd = -1;
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312 | }
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313 | else
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314 | LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
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315 | }
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316 | return fd;
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317 | }
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318 | # endif /* RT_OS_LINUX */
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319 | #endif /* IN_RING3 */
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320 |
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321 | static int pit_get_count(PPITCHANNEL pChan)
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322 | {
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323 | uint64_t d;
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324 | PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
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325 | Assert(TMTimerIsLockOwner(pTimer));
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326 |
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327 | if (EFFECTIVE_MODE(pChan->mode) == 2)
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328 | {
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329 | if (pChan->u64NextTS == UINT64_MAX)
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330 | {
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331 | d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
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332 | return pChan->count - (d % pChan->count); /** @todo check this value. */
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333 | }
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334 | uint64_t Interval = pChan->u64NextTS - pChan->u64ReloadTS;
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335 | if (!Interval)
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336 | return pChan->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
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337 | d = TMTimerGet(pTimer);
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338 | d = ASMMultU64ByU32DivByU32(d - pChan->u64ReloadTS, pChan->count, Interval);
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339 | if (d >= pChan->count)
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340 | return 1;
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341 | return pChan->count - d;
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342 | }
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343 |
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344 | d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
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345 | int counter;
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346 | switch (EFFECTIVE_MODE(pChan->mode))
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347 | {
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348 | case 0:
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349 | case 1:
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350 | case 4:
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351 | case 5:
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352 | counter = (pChan->count - d) & 0xffff;
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353 | break;
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354 | case 3:
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355 | /* XXX: may be incorrect for odd counts */
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356 | counter = pChan->count - ((2 * d) % pChan->count);
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357 | break;
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358 | default:
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359 | counter = pChan->count - (d % pChan->count);
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360 | break;
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361 | }
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362 | /** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
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363 | return counter;
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364 | }
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365 |
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366 | /* get pit output bit */
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367 | static int pit_get_out1(PPITCHANNEL pChan, int64_t current_time)
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368 | {
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369 | PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
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370 | uint64_t d;
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371 | int out;
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372 |
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373 | d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
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374 | switch (EFFECTIVE_MODE(pChan->mode))
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375 | {
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376 | default:
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377 | case 0:
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378 | out = (d >= pChan->count);
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379 | break;
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380 | case 1:
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381 | out = (d < pChan->count);
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382 | break;
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383 | case 2:
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384 | Log2(("pit_get_out1: d=%llx c=%x %x \n", d, pChan->count, (unsigned)(d % pChan->count)));
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385 | if ((d % pChan->count) == 0 && d != 0)
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386 | out = 1;
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387 | else
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388 | out = 0;
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389 | break;
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390 | case 3:
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391 | out = (d % pChan->count) < ((pChan->count + 1) >> 1);
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392 | break;
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393 | case 4:
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394 | case 5:
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395 | out = (d != pChan->count);
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396 | break;
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397 | }
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398 | return out;
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399 | }
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400 |
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401 |
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402 | static int pit_get_out(PPITSTATE pThis, int channel, int64_t current_time)
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403 | {
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404 | PPITCHANNEL pChan = &pThis->channels[channel];
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405 | return pit_get_out1(pChan, current_time);
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406 | }
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407 |
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408 |
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409 | static int pit_get_gate(PPITSTATE pThis, int channel)
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410 | {
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411 | PPITCHANNEL pChan = &pThis->channels[channel];
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412 | return pChan->gate;
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413 | }
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414 |
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415 |
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416 | /* if already latched, do not latch again */
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417 | static void pit_latch_count(PPITCHANNEL pChan)
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418 | {
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419 | if (!pChan->count_latched)
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420 | {
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421 | pChan->latched_count = pit_get_count(pChan);
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422 | pChan->count_latched = pChan->rw_mode;
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423 | LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
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424 | pChan->latched_count, ASMMultU64ByU32DivByU32(pChan->count - pChan->latched_count, 1000000000, PIT_FREQ),
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425 | pChan->count, pChan->mode));
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426 | }
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427 | }
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428 |
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429 | #ifdef IN_RING3
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430 |
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431 | /* val must be 0 or 1 */
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432 | static void pit_set_gate(PPITSTATE pThis, int channel, int val)
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433 | {
|
---|
434 | PPITCHANNEL pChan = &pThis->channels[channel];
|
---|
435 | PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
|
---|
436 |
|
---|
437 | Assert((val & 1) == val);
|
---|
438 | Assert(TMTimerIsLockOwner(pTimer));
|
---|
439 |
|
---|
440 | switch (EFFECTIVE_MODE(pChan->mode))
|
---|
441 | {
|
---|
442 | default:
|
---|
443 | case 0:
|
---|
444 | case 4:
|
---|
445 | /* XXX: just disable/enable counting */
|
---|
446 | break;
|
---|
447 | case 1:
|
---|
448 | case 5:
|
---|
449 | if (pChan->gate < val)
|
---|
450 | {
|
---|
451 | /* restart counting on rising edge */
|
---|
452 | Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
|
---|
453 | pChan->count_load_time = TMTimerGet(pTimer);
|
---|
454 | pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
|
---|
455 | }
|
---|
456 | break;
|
---|
457 | case 2:
|
---|
458 | case 3:
|
---|
459 | if (pChan->gate < val)
|
---|
460 | {
|
---|
461 | /* restart counting on rising edge */
|
---|
462 | Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
|
---|
463 | pChan->count_load_time = pChan->u64ReloadTS = TMTimerGet(pTimer);
|
---|
464 | pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
|
---|
465 | }
|
---|
466 | /* XXX: disable/enable counting */
|
---|
467 | break;
|
---|
468 | }
|
---|
469 | pChan->gate = val;
|
---|
470 | }
|
---|
471 |
|
---|
472 | static void pit_load_count(PPITCHANNEL pChan, int val)
|
---|
473 | {
|
---|
474 | PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
|
---|
475 | Assert(TMTimerIsLockOwner(pTimer));
|
---|
476 |
|
---|
477 | if (val == 0)
|
---|
478 | val = 0x10000;
|
---|
479 | pChan->count_load_time = pChan->u64ReloadTS = TMTimerGet(pTimer);
|
---|
480 | pChan->count = val;
|
---|
481 | pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
|
---|
482 |
|
---|
483 | /* log the new rate (ch 0 only). */
|
---|
484 | if (pChan->pTimerR3 /* ch 0 */)
|
---|
485 | {
|
---|
486 | if (pChan->cRelLogEntries++ < 32)
|
---|
487 | LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
|
---|
488 | pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
|
---|
489 | else
|
---|
490 | Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
|
---|
491 | pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
|
---|
492 | TMTimerSetFrequencyHint(pChan->CTX_SUFF(pTimer), PIT_FREQ / pChan->count);
|
---|
493 | }
|
---|
494 | else
|
---|
495 | Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
|
---|
496 | pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100,
|
---|
497 | pChan - &pChan->CTX_SUFF(pPit)->channels[0]));
|
---|
498 | }
|
---|
499 |
|
---|
500 | /* return -1 if no transition will occur. */
|
---|
501 | static int64_t pit_get_next_transition_time(PPITCHANNEL pChan, uint64_t current_time)
|
---|
502 | {
|
---|
503 | PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
|
---|
504 | uint64_t d, next_time, base;
|
---|
505 | uint32_t period2;
|
---|
506 |
|
---|
507 | d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
|
---|
508 | switch(EFFECTIVE_MODE(pChan->mode))
|
---|
509 | {
|
---|
510 | default:
|
---|
511 | case 0:
|
---|
512 | case 1:
|
---|
513 | if (d < pChan->count)
|
---|
514 | next_time = pChan->count;
|
---|
515 | else
|
---|
516 | return -1;
|
---|
517 | break;
|
---|
518 |
|
---|
519 | /*
|
---|
520 | * Mode 2: The period is 'count' PIT ticks.
|
---|
521 | * When the counter reaches 1 we set the output low (for channel 0 that
|
---|
522 | * means lowering IRQ0). On the next tick, where we should be decrementing
|
---|
523 | * from 1 to 0, the count is loaded and the output goes high (channel 0
|
---|
524 | * means raising IRQ0 again and triggering timer interrupt).
|
---|
525 | *
|
---|
526 | * In VirtualBox we compress the pulse and flip-flop the IRQ line at the
|
---|
527 | * end of the period, which signals an interrupt at the exact same time.
|
---|
528 | */
|
---|
529 | case 2:
|
---|
530 | base = (d / pChan->count) * pChan->count;
|
---|
531 | #ifndef VBOX /* see above */
|
---|
532 | if ((d - base) == 0 && d != 0)
|
---|
533 | next_time = base + pChan->count - 1;
|
---|
534 | else
|
---|
535 | #endif
|
---|
536 | next_time = base + pChan->count;
|
---|
537 | break;
|
---|
538 | case 3:
|
---|
539 | base = (d / pChan->count) * pChan->count;
|
---|
540 | period2 = ((pChan->count + 1) >> 1);
|
---|
541 | if ((d - base) < period2)
|
---|
542 | next_time = base + period2;
|
---|
543 | else
|
---|
544 | next_time = base + pChan->count;
|
---|
545 | break;
|
---|
546 |
|
---|
547 | /* Modes 4 and 5 generate a short pulse at the end of the time delay. This
|
---|
548 | * is similar to mode 2, except modes 4/5 aren't periodic. We use the same
|
---|
549 | * optimization - only use one timer callback and pulse the IRQ.
|
---|
550 | * Note: Tickless Linux kernels use PIT mode 4 with 'nolapic'.
|
---|
551 | */
|
---|
552 | case 4:
|
---|
553 | case 5:
|
---|
554 | #ifdef VBOX
|
---|
555 | if (d <= pChan->count)
|
---|
556 | next_time = pChan->count;
|
---|
557 | #else
|
---|
558 | if (d < pChan->count)
|
---|
559 | next_time = pChan->count;
|
---|
560 | else if (d == pChan->count)
|
---|
561 | next_time = pChan->count + 1;
|
---|
562 | #endif
|
---|
563 | else
|
---|
564 | return -1;
|
---|
565 | break;
|
---|
566 | }
|
---|
567 |
|
---|
568 | /* convert to timer units */
|
---|
569 | LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
|
---|
570 | ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), pChan->mode, pChan->count));
|
---|
571 | next_time = pChan->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
|
---|
572 |
|
---|
573 | /* fix potential rounding problems */
|
---|
574 | if (next_time <= current_time)
|
---|
575 | next_time = current_time;
|
---|
576 |
|
---|
577 | /* Add one to next_time; if we don't, integer truncation will cause
|
---|
578 | * the algorithm to think that at the end of each period, it'pChan still
|
---|
579 | * within the first one instead of at the beginning of the next one.
|
---|
580 | */
|
---|
581 | return next_time + 1;
|
---|
582 | }
|
---|
583 |
|
---|
584 | static void pit_irq_timer_update(PPITCHANNEL pChan, uint64_t current_time, uint64_t now, bool in_timer)
|
---|
585 | {
|
---|
586 | int64_t expire_time;
|
---|
587 | int irq_level;
|
---|
588 | Assert(TMTimerIsLockOwner(pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer)));
|
---|
589 |
|
---|
590 | if (!pChan->CTX_SUFF(pTimer))
|
---|
591 | return;
|
---|
592 | expire_time = pit_get_next_transition_time(pChan, current_time);
|
---|
593 | irq_level = pit_get_out1(pChan, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
|
---|
594 |
|
---|
595 | /* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
|
---|
596 | * but do not modify other aspects of device operation.
|
---|
597 | */
|
---|
598 | if (!pChan->pPitR3->fDisabledByHpet)
|
---|
599 | {
|
---|
600 | PPDMDEVINS pDevIns = pChan->CTX_SUFF(pPit)->pDevIns;
|
---|
601 |
|
---|
602 | switch (EFFECTIVE_MODE(pChan->mode))
|
---|
603 | {
|
---|
604 | case 2:
|
---|
605 | case 4:
|
---|
606 | case 5:
|
---|
607 | /* We just flip-flop the IRQ line to save an extra timer call,
|
---|
608 | * which isn't generally required. However, the pulse is only
|
---|
609 | * generated when running on the timer callback (and thus on
|
---|
610 | * the trailing edge of the output signal pulse).
|
---|
611 | */
|
---|
612 | if (in_timer)
|
---|
613 | {
|
---|
614 | PDMDevHlpISASetIrq(pDevIns, pChan->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
|
---|
615 | break;
|
---|
616 | }
|
---|
617 | /* Else fall through! */
|
---|
618 | default:
|
---|
619 | PDMDevHlpISASetIrq(pDevIns, pChan->irq, irq_level);
|
---|
620 | break;
|
---|
621 | }
|
---|
622 | }
|
---|
623 |
|
---|
624 | if (irq_level)
|
---|
625 | {
|
---|
626 | pChan->u64ReloadTS = now;
|
---|
627 | STAM_COUNTER_INC(&pChan->CTX_SUFF(pPit)->StatPITIrq);
|
---|
628 | }
|
---|
629 |
|
---|
630 | if (expire_time != -1)
|
---|
631 | {
|
---|
632 | Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
|
---|
633 | pChan->u64NextTS = expire_time;
|
---|
634 | TMTimerSet(pChan->CTX_SUFF(pTimer), pChan->u64NextTS);
|
---|
635 | }
|
---|
636 | else
|
---|
637 | {
|
---|
638 | LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", pChan->mode, pChan->count, irq_level));
|
---|
639 | TMTimerStop(pChan->CTX_SUFF(pTimer));
|
---|
640 | pChan->u64NextTS = UINT64_MAX;
|
---|
641 | }
|
---|
642 | pChan->next_transition_time = expire_time;
|
---|
643 | }
|
---|
644 |
|
---|
645 | #endif /* IN_RING3 */
|
---|
646 |
|
---|
647 |
|
---|
648 | /**
|
---|
649 | * @callback_method_impl{FNIOMIOPORTIN}
|
---|
650 | */
|
---|
651 | PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
|
---|
652 | {
|
---|
653 | Log2(("pitIOPortRead: uPort=%#x cb=%x\n", uPort, cb));
|
---|
654 | NOREF(pvUser);
|
---|
655 | uPort &= 3;
|
---|
656 | if (cb != 1 || uPort == 3)
|
---|
657 | {
|
---|
658 | Log(("pitIOPortRead: uPort=%#x cb=%x *pu32=unused!\n", uPort, cb));
|
---|
659 | return VERR_IOM_IOPORT_UNUSED;
|
---|
660 | }
|
---|
661 |
|
---|
662 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
663 | PPITCHANNEL pChan = &pThis->channels[uPort];
|
---|
664 | int ret;
|
---|
665 |
|
---|
666 | DEVPIT_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
|
---|
667 | if (pChan->status_latched)
|
---|
668 | {
|
---|
669 | pChan->status_latched = 0;
|
---|
670 | ret = pChan->status;
|
---|
671 | DEVPIT_UNLOCK(pThis);
|
---|
672 | }
|
---|
673 | else if (pChan->count_latched)
|
---|
674 | {
|
---|
675 | switch (pChan->count_latched)
|
---|
676 | {
|
---|
677 | default:
|
---|
678 | case RW_STATE_LSB:
|
---|
679 | ret = pChan->latched_count & 0xff;
|
---|
680 | pChan->count_latched = 0;
|
---|
681 | break;
|
---|
682 | case RW_STATE_MSB:
|
---|
683 | ret = pChan->latched_count >> 8;
|
---|
684 | pChan->count_latched = 0;
|
---|
685 | break;
|
---|
686 | case RW_STATE_WORD0:
|
---|
687 | ret = pChan->latched_count & 0xff;
|
---|
688 | pChan->count_latched = RW_STATE_MSB;
|
---|
689 | break;
|
---|
690 | }
|
---|
691 | DEVPIT_UNLOCK(pThis);
|
---|
692 | }
|
---|
693 | else
|
---|
694 | {
|
---|
695 | DEVPIT_UNLOCK(pThis);
|
---|
696 | DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
|
---|
697 | int count;
|
---|
698 | switch (pChan->read_state)
|
---|
699 | {
|
---|
700 | default:
|
---|
701 | case RW_STATE_LSB:
|
---|
702 | count = pit_get_count(pChan);
|
---|
703 | ret = count & 0xff;
|
---|
704 | break;
|
---|
705 | case RW_STATE_MSB:
|
---|
706 | count = pit_get_count(pChan);
|
---|
707 | ret = (count >> 8) & 0xff;
|
---|
708 | break;
|
---|
709 | case RW_STATE_WORD0:
|
---|
710 | count = pit_get_count(pChan);
|
---|
711 | ret = count & 0xff;
|
---|
712 | pChan->read_state = RW_STATE_WORD1;
|
---|
713 | break;
|
---|
714 | case RW_STATE_WORD1:
|
---|
715 | count = pit_get_count(pChan);
|
---|
716 | ret = (count >> 8) & 0xff;
|
---|
717 | pChan->read_state = RW_STATE_WORD0;
|
---|
718 | break;
|
---|
719 | }
|
---|
720 | DEVPIT_UNLOCK_BOTH(pThis);
|
---|
721 | }
|
---|
722 |
|
---|
723 | *pu32 = ret;
|
---|
724 | Log2(("pitIOPortRead: uPort=%#x cb=%x *pu32=%#04x\n", uPort, cb, *pu32));
|
---|
725 | return VINF_SUCCESS;
|
---|
726 | }
|
---|
727 |
|
---|
728 |
|
---|
729 | /**
|
---|
730 | * @callback_method_impl{FNIOMIOPORTOUT}
|
---|
731 | */
|
---|
732 | PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
|
---|
733 | {
|
---|
734 | Log2(("pitIOPortWrite: uPort=%#x cb=%x u32=%#04x\n", uPort, cb, u32));
|
---|
735 | NOREF(pvUser);
|
---|
736 | if (cb != 1)
|
---|
737 | return VINF_SUCCESS;
|
---|
738 |
|
---|
739 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
740 | uPort &= 3;
|
---|
741 | if (uPort == 3)
|
---|
742 | {
|
---|
743 | /*
|
---|
744 | * Port 43h - Mode/Command Register.
|
---|
745 | * 7 6 5 4 3 2 1 0
|
---|
746 | * * * . . . . . . Select channel: 0 0 = Channel 0
|
---|
747 | * 0 1 = Channel 1
|
---|
748 | * 1 0 = Channel 2
|
---|
749 | * 1 1 = Read-back command (8254 only)
|
---|
750 | * (Illegal on 8253)
|
---|
751 | * (Illegal on PS/2 {JAM})
|
---|
752 | * . . * * . . . . Command/Access mode: 0 0 = Latch count value command
|
---|
753 | * 0 1 = Access mode: lobyte only
|
---|
754 | * 1 0 = Access mode: hibyte only
|
---|
755 | * 1 1 = Access mode: lobyte/hibyte
|
---|
756 | * . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
|
---|
757 | * 0 1 0 = Mode 2, 0 1 1 = Mode 3,
|
---|
758 | * 1 0 0 = Mode 4, 1 0 1 = Mode 5,
|
---|
759 | * 1 1 0 = Mode 2, 1 1 1 = Mode 3
|
---|
760 | * . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
|
---|
761 | */
|
---|
762 | unsigned channel = u32 >> 6;
|
---|
763 | if (channel == 3)
|
---|
764 | {
|
---|
765 | /* read-back command */
|
---|
766 | DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
|
---|
767 | for (channel = 0; channel < RT_ELEMENTS(pThis->channels); channel++)
|
---|
768 | {
|
---|
769 | PPITCHANNEL pChan = &pThis->channels[channel];
|
---|
770 | if (u32 & (2 << channel)) {
|
---|
771 | if (!(u32 & 0x20))
|
---|
772 | pit_latch_count(pChan);
|
---|
773 | if (!(u32 & 0x10) && !pChan->status_latched)
|
---|
774 | {
|
---|
775 | /* status latch */
|
---|
776 | /* XXX: add BCD and null count */
|
---|
777 | PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
|
---|
778 | pChan->status = (pit_get_out1(pChan, TMTimerGet(pTimer)) << 7)
|
---|
779 | | (pChan->rw_mode << 4)
|
---|
780 | | (pChan->mode << 1)
|
---|
781 | | pChan->bcd;
|
---|
782 | pChan->status_latched = 1;
|
---|
783 | }
|
---|
784 | }
|
---|
785 | }
|
---|
786 | DEVPIT_UNLOCK_BOTH(pThis);
|
---|
787 | }
|
---|
788 | else
|
---|
789 | {
|
---|
790 | PPITCHANNEL pChan = &pThis->channels[channel];
|
---|
791 | unsigned access = (u32 >> 4) & 3;
|
---|
792 | if (access == 0)
|
---|
793 | {
|
---|
794 | DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
|
---|
795 | pit_latch_count(pChan);
|
---|
796 | DEVPIT_UNLOCK_BOTH(pThis);
|
---|
797 | }
|
---|
798 | else
|
---|
799 | {
|
---|
800 | DEVPIT_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
|
---|
801 | pChan->rw_mode = access;
|
---|
802 | pChan->read_state = access;
|
---|
803 | pChan->write_state = access;
|
---|
804 |
|
---|
805 | pChan->mode = (u32 >> 1) & 7;
|
---|
806 | pChan->bcd = u32 & 1;
|
---|
807 | /* XXX: update irq timer ? */
|
---|
808 | DEVPIT_UNLOCK(pThis);
|
---|
809 | }
|
---|
810 | }
|
---|
811 | }
|
---|
812 | else
|
---|
813 | {
|
---|
814 | #ifndef IN_RING3
|
---|
815 | /** @todo There is no reason not to do this in all contexts these
|
---|
816 | * days... */
|
---|
817 | return VINF_IOM_R3_IOPORT_WRITE;
|
---|
818 | #else /* IN_RING3 */
|
---|
819 | /*
|
---|
820 | * Port 40-42h - Channel Data Ports.
|
---|
821 | */
|
---|
822 | PPITCHANNEL pChan = &pThis->channels[uPort];
|
---|
823 | DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
|
---|
824 | switch (pChan->write_state)
|
---|
825 | {
|
---|
826 | default:
|
---|
827 | case RW_STATE_LSB:
|
---|
828 | pit_load_count(pChan, u32);
|
---|
829 | break;
|
---|
830 | case RW_STATE_MSB:
|
---|
831 | pit_load_count(pChan, u32 << 8);
|
---|
832 | break;
|
---|
833 | case RW_STATE_WORD0:
|
---|
834 | pChan->write_latch = u32;
|
---|
835 | pChan->write_state = RW_STATE_WORD1;
|
---|
836 | break;
|
---|
837 | case RW_STATE_WORD1:
|
---|
838 | pit_load_count(pChan, pChan->write_latch | (u32 << 8));
|
---|
839 | pChan->write_state = RW_STATE_WORD0;
|
---|
840 | break;
|
---|
841 | }
|
---|
842 | DEVPIT_UNLOCK_BOTH(pThis);
|
---|
843 | #endif /* !IN_RING3 */
|
---|
844 | }
|
---|
845 | return VINF_SUCCESS;
|
---|
846 | }
|
---|
847 |
|
---|
848 |
|
---|
849 | /**
|
---|
850 | * @callback_method_impl{FNIOMIOPORTIN, Speaker}
|
---|
851 | */
|
---|
852 | PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
|
---|
853 | {
|
---|
854 | RT_NOREF2(pvUser, uPort);
|
---|
855 | if (cb == 1)
|
---|
856 | {
|
---|
857 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
858 | DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
|
---|
859 |
|
---|
860 | const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
|
---|
861 | Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
|
---|
862 |
|
---|
863 | /* bit 6,7 Parity error stuff. */
|
---|
864 | /* bit 5 - mirrors timer 2 output condition. */
|
---|
865 | const int fOut = pit_get_out(pThis, 2, u64Now);
|
---|
866 | /* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 u-op Chan.
|
---|
867 | ASSUMES ns timer freq, see assertion above. */
|
---|
868 | #ifndef FAKE_REFRESH_CLOCK
|
---|
869 | const int fRefresh = (u64Now / 15085) & 1;
|
---|
870 | #else
|
---|
871 | pThis->dummy_refresh_clock ^= 1;
|
---|
872 | const int fRefresh = pThis->dummy_refresh_clock;
|
---|
873 | #endif
|
---|
874 | /* bit 2,3 NMI / parity status stuff. */
|
---|
875 | /* bit 1 - speaker data status */
|
---|
876 | const int fSpeakerStatus = pThis->speaker_data_on;
|
---|
877 | /* bit 0 - timer 2 clock gate to speaker status. */
|
---|
878 | const int fTimer2GateStatus = pit_get_gate(pThis, 2);
|
---|
879 |
|
---|
880 | DEVPIT_UNLOCK_BOTH(pThis);
|
---|
881 |
|
---|
882 | *pu32 = fTimer2GateStatus
|
---|
883 | | (fSpeakerStatus << 1)
|
---|
884 | | (fRefresh << 4)
|
---|
885 | | (fOut << 5);
|
---|
886 | Log(("pitIOPortSpeakerRead: uPort=%#x cb=%x *pu32=%#x\n", uPort, cb, *pu32));
|
---|
887 | return VINF_SUCCESS;
|
---|
888 | }
|
---|
889 | Log(("pitIOPortSpeakerRead: uPort=%#x cb=%x *pu32=unused!\n", uPort, cb));
|
---|
890 | return VERR_IOM_IOPORT_UNUSED;
|
---|
891 | }
|
---|
892 |
|
---|
893 | #ifdef IN_RING3
|
---|
894 |
|
---|
895 | /**
|
---|
896 | * @callback_method_impl{FNIOMIOPORTOUT, Speaker}
|
---|
897 | */
|
---|
898 | PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
|
---|
899 | {
|
---|
900 | RT_NOREF2(pvUser, uPort);
|
---|
901 | if (cb == 1)
|
---|
902 | {
|
---|
903 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
904 | DEVPIT_LOCK_BOTH_RETURN(pThis, VERR_IGNORED);
|
---|
905 |
|
---|
906 | pThis->speaker_data_on = (u32 >> 1) & 1;
|
---|
907 | pit_set_gate(pThis, 2, u32 & 1);
|
---|
908 |
|
---|
909 | /** @todo r=klaus move this to a (system-specific) driver, which can
|
---|
910 | * abstract the details, and if necessary create a thread to minimize
|
---|
911 | * impact on VM execution. */
|
---|
912 | #ifdef RT_OS_LINUX
|
---|
913 | if (pThis->enmSpeakerEmu != PIT_SPEAKER_EMU_NONE)
|
---|
914 | {
|
---|
915 | PPITCHANNEL pChan = &pThis->channels[2];
|
---|
916 | if (pThis->speaker_data_on)
|
---|
917 | {
|
---|
918 | Log2Func(("starting beep freq=%d\n", PIT_FREQ / pChan->count));
|
---|
919 | switch (pThis->enmSpeakerEmu)
|
---|
920 | {
|
---|
921 | case PIT_SPEAKER_EMU_CONSOLE:
|
---|
922 | {
|
---|
923 | int res;
|
---|
924 | res = ioctl(pThis->hHostSpeaker, KIOCSOUND, pChan->count);
|
---|
925 | if (res == -1)
|
---|
926 | {
|
---|
927 | LogRel(("PIT: speaker: ioctl failed errno=%d, disabling emulation\n", errno));
|
---|
928 | pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
|
---|
929 | }
|
---|
930 | break;
|
---|
931 | }
|
---|
932 | case PIT_SPEAKER_EMU_EVDEV:
|
---|
933 | {
|
---|
934 | struct input_event e;
|
---|
935 | e.type = EV_SND;
|
---|
936 | e.code = SND_TONE;
|
---|
937 | e.value = PIT_FREQ / pChan->count;
|
---|
938 | int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
|
---|
939 | NOREF(res);
|
---|
940 | break;
|
---|
941 | }
|
---|
942 | case PIT_SPEAKER_EMU_TTY:
|
---|
943 | {
|
---|
944 | int res = write(pThis->hHostSpeaker, "\a", 1);
|
---|
945 | NOREF(res);
|
---|
946 | break;
|
---|
947 | }
|
---|
948 | case PIT_SPEAKER_EMU_NONE:
|
---|
949 | break;
|
---|
950 | default:
|
---|
951 | Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
|
---|
952 | pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
|
---|
953 | }
|
---|
954 | }
|
---|
955 | else
|
---|
956 | {
|
---|
957 | Log2Func(("stopping beep\n"));
|
---|
958 | switch (pThis->enmSpeakerEmu)
|
---|
959 | {
|
---|
960 | case PIT_SPEAKER_EMU_CONSOLE:
|
---|
961 | /* No error checking here. The Linux device driver
|
---|
962 | * implementation considers it an error (errno=22,
|
---|
963 | * EINVAL) to stop sound if it hasn't been started.
|
---|
964 | * Of course we could detect this by checking only
|
---|
965 | * for enabled->disabled transitions and ignoring
|
---|
966 | * disabled->disabled ones, but it's not worth the
|
---|
967 | * effort. */
|
---|
968 | ioctl(pThis->hHostSpeaker, KIOCSOUND, 0);
|
---|
969 | break;
|
---|
970 | case PIT_SPEAKER_EMU_EVDEV:
|
---|
971 | {
|
---|
972 | struct input_event e;
|
---|
973 | e.type = EV_SND;
|
---|
974 | e.code = SND_TONE;
|
---|
975 | e.value = 0;
|
---|
976 | int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
|
---|
977 | NOREF(res);
|
---|
978 | break;
|
---|
979 | }
|
---|
980 | case PIT_SPEAKER_EMU_TTY:
|
---|
981 | break;
|
---|
982 | case PIT_SPEAKER_EMU_NONE:
|
---|
983 | break;
|
---|
984 | default:
|
---|
985 | Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
|
---|
986 | pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
|
---|
987 | }
|
---|
988 | }
|
---|
989 | }
|
---|
990 | #endif
|
---|
991 |
|
---|
992 | DEVPIT_UNLOCK_BOTH(pThis);
|
---|
993 | }
|
---|
994 | Log(("pitIOPortSpeakerWrite: uPort=%#x cb=%x u32=%#x\n", uPort, cb, u32));
|
---|
995 | return VINF_SUCCESS;
|
---|
996 | }
|
---|
997 |
|
---|
998 |
|
---|
999 | /* -=-=-=-=-=- Saved state -=-=-=-=-=- */
|
---|
1000 |
|
---|
1001 | /**
|
---|
1002 | * @callback_method_impl{FNSSMDEVLIVEEXEC}
|
---|
1003 | */
|
---|
1004 | static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
|
---|
1005 | {
|
---|
1006 | RT_NOREF1(uPass);
|
---|
1007 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
1008 | SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
|
---|
1009 | SSMR3PutU8( pSSM, pThis->channels[0].irq);
|
---|
1010 | SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
|
---|
1011 | return VINF_SSM_DONT_CALL_AGAIN;
|
---|
1012 | }
|
---|
1013 |
|
---|
1014 |
|
---|
1015 | /**
|
---|
1016 | * @callback_method_impl{FNSSMDEVSAVEEXEC}
|
---|
1017 | */
|
---|
1018 | static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
1019 | {
|
---|
1020 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
1021 | PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
|
---|
1022 |
|
---|
1023 | /* The config. */
|
---|
1024 | pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
|
---|
1025 |
|
---|
1026 | /* The state. */
|
---|
1027 | for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
|
---|
1028 | {
|
---|
1029 | PPITCHANNEL pChan = &pThis->channels[i];
|
---|
1030 | SSMR3PutU32(pSSM, pChan->count);
|
---|
1031 | SSMR3PutU16(pSSM, pChan->latched_count);
|
---|
1032 | SSMR3PutU8(pSSM, pChan->count_latched);
|
---|
1033 | SSMR3PutU8(pSSM, pChan->status_latched);
|
---|
1034 | SSMR3PutU8(pSSM, pChan->status);
|
---|
1035 | SSMR3PutU8(pSSM, pChan->read_state);
|
---|
1036 | SSMR3PutU8(pSSM, pChan->write_state);
|
---|
1037 | SSMR3PutU8(pSSM, pChan->write_latch);
|
---|
1038 | SSMR3PutU8(pSSM, pChan->rw_mode);
|
---|
1039 | SSMR3PutU8(pSSM, pChan->mode);
|
---|
1040 | SSMR3PutU8(pSSM, pChan->bcd);
|
---|
1041 | SSMR3PutU8(pSSM, pChan->gate);
|
---|
1042 | SSMR3PutU64(pSSM, pChan->count_load_time);
|
---|
1043 | SSMR3PutU64(pSSM, pChan->u64NextTS);
|
---|
1044 | SSMR3PutU64(pSSM, pChan->u64ReloadTS);
|
---|
1045 | SSMR3PutS64(pSSM, pChan->next_transition_time);
|
---|
1046 | if (pChan->CTX_SUFF(pTimer))
|
---|
1047 | TMR3TimerSave(pChan->CTX_SUFF(pTimer), pSSM);
|
---|
1048 | }
|
---|
1049 |
|
---|
1050 | SSMR3PutS32(pSSM, pThis->speaker_data_on);
|
---|
1051 | #ifdef FAKE_REFRESH_CLOCK
|
---|
1052 | SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
|
---|
1053 | #else
|
---|
1054 | SSMR3PutS32(pSSM, 0);
|
---|
1055 | #endif
|
---|
1056 |
|
---|
1057 | SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
|
---|
1058 |
|
---|
1059 | PDMCritSectLeave(&pThis->CritSect);
|
---|
1060 | return VINF_SUCCESS;
|
---|
1061 | }
|
---|
1062 |
|
---|
1063 |
|
---|
1064 | /**
|
---|
1065 | * @callback_method_impl{FNSSMDEVLOADEXEC}
|
---|
1066 | */
|
---|
1067 | static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
1068 | {
|
---|
1069 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
1070 | int rc;
|
---|
1071 |
|
---|
1072 | if ( uVersion != PIT_SAVED_STATE_VERSION
|
---|
1073 | && uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
|
---|
1074 | && uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
|
---|
1075 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
1076 |
|
---|
1077 | /* The config. */
|
---|
1078 | if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
|
---|
1079 | {
|
---|
1080 | RTIOPORT IOPortBaseCfg;
|
---|
1081 | rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
|
---|
1082 | if (IOPortBaseCfg != pThis->IOPortBaseCfg)
|
---|
1083 | return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
|
---|
1084 | IOPortBaseCfg, pThis->IOPortBaseCfg);
|
---|
1085 |
|
---|
1086 | uint8_t u8Irq;
|
---|
1087 | rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
|
---|
1088 | if (u8Irq != pThis->channels[0].irq)
|
---|
1089 | return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
|
---|
1090 | u8Irq, pThis->channels[0].irq);
|
---|
1091 |
|
---|
1092 | bool fSpeakerCfg;
|
---|
1093 | rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
|
---|
1094 | if (fSpeakerCfg != pThis->fSpeakerCfg)
|
---|
1095 | return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
|
---|
1096 | fSpeakerCfg, pThis->fSpeakerCfg);
|
---|
1097 | }
|
---|
1098 |
|
---|
1099 | if (uPass != SSM_PASS_FINAL)
|
---|
1100 | return VINF_SUCCESS;
|
---|
1101 |
|
---|
1102 | /* The state. */
|
---|
1103 | for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
|
---|
1104 | {
|
---|
1105 | PPITCHANNEL pChan = &pThis->channels[i];
|
---|
1106 | SSMR3GetU32(pSSM, &pChan->count);
|
---|
1107 | SSMR3GetU16(pSSM, &pChan->latched_count);
|
---|
1108 | SSMR3GetU8(pSSM, &pChan->count_latched);
|
---|
1109 | SSMR3GetU8(pSSM, &pChan->status_latched);
|
---|
1110 | SSMR3GetU8(pSSM, &pChan->status);
|
---|
1111 | SSMR3GetU8(pSSM, &pChan->read_state);
|
---|
1112 | SSMR3GetU8(pSSM, &pChan->write_state);
|
---|
1113 | SSMR3GetU8(pSSM, &pChan->write_latch);
|
---|
1114 | SSMR3GetU8(pSSM, &pChan->rw_mode);
|
---|
1115 | SSMR3GetU8(pSSM, &pChan->mode);
|
---|
1116 | SSMR3GetU8(pSSM, &pChan->bcd);
|
---|
1117 | SSMR3GetU8(pSSM, &pChan->gate);
|
---|
1118 | SSMR3GetU64(pSSM, &pChan->count_load_time);
|
---|
1119 | SSMR3GetU64(pSSM, &pChan->u64NextTS);
|
---|
1120 | SSMR3GetU64(pSSM, &pChan->u64ReloadTS);
|
---|
1121 | SSMR3GetS64(pSSM, &pChan->next_transition_time);
|
---|
1122 | if (pChan->CTX_SUFF(pTimer))
|
---|
1123 | {
|
---|
1124 | TMR3TimerLoad(pChan->CTX_SUFF(pTimer), pSSM);
|
---|
1125 | LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
|
---|
1126 | pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100, i));
|
---|
1127 | PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
|
---|
1128 | TMTimerSetFrequencyHint(pChan->CTX_SUFF(pTimer), PIT_FREQ / pChan->count);
|
---|
1129 | PDMCritSectLeave(&pThis->CritSect);
|
---|
1130 | }
|
---|
1131 | pThis->channels[i].cRelLogEntries = 0;
|
---|
1132 | }
|
---|
1133 |
|
---|
1134 | SSMR3GetS32(pSSM, &pThis->speaker_data_on);
|
---|
1135 | #ifdef FAKE_REFRESH_CLOCK
|
---|
1136 | SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
|
---|
1137 | #else
|
---|
1138 | int32_t u32Dummy;
|
---|
1139 | SSMR3GetS32(pSSM, &u32Dummy);
|
---|
1140 | #endif
|
---|
1141 | if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
|
---|
1142 | SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
|
---|
1143 |
|
---|
1144 | return VINF_SUCCESS;
|
---|
1145 | }
|
---|
1146 |
|
---|
1147 |
|
---|
1148 | /* -=-=-=-=-=- Timer -=-=-=-=-=- */
|
---|
1149 |
|
---|
1150 | /**
|
---|
1151 | * @callback_method_impl{FNTMTIMERDEV}
|
---|
1152 | * @param pvUser Pointer to the PIT channel state.
|
---|
1153 | */
|
---|
1154 | static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
|
---|
1155 | {
|
---|
1156 | RT_NOREF1(pDevIns);
|
---|
1157 | PPITCHANNEL pChan = (PPITCHANNEL)pvUser;
|
---|
1158 | STAM_PROFILE_ADV_START(&pChan->CTX_SUFF(pPit)->StatPITHandler, a);
|
---|
1159 |
|
---|
1160 | Log(("pitTimer\n"));
|
---|
1161 | Assert(PDMCritSectIsOwner(&PDMINS_2_DATA(pDevIns, PPITSTATE)->CritSect));
|
---|
1162 | Assert(TMTimerIsLockOwner(pTimer));
|
---|
1163 |
|
---|
1164 | pit_irq_timer_update(pChan, pChan->next_transition_time, TMTimerGet(pTimer), true);
|
---|
1165 |
|
---|
1166 | STAM_PROFILE_ADV_STOP(&pChan->CTX_SUFF(pPit)->StatPITHandler, a);
|
---|
1167 | }
|
---|
1168 |
|
---|
1169 |
|
---|
1170 | /* -=-=-=-=-=- Debug Info -=-=-=-=-=- */
|
---|
1171 |
|
---|
1172 | /**
|
---|
1173 | * @callback_method_impl{FNDBGFHANDLERDEV}
|
---|
1174 | */
|
---|
1175 | static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
1176 | {
|
---|
1177 | RT_NOREF1(pszArgs);
|
---|
1178 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
1179 | unsigned i;
|
---|
1180 | for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
|
---|
1181 | {
|
---|
1182 | const PITCHANNEL *pChan = &pThis->channels[i];
|
---|
1183 |
|
---|
1184 | pHlp->pfnPrintf(pHlp,
|
---|
1185 | "PIT (i8254) channel %d status: irq=%#x\n"
|
---|
1186 | " count=%08x" " latched_count=%04x count_latched=%02x\n"
|
---|
1187 | " status=%02x status_latched=%02x read_state=%02x\n"
|
---|
1188 | " write_state=%02x write_latch=%02x rw_mode=%02x\n"
|
---|
1189 | " mode=%02x bcd=%02x gate=%02x\n"
|
---|
1190 | " count_load_time=%016RX64 next_transition_time=%016RX64\n"
|
---|
1191 | " u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
|
---|
1192 | ,
|
---|
1193 | i, pChan->irq,
|
---|
1194 | pChan->count, pChan->latched_count, pChan->count_latched,
|
---|
1195 | pChan->status, pChan->status_latched, pChan->read_state,
|
---|
1196 | pChan->write_state, pChan->write_latch, pChan->rw_mode,
|
---|
1197 | pChan->mode, pChan->bcd, pChan->gate,
|
---|
1198 | pChan->count_load_time, pChan->next_transition_time,
|
---|
1199 | pChan->u64ReloadTS, pChan->u64NextTS);
|
---|
1200 | }
|
---|
1201 | #ifdef FAKE_REFRESH_CLOCK
|
---|
1202 | pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
|
---|
1203 | pThis->speaker_data_on, pThis->dummy_refresh_clock);
|
---|
1204 | #else
|
---|
1205 | pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
|
---|
1206 | #endif
|
---|
1207 | if (pThis->fDisabledByHpet)
|
---|
1208 | pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
|
---|
1209 | }
|
---|
1210 |
|
---|
1211 |
|
---|
1212 | /* -=-=-=-=-=- IHpetLegacyNotify -=-=-=-=-=- */
|
---|
1213 |
|
---|
1214 | /**
|
---|
1215 | * @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
|
---|
1216 | */
|
---|
1217 | static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
|
---|
1218 | {
|
---|
1219 | PPITSTATE pThis = RT_FROM_MEMBER(pInterface, PITSTATE, IHpetLegacyNotify);
|
---|
1220 | PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
|
---|
1221 |
|
---|
1222 | pThis->fDisabledByHpet = fActivated;
|
---|
1223 |
|
---|
1224 | PDMCritSectLeave(&pThis->CritSect);
|
---|
1225 | }
|
---|
1226 |
|
---|
1227 |
|
---|
1228 | /* -=-=-=-=-=- PDMDEVINS::IBase -=-=-=-=-=- */
|
---|
1229 |
|
---|
1230 | /**
|
---|
1231 | * @interface_method_impl{PDMIBASE,pfnQueryInterface}
|
---|
1232 | */
|
---|
1233 | static DECLCALLBACK(void *) pitQueryInterface(PPDMIBASE pInterface, const char *pszIID)
|
---|
1234 | {
|
---|
1235 | PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
|
---|
1236 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
1237 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
|
---|
1238 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
|
---|
1239 | return NULL;
|
---|
1240 | }
|
---|
1241 |
|
---|
1242 |
|
---|
1243 | /* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
|
---|
1244 |
|
---|
1245 | /**
|
---|
1246 | * @interface_method_impl{PDMDEVREG,pfnRelocate}
|
---|
1247 | */
|
---|
1248 | static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
|
---|
1249 | {
|
---|
1250 | RT_NOREF1(offDelta);
|
---|
1251 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
1252 | LogFlow(("pitRelocate: \n"));
|
---|
1253 |
|
---|
1254 | for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
|
---|
1255 | {
|
---|
1256 | PPITCHANNEL pChan = &pThis->channels[i];
|
---|
1257 | if (pChan->pTimerR3)
|
---|
1258 | pChan->pTimerRC = TMTimerRCPtr(pChan->pTimerR3);
|
---|
1259 | pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
|
---|
1260 | }
|
---|
1261 | }
|
---|
1262 |
|
---|
1263 |
|
---|
1264 | /**
|
---|
1265 | * @interface_method_impl{PDMDEVREG,pfnReset}
|
---|
1266 | */
|
---|
1267 | static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
|
---|
1268 | {
|
---|
1269 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
1270 | LogFlow(("pitReset: \n"));
|
---|
1271 |
|
---|
1272 | DEVPIT_R3_LOCK_BOTH(pThis);
|
---|
1273 |
|
---|
1274 | pThis->fDisabledByHpet = false;
|
---|
1275 |
|
---|
1276 | for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
|
---|
1277 | {
|
---|
1278 | PPITCHANNEL pChan = &pThis->channels[i];
|
---|
1279 |
|
---|
1280 | #if 1 /* Set everything back to virgin state. (might not be strictly correct) */
|
---|
1281 | pChan->latched_count = 0;
|
---|
1282 | pChan->count_latched = 0;
|
---|
1283 | pChan->status_latched = 0;
|
---|
1284 | pChan->status = 0;
|
---|
1285 | pChan->read_state = 0;
|
---|
1286 | pChan->write_state = 0;
|
---|
1287 | pChan->write_latch = 0;
|
---|
1288 | pChan->rw_mode = 0;
|
---|
1289 | pChan->bcd = 0;
|
---|
1290 | #endif
|
---|
1291 | pChan->u64NextTS = UINT64_MAX;
|
---|
1292 | pChan->cRelLogEntries = 0;
|
---|
1293 | pChan->mode = 3;
|
---|
1294 | pChan->gate = (i != 2);
|
---|
1295 | pit_load_count(pChan, 0);
|
---|
1296 | }
|
---|
1297 |
|
---|
1298 | DEVPIT_UNLOCK_BOTH(pThis);
|
---|
1299 | }
|
---|
1300 |
|
---|
1301 |
|
---|
1302 | /**
|
---|
1303 | * @interface_method_impl{PDMDEVREG,pfnConstruct}
|
---|
1304 | */
|
---|
1305 | static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
|
---|
1306 | {
|
---|
1307 | PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
|
---|
1308 | int rc;
|
---|
1309 | uint8_t u8Irq;
|
---|
1310 | uint16_t u16Base;
|
---|
1311 | bool fSpeaker;
|
---|
1312 | bool fGCEnabled;
|
---|
1313 | bool fR0Enabled;
|
---|
1314 | unsigned i;
|
---|
1315 | Assert(iInstance == 0);
|
---|
1316 |
|
---|
1317 | /*
|
---|
1318 | * Validate configuration.
|
---|
1319 | */
|
---|
1320 | if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0"
|
---|
1321 | "SpeakerEnabled\0" "PassthroughSpeaker\0" "PassthroughSpeakerDevice\0"
|
---|
1322 | "R0Enabled\0" "GCEnabled\0"))
|
---|
1323 | return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
|
---|
1324 |
|
---|
1325 | /*
|
---|
1326 | * Init the data.
|
---|
1327 | */
|
---|
1328 | rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
|
---|
1329 | if (RT_FAILURE(rc))
|
---|
1330 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
1331 | N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
|
---|
1332 |
|
---|
1333 | rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
|
---|
1334 | if (RT_FAILURE(rc))
|
---|
1335 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
1336 | N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
|
---|
1337 |
|
---|
1338 | rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
|
---|
1339 | if (RT_FAILURE(rc))
|
---|
1340 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
1341 | N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
|
---|
1342 |
|
---|
1343 | uint8_t uPassthroughSpeaker;
|
---|
1344 | char *pszPassthroughSpeakerDevice = NULL;
|
---|
1345 | rc = CFGMR3QueryU8Def(pCfg, "PassthroughSpeaker", &uPassthroughSpeaker, 0);
|
---|
1346 | if (RT_FAILURE(rc))
|
---|
1347 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
1348 | N_("Configuration error: failed to read PassthroughSpeaker as uint8_t"));
|
---|
1349 | if (uPassthroughSpeaker)
|
---|
1350 | {
|
---|
1351 | rc = CFGMR3QueryStringAllocDef(pCfg, "PassthroughSpeakerDevice", &pszPassthroughSpeakerDevice, NULL);
|
---|
1352 | if (RT_FAILURE(rc))
|
---|
1353 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
1354 | N_("Configuration error: failed to read PassthroughSpeakerDevice as string"));
|
---|
1355 | }
|
---|
1356 |
|
---|
1357 | rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
|
---|
1358 | if (RT_FAILURE(rc))
|
---|
1359 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
1360 | N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
|
---|
1361 |
|
---|
1362 | rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
|
---|
1363 | if (RT_FAILURE(rc))
|
---|
1364 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
1365 | N_("Configuration error: failed to read R0Enabled as boolean"));
|
---|
1366 |
|
---|
1367 | pThis->pDevIns = pDevIns;
|
---|
1368 | pThis->IOPortBaseCfg = u16Base;
|
---|
1369 | pThis->fSpeakerCfg = fSpeaker;
|
---|
1370 | pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
|
---|
1371 | if (uPassthroughSpeaker)
|
---|
1372 | {
|
---|
1373 | /** @todo r=klaus move this to a (system-specific) driver */
|
---|
1374 | #ifdef RT_OS_LINUX
|
---|
1375 | int fd = -1;
|
---|
1376 | if ((uPassthroughSpeaker == 1 || uPassthroughSpeaker == 100) && fd == -1)
|
---|
1377 | fd = pitTryDeviceOpenSanitizeIoctl("/dev/input/by-path/platform-pcspkr-event-spkr", O_WRONLY);
|
---|
1378 | if ((uPassthroughSpeaker == 2 || uPassthroughSpeaker == 100) && fd == -1)
|
---|
1379 | fd = pitTryDeviceOpenSanitizeIoctl("/dev/tty", O_WRONLY);
|
---|
1380 | if ((uPassthroughSpeaker == 3 || uPassthroughSpeaker == 100) && fd == -1)
|
---|
1381 | {
|
---|
1382 | fd = pitTryDeviceOpenSanitizeIoctl("/dev/tty0", O_WRONLY);
|
---|
1383 | if (fd == -1)
|
---|
1384 | fd = pitTryDeviceOpenSanitizeIoctl("/dev/vc/0", O_WRONLY);
|
---|
1385 | }
|
---|
1386 | if ((uPassthroughSpeaker == 9 || uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
|
---|
1387 | fd = pitTryDeviceOpenSanitizeIoctl(pszPassthroughSpeakerDevice, O_WRONLY);
|
---|
1388 | if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
|
---|
1389 | {
|
---|
1390 | pThis->hHostSpeaker = fd;
|
---|
1391 | if (ioctl(fd, EVIOCGSND(0)) != -1)
|
---|
1392 | {
|
---|
1393 | pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_EVDEV;
|
---|
1394 | LogRel(("PIT: speaker: emulation mode evdev\n"));
|
---|
1395 | }
|
---|
1396 | else
|
---|
1397 | {
|
---|
1398 | pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_CONSOLE;
|
---|
1399 | LogRel(("PIT: speaker: emulation mode console\n"));
|
---|
1400 | }
|
---|
1401 | }
|
---|
1402 | if ((uPassthroughSpeaker == 70 || uPassthroughSpeaker == 100) && fd == -1)
|
---|
1403 | fd = pitTryDeviceOpen("/dev/tty", O_WRONLY);
|
---|
1404 | if ((uPassthroughSpeaker == 79 || uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
|
---|
1405 | fd = pitTryDeviceOpen(pszPassthroughSpeakerDevice, O_WRONLY);
|
---|
1406 | if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
|
---|
1407 | {
|
---|
1408 | pThis->hHostSpeaker = fd;
|
---|
1409 | pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_TTY;
|
---|
1410 | LogRel(("PIT: speaker: emulation mode tty\n"));
|
---|
1411 | }
|
---|
1412 | if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE)
|
---|
1413 | {
|
---|
1414 | Assert(fd == -1);
|
---|
1415 | LogRel(("PIT: speaker: no emulation possible\n"));
|
---|
1416 | }
|
---|
1417 | #else
|
---|
1418 | LogRel(("PIT: speaker: emulation deactivated\n"));
|
---|
1419 | #endif
|
---|
1420 | if (pszPassthroughSpeakerDevice)
|
---|
1421 | {
|
---|
1422 | MMR3HeapFree(pszPassthroughSpeakerDevice);
|
---|
1423 | pszPassthroughSpeakerDevice = NULL;
|
---|
1424 | }
|
---|
1425 | }
|
---|
1426 | pThis->channels[0].irq = u8Irq;
|
---|
1427 | for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
|
---|
1428 | {
|
---|
1429 | pThis->channels[i].pPitR3 = pThis;
|
---|
1430 | pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
|
---|
1431 | pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
|
---|
1432 | }
|
---|
1433 |
|
---|
1434 | /*
|
---|
1435 | * Interfaces
|
---|
1436 | */
|
---|
1437 | /* IBase */
|
---|
1438 | pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
|
---|
1439 | /* IHpetLegacyNotify */
|
---|
1440 | pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
|
---|
1441 |
|
---|
1442 | /*
|
---|
1443 | * We do our own locking. This must be done before creating timers.
|
---|
1444 | */
|
---|
1445 | rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "pit#%u", iInstance);
|
---|
1446 | AssertRCReturn(rc, rc);
|
---|
1447 |
|
---|
1448 | rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
|
---|
1449 | AssertRCReturn(rc, rc);
|
---|
1450 |
|
---|
1451 | /*
|
---|
1452 | * Create the timer, make it take our critsect.
|
---|
1453 | */
|
---|
1454 | rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
|
---|
1455 | TMTIMER_FLAGS_NO_CRIT_SECT, "i8254 Programmable Interval Timer",
|
---|
1456 | &pThis->channels[0].pTimerR3);
|
---|
1457 | if (RT_FAILURE(rc))
|
---|
1458 | return rc;
|
---|
1459 | pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
|
---|
1460 | pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
|
---|
1461 | rc = TMR3TimerSetCritSect(pThis->channels[0].pTimerR3, &pThis->CritSect);
|
---|
1462 | AssertRCReturn(rc, rc);
|
---|
1463 |
|
---|
1464 | /*
|
---|
1465 | * Register I/O ports.
|
---|
1466 | */
|
---|
1467 | rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
|
---|
1468 | if (RT_FAILURE(rc))
|
---|
1469 | return rc;
|
---|
1470 | if (fGCEnabled)
|
---|
1471 | {
|
---|
1472 | rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
|
---|
1473 | if (RT_FAILURE(rc))
|
---|
1474 | return rc;
|
---|
1475 | }
|
---|
1476 | if (fR0Enabled)
|
---|
1477 | {
|
---|
1478 | rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
|
---|
1479 | if (RT_FAILURE(rc))
|
---|
1480 | return rc;
|
---|
1481 | }
|
---|
1482 |
|
---|
1483 | if (fSpeaker)
|
---|
1484 | {
|
---|
1485 | rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
|
---|
1486 | if (RT_FAILURE(rc))
|
---|
1487 | return rc;
|
---|
1488 | if (fGCEnabled)
|
---|
1489 | {
|
---|
1490 | rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
|
---|
1491 | if (RT_FAILURE(rc))
|
---|
1492 | return rc;
|
---|
1493 | }
|
---|
1494 | }
|
---|
1495 |
|
---|
1496 | /*
|
---|
1497 | * Saved state.
|
---|
1498 | */
|
---|
1499 | rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
|
---|
1500 | if (RT_FAILURE(rc))
|
---|
1501 | return rc;
|
---|
1502 |
|
---|
1503 | /*
|
---|
1504 | * Initialize the device state.
|
---|
1505 | */
|
---|
1506 | pitReset(pDevIns);
|
---|
1507 |
|
---|
1508 | /*
|
---|
1509 | * Register statistics and debug info.
|
---|
1510 | */
|
---|
1511 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
|
---|
1512 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
|
---|
1513 |
|
---|
1514 | PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
|
---|
1515 |
|
---|
1516 | return VINF_SUCCESS;
|
---|
1517 | }
|
---|
1518 |
|
---|
1519 |
|
---|
1520 | /**
|
---|
1521 | * The device registration structure.
|
---|
1522 | */
|
---|
1523 | const PDMDEVREG g_DeviceI8254 =
|
---|
1524 | {
|
---|
1525 | /* u32Version */
|
---|
1526 | PDM_DEVREG_VERSION,
|
---|
1527 | /* szName */
|
---|
1528 | "i8254",
|
---|
1529 | /* szRCMod */
|
---|
1530 | "VBoxDDRC.rc",
|
---|
1531 | /* szR0Mod */
|
---|
1532 | "VBoxDDR0.r0",
|
---|
1533 | /* pszDescription */
|
---|
1534 | "Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
|
---|
1535 | /* fFlags */
|
---|
1536 | PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
|
---|
1537 | /* fClass */
|
---|
1538 | PDM_DEVREG_CLASS_PIT,
|
---|
1539 | /* cMaxInstances */
|
---|
1540 | 1,
|
---|
1541 | /* cbInstance */
|
---|
1542 | sizeof(PITSTATE),
|
---|
1543 | /* pfnConstruct */
|
---|
1544 | pitConstruct,
|
---|
1545 | /* pfnDestruct */
|
---|
1546 | NULL,
|
---|
1547 | /* pfnRelocate */
|
---|
1548 | pitRelocate,
|
---|
1549 | /* pfnMemSetup */
|
---|
1550 | NULL,
|
---|
1551 | /* pfnPowerOn */
|
---|
1552 | NULL,
|
---|
1553 | /* pfnReset */
|
---|
1554 | pitReset,
|
---|
1555 | /* pfnSuspend */
|
---|
1556 | NULL,
|
---|
1557 | /* pfnResume */
|
---|
1558 | NULL,
|
---|
1559 | /* pfnAttach */
|
---|
1560 | NULL,
|
---|
1561 | /* pfnDetach */
|
---|
1562 | NULL,
|
---|
1563 | /* pfnQueryInterface */
|
---|
1564 | NULL,
|
---|
1565 | /* pfnInitComplete */
|
---|
1566 | NULL,
|
---|
1567 | /* pfnPowerOff */
|
---|
1568 | NULL,
|
---|
1569 | /* pfnSoftReset */
|
---|
1570 | NULL,
|
---|
1571 | /* u32VersionEnd */
|
---|
1572 | PDM_DEVREG_VERSION
|
---|
1573 | };
|
---|
1574 |
|
---|
1575 | #endif /* IN_RING3 */
|
---|
1576 | #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
|
---|