DevPit-i8254.cpp@ 18719

Last change on this file since 18719 was 16158, checked in by vboxsync, 16 years ago
reapplied PIT fix from 41876
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 37.0 KB

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1	/* $Id: DevPit-i8254.cpp 16158 2009-01-22 10:21:12Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	* --------------------------------------------------------------------
21	*
22	* This code is based on:
23	*
24	* QEMU 8253/8254 interval timer emulation
25	*
26	* Copyright (c) 2003-2004 Fabrice Bellard
27	*
28	* Permission is hereby granted, free of charge, to any person obtaining a copy
29	* of this software and associated documentation files (the "Software"), to deal
30	* in the Software without restriction, including without limitation the rights
31	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32	* copies of the Software, and to permit persons to whom the Software is
33	* furnished to do so, subject to the following conditions:
34	*
35	* The above copyright notice and this permission notice shall be included in
36	* all copies or substantial portions of the Software.
37	*
38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44	* THE SOFTWARE.
45	*/
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_PIT
51	#include <VBox/pdmdev.h>
52	#include <VBox/log.h>
53	#include <VBox/stam.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm.h>
56
57	#include "../Builtins.h"
58
59
60	/*******************************************************************************
61	* Defined Constants And Macros *
62	*******************************************************************************/
63	/** The PIT frequency. */
64	#define PIT_FREQ 1193182
65
66	#define RW_STATE_LSB 1
67	#define RW_STATE_MSB 2
68	#define RW_STATE_WORD0 3
69	#define RW_STATE_WORD1 4
70
71	/** The version of the saved state. */
72	#define PIT_SAVED_STATE_VERSION 2
73
74	/** @def FAKE_REFRESH_CLOCK
75	* Define this to flip the 15usec refresh bit on every read.
76	* If not defined, it will be flipped correctly. */
77	/* #define FAKE_REFRESH_CLOCK */
78	#ifdef DOXYGEN_RUNNING
79	# define FAKE_REFRESH_CLOCK
80	#endif
81
82
83	/*******************************************************************************
84	* Structures and Typedefs *
85	*******************************************************************************/
86	typedef struct PITChannelState
87	{
88	/** Pointer to the instance data - R3 Ptr. */
89	R3PTRTYPE(struct PITState *) pPitR3;
90	/** The timer - R3 Ptr. */
91	PTMTIMERR3 pTimerR3;
92	/** Pointer to the instance data - R0 Ptr. */
93	R0PTRTYPE(struct PITState *) pPitR0;
94	/** The timer - R0 Ptr. */
95	PTMTIMERR0 pTimerR0;
96	/** Pointer to the instance data - RC Ptr. */
97	RCPTRTYPE(struct PITState *) pPitRC;
98	/** The timer - RC Ptr. */
99	PTMTIMERRC pTimerRC;
100	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
101	uint64_t u64ReloadTS;
102	/** The actual time of the next tick.
103	* As apposed to the next_transition_time which contains the correct time of the next tick. */
104	uint64_t u64NextTS;
105
106	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
107	uint64_t count_load_time;
108	/* irq handling */
109	int64_t next_transition_time;
110	int32_t irq;
111	/** Number of release log entries. Used to prevent floading. */
112	uint32_t cRelLogEntries;
113
114	uint32_t count; /* can be 65536 */
115	uint16_t latched_count;
116	uint8_t count_latched;
117	uint8_t status_latched;
118
119	uint8_t status;
120	uint8_t read_state;
121	uint8_t write_state;
122	uint8_t write_latch;
123
124	uint8_t rw_mode;
125	uint8_t mode;
126	uint8_t bcd; /* not supported */
127	uint8_t gate; /* timer start */
128
129	} PITChannelState;
130
131	typedef struct PITState
132	{
133	PITChannelState channels[3];
134	/** Speaker data. */
135	int32_t speaker_data_on;
136	#ifdef FAKE_REFRESH_CLOCK
137	/** Speaker dummy. */
138	int32_t dummy_refresh_clock;
139	#else
140	uint32_t Alignment1;
141	#endif
142	/** Pointer to the device instance. */
143	PPDMDEVINSR3 pDevIns;
144	#if HC_ARCH_BITS == 32
145	uint32_t Alignment0;
146	#endif
147	/** Number of IRQs that's been raised. */
148	STAMCOUNTER StatPITIrq;
149	/** Profiling the timer callback handler. */
150	STAMPROFILEADV StatPITHandler;
151	} PITState;
152
153
154	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
155	/*******************************************************************************
156	* Internal Functions *
157	*******************************************************************************/
158	__BEGIN_DECLS
159	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
160	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
161	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
162	#ifdef IN_RING3
163	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
164	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
165	#endif
166	__END_DECLS
167
168
169
170
171	static int pit_get_count(PITChannelState *s)
172	{
173	uint64_t d;
174	int counter;
175	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
176
177	if (s->mode == 2)
178	{
179	if (s->u64NextTS == UINT64_MAX)
180	{
181	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
182	return s->count - (d % s->count); /** @todo check this value. */
183	}
184	d = TMTimerGet(pTimer);
185	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
186	if (d >= s->count)
187	return 1;
188	return s->count - d;
189	}
190	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
191	switch(s->mode) {
192	case 0:
193	case 1:
194	case 4:
195	case 5:
196	counter = (s->count - d) & 0xffff;
197	break;
198	case 3:
199	/* XXX: may be incorrect for odd counts */
200	counter = s->count - ((2 * d) % s->count);
201	break;
202	default:
203	counter = s->count - (d % s->count);
204	break;
205	}
206	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
207	return counter;
208	}
209
210	/* get pit output bit */
211	static int pit_get_out1(PITChannelState *s, int64_t current_time)
212	{
213	uint64_t d;
214	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
215	int out;
216
217	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
218	switch(s->mode) {
219	default:
220	case 0:
221	out = (d >= s->count);
222	break;
223	case 1:
224	out = (d < s->count);
225	break;
226	case 2:
227	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
228	if ((d % s->count) == 0 && d != 0)
229	out = 1;
230	else
231	out = 0;
232	break;
233	case 3:
234	out = (d % s->count) < ((s->count + 1) >> 1);
235	break;
236	case 4:
237	case 5:
238	out = (d == s->count);
239	break;
240	}
241	return out;
242	}
243
244
245	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
246	{
247	PITChannelState *s = &pit->channels[channel];
248	return pit_get_out1(s, current_time);
249	}
250
251
252	static int pit_get_gate(PITState *pit, int channel)
253	{
254	PITChannelState *s = &pit->channels[channel];
255	return s->gate;
256	}
257
258
259	/* if already latched, do not latch again */
260	static void pit_latch_count(PITChannelState *s)
261	{
262	if (!s->count_latched) {
263	s->latched_count = pit_get_count(s);
264	s->count_latched = s->rw_mode;
265	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
266	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
267	}
268	}
269
270	#ifdef IN_RING3
271
272	/* val must be 0 or 1 */
273	static void pit_set_gate(PITState *pit, int channel, int val)
274	{
275	PITChannelState *s = &pit->channels[channel];
276	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
277	Assert((val & 1) == val);
278
279	switch(s->mode) {
280	default:
281	case 0:
282	case 4:
283	/* XXX: just disable/enable counting */
284	break;
285	case 1:
286	case 5:
287	if (s->gate < val) {
288	/* restart counting on rising edge */
289	s->count_load_time = TMTimerGet(pTimer);
290	pit_irq_timer_update(s, s->count_load_time);
291	}
292	break;
293	case 2:
294	case 3:
295	if (s->gate < val) {
296	/* restart counting on rising edge */
297	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
298	pit_irq_timer_update(s, s->count_load_time);
299	}
300	/* XXX: disable/enable counting */
301	break;
302	}
303	s->gate = val;
304	}
305
306	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
307	{
308	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
309	if (val == 0)
310	val = 0x10000;
311	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
312	s->count = val;
313	pit_irq_timer_update(s, s->count_load_time);
314
315	/* log the new rate (ch 0 only). */
316	if ( s->pTimerR3 /* ch 0 */
317	&& s->cRelLogEntries++ < 32)
318	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
319	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
320	}
321
322	/* return -1 if no transition will occur. */
323	static int64_t pit_get_next_transition_time(PITChannelState *s,
324	uint64_t current_time)
325	{
326	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
327	uint64_t d, next_time, base;
328	uint32_t period2;
329
330	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
331	switch(s->mode) {
332	default:
333	case 0:
334	case 1:
335	if (d < s->count)
336	next_time = s->count;
337	else
338	return -1;
339	break;
340	/*
341	* Mode 2: The period is count + 1 PIT ticks.
342	* When the counter reaches 1 we sent the output low (for channel 0 that
343	* means raise an irq). On the next tick, where we should be decrementing
344	* from 1 to 0, the count is loaded and the output goes high (channel 0
345	* means clearing the irq).
346	*
347	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
348	* the irq. We also don't set it until we reach 0, which is a tick late - will
349	* try fix that later some day.
350	*/
351	case 2:
352	base = (d / s->count) * s->count;
353	#ifndef VBOX /* see above */
354	if ((d - base) == 0 && d != 0)
355	next_time = base + s->count;
356	else
357	#endif
358	next_time = base + s->count + 1;
359	break;
360	case 3:
361	base = (d / s->count) * s->count;
362	period2 = ((s->count + 1) >> 1);
363	if ((d - base) < period2)
364	next_time = base + period2;
365	else
366	next_time = base + s->count;
367	break;
368	case 4:
369	case 5:
370	if (d < s->count)
371	next_time = s->count;
372	else if (d == s->count)
373	next_time = s->count + 1;
374	else
375	return -1;
376	break;
377	}
378	/* convert to timer units */
379	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
380	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
381	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
382	/* fix potential rounding problems */
383	/* XXX: better solution: use a clock at PIT_FREQ Hz */
384	if (next_time <= current_time)
385	next_time = current_time + 1;
386	return next_time;
387	}
388
389	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
390	{
391	uint64_t now;
392	int64_t expire_time;
393	int irq_level;
394	PPDMDEVINS pDevIns;
395	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
396
397	if (!s->CTX_SUFF(pTimer))
398	return;
399	expire_time = pit_get_next_transition_time(s, current_time);
400	irq_level = pit_get_out1(s, current_time);
401
402	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
403	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
404	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
405	if (irq_level)
406	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
407	now = TMTimerGet(pTimer);
408	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
409	if (irq_level)
410	{
411	s->u64ReloadTS = now;
412	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
413	}
414
415	if (expire_time != -1)
416	{
417	s->u64NextTS = expire_time;
418	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
419	}
420	else
421	{
422	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
423	TMTimerStop(s->CTX_SUFF(pTimer));
424	s->u64NextTS = UINT64_MAX;
425	}
426	s->next_transition_time = expire_time;
427	}
428
429	#endif /* IN_RING3 */
430
431
432	/**
433	* Port I/O Handler for IN operations.
434	*
435	* @returns VBox status code.
436	*
437	* @param pDevIns The device instance.
438	* @param pvUser User argument - ignored.
439	* @param Port Port number used for the IN operation.
440	* @param pu32 Where to store the result.
441	* @param cb Number of bytes read.
442	*/
443	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
444	{
445	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
446	NOREF(pvUser);
447	Port &= 3;
448	if (cb != 1 \|\| Port == 3)
449	{
450	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
451	return VERR_IOM_IOPORT_UNUSED;
452	}
453
454	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
455	int ret;
456	PITChannelState *s = &pit->channels[Port];
457	if (s->status_latched)
458	{
459	s->status_latched = 0;
460	ret = s->status;
461	}
462	else if (s->count_latched)
463	{
464	switch (s->count_latched)
465	{
466	default:
467	case RW_STATE_LSB:
468	ret = s->latched_count & 0xff;
469	s->count_latched = 0;
470	break;
471	case RW_STATE_MSB:
472	ret = s->latched_count >> 8;
473	s->count_latched = 0;
474	break;
475	case RW_STATE_WORD0:
476	ret = s->latched_count & 0xff;
477	s->count_latched = RW_STATE_MSB;
478	break;
479	}
480	}
481	else
482	{
483	int count;
484	switch (s->read_state)
485	{
486	default:
487	case RW_STATE_LSB:
488	count = pit_get_count(s);
489	ret = count & 0xff;
490	break;
491	case RW_STATE_MSB:
492	count = pit_get_count(s);
493	ret = (count >> 8) & 0xff;
494	break;
495	case RW_STATE_WORD0:
496	count = pit_get_count(s);
497	ret = count & 0xff;
498	s->read_state = RW_STATE_WORD1;
499	break;
500	case RW_STATE_WORD1:
501	count = pit_get_count(s);
502	ret = (count >> 8) & 0xff;
503	s->read_state = RW_STATE_WORD0;
504	break;
505	}
506	}
507
508	*pu32 = ret;
509	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
510	return VINF_SUCCESS;
511	}
512
513
514	/**
515	* Port I/O Handler for OUT operations.
516	*
517	* @returns VBox status code.
518	*
519	* @param pDevIns The device instance.
520	* @param pvUser User argument - ignored.
521	* @param Port Port number used for the IN operation.
522	* @param u32 The value to output.
523	* @param cb The value size in bytes.
524	*/
525	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
526	{
527	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
528	NOREF(pvUser);
529	if (cb != 1)
530	return VINF_SUCCESS;
531
532	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
533	Port &= 3;
534	if (Port == 3)
535	{
536	/*
537	* Port 43h - Mode/Command Register.
538	* 7 6 5 4 3 2 1 0
539	* * * . . . . . . Select channel: 0 0 = Channel 0
540	* 0 1 = Channel 1
541	* 1 0 = Channel 2
542	* 1 1 = Read-back command (8254 only)
543	* (Illegal on 8253)
544	* (Illegal on PS/2 {JAM})
545	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
546	* 0 1 = Access mode: lobyte only
547	* 1 0 = Access mode: hibyte only
548	* 1 1 = Access mode: lobyte/hibyte
549	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
550	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
551	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
552	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
553	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
554	*/
555	unsigned channel = u32 >> 6;
556	if (channel == 3)
557	{
558	/* read-back command */
559	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
560	{
561	PITChannelState *s = &pit->channels[channel];
562	if (u32 & (2 << channel)) {
563	if (!(u32 & 0x20))
564	pit_latch_count(s);
565	if (!(u32 & 0x10) && !s->status_latched)
566	{
567	/* status latch */
568	/* XXX: add BCD and null count */
569	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
570	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
571	\| (s->rw_mode << 4)
572	\| (s->mode << 1)
573	\| s->bcd;
574	s->status_latched = 1;
575	}
576	}
577	}
578	}
579	else
580	{
581	PITChannelState *s = &pit->channels[channel];
582	unsigned access = (u32 >> 4) & 3;
583	if (access == 0)
584	pit_latch_count(s);
585	else
586	{
587	s->rw_mode = access;
588	s->read_state = access;
589	s->write_state = access;
590
591	s->mode = (u32 >> 1) & 7;
592	s->bcd = u32 & 1;
593	/* XXX: update irq timer ? */
594	}
595	}
596	}
597	else
598	{
599	#ifndef IN_RING3
600	return VINF_IOM_HC_IOPORT_WRITE;
601	#else /* IN_RING3 */
602	/*
603	* Port 40-42h - Channel Data Ports.
604	*/
605	PITChannelState *s = &pit->channels[Port];
606	switch(s->write_state)
607	{
608	default:
609	case RW_STATE_LSB:
610	pit_load_count(s, u32);
611	break;
612	case RW_STATE_MSB:
613	pit_load_count(s, u32 << 8);
614	break;
615	case RW_STATE_WORD0:
616	s->write_latch = u32;
617	s->write_state = RW_STATE_WORD1;
618	break;
619	case RW_STATE_WORD1:
620	pit_load_count(s, s->write_latch \| (u32 << 8));
621	s->write_state = RW_STATE_WORD0;
622	break;
623	}
624	#endif /* !IN_RING3 */
625	}
626	return VINF_SUCCESS;
627	}
628
629
630	/**
631	* Port I/O Handler for speaker IN operations.
632	*
633	* @returns VBox status code.
634	*
635	* @param pDevIns The device instance.
636	* @param pvUser User argument - ignored.
637	* @param Port Port number used for the IN operation.
638	* @param pu32 Where to store the result.
639	* @param cb Number of bytes read.
640	*/
641	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
642	{
643	NOREF(pvUser);
644	if (cb == 1)
645	{
646	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
647	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
648	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
649
650	/* bit 6,7 Parity error stuff. */
651	/* bit 5 - mirrors timer 2 output condition. */
652	const int fOut = pit_get_out(pThis, 2, u64Now);
653	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
654	ASSUMES ns timer freq, see assertion above. */
655	#ifndef FAKE_REFRESH_CLOCK
656	const int fRefresh = (u64Now / 15085) & 1;
657	#else
658	pThis->dummy_refresh_clock ^= 1;
659	const int fRefresh = pThis->dummy_refresh_clock;
660	#endif
661	/* bit 2,3 NMI / parity status stuff. */
662	/* bit 1 - speaker data status */
663	const int fSpeakerStatus = pThis->speaker_data_on;
664	/* bit 0 - timer 2 clock gate to speaker status. */
665	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
666
667	*pu32 = fTimer2GateStatus
668	\| (fSpeakerStatus << 1)
669	\| (fRefresh << 4)
670	\| (fOut << 5);
671	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
672	return VINF_SUCCESS;
673	}
674	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
675	return VERR_IOM_IOPORT_UNUSED;
676	}
677
678	#ifdef IN_RING3
679
680	/**
681	* Port I/O Handler for speaker OUT operations.
682	*
683	* @returns VBox status code.
684	*
685	* @param pDevIns The device instance.
686	* @param pvUser User argument - ignored.
687	* @param Port Port number used for the IN operation.
688	* @param u32 The value to output.
689	* @param cb The value size in bytes.
690	*/
691	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
692	{
693	NOREF(pvUser);
694	if (cb == 1)
695	{
696	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
697	pThis->speaker_data_on = (u32 >> 1) & 1;
698	pit_set_gate(pThis, 2, u32 & 1);
699	}
700	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
701	return VINF_SUCCESS;
702	}
703
704
705	/**
706	* Saves a state of the programmable interval timer device.
707	*
708	* @returns VBox status code.
709	* @param pDevIns The device instance.
710	* @param pSSMHandle The handle to save the state to.
711	*/
712	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
713	{
714	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
715	unsigned i;
716
717	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
718	{
719	PITChannelState *s = &pThis->channels[i];
720	SSMR3PutU32(pSSMHandle, s->count);
721	SSMR3PutU16(pSSMHandle, s->latched_count);
722	SSMR3PutU8(pSSMHandle, s->count_latched);
723	SSMR3PutU8(pSSMHandle, s->status_latched);
724	SSMR3PutU8(pSSMHandle, s->status);
725	SSMR3PutU8(pSSMHandle, s->read_state);
726	SSMR3PutU8(pSSMHandle, s->write_state);
727	SSMR3PutU8(pSSMHandle, s->write_latch);
728	SSMR3PutU8(pSSMHandle, s->rw_mode);
729	SSMR3PutU8(pSSMHandle, s->mode);
730	SSMR3PutU8(pSSMHandle, s->bcd);
731	SSMR3PutU8(pSSMHandle, s->gate);
732	SSMR3PutU64(pSSMHandle, s->count_load_time);
733	SSMR3PutU64(pSSMHandle, s->u64NextTS);
734	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
735	SSMR3PutS64(pSSMHandle, s->next_transition_time);
736	if (s->CTX_SUFF(pTimer))
737	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSMHandle);
738	}
739
740	SSMR3PutS32(pSSMHandle, pThis->speaker_data_on);
741	#ifdef FAKE_REFRESH_CLOCK
742	return SSMR3PutS32(pSSMHandle, pThis->dummy_refresh_clock);
743	#else
744	return SSMR3PutS32(pSSMHandle, 0);
745	#endif
746	}
747
748
749	/**
750	* Loads a saved programmable interval timer device state.
751	*
752	* @returns VBox status code.
753	* @param pDevIns The device instance.
754	* @param pSSMHandle The handle to the saved state.
755	* @param u32Version The data unit version number.
756	*/
757	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
758	{
759	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
760	unsigned i;
761
762	if (u32Version != PIT_SAVED_STATE_VERSION)
763	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
764
765	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
766	{
767	PITChannelState *s = &pThis->channels[i];
768	SSMR3GetU32(pSSMHandle, &s->count);
769	SSMR3GetU16(pSSMHandle, &s->latched_count);
770	SSMR3GetU8(pSSMHandle, &s->count_latched);
771	SSMR3GetU8(pSSMHandle, &s->status_latched);
772	SSMR3GetU8(pSSMHandle, &s->status);
773	SSMR3GetU8(pSSMHandle, &s->read_state);
774	SSMR3GetU8(pSSMHandle, &s->write_state);
775	SSMR3GetU8(pSSMHandle, &s->write_latch);
776	SSMR3GetU8(pSSMHandle, &s->rw_mode);
777	SSMR3GetU8(pSSMHandle, &s->mode);
778	SSMR3GetU8(pSSMHandle, &s->bcd);
779	SSMR3GetU8(pSSMHandle, &s->gate);
780	SSMR3GetU64(pSSMHandle, &s->count_load_time);
781	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
782	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
783	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
784	if (s->CTX_SUFF(pTimer))
785	{
786	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSMHandle);
787	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
788	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
789	}
790	pThis->channels[0].cRelLogEntries = 0;
791	}
792
793	SSMR3GetS32(pSSMHandle, &pThis->speaker_data_on);
794	#ifdef FAKE_REFRESH_CLOCK
795	return SSMR3GetS32(pSSMHandle, &pThis->dummy_refresh_clock);
796	#else
797	int32_t u32Dummy;
798	return SSMR3GetS32(pSSMHandle, &u32Dummy);
799	#endif
800	}
801
802
803	/**
804	* Device timer callback function.
805	*
806	* @param pDevIns Device instance of the device which registered the timer.
807	* @param pTimer The timer handle.
808	*/
809	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
810	{
811	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
812	PITChannelState *s = &pThis->channels[0];
813	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
814	pit_irq_timer_update(s, s->next_transition_time);
815	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
816	}
817
818
819	/**
820	* Relocation notification.
821	*
822	* @returns VBox status.
823	* @param pDevIns The device instance data.
824	* @param offDelta The delta relative to the old address.
825	*/
826	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
827	{
828	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
829	unsigned i;
830	LogFlow(("pitRelocate: \n"));
831
832	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
833	{
834	PITChannelState *pCh = &pThis->channels[i];
835	if (pCh->pTimerR3)
836	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
837	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
838	}
839	}
840
841	/** @todo remove this! */
842	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
843
844	/**
845	* Reset notification.
846	*
847	* @returns VBox status.
848	* @param pDevIns The device instance data.
849	*/
850	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
851	{
852	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
853	unsigned i;
854	LogFlow(("pitReset: \n"));
855
856	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
857	{
858	PITChannelState *s = &pThis->channels[i];
859
860	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
861	s->latched_count = 0;
862	s->count_latched = 0;
863	s->status_latched = 0;
864	s->status = 0;
865	s->read_state = 0;
866	s->write_state = 0;
867	s->write_latch = 0;
868	s->rw_mode = 0;
869	s->bcd = 0;
870	#endif
871	s->u64NextTS = UINT64_MAX;
872	s->cRelLogEntries = 0;
873	s->mode = 3;
874	s->gate = (i != 2);
875	pit_load_count(s, 0);
876	}
877	}
878
879
880	/**
881	* Info handler, device version.
882	*
883	* @param pDevIns Device instance which registered the info.
884	* @param pHlp Callback functions for doing output.
885	* @param pszArgs Argument string. Optional and specific to the handler.
886	*/
887	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
888	{
889	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
890	unsigned i;
891	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
892	{
893	const PITChannelState *pCh = &pThis->channels[i];
894
895	pHlp->pfnPrintf(pHlp,
896	"PIT (i8254) channel %d status: irq=%#x\n"
897	" count=%08x" " latched_count=%04x count_latched=%02x\n"
898	" status=%02x status_latched=%02x read_state=%02x\n"
899	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
900	" mode=%02x bcd=%02x gate=%02x\n"
901	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
902	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
903	,
904	i, pCh->irq,
905	pCh->count, pCh->latched_count, pCh->count_latched,
906	pCh->status, pCh->status_latched, pCh->read_state,
907	pCh->write_state, pCh->write_latch, pCh->rw_mode,
908	pCh->mode, pCh->bcd, pCh->gate,
909	pCh->count_load_time, pCh->next_transition_time,
910	pCh->u64ReloadTS, pCh->u64NextTS);
911	}
912	#ifdef FAKE_REFRESH_CLOCK
913	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
914	pThis->speaker_data_on, pThis->dummy_refresh_clock);
915	#else
916	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
917	#endif
918	}
919
920
921	/**
922	* Construct a device instance for a VM.
923	*
924	* @returns VBox status.
925	* @param pDevIns The device instance data.
926	* If the registration structure is needed, pDevIns->pDevReg points to it.
927	* @param iInstance Instance number. Use this to figure out which registers and such to use.
928	* The device number is also found in pDevIns->iInstance, but since it's
929	* likely to be freqently used PDM passes it as parameter.
930	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
931	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
932	* iInstance it's expected to be used a bit in this function.
933	*/
934	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
935	{
936	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
937	int rc;
938	uint8_t u8Irq;
939	uint16_t u16Base;
940	bool fSpeaker;
941	bool fGCEnabled;
942	bool fR0Enabled;
943	unsigned i;
944	Assert(iInstance == 0);
945
946	/*
947	* Validate configuration.
948	*/
949	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0" "Base\0" "Speaker\0" "GCEnabled\0" "R0Enabled\0"))
950	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
951
952	/*
953	* Init the data.
954	*/
955	rc = CFGMR3QueryU8Def(pCfgHandle, "Irq", &u8Irq, 0);
956	if (RT_FAILURE(rc))
957	return PDMDEV_SET_ERROR(pDevIns, rc,
958	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
959
960	rc = CFGMR3QueryU16Def(pCfgHandle, "Base", &u16Base, 0x40);
961	if (RT_FAILURE(rc))
962	return PDMDEV_SET_ERROR(pDevIns, rc,
963	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
964
965	rc = CFGMR3QueryBoolDef(pCfgHandle, "SpeakerEnabled", &fSpeaker, true);
966	if (RT_FAILURE(rc))
967	return PDMDEV_SET_ERROR(pDevIns, rc,
968	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
969
970	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
971	if (RT_FAILURE(rc))
972	return PDMDEV_SET_ERROR(pDevIns, rc,
973	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
974
975	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
976	if (RT_FAILURE(rc))
977	return PDMDEV_SET_ERROR(pDevIns, rc,
978	N_("Configuration error: failed to read R0Enabled as boolean"));
979
980	pThis->pDevIns = pDevIns;
981	pThis->channels[0].irq = u8Irq;
982	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
983	{
984	pThis->channels[i].pPitR3 = pThis;
985	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
986	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
987	}
988
989	/*
990	* Create timer, register I/O Ports and save state.
991	*/
992	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, "i8254 Programmable Interval Timer",
993	&pThis->channels[0].pTimerR3);
994	if (RT_FAILURE(rc))
995	return rc;
996	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
997	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
998
999	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1000	if (RT_FAILURE(rc))
1001	return rc;
1002	if (fGCEnabled)
1003	{
1004	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1005	if (RT_FAILURE(rc))
1006	return rc;
1007	}
1008	if (fR0Enabled)
1009	{
1010	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1011	if (RT_FAILURE(rc))
1012	return rc;
1013	}
1014
1015	if (fSpeaker)
1016	{
1017	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1018	if (RT_FAILURE(rc))
1019	return rc;
1020	if (fGCEnabled)
1021	{
1022	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1023	if (RT_FAILURE(rc))
1024	return rc;
1025	}
1026	}
1027
1028	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pThis),
1029	NULL, pitSaveExec, NULL,
1030	NULL, pitLoadExec, NULL);
1031	if (RT_FAILURE(rc))
1032	return rc;
1033
1034	/*
1035	* Initialize the device state.
1036	*/
1037	pitReset(pDevIns);
1038
1039	/*
1040	* Register statistics and debug info.
1041	*/
1042	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1043	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1044
1045	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1046
1047	return VINF_SUCCESS;
1048	}
1049
1050
1051	/**
1052	* The device registration structure.
1053	*/
1054	const PDMDEVREG g_DeviceI8254 =
1055	{
1056	/* u32Version */
1057	PDM_DEVREG_VERSION,
1058	/* szDeviceName */
1059	"i8254",
1060	/* szRCMod */
1061	"VBoxDDGC.gc",
1062	/* szR0Mod */
1063	"VBoxDDR0.r0",
1064	/* pszDescription */
1065	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1066	/* fFlags */
1067	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1068	/* fClass */
1069	PDM_DEVREG_CLASS_PIT,
1070	/* cMaxInstances */
1071	1,
1072	/* cbInstance */
1073	sizeof(PITState),
1074	/* pfnConstruct */
1075	pitConstruct,
1076	/* pfnDestruct */
1077	NULL,
1078	/* pfnRelocate */
1079	pitRelocate,
1080	/* pfnIOCtl */
1081	NULL,
1082	/* pfnPowerOn */
1083	NULL,
1084	/* pfnReset */
1085	pitReset,
1086	/* pfnSuspend */
1087	NULL,
1088	/* pfnResume */
1089	NULL,
1090	/* pfnAttach */
1091	NULL,
1092	/* pfnDetach */
1093	NULL,
1094	/* pfnQueryInterface. */
1095	NULL,
1096	/* pfnInitComplete */
1097	NULL,
1098	/* pfnPowerOff */
1099	NULL,
1100	/* pfnSoftReset */
1101	NULL,
1102	/* u32VersionEnd */
1103	PDM_DEVREG_VERSION
1104	};
1105
1106	#endif /* IN_RING3 */
1107	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 18719

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