DevPit-i8254.cpp@ 2285

Last change on this file since 2285 was 2285, checked in by vboxsync, 18 years ago
TMCLOCK_VIRTUAL_SYNC changes. (define VBOX_WITH_VIRTUAL_SYNC_TIMERS to enable)
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 38.5 KB

Line
1	/** @file
2	*
3	* VBox basic PC devices:
4	* Intel 8254 programmable interval timer
5	*/
6
7	/*
8	* Copyright (C) 2006 InnoTek Systemberatung GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* If you received this file as part of a commercial VirtualBox
19	* distribution, then only the terms of your commercial VirtualBox
20	* license agreement apply instead of the previous paragraph.
21	*
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU 8253/8254 interval timer emulation
27	*
28	* Copyright (c) 2003-2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*******************************************************************************
51	* Header Files *
52	*******************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PIT
54	#include <VBox/pdm.h>
55	#include <VBox/log.h>
56	#include <VBox/stam.h>
57	#include <iprt/assert.h>
58	#include <iprt/asm.h>
59
60	#include "Builtins.h"
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The version of the saved state. */
74	#define PIT_SAVED_STATE_VERSION 2
75
76
77	/*******************************************************************************
78	* Structures and Typedefs *
79	*******************************************************************************/
80	typedef struct PITChannelState
81	{
82	/** Pointer to the instance data - HCPtr. */
83	HCPTRTYPE(struct PITState *) pPitHC;
84	/** The timer - HCPtr. */
85	PTMTIMERHC pTimerHC;
86	/** Pointer to the instance data - GCPtr. */
87	GCPTRTYPE(struct PITState *) pPitGC;
88	/** The timer - HCPtr. */
89	PTMTIMERGC pTimerGC;
90	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
91	uint64_t u64ReloadTS;
92	/** The actual time of the next tick.
93	* As apposed to the next_transition_time which contains the correct time of the next tick. */
94	uint64_t u64NextTS;
95	#ifndef VBOX_WITH_VIRTUAL_SYNC_TIMERS
96	/** When to give up catching up. (negative number) */
97	int64_t i64MaxCatchupTS;
98	#endif
99
100	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
101	uint64_t count_load_time;
102	/* irq handling */
103	int64_t next_transition_time;
104	int32_t irq;
105	uint32_t padding;
106
107	uint32_t count; /* can be 65536 */
108	uint16_t latched_count;
109	uint8_t count_latched;
110	uint8_t status_latched;
111
112	uint8_t status;
113	uint8_t read_state;
114	uint8_t write_state;
115	uint8_t write_latch;
116
117	uint8_t rw_mode;
118	uint8_t mode;
119	uint8_t bcd; /* not supported */
120	uint8_t gate; /* timer start */
121
122	} PITChannelState;
123
124	typedef struct PITState
125	{
126	PITChannelState channels[3];
127	/** Speaker data. */
128	int32_t speaker_data_on;
129	/** Speaker dummy. */
130	int32_t dummy_refresh_clock;
131	/** Pointer to the device instance. */
132	HCPTRTYPE(PPDMDEVINS) pDevIns;
133	#if HC_ARCH_BITS == 32
134	uint32_t Alignment0;
135	#endif
136	/** Number of IRQs that's been raised. */
137	STAMCOUNTER StatPITIrq;
138	/** Profiling the timer callback handler. */
139	STAMPROFILEADV StatPITHandler;
140	#ifndef VBOX_WITH_VIRTUAL_SYNC_TIMERS
141	/** The number of times we've had to speed up the time because we lagged too far behind. */
142	STAMCOUNTER StatPITCatchup;
143	/** The number of times we've lagged too far behind for it to be worth trying to catch up. */
144	STAMCOUNTER StatPITGiveup;
145	#endif
146	} PITState;
147
148
149	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
150	/*******************************************************************************
151	* Internal Functions *
152	*******************************************************************************/
153	__BEGIN_DECLS
154	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
155	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
156	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
157	#ifdef IN_RING3
158	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
159	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
160	#endif
161	__END_DECLS
162
163
164
165
166	static int pit_get_count(PITChannelState *s)
167	{
168	uint64_t d;
169	int counter;
170	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
171
172	if (s->mode == 2) /** @todo Implement proper virtual time and get rid of this hack.. */
173	{
174	#if 0
175	d = TMTimerGet(pTimer);
176	d -= s->u64ReloadTS;
177	d = ASMMultU64ByU32DivByU32(d, PIT_FREQ, TMTimerGetFreq(pTimer));
178	#else /* variable time because of catch up */
179	if (s->u64NextTS == UINT64_MAX)
180	return 1; /** @todo check this value. */
181	d = TMTimerGet(pTimer);
182	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
183	#endif
184	if (d >= s->count)
185	return 1;
186	return s->count - d;
187	}
188	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
189	switch(s->mode) {
190	case 0:
191	case 1:
192	case 4:
193	case 5:
194	counter = (s->count - d) & 0xffff;
195	break;
196	case 3:
197	/* XXX: may be incorrect for odd counts */
198	counter = s->count - ((2 * d) % s->count);
199	break;
200	default:
201	counter = s->count - (d % s->count);
202	break;
203	}
204	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
205	return counter;
206	}
207
208	/* get pit output bit */
209	static int pit_get_out1(PITChannelState *s, int64_t current_time)
210	{
211	uint64_t d;
212	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
213	int out;
214
215	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
216	switch(s->mode) {
217	default:
218	case 0:
219	out = (d >= s->count);
220	break;
221	case 1:
222	out = (d < s->count);
223	break;
224	case 2:
225	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
226	if ((d % s->count) == 0 && d != 0)
227	out = 1;
228	else
229	out = 0;
230	break;
231	case 3:
232	out = (d % s->count) < ((s->count + 1) >> 1);
233	break;
234	case 4:
235	case 5:
236	out = (d == s->count);
237	break;
238	}
239	return out;
240	}
241
242
243	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
244	{
245	PITChannelState *s = &pit->channels[channel];
246	return pit_get_out1(s, current_time);
247	}
248
249
250	static int pit_get_gate(PITState *pit, int channel)
251	{
252	PITChannelState *s = &pit->channels[channel];
253	return s->gate;
254	}
255
256
257	/* if already latched, do not latch again */
258	static void pit_latch_count(PITChannelState *s)
259	{
260	if (!s->count_latched) {
261	s->latched_count = pit_get_count(s);
262	s->count_latched = s->rw_mode;
263	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
264	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
265	}
266	}
267
268	#ifdef IN_RING3
269
270	/* val must be 0 or 1 */
271	static void pit_set_gate(PITState *pit, int channel, int val)
272	{
273	PITChannelState *s = &pit->channels[channel];
274	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
275
276	switch(s->mode) {
277	default:
278	case 0:
279	case 4:
280	/* XXX: just disable/enable counting */
281	break;
282	case 1:
283	case 5:
284	if (s->gate < val) {
285	/* restart counting on rising edge */
286	s->count_load_time = TMTimerGet(pTimer);
287	pit_irq_timer_update(s, s->count_load_time);
288	}
289	break;
290	case 2:
291	case 3:
292	if (s->gate < val) {
293	/* restart counting on rising edge */
294	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
295	pit_irq_timer_update(s, s->count_load_time);
296	}
297	/* XXX: disable/enable counting */
298	break;
299	}
300	s->gate = val;
301	}
302
303	static inline void pit_load_count(PITChannelState *s, int val)
304	{
305	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
306	if (val == 0)
307	val = 0x10000;
308	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
309	s->count = val;
310	pit_irq_timer_update(s, s->count_load_time);
311	}
312
313	/* return -1 if no transition will occur. */
314	static int64_t pit_get_next_transition_time(PITChannelState *s,
315	uint64_t current_time)
316	{
317	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
318	uint64_t d, next_time, base;
319	uint32_t period2;
320
321	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
322	switch(s->mode) {
323	default:
324	case 0:
325	case 1:
326	if (d < s->count)
327	next_time = s->count;
328	else
329	return -1;
330	break;
331	/*
332	* Mode 2: The period is count + 1 PIT ticks.
333	* When the counter reaches 1 we sent the output low (for channel 0 that
334	* means raise an irq). On the next tick, where we should be decrementing
335	* from 1 to 0, the count is loaded and the output goes high (channel 0
336	* means clearing the irq).
337	*
338	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
339	* the irq. We also don't set it until we reach 0, which is a tick late - will
340	* try fix that later some day.
341	*/
342	case 2:
343	base = (d / s->count) * s->count;
344	#ifndef VBOX /* see above */
345	if ((d - base) == 0 && d != 0)
346	next_time = base + s->count;
347	else
348	#endif
349	next_time = base + s->count + 1;
350	break;
351	case 3:
352	base = (d / s->count) * s->count;
353	period2 = ((s->count + 1) >> 1);
354	if ((d - base) < period2)
355	next_time = base + period2;
356	else
357	next_time = base + s->count;
358	break;
359	case 4:
360	case 5:
361	if (d < s->count)
362	next_time = s->count;
363	else if (d == s->count)
364	next_time = s->count + 1;
365	else
366	return -1;
367	break;
368	}
369	/* convert to timer units */
370	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
371	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
372	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
373	/* fix potential rounding problems */
374	/* XXX: better solution: use a clock at PIT_FREQ Hz */
375	if (next_time <= current_time)
376	next_time = current_time + 1;
377	return next_time;
378	}
379
380	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
381	{
382	uint64_t now;
383	int64_t expire_time;
384	int irq_level;
385	PPDMDEVINS pDevIns;
386	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
387
388	if (!s->CTXSUFF(pTimer))
389	return;
390	expire_time = pit_get_next_transition_time(s, current_time);
391	irq_level = pit_get_out1(s, current_time);
392
393	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
394	pDevIns = s->CTXSUFF(pPit)->pDevIns;
395	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
396	if (irq_level)
397	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
398	now = TMTimerGet(pTimer);
399	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
400	if (irq_level)
401	{
402	s->u64ReloadTS = now;
403	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITIrq);
404	}
405
406	#ifdef VBOX_WITH_VIRTUAL_SYNC_TIMERS
407	if (expire_time != -1)
408	{
409	s->u64NextTS = expire_time;
410	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
411	}
412	#else
413	/* check if it expires too soon - move at 4x rate if it does. */
414	if (expire_time != -1)
415	{
416	int64_t delta = expire_time - now;
417	const int64_t quarter = (expire_time - s->next_transition_time) >> 2;
418	if (delta <= quarter && s->next_transition_time != -1)
419	{
420	if (delta >= s->i64MaxCatchupTS)
421	{
422	/* If we set the timer to 'expire_time' we could end up with flooding the guest
423	* with timer interrupts because the next interrupt(s) would probably raise
424	* immediately. Therefore we set the timer to 'now + quarter' with quarter>0.
425	* This delays the adaption a little bit. */
426	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITCatchup);
427	s->u64NextTS = now + quarter;
428	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64 delta=%9RI64\n",
429	s->mode, s->count, irq_level, quarter, s->u64NextTS, now, s->count_load_time,
430	ASMMultU64ByU32DivByU32(s->u64NextTS - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer)), delta));
431	}
432	else
433	{
434	/* We are too far away from the real time. Hard synchronize. */
435	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITGiveup);
436	s->u64NextTS = expire_time = pit_get_next_transition_time(s, now);
437	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64 delta=%9RI64 giving up!\n",
438	s->mode, s->count, irq_level, quarter, s->u64NextTS, now, s->count_load_time,
439	ASMMultU64ByU32DivByU32(s->u64NextTS - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer)), delta));
440	}
441	}
442	else
443	{
444	/* Everything is fine, just set the timer to the regular next expire_time. */
445	s->u64NextTS = expire_time;
446	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64\n",
447	s->mode, s->count, irq_level, expire_time - now, expire_time, now, s->count_load_time,
448	ASMMultU64ByU32DivByU32(expire_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer))));
449	}
450	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
451	}
452	#endif
453	else
454	{
455	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
456	TMTimerStop(s->CTXSUFF(pTimer));
457	s->u64NextTS = UINT64_MAX;
458	}
459	s->next_transition_time = expire_time;
460	}
461
462	#endif /* IN_RING3 */
463
464
465	/**
466	* Port I/O Handler for IN operations.
467	*
468	* @returns VBox status code.
469	*
470	* @param pDevIns The device instance.
471	* @param pvUser User argument - ignored.
472	* @param Port Port number used for the IN operation.
473	* @param pu32 Where to store the result.
474	* @param cb Number of bytes read.
475	*/
476	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
477	{
478	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
479	NOREF(pvUser);
480	Port &= 3;
481	if (cb != 1 \|\| Port == 3)
482	{
483	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
484	return VERR_IOM_IOPORT_UNUSED;
485	}
486
487	PITState pit = PDMINS2DATA(pDevIns, PITState );
488	int ret;
489	PITChannelState *s = &pit->channels[Port];
490	if (s->status_latched)
491	{
492	s->status_latched = 0;
493	ret = s->status;
494	}
495	else if (s->count_latched)
496	{
497	switch (s->count_latched)
498	{
499	default:
500	case RW_STATE_LSB:
501	ret = s->latched_count & 0xff;
502	s->count_latched = 0;
503	break;
504	case RW_STATE_MSB:
505	ret = s->latched_count >> 8;
506	s->count_latched = 0;
507	break;
508	case RW_STATE_WORD0:
509	ret = s->latched_count & 0xff;
510	s->count_latched = RW_STATE_MSB;
511	break;
512	}
513	}
514	else
515	{
516	int count;
517	switch (s->read_state)
518	{
519	default:
520	case RW_STATE_LSB:
521	count = pit_get_count(s);
522	ret = count & 0xff;
523	break;
524	case RW_STATE_MSB:
525	count = pit_get_count(s);
526	ret = (count >> 8) & 0xff;
527	break;
528	case RW_STATE_WORD0:
529	count = pit_get_count(s);
530	ret = count & 0xff;
531	s->read_state = RW_STATE_WORD1;
532	break;
533	case RW_STATE_WORD1:
534	count = pit_get_count(s);
535	ret = (count >> 8) & 0xff;
536	s->read_state = RW_STATE_WORD0;
537	break;
538	}
539	}
540
541	*pu32 = ret;
542	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
543	return VINF_SUCCESS;
544	}
545
546
547	/**
548	* Port I/O Handler for OUT operations.
549	*
550	* @returns VBox status code.
551	*
552	* @param pDevIns The device instance.
553	* @param pvUser User argument - ignored.
554	* @param Port Port number used for the IN operation.
555	* @param u32 The value to output.
556	* @param cb The value size in bytes.
557	*/
558	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
559	{
560	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
561	NOREF(pvUser);
562	if (cb != 1)
563	return VINF_SUCCESS;
564
565	PITState pit = PDMINS2DATA(pDevIns, PITState );
566	Port &= 3;
567	if (Port == 3)
568	{
569	/*
570	* Port 43h - Mode/Command Register.
571	* 7 6 5 4 3 2 1 0
572	* * * . . . . . . Select channel: 0 0 = Channel 0
573	* 0 1 = Channel 1
574	* 1 0 = Channel 2
575	* 1 1 = Read-back command (8254 only)
576	* (Illegal on 8253)
577	* (Illegal on PS/2 {JAM})
578	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
579	* 0 1 = Access mode: lobyte only
580	* 1 0 = Access mode: hibyte only
581	* 1 1 = Access mode: lobyte/hibyte
582	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
583	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
584	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
585	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
586	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
587	*/
588	unsigned channel = u32 >> 6;
589	if (channel == 3)
590	{
591	/* read-back command */
592	for (channel = 0; channel < ELEMENTS(pit->channels); channel++)
593	{
594	PITChannelState *s = &pit->channels[channel];
595	if (u32 & (2 << channel)) {
596	if (!(u32 & 0x20))
597	pit_latch_count(s);
598	if (!(u32 & 0x10) && !s->status_latched)
599	{
600	/* status latch */
601	/* XXX: add BCD and null count */
602	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
603	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
604	\| (s->rw_mode << 4)
605	\| (s->mode << 1)
606	\| s->bcd;
607	s->status_latched = 1;
608	}
609	}
610	}
611	}
612	else
613	{
614	PITChannelState *s = &pit->channels[channel];
615	unsigned access = (u32 >> 4) & 3;
616	if (access == 0)
617	pit_latch_count(s);
618	else
619	{
620	s->rw_mode = access;
621	s->read_state = access;
622	s->write_state = access;
623
624	s->mode = (u32 >> 1) & 7;
625	s->bcd = u32 & 1;
626	/* XXX: update irq timer ? */
627	}
628	}
629	}
630	else
631	{
632	#ifndef IN_RING3
633	return VINF_IOM_HC_IOPORT_WRITE;
634	#else /* IN_RING3 */
635	/*
636	* Port 40-42h - Channel Data Ports.
637	*/
638	PITChannelState *s = &pit->channels[Port];
639	switch(s->write_state)
640	{
641	default:
642	case RW_STATE_LSB:
643	pit_load_count(s, u32);
644	break;
645	case RW_STATE_MSB:
646	pit_load_count(s, u32 << 8);
647	break;
648	case RW_STATE_WORD0:
649	s->write_latch = u32;
650	s->write_state = RW_STATE_WORD1;
651	break;
652	case RW_STATE_WORD1:
653	pit_load_count(s, s->write_latch \| (u32 << 8));
654	s->write_state = RW_STATE_WORD0;
655	break;
656	}
657	#endif /* !IN_RING3 */
658	}
659	return VINF_SUCCESS;
660	}
661
662
663	/**
664	* Port I/O Handler for speaker IN operations.
665	*
666	* @returns VBox status code.
667	*
668	* @param pDevIns The device instance.
669	* @param pvUser User argument - ignored.
670	* @param Port Port number used for the IN operation.
671	* @param pu32 Where to store the result.
672	* @param cb Number of bytes read.
673	*/
674	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
675	{
676	NOREF(pvUser);
677	if (cb == 1)
678	{
679	PITState pData = PDMINS2DATA(pDevIns, PITState );
680	int out = pit_get_out(pData, 2, TMTimerGet(pData->channels[0].CTXSUFF(pTimer)));
681	pData->dummy_refresh_clock ^= 1;
682	*pu32 = (pData->speaker_data_on << 1) \| pit_get_gate(pData, 2) \| (out << 5) \| (pData->dummy_refresh_clock << 4);
683	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
684	return VINF_SUCCESS;
685	}
686	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
687	return VERR_IOM_IOPORT_UNUSED;
688	}
689
690	#ifdef IN_RING3
691
692	/**
693	* Port I/O Handler for speaker OUT operations.
694	*
695	* @returns VBox status code.
696	*
697	* @param pDevIns The device instance.
698	* @param pvUser User argument - ignored.
699	* @param Port Port number used for the IN operation.
700	* @param u32 The value to output.
701	* @param cb The value size in bytes.
702	*/
703	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
704	{
705	NOREF(pvUser);
706	if (cb == 1)
707	{
708	PITState pData = PDMINS2DATA(pDevIns, PITState );
709	pData->speaker_data_on = (u32 >> 1) & 1;
710	pit_set_gate(pData, 2, u32 & 1);
711	}
712	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
713	return VINF_SUCCESS;
714	}
715
716
717	/**
718	* Saves a state of the programmable interval timer device.
719	*
720	* @returns VBox status code.
721	* @param pDevIns The device instance.
722	* @param pSSMHandle The handle to save the state to.
723	*/
724	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
725	{
726	PITState pData = PDMINS2DATA(pDevIns, PITState );
727	unsigned i;
728
729	for (i = 0; i < ELEMENTS(pData->channels); i++)
730	{
731	PITChannelState *s = &pData->channels[i];
732	SSMR3PutU32(pSSMHandle, s->count);
733	SSMR3PutU16(pSSMHandle, s->latched_count);
734	SSMR3PutU8(pSSMHandle, s->count_latched);
735	SSMR3PutU8(pSSMHandle, s->status_latched);
736	SSMR3PutU8(pSSMHandle, s->status);
737	SSMR3PutU8(pSSMHandle, s->read_state);
738	SSMR3PutU8(pSSMHandle, s->write_state);
739	SSMR3PutU8(pSSMHandle, s->write_latch);
740	SSMR3PutU8(pSSMHandle, s->rw_mode);
741	SSMR3PutU8(pSSMHandle, s->mode);
742	SSMR3PutU8(pSSMHandle, s->bcd);
743	SSMR3PutU8(pSSMHandle, s->gate);
744	SSMR3PutU64(pSSMHandle, s->count_load_time);
745	SSMR3PutU64(pSSMHandle, s->u64NextTS);
746	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
747	SSMR3PutS64(pSSMHandle, s->next_transition_time);
748	if (s->CTXSUFF(pTimer))
749	TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
750	}
751
752	SSMR3PutS32(pSSMHandle, pData->speaker_data_on);
753	return SSMR3PutS32(pSSMHandle, pData->dummy_refresh_clock);
754	}
755
756
757	/**
758	* Loads a saved programmable interval timer device state.
759	*
760	* @returns VBox status code.
761	* @param pDevIns The device instance.
762	* @param pSSMHandle The handle to the saved state.
763	* @param u32Version The data unit version number.
764	*/
765	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
766	{
767	PITState pData = PDMINS2DATA(pDevIns, PITState );
768	unsigned i;
769
770	if (u32Version != PIT_SAVED_STATE_VERSION)
771	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
772
773	for (i = 0; i < ELEMENTS(pData->channels); i++)
774	{
775	PITChannelState *s = &pData->channels[i];
776	SSMR3GetU32(pSSMHandle, &s->count);
777	SSMR3GetU16(pSSMHandle, &s->latched_count);
778	SSMR3GetU8(pSSMHandle, &s->count_latched);
779	SSMR3GetU8(pSSMHandle, &s->status_latched);
780	SSMR3GetU8(pSSMHandle, &s->status);
781	SSMR3GetU8(pSSMHandle, &s->read_state);
782	SSMR3GetU8(pSSMHandle, &s->write_state);
783	SSMR3GetU8(pSSMHandle, &s->write_latch);
784	SSMR3GetU8(pSSMHandle, &s->rw_mode);
785	SSMR3GetU8(pSSMHandle, &s->mode);
786	SSMR3GetU8(pSSMHandle, &s->bcd);
787	SSMR3GetU8(pSSMHandle, &s->gate);
788	SSMR3GetU64(pSSMHandle, &s->count_load_time);
789	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
790	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
791	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
792	if (s->CTXSUFF(pTimer))
793	TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
794	}
795
796	SSMR3GetS32(pSSMHandle, &pData->speaker_data_on);
797	return SSMR3GetS32(pSSMHandle, &pData->dummy_refresh_clock);
798	}
799
800
801	/**
802	* Device timer callback function.
803	*
804	* @param pDevIns Device instance of the device which registered the timer.
805	* @param pTimer The timer handle.
806	*/
807	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
808	{
809	PITState pData = PDMINS2DATA(pDevIns, PITState );
810	PITChannelState *s = &pData->channels[0];
811	STAM_PROFILE_ADV_START(&s->CTXSUFF(pPit)->StatPITHandler, a);
812	pit_irq_timer_update(s, s->next_transition_time);
813	STAM_PROFILE_ADV_STOP(&s->CTXSUFF(pPit)->StatPITHandler, a);
814	}
815
816
817	/**
818	* Relocation notification.
819	*
820	* @returns VBox status.
821	* @param pDevIns The device instance data.
822	* @param offDelta The delta relative to the old address.
823	*/
824	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
825	{
826	PITState pData = PDMINS2DATA(pDevIns, PITState );
827	unsigned i;
828	LogFlow(("pitRelocate: \n"));
829
830	for (i = 0; i < ELEMENTS(pData->channels); i++)
831	{
832	PITChannelState *pCh = &pData->channels[i];
833	if (pCh->pTimerHC)
834	pCh->pTimerGC = TMTimerGCPtr(pCh->pTimerHC);
835	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
836	}
837	}
838
839	/** @todo remove this! */
840	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
841
842	/**
843	* Reset notification.
844	*
845	* @returns VBox status.
846	* @param pDevIns The device instance data.
847	*/
848	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
849	{
850	PITState pData = PDMINS2DATA(pDevIns, PITState );
851	unsigned i;
852	LogFlow(("pitReset: \n"));
853
854	for (i = 0; i < ELEMENTS(pData->channels); i++)
855	{
856	PITChannelState *s = &pData->channels[i];
857
858	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
859	s->latched_count = 0;
860	s->count_latched = 0;
861	s->status_latched = 0;
862	s->status = 0;
863	s->read_state = 0;
864	s->write_state = 0;
865	s->write_latch = 0;
866	s->rw_mode = 0;
867	s->bcd = 0;
868	#endif
869	s->mode = 3;
870	s->gate = (i != 2);
871	pit_load_count(s, 0);
872	}
873	/** @todo remove when #1589 is resolved. */
874	pitInfo(pDevIns, DBGFR3InfoLogRelHlp(), NULL);
875	}
876
877
878	/**
879	* Info handler, device version.
880	*
881	* @param pDevIns Device instance which registered the info.
882	* @param pHlp Callback functions for doing output.
883	* @param pszArgs Argument string. Optional and specific to the handler.
884	*/
885	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
886	{
887	PITState pData = PDMINS2DATA(pDevIns, PITState );
888	unsigned i;
889	for (i = 0; i < ELEMENTS(pData->channels); i++)
890	{
891	const PITChannelState *pCh = &pData->channels[i];
892
893	pHlp->pfnPrintf(pHlp,
894	"PIT (i8254) channel %d status: irq=%#x\n"
895	" count=%08x" " latched_count=%04x count_latched=%02x\n"
896	" status=%02x status_latched=%02x read_state=%02x\n"
897	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
898	" mode=%02x bcd=%02x gate=%02x\n"
899	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
900	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
901	,
902	i, pCh->irq,
903	pCh->count, pCh->latched_count, pCh->count_latched,
904	pCh->status, pCh->status_latched, pCh->read_state,
905	pCh->write_state, pCh->write_latch, pCh->rw_mode,
906	pCh->mode, pCh->bcd, pCh->gate,
907	pCh->count_load_time, pCh->next_transition_time,
908	pCh->u64ReloadTS, pCh->u64NextTS);
909	}
910	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
911	pData->speaker_data_on, pData->dummy_refresh_clock);
912	}
913
914
915	/**
916	* Construct a device instance for a VM.
917	*
918	* @returns VBox status.
919	* @param pDevIns The device instance data.
920	* If the registration structure is needed, pDevIns->pDevReg points to it.
921	* @param iInstance Instance number. Use this to figure out which registers and such to use.
922	* The device number is also found in pDevIns->iInstance, but since it's
923	* likely to be freqently used PDM passes it as parameter.
924	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
925	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
926	* iInstance it's expected to be used a bit in this function.
927	*/
928	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
929	{
930	PITState pData = PDMINS2DATA(pDevIns, PITState );
931	int rc;
932	uint8_t u8Irq;
933	uint16_t u16Base;
934	bool fSpeaker;
935	bool fGCEnabled;
936	bool fR0Enabled;
937	unsigned i;
938	Assert(iInstance == 0);
939
940	/*
941	* Validate configuration.
942	*/
943	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0Speaker\0GCEnabled\0R0Enabled"))
944	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
945
946	/*
947	* Init the data.
948	*/
949	rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
950	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
951	u8Irq = 0;
952	else if (VBOX_FAILURE(rc))
953	return PDMDEV_SET_ERROR(pDevIns, rc,
954	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
955
956	rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
957	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
958	u16Base = 0x40;
959	else if (VBOX_FAILURE(rc))
960	return PDMDEV_SET_ERROR(pDevIns, rc,
961	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
962
963	rc = CFGMR3QueryBool(pCfgHandle, "SpeakerEnabled", &fSpeaker);
964	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
965	fSpeaker = true;
966	else if (VBOX_FAILURE(rc))
967	return PDMDEV_SET_ERROR(pDevIns, rc,
968	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
969
970	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
971	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
972	fGCEnabled = true;
973	else if (VBOX_FAILURE(rc))
974	return PDMDEV_SET_ERROR(pDevIns, rc,
975	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
976
977	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
978	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
979	fR0Enabled = true;
980	else if (VBOX_FAILURE(rc))
981	return PDMDEV_SET_ERROR(pDevIns, rc,
982	N_("Configuration error: failed to read R0Enabled as boolean"));
983
984	pData->pDevIns = pDevIns;
985	pData->channels[0].irq = u8Irq;
986	for (i = 0; i < ELEMENTS(pData->channels); i++)
987	{
988	pData->channels[i].pPitHC = pData;
989	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
990	}
991
992	/*
993	* Create timer, register I/O Ports and save state.
994	*/
995	#ifdef VBOX_WITH_VIRTUAL_SYNC_TIMERS
996	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, "i8254 Programmable Interval Timer",
997	#else
998	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pitTimer, "i8254 Programmable Interval Timer",
999	#endif
1000	&pData->channels[0].CTXSUFF(pTimer));
1001	if (VBOX_FAILURE(rc))
1002	{
1003	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
1004	return rc;
1005	}
1006
1007	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1008	if (VBOX_FAILURE(rc))
1009	return rc;
1010	if (fGCEnabled)
1011	{
1012	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1013	if (VBOX_FAILURE(rc))
1014	return rc;
1015	}
1016	if (fR0Enabled)
1017	{
1018	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1019	if (VBOX_FAILURE(rc))
1020	return rc;
1021	}
1022
1023	if (fSpeaker)
1024	{
1025	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1026	if (VBOX_FAILURE(rc))
1027	return rc;
1028	if (fGCEnabled)
1029	{
1030	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1031	if (VBOX_FAILURE(rc))
1032	return rc;
1033	}
1034	}
1035
1036	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pData),
1037	NULL, pitSaveExec, NULL,
1038	NULL, pitLoadExec, NULL);
1039	if (VBOX_FAILURE(rc))
1040	return rc;
1041
1042	#ifndef VBOX_WITH_VIRTUAL_SYNC_TIMERS
1043	/*
1044	* Calculate max catchup time.
1045	*/
1046	pData->channels[0].i64MaxCatchupTS = pData->channels[1].i64MaxCatchupTS
1047	= pData->channels[2].i64MaxCatchupTS = -TMTimerFromMilli(pData->channels[0].CTXSUFF(pTimer), 1000602); /* 2 min */
1048	#endif
1049
1050	/*
1051	* Initialize the device state.
1052	*/
1053	pitReset(pDevIns);
1054
1055	/*
1056	* Register statistics and debug info.
1057	*/
1058	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1059	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1060	#ifndef VBOX_WITH_VIRTUAL_SYNC_TIMERS
1061	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITCatchup, STAMTYPE_COUNTER, "/TM/PIT/Catchup", STAMUNIT_OCCURENCES, "The number of times we lagged too far behind.");
1062	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITGiveup, STAMTYPE_COUNTER, "/TM/PIT/Giveup", STAMUNIT_OCCURENCES, "The number of times we lagged so far behind that we simply gave up.");
1063	#endif
1064
1065	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1066
1067	return VINF_SUCCESS;
1068	}
1069
1070
1071	/**
1072	* The device registration structure.
1073	*/
1074	const PDMDEVREG g_DeviceI8254 =
1075	{
1076	/* u32Version */
1077	PDM_DEVREG_VERSION,
1078	/* szDeviceName */
1079	"i8254",
1080	/* szGCMod */
1081	"VBoxDDGC.gc",
1082	/* szR0Mod */
1083	"VBoxDDR0.r0",
1084	/* pszDescription */
1085	"i8254 Programmable Interval Timer And Dummy Speaker",
1086	/* fFlags */
1087	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1088	/* fClass */
1089	PDM_DEVREG_CLASS_PIT,
1090	/* cMaxInstances */
1091	1,
1092	/* cbInstance */
1093	sizeof(PITState),
1094	/* pfnConstruct */
1095	pitConstruct,
1096	/* pfnDestruct */
1097	NULL,
1098	/* pfnRelocate */
1099	pitRelocate,
1100	/* pfnIOCtl */
1101	NULL,
1102	/* pfnPowerOn */
1103	NULL,
1104	/* pfnReset */
1105	pitReset,
1106	/* pfnSuspend */
1107	NULL,
1108	/* pfnResume */
1109	NULL,
1110	/* pfnAttach */
1111	NULL,
1112	/* pfnDetach */
1113	NULL,
1114	/* pfnQueryInterface. */
1115	NULL
1116	};
1117
1118	#endif /* IN_RING3 */
1119	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1120

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 2285

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