DevPit-i8254.cpp@ 27125

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1	/* $Id: DevPit-i8254.cpp 27125 2010-03-05 18:31:16Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	* --------------------------------------------------------------------
21	*
22	* This code is based on:
23	*
24	* QEMU 8253/8254 interval timer emulation
25	*
26	* Copyright (c) 2003-2004 Fabrice Bellard
27	*
28	* Permission is hereby granted, free of charge, to any person obtaining a copy
29	* of this software and associated documentation files (the "Software"), to deal
30	* in the Software without restriction, including without limitation the rights
31	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32	* copies of the Software, and to permit persons to whom the Software is
33	* furnished to do so, subject to the following conditions:
34	*
35	* The above copyright notice and this permission notice shall be included in
36	* all copies or substantial portions of the Software.
37	*
38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44	* THE SOFTWARE.
45	*/
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_PIT
51	#include <VBox/pdmdev.h>
52	#include <VBox/log.h>
53	#include <VBox/stam.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm.h>
56
57	#ifdef IN_RING3
58	# include <iprt/alloc.h>
59	# include <iprt/string.h>
60	# include <iprt/uuid.h>
61	#endif /* IN_RING3 */
62
63	#include "../Builtins.h"
64
65
66	/*******************************************************************************
67	* Defined Constants And Macros *
68	*******************************************************************************/
69	/** The PIT frequency. */
70	#define PIT_FREQ 1193182
71
72	#define RW_STATE_LSB 1
73	#define RW_STATE_MSB 2
74	#define RW_STATE_WORD0 3
75	#define RW_STATE_WORD1 4
76
77	/** The current saved state version. */
78	#define PIT_SAVED_STATE_VERSION 4
79	/** The saved state version used by VirtualBox 3.1 and earlier.
80	* This did not include disable by HPET flag. */
81	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
82	/** The saved state version used by VirtualBox 3.0 and earlier.
83	* This did not include the config part. */
84	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
85
86	/** @def FAKE_REFRESH_CLOCK
87	* Define this to flip the 15usec refresh bit on every read.
88	* If not defined, it will be flipped correctly. */
89	/* #define FAKE_REFRESH_CLOCK */
90	#ifdef DOXYGEN_RUNNING
91	# define FAKE_REFRESH_CLOCK
92	#endif
93
94
95	/*******************************************************************************
96	* Structures and Typedefs *
97	*******************************************************************************/
98	typedef struct PITChannelState
99	{
100	/** Pointer to the instance data - R3 Ptr. */
101	R3PTRTYPE(struct PITState *) pPitR3;
102	/** The timer - R3 Ptr. */
103	PTMTIMERR3 pTimerR3;
104	/** Pointer to the instance data - R0 Ptr. */
105	R0PTRTYPE(struct PITState *) pPitR0;
106	/** The timer - R0 Ptr. */
107	PTMTIMERR0 pTimerR0;
108	/** Pointer to the instance data - RC Ptr. */
109	RCPTRTYPE(struct PITState *) pPitRC;
110	/** The timer - RC Ptr. */
111	PTMTIMERRC pTimerRC;
112	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
113	uint64_t u64ReloadTS;
114	/** The actual time of the next tick.
115	* As apposed to the next_transition_time which contains the correct time of the next tick. */
116	uint64_t u64NextTS;
117
118	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
119	uint64_t count_load_time;
120	/* irq handling */
121	int64_t next_transition_time;
122	int32_t irq;
123	/** Number of release log entries. Used to prevent floading. */
124	uint32_t cRelLogEntries;
125
126	uint32_t count; /* can be 65536 */
127	uint16_t latched_count;
128	uint8_t count_latched;
129	uint8_t status_latched;
130
131	uint8_t status;
132	uint8_t read_state;
133	uint8_t write_state;
134	uint8_t write_latch;
135
136	uint8_t rw_mode;
137	uint8_t mode;
138	uint8_t bcd; /* not supported */
139	uint8_t gate; /* timer start */
140
141	} PITChannelState;
142
143	typedef struct PITState
144	{
145	PITChannelState channels[3];
146	/** Speaker data. */
147	int32_t speaker_data_on;
148	#ifdef FAKE_REFRESH_CLOCK
149	/** Speaker dummy. */
150	int32_t dummy_refresh_clock;
151	#else
152	uint32_t Alignment1;
153	#endif
154	/** Config: I/O port base. */
155	RTIOPORT IOPortBaseCfg;
156	/** Config: Speaker enabled. */
157	bool fSpeakerCfg;
158	uint8_t fDisabledByHpet;
159	#if HC_ARCH_BITS == 64
160	bool afAlignment0[4];
161	#endif
162	/** PIT port interface. */
163	PDMIPITPORT IPITPort;
164	/** Pointer to the device instance. */
165	PPDMDEVINSR3 pDevIns;
166	#if HC_ARCH_BITS == 32
167	uint32_t alignment1;
168	#endif
169	/** Number of IRQs that's been raised. */
170	STAMCOUNTER StatPITIrq;
171	/** Profiling the timer callback handler. */
172	STAMPROFILEADV StatPITHandler;
173	} PITState;
174
175
176	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
177	/*******************************************************************************
178	* Internal Functions *
179	*******************************************************************************/
180	RT_C_DECLS_BEGIN
181	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
182	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
183	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
184	#ifdef IN_RING3
185	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
186	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now);
187	#endif
188	RT_C_DECLS_END
189
190
191
192
193	static int pit_get_count(PITChannelState *s)
194	{
195	uint64_t d;
196	int counter;
197	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
198
199	if (s->mode == 2)
200	{
201	if (s->u64NextTS == UINT64_MAX)
202	{
203	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
204	return s->count - (d % s->count); /** @todo check this value. */
205	}
206	uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
207	if (!Interval)
208	return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
209	d = TMTimerGet(pTimer);
210	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
211	if (d >= s->count)
212	return 1;
213	return s->count - d;
214	}
215	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
216	switch(s->mode) {
217	case 0:
218	case 1:
219	case 4:
220	case 5:
221	counter = (s->count - d) & 0xffff;
222	break;
223	case 3:
224	/* XXX: may be incorrect for odd counts */
225	counter = s->count - ((2 * d) % s->count);
226	break;
227	default:
228	counter = s->count - (d % s->count);
229	break;
230	}
231	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
232	return counter;
233	}
234
235	/* get pit output bit */
236	static int pit_get_out1(PITChannelState *s, int64_t current_time)
237	{
238	uint64_t d;
239	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
240	int out;
241
242	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
243	switch(s->mode) {
244	default:
245	case 0:
246	out = (d >= s->count);
247	break;
248	case 1:
249	out = (d < s->count);
250	break;
251	case 2:
252	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
253	if ((d % s->count) == 0 && d != 0)
254	out = 1;
255	else
256	out = 0;
257	break;
258	case 3:
259	out = (d % s->count) < ((s->count + 1) >> 1);
260	break;
261	case 4:
262	case 5:
263	out = (d == s->count);
264	break;
265	}
266	return out;
267	}
268
269
270	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
271	{
272	PITChannelState *s = &pit->channels[channel];
273	return pit_get_out1(s, current_time);
274	}
275
276
277	static int pit_get_gate(PITState *pit, int channel)
278	{
279	PITChannelState *s = &pit->channels[channel];
280	return s->gate;
281	}
282
283
284	/* if already latched, do not latch again */
285	static void pit_latch_count(PITChannelState *s)
286	{
287	if (!s->count_latched) {
288	s->latched_count = pit_get_count(s);
289	s->count_latched = s->rw_mode;
290	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
291	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
292	}
293	}
294
295	#ifdef IN_RING3
296
297	/* val must be 0 or 1 */
298	static void pit_set_gate(PITState *pit, int channel, int val)
299	{
300	PITChannelState *s = &pit->channels[channel];
301	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
302	Assert((val & 1) == val);
303
304	switch(s->mode) {
305	default:
306	case 0:
307	case 4:
308	/* XXX: just disable/enable counting */
309	break;
310	case 1:
311	case 5:
312	if (s->gate < val) {
313	/* restart counting on rising edge */
314	Log(("pit_set_gate: restarting mode %d\n", s->mode));
315	s->count_load_time = TMTimerGet(pTimer);
316	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
317	}
318	break;
319	case 2:
320	case 3:
321	if (s->gate < val) {
322	/* restart counting on rising edge */
323	Log(("pit_set_gate: restarting mode %d\n", s->mode));
324	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
325	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
326	}
327	/* XXX: disable/enable counting */
328	break;
329	}
330	s->gate = val;
331	}
332
333	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
334	{
335	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
336	if (val == 0)
337	val = 0x10000;
338	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
339	s->count = val;
340	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
341
342	/* log the new rate (ch 0 only). */
343	if ( s->pTimerR3 /* ch 0 */
344	&& s->cRelLogEntries++ < 32)
345	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
346	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
347	else
348	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
349	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
350	}
351
352	/* return -1 if no transition will occur. */
353	static int64_t pit_get_next_transition_time(PITChannelState *s,
354	uint64_t current_time)
355	{
356	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
357	uint64_t d, next_time, base;
358	uint32_t period2;
359
360	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
361	switch(s->mode) {
362	default:
363	case 0:
364	case 1:
365	if (d < s->count)
366	next_time = s->count;
367	else
368	return -1;
369	break;
370	/*
371	* Mode 2: The period is count + 1 PIT ticks.
372	* When the counter reaches 1 we sent the output low (for channel 0 that
373	* means raise an irq). On the next tick, where we should be decrementing
374	* from 1 to 0, the count is loaded and the output goes high (channel 0
375	* means clearing the irq).
376	*
377	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
378	* the irq. We also don't set it until we reach 0, which is a tick late - will
379	* try fix that later some day.
380	*/
381	case 2:
382	base = (d / s->count) * s->count;
383	#ifndef VBOX /* see above */
384	if ((d - base) == 0 && d != 0)
385	next_time = base + s->count;
386	else
387	#endif
388	next_time = base + s->count + 1;
389	break;
390	case 3:
391	base = (d / s->count) * s->count;
392	period2 = ((s->count + 1) >> 1);
393	if ((d - base) < period2)
394	next_time = base + period2;
395	else
396	next_time = base + s->count;
397	break;
398	case 4:
399	case 5:
400	if (d < s->count)
401	next_time = s->count;
402	else if (d == s->count)
403	next_time = s->count + 1;
404	else
405	return -1;
406	break;
407	}
408	/* convert to timer units */
409	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
410	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
411	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
412	/* fix potential rounding problems */
413	/* XXX: better solution: use a clock at PIT_FREQ Hz */
414	if (next_time <= current_time)
415	next_time = current_time + 1;
416	return next_time;
417	}
418
419	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now)
420	{
421	int64_t expire_time;
422	int irq_level;
423	PPDMDEVINS pDevIns;
424	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
425
426	if (!s->CTX_SUFF(pTimer))
427	return;
428	expire_time = pit_get_next_transition_time(s, current_time);
429	irq_level = pit_get_out1(s, current_time);
430
431	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
432	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
433
434	/* If PIT disabled by HPET - just disconnect ticks from interrupt controllers, and not modify
435	* other moments of device functioning.
436	* @todo: is it correct?
437	*/
438	if (!s->pPitR3->fDisabledByHpet)
439	{
440	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
441	if (irq_level)
442	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
443	}
444
445	if (irq_level)
446	{
447	s->u64ReloadTS = now;
448	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
449	}
450
451	if (expire_time != -1)
452	{
453	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
454	s->u64NextTS = expire_time;
455	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
456	}
457	else
458	{
459	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
460	TMTimerStop(s->CTX_SUFF(pTimer));
461	s->u64NextTS = UINT64_MAX;
462	}
463	s->next_transition_time = expire_time;
464	}
465
466	#endif /* IN_RING3 */
467
468
469	/**
470	* Port I/O Handler for IN operations.
471	*
472	* @returns VBox status code.
473	*
474	* @param pDevIns The device instance.
475	* @param pvUser User argument - ignored.
476	* @param Port Port number used for the IN operation.
477	* @param pu32 Where to store the result.
478	* @param cb Number of bytes read.
479	*/
480	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
481	{
482	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
483	NOREF(pvUser);
484	Port &= 3;
485	if (cb != 1 \|\| Port == 3)
486	{
487	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
488	return VERR_IOM_IOPORT_UNUSED;
489	}
490
491	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
492	int ret;
493	PITChannelState *s = &pit->channels[Port];
494	if (s->status_latched)
495	{
496	s->status_latched = 0;
497	ret = s->status;
498	}
499	else if (s->count_latched)
500	{
501	switch (s->count_latched)
502	{
503	default:
504	case RW_STATE_LSB:
505	ret = s->latched_count & 0xff;
506	s->count_latched = 0;
507	break;
508	case RW_STATE_MSB:
509	ret = s->latched_count >> 8;
510	s->count_latched = 0;
511	break;
512	case RW_STATE_WORD0:
513	ret = s->latched_count & 0xff;
514	s->count_latched = RW_STATE_MSB;
515	break;
516	}
517	}
518	else
519	{
520	int count;
521	switch (s->read_state)
522	{
523	default:
524	case RW_STATE_LSB:
525	count = pit_get_count(s);
526	ret = count & 0xff;
527	break;
528	case RW_STATE_MSB:
529	count = pit_get_count(s);
530	ret = (count >> 8) & 0xff;
531	break;
532	case RW_STATE_WORD0:
533	count = pit_get_count(s);
534	ret = count & 0xff;
535	s->read_state = RW_STATE_WORD1;
536	break;
537	case RW_STATE_WORD1:
538	count = pit_get_count(s);
539	ret = (count >> 8) & 0xff;
540	s->read_state = RW_STATE_WORD0;
541	break;
542	}
543	}
544
545	*pu32 = ret;
546	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
547	return VINF_SUCCESS;
548	}
549
550
551	/**
552	* Port I/O Handler for OUT operations.
553	*
554	* @returns VBox status code.
555	*
556	* @param pDevIns The device instance.
557	* @param pvUser User argument - ignored.
558	* @param Port Port number used for the IN operation.
559	* @param u32 The value to output.
560	* @param cb The value size in bytes.
561	*/
562	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
563	{
564	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
565	NOREF(pvUser);
566	if (cb != 1)
567	return VINF_SUCCESS;
568
569	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
570	Port &= 3;
571	if (Port == 3)
572	{
573	/*
574	* Port 43h - Mode/Command Register.
575	* 7 6 5 4 3 2 1 0
576	* * * . . . . . . Select channel: 0 0 = Channel 0
577	* 0 1 = Channel 1
578	* 1 0 = Channel 2
579	* 1 1 = Read-back command (8254 only)
580	* (Illegal on 8253)
581	* (Illegal on PS/2 {JAM})
582	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
583	* 0 1 = Access mode: lobyte only
584	* 1 0 = Access mode: hibyte only
585	* 1 1 = Access mode: lobyte/hibyte
586	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
587	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
588	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
589	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
590	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
591	*/
592	unsigned channel = u32 >> 6;
593	if (channel == 3)
594	{
595	/* read-back command */
596	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
597	{
598	PITChannelState *s = &pit->channels[channel];
599	if (u32 & (2 << channel)) {
600	if (!(u32 & 0x20))
601	pit_latch_count(s);
602	if (!(u32 & 0x10) && !s->status_latched)
603	{
604	/* status latch */
605	/* XXX: add BCD and null count */
606	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
607	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
608	\| (s->rw_mode << 4)
609	\| (s->mode << 1)
610	\| s->bcd;
611	s->status_latched = 1;
612	}
613	}
614	}
615	}
616	else
617	{
618	PITChannelState *s = &pit->channels[channel];
619	unsigned access = (u32 >> 4) & 3;
620	if (access == 0)
621	pit_latch_count(s);
622	else
623	{
624	s->rw_mode = access;
625	s->read_state = access;
626	s->write_state = access;
627
628	s->mode = (u32 >> 1) & 7;
629	s->bcd = u32 & 1;
630	/* XXX: update irq timer ? */
631	}
632	}
633	}
634	else
635	{
636	#ifndef IN_RING3
637	return VINF_IOM_HC_IOPORT_WRITE;
638	#else /* IN_RING3 */
639	/*
640	* Port 40-42h - Channel Data Ports.
641	*/
642	PITChannelState *s = &pit->channels[Port];
643	switch(s->write_state)
644	{
645	default:
646	case RW_STATE_LSB:
647	pit_load_count(s, u32);
648	break;
649	case RW_STATE_MSB:
650	pit_load_count(s, u32 << 8);
651	break;
652	case RW_STATE_WORD0:
653	s->write_latch = u32;
654	s->write_state = RW_STATE_WORD1;
655	break;
656	case RW_STATE_WORD1:
657	pit_load_count(s, s->write_latch \| (u32 << 8));
658	s->write_state = RW_STATE_WORD0;
659	break;
660	}
661	#endif /* !IN_RING3 */
662	}
663	return VINF_SUCCESS;
664	}
665
666
667	/**
668	* Port I/O Handler for speaker IN operations.
669	*
670	* @returns VBox status code.
671	*
672	* @param pDevIns The device instance.
673	* @param pvUser User argument - ignored.
674	* @param Port Port number used for the IN operation.
675	* @param pu32 Where to store the result.
676	* @param cb Number of bytes read.
677	*/
678	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
679	{
680	NOREF(pvUser);
681	if (cb == 1)
682	{
683	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
684	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
685	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
686
687	/* bit 6,7 Parity error stuff. */
688	/* bit 5 - mirrors timer 2 output condition. */
689	const int fOut = pit_get_out(pThis, 2, u64Now);
690	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
691	ASSUMES ns timer freq, see assertion above. */
692	#ifndef FAKE_REFRESH_CLOCK
693	const int fRefresh = (u64Now / 15085) & 1;
694	#else
695	pThis->dummy_refresh_clock ^= 1;
696	const int fRefresh = pThis->dummy_refresh_clock;
697	#endif
698	/* bit 2,3 NMI / parity status stuff. */
699	/* bit 1 - speaker data status */
700	const int fSpeakerStatus = pThis->speaker_data_on;
701	/* bit 0 - timer 2 clock gate to speaker status. */
702	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
703
704	*pu32 = fTimer2GateStatus
705	\| (fSpeakerStatus << 1)
706	\| (fRefresh << 4)
707	\| (fOut << 5);
708	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
709	return VINF_SUCCESS;
710	}
711	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
712	return VERR_IOM_IOPORT_UNUSED;
713	}
714
715	#ifdef IN_RING3
716
717	/**
718	* Port I/O Handler for speaker OUT operations.
719	*
720	* @returns VBox status code.
721	*
722	* @param pDevIns The device instance.
723	* @param pvUser User argument - ignored.
724	* @param Port Port number used for the IN operation.
725	* @param u32 The value to output.
726	* @param cb The value size in bytes.
727	*/
728	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
729	{
730	NOREF(pvUser);
731	if (cb == 1)
732	{
733	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
734	pThis->speaker_data_on = (u32 >> 1) & 1;
735	pit_set_gate(pThis, 2, u32 & 1);
736	}
737	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
738	return VINF_SUCCESS;
739	}
740
741
742	/**
743	* @copydoc FNSSMDEVLIVEEXEC
744	*/
745	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
746	{
747	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
748	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
749	SSMR3PutU8( pSSM, pThis->channels[0].irq);
750	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
751	return VINF_SSM_DONT_CALL_AGAIN;
752	}
753
754
755	/**
756	* @copydoc FNSSMDEVSAVEEXEC
757	*/
758	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
759	{
760	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
761	unsigned i;
762
763	/* The config. */
764	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
765
766	/* The state. */
767	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
768	{
769	PITChannelState *s = &pThis->channels[i];
770	SSMR3PutU32(pSSM, s->count);
771	SSMR3PutU16(pSSM, s->latched_count);
772	SSMR3PutU8(pSSM, s->count_latched);
773	SSMR3PutU8(pSSM, s->status_latched);
774	SSMR3PutU8(pSSM, s->status);
775	SSMR3PutU8(pSSM, s->read_state);
776	SSMR3PutU8(pSSM, s->write_state);
777	SSMR3PutU8(pSSM, s->write_latch);
778	SSMR3PutU8(pSSM, s->rw_mode);
779	SSMR3PutU8(pSSM, s->mode);
780	SSMR3PutU8(pSSM, s->bcd);
781	SSMR3PutU8(pSSM, s->gate);
782	SSMR3PutU64(pSSM, s->count_load_time);
783	SSMR3PutU64(pSSM, s->u64NextTS);
784	SSMR3PutU64(pSSM, s->u64ReloadTS);
785	SSMR3PutS64(pSSM, s->next_transition_time);
786	if (s->CTX_SUFF(pTimer))
787	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
788	}
789
790	SSMR3PutS32(pSSM, pThis->speaker_data_on);
791
792
793	#ifdef FAKE_REFRESH_CLOCK
794	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
795	#else
796	SSMR3PutS32(pSSM, 0);
797	#endif
798
799	SSMR3PutU8(pSSM, pThis->fDisabledByHpet);
800
801	return 0;
802	}
803
804
805	/**
806	* @copydoc FNSSMDEVLOADEXEC
807	*/
808	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
809	{
810	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
811	int rc;
812
813	if ( uVersion != PIT_SAVED_STATE_VERSION
814	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
815	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
816	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
817
818	/* The config. */
819	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
820	{
821	RTIOPORT IOPortBaseCfg;
822	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
823	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
824	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
825	IOPortBaseCfg, pThis->IOPortBaseCfg);
826
827	uint8_t u8Irq;
828	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
829	if (u8Irq != pThis->channels[0].irq)
830	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
831	u8Irq, pThis->channels[0].irq);
832
833	bool fSpeakerCfg;
834	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
835	if (fSpeakerCfg != pThis->fSpeakerCfg)
836	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
837	fSpeakerCfg, pThis->fSpeakerCfg);
838	}
839
840	if (uPass != SSM_PASS_FINAL)
841	return VINF_SUCCESS;
842
843	/* The state. */
844	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
845	{
846	PITChannelState *s = &pThis->channels[i];
847	SSMR3GetU32(pSSM, &s->count);
848	SSMR3GetU16(pSSM, &s->latched_count);
849	SSMR3GetU8(pSSM, &s->count_latched);
850	SSMR3GetU8(pSSM, &s->status_latched);
851	SSMR3GetU8(pSSM, &s->status);
852	SSMR3GetU8(pSSM, &s->read_state);
853	SSMR3GetU8(pSSM, &s->write_state);
854	SSMR3GetU8(pSSM, &s->write_latch);
855	SSMR3GetU8(pSSM, &s->rw_mode);
856	SSMR3GetU8(pSSM, &s->mode);
857	SSMR3GetU8(pSSM, &s->bcd);
858	SSMR3GetU8(pSSM, &s->gate);
859	SSMR3GetU64(pSSM, &s->count_load_time);
860	SSMR3GetU64(pSSM, &s->u64NextTS);
861	SSMR3GetU64(pSSM, &s->u64ReloadTS);
862	SSMR3GetS64(pSSM, &s->next_transition_time);
863	if (s->CTX_SUFF(pTimer))
864	{
865	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
866	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
867	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
868	}
869	pThis->channels[0].cRelLogEntries = 0;
870	}
871
872	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
873	#ifdef FAKE_REFRESH_CLOCK
874	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
875	#else
876	int32_t u32Dummy;
877	SSMR3GetS32(pSSM, &u32Dummy);
878	#endif
879
880	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
881	SSMR3GetU8(pSSM, &pThis->fDisabledByHpet);
882
883	return 0;
884	}
885
886
887	/**
888	* Device timer callback function.
889	*
890	* @param pDevIns Device instance of the device which registered the timer.
891	* @param pTimer The timer handle.
892	* @param pvUser Pointer to the PIT channel state.
893	*/
894	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
895	{
896	PITChannelState s = (PITChannelState )pvUser;
897	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
898	Log(("pitTimer\n"));
899	pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer));
900	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
901	}
902
903
904	/**
905	* Relocation notification.
906	*
907	* @returns VBox status.
908	* @param pDevIns The device instance data.
909	* @param offDelta The delta relative to the old address.
910	*/
911	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
912	{
913	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
914	unsigned i;
915	LogFlow(("pitRelocate: \n"));
916
917	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
918	{
919	PITChannelState *pCh = &pThis->channels[i];
920	if (pCh->pTimerR3)
921	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
922	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
923	}
924	}
925
926	/** @todo remove this! */
927	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
928
929	/**
930	* Reset notification.
931	*
932	* @returns VBox status.
933	* @param pDevIns The device instance data.
934	*/
935	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
936	{
937	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
938	unsigned i;
939	LogFlow(("pitReset: \n"));
940
941	pThis->fDisabledByHpet = false;
942
943	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
944	{
945	PITChannelState *s = &pThis->channels[i];
946
947	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
948	s->latched_count = 0;
949	s->count_latched = 0;
950	s->status_latched = 0;
951	s->status = 0;
952	s->read_state = 0;
953	s->write_state = 0;
954	s->write_latch = 0;
955	s->rw_mode = 0;
956	s->bcd = 0;
957	#endif
958	s->u64NextTS = UINT64_MAX;
959	s->cRelLogEntries = 0;
960	s->mode = 3;
961	s->gate = (i != 2);
962	pit_load_count(s, 0);
963	}
964	}
965
966
967	/**
968	* Info handler, device version.
969	*
970	* @param pDevIns Device instance which registered the info.
971	* @param pHlp Callback functions for doing output.
972	* @param pszArgs Argument string. Optional and specific to the handler.
973	*/
974	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
975	{
976	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
977	unsigned i;
978	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
979	{
980	const PITChannelState *pCh = &pThis->channels[i];
981
982	pHlp->pfnPrintf(pHlp,
983	"PIT (i8254) channel %d status: irq=%#x\n"
984	" count=%08x" " latched_count=%04x count_latched=%02x\n"
985	" status=%02x status_latched=%02x read_state=%02x\n"
986	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
987	" mode=%02x bcd=%02x gate=%02x\n"
988	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
989	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
990	,
991	i, pCh->irq,
992	pCh->count, pCh->latched_count, pCh->count_latched,
993	pCh->status, pCh->status_latched, pCh->read_state,
994	pCh->write_state, pCh->write_latch, pCh->rw_mode,
995	pCh->mode, pCh->bcd, pCh->gate,
996	pCh->count_load_time, pCh->next_transition_time,
997	pCh->u64ReloadTS, pCh->u64NextTS);
998	}
999	#ifdef FAKE_REFRESH_CLOCK
1000	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
1001	pThis->speaker_data_on, pThis->dummy_refresh_clock);
1002	#else
1003	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
1004	#endif
1005	if (pThis->fDisabledByHpet)
1006	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
1007	}
1008
1009	/**
1010	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1011	*/
1012	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
1013	{
1014	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
1015	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1016	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
1017	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIPITPORT, &pThis->IPITPort);
1018	return NULL;
1019	}
1020
1021	/**
1022	* @interface_method_impl{PDMIPITPORT,pfnNotifyHpetLegacy}
1023	*
1024	* @returns VBox status code
1025	* @param pInterface Pointer to the interface structure containing the called function pointer.
1026	*/
1027	static DECLCALLBACK(int) pitNotifyHpetLegacy(PPDMIPITPORT pInterface, bool fActivate)
1028	{
1029	PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IPITPort);
1030	pThis->fDisabledByHpet = fActivate;
1031	return VINF_SUCCESS;
1032	}
1033
1034	/**
1035	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1036	*/
1037	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1038	{
1039	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1040	int rc;
1041	uint8_t u8Irq;
1042	uint16_t u16Base;
1043	bool fSpeaker;
1044	bool fGCEnabled;
1045	bool fR0Enabled;
1046	unsigned i;
1047	Assert(iInstance == 0);
1048
1049	/*
1050	* Validate configuration.
1051	*/
1052	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1053	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1054
1055	/*
1056	* Init the data.
1057	*/
1058	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1059	if (RT_FAILURE(rc))
1060	return PDMDEV_SET_ERROR(pDevIns, rc,
1061	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1062
1063	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1064	if (RT_FAILURE(rc))
1065	return PDMDEV_SET_ERROR(pDevIns, rc,
1066	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1067
1068	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1069	if (RT_FAILURE(rc))
1070	return PDMDEV_SET_ERROR(pDevIns, rc,
1071	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1072
1073	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1074	if (RT_FAILURE(rc))
1075	return PDMDEV_SET_ERROR(pDevIns, rc,
1076	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1077
1078	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1079	if (RT_FAILURE(rc))
1080	return PDMDEV_SET_ERROR(pDevIns, rc,
1081	N_("Configuration error: failed to read R0Enabled as boolean"));
1082
1083	pThis->pDevIns = pDevIns;
1084	pThis->IOPortBaseCfg = u16Base;
1085	pThis->fSpeakerCfg = fSpeaker;
1086	pThis->channels[0].irq = u8Irq;
1087	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1088	{
1089	pThis->channels[i].pPitR3 = pThis;
1090	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1091	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1092	}
1093
1094	/*
1095	* Create timer, register I/O Ports and save state.
1096	*/
1097	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1098	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1099	&pThis->channels[0].pTimerR3);
1100	if (RT_FAILURE(rc))
1101	return rc;
1102	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1103	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1104
1105	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1106	if (RT_FAILURE(rc))
1107	return rc;
1108	if (fGCEnabled)
1109	{
1110	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1111	if (RT_FAILURE(rc))
1112	return rc;
1113	}
1114	if (fR0Enabled)
1115	{
1116	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1117	if (RT_FAILURE(rc))
1118	return rc;
1119	}
1120
1121	if (fSpeaker)
1122	{
1123	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1124	if (RT_FAILURE(rc))
1125	return rc;
1126	if (fGCEnabled)
1127	{
1128	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1129	if (RT_FAILURE(rc))
1130	return rc;
1131	}
1132	}
1133
1134	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1135	if (RT_FAILURE(rc))
1136	return rc;
1137
1138	/*
1139	* Interfaces
1140	*/
1141	/* IBase */
1142	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1143	/* IPITPort */
1144	pThis->IPITPort.pfnNotifyHpetLegacy = pitNotifyHpetLegacy;
1145
1146	/*
1147	* Initialize the device state.
1148	*/
1149	pitReset(pDevIns);
1150
1151	/*
1152	* Register statistics and debug info.
1153	*/
1154	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1155	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1156
1157	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1158
1159	return VINF_SUCCESS;
1160	}
1161
1162
1163	/**
1164	* The device registration structure.
1165	*/
1166	const PDMDEVREG g_DeviceI8254 =
1167	{
1168	/* u32Version */
1169	PDM_DEVREG_VERSION,
1170	/* szName */
1171	"i8254",
1172	/* szRCMod */
1173	"VBoxDDGC.gc",
1174	/* szR0Mod */
1175	"VBoxDDR0.r0",
1176	/* pszDescription */
1177	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1178	/* fFlags */
1179	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1180	/* fClass */
1181	PDM_DEVREG_CLASS_PIT,
1182	/* cMaxInstances */
1183	1,
1184	/* cbInstance */
1185	sizeof(PITState),
1186	/* pfnConstruct */
1187	pitConstruct,
1188	/* pfnDestruct */
1189	NULL,
1190	/* pfnRelocate */
1191	pitRelocate,
1192	/* pfnIOCtl */
1193	NULL,
1194	/* pfnPowerOn */
1195	NULL,
1196	/* pfnReset */
1197	pitReset,
1198	/* pfnSuspend */
1199	NULL,
1200	/* pfnResume */
1201	NULL,
1202	/* pfnAttach */
1203	NULL,
1204	/* pfnDetach */
1205	NULL,
1206	/* pfnQueryInterface */
1207	NULL,
1208	/* pfnInitComplete */
1209	NULL,
1210	/* pfnPowerOff */
1211	NULL,
1212	/* pfnSoftReset */
1213	NULL,
1214	/* u32VersionEnd */
1215	PDM_DEVREG_VERSION
1216	};
1217
1218	#endif /* IN_RING3 */
1219	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 27125

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