DevPit-i8254.cpp@ 34691

Last change on this file since 34691 was 34691, checked in by vboxsync, 14 years ago
PIT: Fixed mode 3 timer interrupts (no longer doubled IRQ0 frequency).
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File size: 40.4 KB

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1	/* $Id: DevPit-i8254.cpp 34691 2010-12-03 12:43:16Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PIT
47	#include <VBox/pdmdev.h>
48	#include <VBox/log.h>
49	#include <VBox/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm-math.h>
52
53	#ifdef IN_RING3
54	# include <iprt/alloc.h>
55	# include <iprt/string.h>
56	# include <iprt/uuid.h>
57	#endif /* IN_RING3 */
58
59	#include "../Builtins.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The current saved state version. */
74	#define PIT_SAVED_STATE_VERSION 4
75	/** The saved state version used by VirtualBox 3.1 and earlier.
76	* This did not include disable by HPET flag. */
77	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
78	/** The saved state version used by VirtualBox 3.0 and earlier.
79	* This did not include the config part. */
80	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
81
82	/** @def FAKE_REFRESH_CLOCK
83	* Define this to flip the 15usec refresh bit on every read.
84	* If not defined, it will be flipped correctly. */
85	/* #define FAKE_REFRESH_CLOCK */
86	#ifdef DOXYGEN_RUNNING
87	# define FAKE_REFRESH_CLOCK
88	#endif
89
90
91	/*******************************************************************************
92	* Structures and Typedefs *
93	*******************************************************************************/
94	typedef struct PITChannelState
95	{
96	/** Pointer to the instance data - R3 Ptr. */
97	R3PTRTYPE(struct PITState *) pPitR3;
98	/** The timer - R3 Ptr. */
99	PTMTIMERR3 pTimerR3;
100	/** Pointer to the instance data - R0 Ptr. */
101	R0PTRTYPE(struct PITState *) pPitR0;
102	/** The timer - R0 Ptr. */
103	PTMTIMERR0 pTimerR0;
104	/** Pointer to the instance data - RC Ptr. */
105	RCPTRTYPE(struct PITState *) pPitRC;
106	/** The timer - RC Ptr. */
107	PTMTIMERRC pTimerRC;
108	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
109	uint64_t u64ReloadTS;
110	/** The actual time of the next tick.
111	* As apposed to the next_transition_time which contains the correct time of the next tick. */
112	uint64_t u64NextTS;
113
114	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
115	uint64_t count_load_time;
116	/* irq handling */
117	int64_t next_transition_time;
118	int32_t irq;
119	/** Number of release log entries. Used to prevent flooding. */
120	uint32_t cRelLogEntries;
121
122	uint32_t count; /* can be 65536 */
123	uint16_t latched_count;
124	uint8_t count_latched;
125	uint8_t status_latched;
126
127	uint8_t status;
128	uint8_t read_state;
129	uint8_t write_state;
130	uint8_t write_latch;
131
132	uint8_t rw_mode;
133	uint8_t mode;
134	uint8_t bcd; /* not supported */
135	uint8_t gate; /* timer start */
136
137	} PITChannelState;
138
139	typedef struct PITState
140	{
141	PITChannelState channels[3];
142	/** Speaker data. */
143	int32_t speaker_data_on;
144	#ifdef FAKE_REFRESH_CLOCK
145	/** Speaker dummy. */
146	int32_t dummy_refresh_clock;
147	#else
148	uint32_t Alignment1;
149	#endif
150	/** Config: I/O port base. */
151	RTIOPORT IOPortBaseCfg;
152	/** Config: Speaker enabled. */
153	bool fSpeakerCfg;
154	bool fDisabledByHpet;
155	bool afAlignment0[HC_ARCH_BITS == 32 ? 4 : 4];
156	/** PIT port interface. */
157	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
158	/** Pointer to the device instance. */
159	PPDMDEVINSR3 pDevIns;
160	/** Number of IRQs that's been raised. */
161	STAMCOUNTER StatPITIrq;
162	/** Profiling the timer callback handler. */
163	STAMPROFILEADV StatPITHandler;
164	} PITState;
165
166
167	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
168	/*******************************************************************************
169	* Internal Functions *
170	*******************************************************************************/
171	RT_C_DECLS_BEGIN
172	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
173	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
174	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
175	#ifdef IN_RING3
176	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
177	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now);
178	#endif
179	RT_C_DECLS_END
180
181
182
183
184	static int pit_get_count(PITChannelState *s)
185	{
186	uint64_t d;
187	int counter;
188	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
189
190	if (s->mode == 2)
191	{
192	if (s->u64NextTS == UINT64_MAX)
193	{
194	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
195	return s->count - (d % s->count); /** @todo check this value. */
196	}
197	uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
198	if (!Interval)
199	return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
200	d = TMTimerGet(pTimer);
201	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
202	if (d >= s->count)
203	return 1;
204	return s->count - d;
205	}
206	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
207	switch(s->mode) {
208	case 0:
209	case 1:
210	case 4:
211	case 5:
212	counter = (s->count - d) & 0xffff;
213	break;
214	case 3:
215	/* XXX: may be incorrect for odd counts */
216	counter = s->count - ((2 * d) % s->count);
217	break;
218	default:
219	counter = s->count - (d % s->count);
220	break;
221	}
222	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
223	return counter;
224	}
225
226	/* get pit output bit */
227	static int pit_get_out1(PITChannelState *s, int64_t current_time)
228	{
229	uint64_t d;
230	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
231	int out;
232
233	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
234	switch(s->mode) {
235	default:
236	case 0:
237	out = (d >= s->count);
238	break;
239	case 1:
240	out = (d < s->count);
241	break;
242	case 2:
243	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
244	if ((d % s->count) == 0 && d != 0)
245	out = 1;
246	else
247	out = 0;
248	break;
249	case 3:
250	out = (d % s->count) < ((s->count + 1) >> 1);
251	break;
252	case 4:
253	case 5:
254	out = (d == s->count);
255	break;
256	}
257	return out;
258	}
259
260
261	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
262	{
263	PITChannelState *s = &pit->channels[channel];
264	return pit_get_out1(s, current_time);
265	}
266
267
268	static int pit_get_gate(PITState *pit, int channel)
269	{
270	PITChannelState *s = &pit->channels[channel];
271	return s->gate;
272	}
273
274
275	/* if already latched, do not latch again */
276	static void pit_latch_count(PITChannelState *s)
277	{
278	if (!s->count_latched) {
279	s->latched_count = pit_get_count(s);
280	s->count_latched = s->rw_mode;
281	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
282	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
283	}
284	}
285
286	#ifdef IN_RING3
287
288	/* val must be 0 or 1 */
289	static void pit_set_gate(PITState *pit, int channel, int val)
290	{
291	PITChannelState *s = &pit->channels[channel];
292	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
293	Assert((val & 1) == val);
294
295	switch(s->mode) {
296	default:
297	case 0:
298	case 4:
299	/* XXX: just disable/enable counting */
300	break;
301	case 1:
302	case 5:
303	if (s->gate < val) {
304	/* restart counting on rising edge */
305	Log(("pit_set_gate: restarting mode %d\n", s->mode));
306	s->count_load_time = TMTimerGet(pTimer);
307	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
308	}
309	break;
310	case 2:
311	case 3:
312	if (s->gate < val) {
313	/* restart counting on rising edge */
314	Log(("pit_set_gate: restarting mode %d\n", s->mode));
315	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
316	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
317	}
318	/* XXX: disable/enable counting */
319	break;
320	}
321	s->gate = val;
322	}
323
324	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
325	{
326	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
327	if (val == 0)
328	val = 0x10000;
329	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
330	s->count = val;
331	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
332
333	/* log the new rate (ch 0 only). */
334	if (s->pTimerR3 /* ch 0 */)
335	{
336	if (s->cRelLogEntries++ < 32)
337	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
338	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
339	else
340	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
341	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
342	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
343	}
344	else
345	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
346	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100,
347	s - &s->CTX_SUFF(pPit)->channels[0]));
348	}
349
350	/* return -1 if no transition will occur. */
351	static int64_t pit_get_next_transition_time(PITChannelState *s,
352	uint64_t current_time)
353	{
354	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
355	uint64_t d, next_time, base;
356	uint32_t period2;
357
358	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
359	switch(s->mode) {
360	default:
361	case 0:
362	case 1:
363	if (d < s->count)
364	next_time = s->count;
365	else
366	return -1;
367	break;
368	/*
369	* Mode 2: The period is count + 1 PIT ticks.
370	* When the counter reaches 1 we sent the output low (for channel 0 that
371	* means raise an irq). On the next tick, where we should be decrementing
372	* from 1 to 0, the count is loaded and the output goes high (channel 0
373	* means clearing the irq).
374	*
375	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
376	* the irq. We also don't set it until we reach 0, which is a tick late - will
377	* try fix that later some day.
378	*/
379	case 2:
380	base = (d / s->count) * s->count;
381	#ifndef VBOX /* see above */
382	if ((d - base) == 0 && d != 0)
383	next_time = base + s->count;
384	else
385	#endif
386	next_time = base + s->count + 1;
387	break;
388	case 3:
389	base = (d / s->count) * s->count;
390	period2 = ((s->count + 1) >> 1);
391	if ((d - base) < period2)
392	next_time = base + period2;
393	else
394	next_time = base + s->count;
395	break;
396	case 4:
397	case 5:
398	if (d < s->count)
399	next_time = s->count;
400	else if (d == s->count)
401	next_time = s->count + 1;
402	else
403	return -1;
404	break;
405	}
406	/* convert to timer units */
407	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
408	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
409	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
410	/* fix potential rounding problems */
411	/* XXX: better solution: use a clock at PIT_FREQ Hz */
412	if (next_time <= current_time)
413	next_time = current_time + 1;
414	return next_time;
415	}
416
417	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now)
418	{
419	int64_t expire_time;
420	int irq_level;
421	PPDMDEVINS pDevIns;
422	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
423
424	if (!s->CTX_SUFF(pTimer))
425	return;
426	expire_time = pit_get_next_transition_time(s, current_time);
427	irq_level = pit_get_out1(s, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
428
429	/* If PIT disabled by HPET - just disconnect ticks from interrupt controllers, and not modify
430	* other moments of device functioning.
431	* @todo: is it correct?
432	*/
433	if (!s->pPitR3->fDisabledByHpet)
434	{
435	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
436
437	if (s->mode == 2)
438	{
439	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for years). */
440	PDMDevHlpISASetIrq(pDevIns, s->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
441	} else
442	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
443	}
444
445	if (irq_level)
446	{
447	s->u64ReloadTS = now;
448	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
449	}
450
451	if (expire_time != -1)
452	{
453	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
454	s->u64NextTS = expire_time;
455	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
456	}
457	else
458	{
459	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
460	TMTimerStop(s->CTX_SUFF(pTimer));
461	s->u64NextTS = UINT64_MAX;
462	}
463	s->next_transition_time = expire_time;
464	}
465
466	#endif /* IN_RING3 */
467
468
469	/**
470	* Port I/O Handler for IN operations.
471	*
472	* @returns VBox status code.
473	*
474	* @param pDevIns The device instance.
475	* @param pvUser User argument - ignored.
476	* @param Port Port number used for the IN operation.
477	* @param pu32 Where to store the result.
478	* @param cb Number of bytes read.
479	*/
480	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
481	{
482	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
483	NOREF(pvUser);
484	Port &= 3;
485	if (cb != 1 \|\| Port == 3)
486	{
487	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
488	return VERR_IOM_IOPORT_UNUSED;
489	}
490
491	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
492	int ret;
493	PITChannelState *s = &pit->channels[Port];
494	if (s->status_latched)
495	{
496	s->status_latched = 0;
497	ret = s->status;
498	}
499	else if (s->count_latched)
500	{
501	switch (s->count_latched)
502	{
503	default:
504	case RW_STATE_LSB:
505	ret = s->latched_count & 0xff;
506	s->count_latched = 0;
507	break;
508	case RW_STATE_MSB:
509	ret = s->latched_count >> 8;
510	s->count_latched = 0;
511	break;
512	case RW_STATE_WORD0:
513	ret = s->latched_count & 0xff;
514	s->count_latched = RW_STATE_MSB;
515	break;
516	}
517	}
518	else
519	{
520	int count;
521	switch (s->read_state)
522	{
523	default:
524	case RW_STATE_LSB:
525	count = pit_get_count(s);
526	ret = count & 0xff;
527	break;
528	case RW_STATE_MSB:
529	count = pit_get_count(s);
530	ret = (count >> 8) & 0xff;
531	break;
532	case RW_STATE_WORD0:
533	count = pit_get_count(s);
534	ret = count & 0xff;
535	s->read_state = RW_STATE_WORD1;
536	break;
537	case RW_STATE_WORD1:
538	count = pit_get_count(s);
539	ret = (count >> 8) & 0xff;
540	s->read_state = RW_STATE_WORD0;
541	break;
542	}
543	}
544
545	*pu32 = ret;
546	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
547	return VINF_SUCCESS;
548	}
549
550
551	/**
552	* Port I/O Handler for OUT operations.
553	*
554	* @returns VBox status code.
555	*
556	* @param pDevIns The device instance.
557	* @param pvUser User argument - ignored.
558	* @param Port Port number used for the IN operation.
559	* @param u32 The value to output.
560	* @param cb The value size in bytes.
561	*/
562	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
563	{
564	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
565	NOREF(pvUser);
566	if (cb != 1)
567	return VINF_SUCCESS;
568
569	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
570	Port &= 3;
571	if (Port == 3)
572	{
573	/*
574	* Port 43h - Mode/Command Register.
575	* 7 6 5 4 3 2 1 0
576	* * * . . . . . . Select channel: 0 0 = Channel 0
577	* 0 1 = Channel 1
578	* 1 0 = Channel 2
579	* 1 1 = Read-back command (8254 only)
580	* (Illegal on 8253)
581	* (Illegal on PS/2 {JAM})
582	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
583	* 0 1 = Access mode: lobyte only
584	* 1 0 = Access mode: hibyte only
585	* 1 1 = Access mode: lobyte/hibyte
586	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
587	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
588	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
589	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
590	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
591	*/
592	unsigned channel = u32 >> 6;
593	if (channel == 3)
594	{
595	/* read-back command */
596	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
597	{
598	PITChannelState *s = &pit->channels[channel];
599	if (u32 & (2 << channel)) {
600	if (!(u32 & 0x20))
601	pit_latch_count(s);
602	if (!(u32 & 0x10) && !s->status_latched)
603	{
604	/* status latch */
605	/* XXX: add BCD and null count */
606	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
607	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
608	\| (s->rw_mode << 4)
609	\| (s->mode << 1)
610	\| s->bcd;
611	s->status_latched = 1;
612	}
613	}
614	}
615	}
616	else
617	{
618	PITChannelState *s = &pit->channels[channel];
619	unsigned access = (u32 >> 4) & 3;
620	if (access == 0)
621	pit_latch_count(s);
622	else
623	{
624	s->rw_mode = access;
625	s->read_state = access;
626	s->write_state = access;
627
628	s->mode = (u32 >> 1) & 7;
629	s->bcd = u32 & 1;
630	/* XXX: update irq timer ? */
631	}
632	}
633	}
634	else
635	{
636	#ifndef IN_RING3
637	return VINF_IOM_HC_IOPORT_WRITE;
638	#else /* IN_RING3 */
639	/*
640	* Port 40-42h - Channel Data Ports.
641	*/
642	PITChannelState *s = &pit->channels[Port];
643	switch(s->write_state)
644	{
645	default:
646	case RW_STATE_LSB:
647	pit_load_count(s, u32);
648	break;
649	case RW_STATE_MSB:
650	pit_load_count(s, u32 << 8);
651	break;
652	case RW_STATE_WORD0:
653	s->write_latch = u32;
654	s->write_state = RW_STATE_WORD1;
655	break;
656	case RW_STATE_WORD1:
657	pit_load_count(s, s->write_latch \| (u32 << 8));
658	s->write_state = RW_STATE_WORD0;
659	break;
660	}
661	#endif /* !IN_RING3 */
662	}
663	return VINF_SUCCESS;
664	}
665
666
667	/**
668	* Port I/O Handler for speaker IN operations.
669	*
670	* @returns VBox status code.
671	*
672	* @param pDevIns The device instance.
673	* @param pvUser User argument - ignored.
674	* @param Port Port number used for the IN operation.
675	* @param pu32 Where to store the result.
676	* @param cb Number of bytes read.
677	*/
678	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
679	{
680	NOREF(pvUser);
681	if (cb == 1)
682	{
683	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
684	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
685	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
686
687	/* bit 6,7 Parity error stuff. */
688	/* bit 5 - mirrors timer 2 output condition. */
689	const int fOut = pit_get_out(pThis, 2, u64Now);
690	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
691	ASSUMES ns timer freq, see assertion above. */
692	#ifndef FAKE_REFRESH_CLOCK
693	const int fRefresh = (u64Now / 15085) & 1;
694	#else
695	pThis->dummy_refresh_clock ^= 1;
696	const int fRefresh = pThis->dummy_refresh_clock;
697	#endif
698	/* bit 2,3 NMI / parity status stuff. */
699	/* bit 1 - speaker data status */
700	const int fSpeakerStatus = pThis->speaker_data_on;
701	/* bit 0 - timer 2 clock gate to speaker status. */
702	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
703
704	*pu32 = fTimer2GateStatus
705	\| (fSpeakerStatus << 1)
706	\| (fRefresh << 4)
707	\| (fOut << 5);
708	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
709	return VINF_SUCCESS;
710	}
711	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
712	return VERR_IOM_IOPORT_UNUSED;
713	}
714
715	#ifdef IN_RING3
716
717	/**
718	* Port I/O Handler for speaker OUT operations.
719	*
720	* @returns VBox status code.
721	*
722	* @param pDevIns The device instance.
723	* @param pvUser User argument - ignored.
724	* @param Port Port number used for the IN operation.
725	* @param u32 The value to output.
726	* @param cb The value size in bytes.
727	*/
728	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
729	{
730	NOREF(pvUser);
731	if (cb == 1)
732	{
733	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
734	pThis->speaker_data_on = (u32 >> 1) & 1;
735	pit_set_gate(pThis, 2, u32 & 1);
736	}
737	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
738	return VINF_SUCCESS;
739	}
740
741
742	/**
743	* @copydoc FNSSMDEVLIVEEXEC
744	*/
745	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
746	{
747	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
748	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
749	SSMR3PutU8( pSSM, pThis->channels[0].irq);
750	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
751	return VINF_SSM_DONT_CALL_AGAIN;
752	}
753
754
755	/**
756	* @copydoc FNSSMDEVSAVEEXEC
757	*/
758	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
759	{
760	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
761	unsigned i;
762
763	/* The config. */
764	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
765
766	/* The state. */
767	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
768	{
769	PITChannelState *s = &pThis->channels[i];
770	SSMR3PutU32(pSSM, s->count);
771	SSMR3PutU16(pSSM, s->latched_count);
772	SSMR3PutU8(pSSM, s->count_latched);
773	SSMR3PutU8(pSSM, s->status_latched);
774	SSMR3PutU8(pSSM, s->status);
775	SSMR3PutU8(pSSM, s->read_state);
776	SSMR3PutU8(pSSM, s->write_state);
777	SSMR3PutU8(pSSM, s->write_latch);
778	SSMR3PutU8(pSSM, s->rw_mode);
779	SSMR3PutU8(pSSM, s->mode);
780	SSMR3PutU8(pSSM, s->bcd);
781	SSMR3PutU8(pSSM, s->gate);
782	SSMR3PutU64(pSSM, s->count_load_time);
783	SSMR3PutU64(pSSM, s->u64NextTS);
784	SSMR3PutU64(pSSM, s->u64ReloadTS);
785	SSMR3PutS64(pSSM, s->next_transition_time);
786	if (s->CTX_SUFF(pTimer))
787	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
788	}
789
790	SSMR3PutS32(pSSM, pThis->speaker_data_on);
791	#ifdef FAKE_REFRESH_CLOCK
792	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
793	#else
794	SSMR3PutS32(pSSM, 0);
795	#endif
796
797	return SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
798	}
799
800
801	/**
802	* @copydoc FNSSMDEVLOADEXEC
803	*/
804	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
805	{
806	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
807	int rc;
808
809	if ( uVersion != PIT_SAVED_STATE_VERSION
810	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
811	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
812	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
813
814	/* The config. */
815	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
816	{
817	RTIOPORT IOPortBaseCfg;
818	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
819	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
820	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
821	IOPortBaseCfg, pThis->IOPortBaseCfg);
822
823	uint8_t u8Irq;
824	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
825	if (u8Irq != pThis->channels[0].irq)
826	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
827	u8Irq, pThis->channels[0].irq);
828
829	bool fSpeakerCfg;
830	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
831	if (fSpeakerCfg != pThis->fSpeakerCfg)
832	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
833	fSpeakerCfg, pThis->fSpeakerCfg);
834	}
835
836	if (uPass != SSM_PASS_FINAL)
837	return VINF_SUCCESS;
838
839	/* The state. */
840	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
841	{
842	PITChannelState *s = &pThis->channels[i];
843	SSMR3GetU32(pSSM, &s->count);
844	SSMR3GetU16(pSSM, &s->latched_count);
845	SSMR3GetU8(pSSM, &s->count_latched);
846	SSMR3GetU8(pSSM, &s->status_latched);
847	SSMR3GetU8(pSSM, &s->status);
848	SSMR3GetU8(pSSM, &s->read_state);
849	SSMR3GetU8(pSSM, &s->write_state);
850	SSMR3GetU8(pSSM, &s->write_latch);
851	SSMR3GetU8(pSSM, &s->rw_mode);
852	SSMR3GetU8(pSSM, &s->mode);
853	SSMR3GetU8(pSSM, &s->bcd);
854	SSMR3GetU8(pSSM, &s->gate);
855	SSMR3GetU64(pSSM, &s->count_load_time);
856	SSMR3GetU64(pSSM, &s->u64NextTS);
857	SSMR3GetU64(pSSM, &s->u64ReloadTS);
858	SSMR3GetS64(pSSM, &s->next_transition_time);
859	if (s->CTX_SUFF(pTimer))
860	{
861	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
862	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
863	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
864	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
865	}
866	pThis->channels[i].cRelLogEntries = 0;
867	}
868
869	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
870	#ifdef FAKE_REFRESH_CLOCK
871	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
872	#else
873	int32_t u32Dummy;
874	SSMR3GetS32(pSSM, &u32Dummy);
875	#endif
876	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
877	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
878
879	return VINF_SUCCESS;
880	}
881
882
883	/**
884	* Device timer callback function.
885	*
886	* @param pDevIns Device instance of the device which registered the timer.
887	* @param pTimer The timer handle.
888	* @param pvUser Pointer to the PIT channel state.
889	*/
890	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
891	{
892	PITChannelState s = (PITChannelState )pvUser;
893	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
894	Log(("pitTimer\n"));
895	pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer));
896	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
897	}
898
899
900	/**
901	* Info handler, device version.
902	*
903	* @param pDevIns Device instance which registered the info.
904	* @param pHlp Callback functions for doing output.
905	* @param pszArgs Argument string. Optional and specific to the handler.
906	*/
907	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
908	{
909	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
910	unsigned i;
911	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
912	{
913	const PITChannelState *pCh = &pThis->channels[i];
914
915	pHlp->pfnPrintf(pHlp,
916	"PIT (i8254) channel %d status: irq=%#x\n"
917	" count=%08x" " latched_count=%04x count_latched=%02x\n"
918	" status=%02x status_latched=%02x read_state=%02x\n"
919	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
920	" mode=%02x bcd=%02x gate=%02x\n"
921	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
922	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
923	,
924	i, pCh->irq,
925	pCh->count, pCh->latched_count, pCh->count_latched,
926	pCh->status, pCh->status_latched, pCh->read_state,
927	pCh->write_state, pCh->write_latch, pCh->rw_mode,
928	pCh->mode, pCh->bcd, pCh->gate,
929	pCh->count_load_time, pCh->next_transition_time,
930	pCh->u64ReloadTS, pCh->u64NextTS);
931	}
932	#ifdef FAKE_REFRESH_CLOCK
933	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
934	pThis->speaker_data_on, pThis->dummy_refresh_clock);
935	#else
936	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
937	#endif
938	if (pThis->fDisabledByHpet)
939	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
940	}
941
942
943	/**
944	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
945	*/
946	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
947	{
948	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
949	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
950	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
951	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
952	return NULL;
953	}
954
955
956	/**
957	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
958	*/
959	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
960	{
961	PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IHpetLegacyNotify);
962	pThis->fDisabledByHpet = fActivated;
963	}
964
965
966	/**
967	* Relocation notification.
968	*
969	* @returns VBox status.
970	* @param pDevIns The device instance data.
971	* @param offDelta The delta relative to the old address.
972	*/
973	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
974	{
975	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
976	unsigned i;
977	LogFlow(("pitRelocate: \n"));
978
979	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
980	{
981	PITChannelState *pCh = &pThis->channels[i];
982	if (pCh->pTimerR3)
983	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
984	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
985	}
986	}
987
988
989	/**
990	* Reset notification.
991	*
992	* @returns VBox status.
993	* @param pDevIns The device instance data.
994	*/
995	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
996	{
997	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
998	unsigned i;
999	LogFlow(("pitReset: \n"));
1000
1001	pThis->fDisabledByHpet = false;
1002
1003	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1004	{
1005	PITChannelState *s = &pThis->channels[i];
1006
1007	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1008	s->latched_count = 0;
1009	s->count_latched = 0;
1010	s->status_latched = 0;
1011	s->status = 0;
1012	s->read_state = 0;
1013	s->write_state = 0;
1014	s->write_latch = 0;
1015	s->rw_mode = 0;
1016	s->bcd = 0;
1017	#endif
1018	s->u64NextTS = UINT64_MAX;
1019	s->cRelLogEntries = 0;
1020	s->mode = 3;
1021	s->gate = (i != 2);
1022	pit_load_count(s, 0);
1023	}
1024	}
1025
1026
1027	/**
1028	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1029	*/
1030	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1031	{
1032	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1033	int rc;
1034	uint8_t u8Irq;
1035	uint16_t u16Base;
1036	bool fSpeaker;
1037	bool fGCEnabled;
1038	bool fR0Enabled;
1039	unsigned i;
1040	Assert(iInstance == 0);
1041
1042	/*
1043	* Validate configuration.
1044	*/
1045	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1046	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1047
1048	/*
1049	* Init the data.
1050	*/
1051	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1052	if (RT_FAILURE(rc))
1053	return PDMDEV_SET_ERROR(pDevIns, rc,
1054	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1055
1056	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1057	if (RT_FAILURE(rc))
1058	return PDMDEV_SET_ERROR(pDevIns, rc,
1059	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1060
1061	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1062	if (RT_FAILURE(rc))
1063	return PDMDEV_SET_ERROR(pDevIns, rc,
1064	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1065
1066	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1067	if (RT_FAILURE(rc))
1068	return PDMDEV_SET_ERROR(pDevIns, rc,
1069	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1070
1071	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1072	if (RT_FAILURE(rc))
1073	return PDMDEV_SET_ERROR(pDevIns, rc,
1074	N_("Configuration error: failed to read R0Enabled as boolean"));
1075
1076	pThis->pDevIns = pDevIns;
1077	pThis->IOPortBaseCfg = u16Base;
1078	pThis->fSpeakerCfg = fSpeaker;
1079	pThis->channels[0].irq = u8Irq;
1080	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1081	{
1082	pThis->channels[i].pPitR3 = pThis;
1083	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1084	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1085	}
1086
1087	/*
1088	* Interfaces
1089	*/
1090	/* IBase */
1091	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1092	/* IHpetLegacyNotify */
1093	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1094
1095	/*
1096	* Create timer, register I/O Ports and save state.
1097	*/
1098	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1099	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1100	&pThis->channels[0].pTimerR3);
1101	if (RT_FAILURE(rc))
1102	return rc;
1103	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1104	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1105
1106	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1107	if (RT_FAILURE(rc))
1108	return rc;
1109	if (fGCEnabled)
1110	{
1111	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1112	if (RT_FAILURE(rc))
1113	return rc;
1114	}
1115	if (fR0Enabled)
1116	{
1117	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1118	if (RT_FAILURE(rc))
1119	return rc;
1120	}
1121
1122	if (fSpeaker)
1123	{
1124	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1125	if (RT_FAILURE(rc))
1126	return rc;
1127	if (fGCEnabled)
1128	{
1129	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1130	if (RT_FAILURE(rc))
1131	return rc;
1132	}
1133	}
1134
1135	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1136	if (RT_FAILURE(rc))
1137	return rc;
1138
1139	/*
1140	* Initialize the device state.
1141	*/
1142	pitReset(pDevIns);
1143
1144	/*
1145	* Register statistics and debug info.
1146	*/
1147	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1148	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1149
1150	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1151
1152	return VINF_SUCCESS;
1153	}
1154
1155
1156	/**
1157	* The device registration structure.
1158	*/
1159	const PDMDEVREG g_DeviceI8254 =
1160	{
1161	/* u32Version */
1162	PDM_DEVREG_VERSION,
1163	/* szName */
1164	"i8254",
1165	/* szRCMod */
1166	"VBoxDDGC.gc",
1167	/* szR0Mod */
1168	"VBoxDDR0.r0",
1169	/* pszDescription */
1170	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1171	/* fFlags */
1172	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1173	/* fClass */
1174	PDM_DEVREG_CLASS_PIT,
1175	/* cMaxInstances */
1176	1,
1177	/* cbInstance */
1178	sizeof(PITState),
1179	/* pfnConstruct */
1180	pitConstruct,
1181	/* pfnDestruct */
1182	NULL,
1183	/* pfnRelocate */
1184	pitRelocate,
1185	/* pfnIOCtl */
1186	NULL,
1187	/* pfnPowerOn */
1188	NULL,
1189	/* pfnReset */
1190	pitReset,
1191	/* pfnSuspend */
1192	NULL,
1193	/* pfnResume */
1194	NULL,
1195	/* pfnAttach */
1196	NULL,
1197	/* pfnDetach */
1198	NULL,
1199	/* pfnQueryInterface */
1200	NULL,
1201	/* pfnInitComplete */
1202	NULL,
1203	/* pfnPowerOff */
1204	NULL,
1205	/* pfnSoftReset */
1206	NULL,
1207	/* u32VersionEnd */
1208	PDM_DEVREG_VERSION
1209	};
1210
1211	#endif /* IN_RING3 */
1212	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 34691

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