DevPit-i8254.cpp@ 34914

Last change on this file since 34914 was 34900, checked in by vboxsync, 14 years ago
Moved rounding fix so that the PIT IRQ stat still works.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 40.6 KB

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1	/* $Id: DevPit-i8254.cpp 34900 2010-12-09 15:24:38Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PIT
47	#include <VBox/pdmdev.h>
48	#include <VBox/log.h>
49	#include <VBox/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm-math.h>
52
53	#ifdef IN_RING3
54	# include <iprt/alloc.h>
55	# include <iprt/string.h>
56	# include <iprt/uuid.h>
57	#endif /* IN_RING3 */
58
59	#include "../Builtins.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The current saved state version. */
74	#define PIT_SAVED_STATE_VERSION 4
75	/** The saved state version used by VirtualBox 3.1 and earlier.
76	* This did not include disable by HPET flag. */
77	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
78	/** The saved state version used by VirtualBox 3.0 and earlier.
79	* This did not include the config part. */
80	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
81
82	/** @def FAKE_REFRESH_CLOCK
83	* Define this to flip the 15usec refresh bit on every read.
84	* If not defined, it will be flipped correctly. */
85	/* #define FAKE_REFRESH_CLOCK */
86	#ifdef DOXYGEN_RUNNING
87	# define FAKE_REFRESH_CLOCK
88	#endif
89
90
91	/*******************************************************************************
92	* Structures and Typedefs *
93	*******************************************************************************/
94	typedef struct PITChannelState
95	{
96	/** Pointer to the instance data - R3 Ptr. */
97	R3PTRTYPE(struct PITState *) pPitR3;
98	/** The timer - R3 Ptr. */
99	PTMTIMERR3 pTimerR3;
100	/** Pointer to the instance data - R0 Ptr. */
101	R0PTRTYPE(struct PITState *) pPitR0;
102	/** The timer - R0 Ptr. */
103	PTMTIMERR0 pTimerR0;
104	/** Pointer to the instance data - RC Ptr. */
105	RCPTRTYPE(struct PITState *) pPitRC;
106	/** The timer - RC Ptr. */
107	PTMTIMERRC pTimerRC;
108	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
109	uint64_t u64ReloadTS;
110	/** The actual time of the next tick.
111	* As apposed to the next_transition_time which contains the correct time of the next tick. */
112	uint64_t u64NextTS;
113
114	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
115	uint64_t count_load_time;
116	/* irq handling */
117	int64_t next_transition_time;
118	int32_t irq;
119	/** Number of release log entries. Used to prevent flooding. */
120	uint32_t cRelLogEntries;
121
122	uint32_t count; /* can be 65536 */
123	uint16_t latched_count;
124	uint8_t count_latched;
125	uint8_t status_latched;
126
127	uint8_t status;
128	uint8_t read_state;
129	uint8_t write_state;
130	uint8_t write_latch;
131
132	uint8_t rw_mode;
133	uint8_t mode;
134	uint8_t bcd; /* not supported */
135	uint8_t gate; /* timer start */
136
137	} PITChannelState;
138
139	typedef struct PITState
140	{
141	PITChannelState channels[3];
142	/** Speaker data. */
143	int32_t speaker_data_on;
144	#ifdef FAKE_REFRESH_CLOCK
145	/** Speaker dummy. */
146	int32_t dummy_refresh_clock;
147	#else
148	uint32_t Alignment1;
149	#endif
150	/** Config: I/O port base. */
151	RTIOPORT IOPortBaseCfg;
152	/** Config: Speaker enabled. */
153	bool fSpeakerCfg;
154	bool fDisabledByHpet;
155	bool afAlignment0[HC_ARCH_BITS == 32 ? 4 : 4];
156	/** PIT port interface. */
157	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
158	/** Pointer to the device instance. */
159	PPDMDEVINSR3 pDevIns;
160	/** Number of IRQs that's been raised. */
161	STAMCOUNTER StatPITIrq;
162	/** Profiling the timer callback handler. */
163	STAMPROFILEADV StatPITHandler;
164	} PITState;
165
166
167	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
168	/*******************************************************************************
169	* Internal Functions *
170	*******************************************************************************/
171	RT_C_DECLS_BEGIN
172	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
173	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
174	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
175	#ifdef IN_RING3
176	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
177	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now);
178	#endif
179	RT_C_DECLS_END
180
181
182
183
184	static int pit_get_count(PITChannelState *s)
185	{
186	uint64_t d;
187	int counter;
188	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
189
190	if (s->mode == 2)
191	{
192	if (s->u64NextTS == UINT64_MAX)
193	{
194	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
195	return s->count - (d % s->count); /** @todo check this value. */
196	}
197	uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
198	if (!Interval)
199	return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
200	d = TMTimerGet(pTimer);
201	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
202	if (d >= s->count)
203	return 1;
204	return s->count - d;
205	}
206	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
207	switch(s->mode) {
208	case 0:
209	case 1:
210	case 4:
211	case 5:
212	counter = (s->count - d) & 0xffff;
213	break;
214	case 3:
215	/* XXX: may be incorrect for odd counts */
216	counter = s->count - ((2 * d) % s->count);
217	break;
218	default:
219	counter = s->count - (d % s->count);
220	break;
221	}
222	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
223	return counter;
224	}
225
226	/* get pit output bit */
227	static int pit_get_out1(PITChannelState *s, int64_t current_time)
228	{
229	uint64_t d;
230	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
231	int out;
232
233	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
234	switch(s->mode) {
235	default:
236	case 0:
237	out = (d >= s->count);
238	break;
239	case 1:
240	out = (d < s->count);
241	break;
242	case 2:
243	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
244	if ((d % s->count) == 0 && d != 0)
245	out = 1;
246	else
247	out = 0;
248	break;
249	case 3:
250	out = (d % s->count) < ((s->count + 1) >> 1);
251	break;
252	case 4:
253	case 5:
254	out = (d == s->count);
255	break;
256	}
257	return out;
258	}
259
260
261	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
262	{
263	PITChannelState *s = &pit->channels[channel];
264	return pit_get_out1(s, current_time);
265	}
266
267
268	static int pit_get_gate(PITState *pit, int channel)
269	{
270	PITChannelState *s = &pit->channels[channel];
271	return s->gate;
272	}
273
274
275	/* if already latched, do not latch again */
276	static void pit_latch_count(PITChannelState *s)
277	{
278	if (!s->count_latched) {
279	s->latched_count = pit_get_count(s);
280	s->count_latched = s->rw_mode;
281	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
282	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
283	}
284	}
285
286	#ifdef IN_RING3
287
288	/* val must be 0 or 1 */
289	static void pit_set_gate(PITState *pit, int channel, int val)
290	{
291	PITChannelState *s = &pit->channels[channel];
292	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
293	Assert((val & 1) == val);
294
295	switch(s->mode) {
296	default:
297	case 0:
298	case 4:
299	/* XXX: just disable/enable counting */
300	break;
301	case 1:
302	case 5:
303	if (s->gate < val) {
304	/* restart counting on rising edge */
305	Log(("pit_set_gate: restarting mode %d\n", s->mode));
306	s->count_load_time = TMTimerGet(pTimer);
307	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
308	}
309	break;
310	case 2:
311	case 3:
312	if (s->gate < val) {
313	/* restart counting on rising edge */
314	Log(("pit_set_gate: restarting mode %d\n", s->mode));
315	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
316	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
317	}
318	/* XXX: disable/enable counting */
319	break;
320	}
321	s->gate = val;
322	}
323
324	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
325	{
326	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
327	if (val == 0)
328	val = 0x10000;
329	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
330	s->count = val;
331	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
332
333	/* log the new rate (ch 0 only). */
334	if (s->pTimerR3 /* ch 0 */)
335	{
336	if (s->cRelLogEntries++ < 32)
337	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
338	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
339	else
340	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
341	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
342	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
343	}
344	else
345	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
346	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100,
347	s - &s->CTX_SUFF(pPit)->channels[0]));
348	}
349
350	/* return -1 if no transition will occur. */
351	static int64_t pit_get_next_transition_time(PITChannelState *s,
352	uint64_t current_time)
353	{
354	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
355	uint64_t d, next_time, base;
356	uint32_t period2;
357
358	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
359	switch(s->mode) {
360	default:
361	case 0:
362	case 1:
363	if (d < s->count)
364	next_time = s->count;
365	else
366	return -1;
367	break;
368	/*
369	* Mode 2: The period is 'count' PIT ticks.
370	* When the counter reaches 1 we set the output low (for channel 0 that
371	* means lowering IRQ0). On the next tick, where we should be decrementing
372	* from 1 to 0, the count is loaded and the output goes high (channel 0
373	* means raising IRQ0 again and triggering timer interrupt).
374	*
375	* In VirtualBox we compress the pulse and flip-flop the IRQ line at the
376	* end of the period, which signals an interrupt at the exact same time.
377	*/
378	case 2:
379	base = (d / s->count) * s->count;
380	#ifndef VBOX /* see above */
381	if ((d - base) == 0 && d != 0)
382	next_time = base + s->count - 1;
383	else
384	#endif
385	next_time = base + s->count;
386	break;
387	case 3:
388	base = (d / s->count) * s->count;
389	period2 = ((s->count + 1) >> 1);
390	if ((d - base) < period2)
391	next_time = base + period2;
392	else
393	next_time = base + s->count;
394	break;
395	case 4:
396	case 5:
397	if (d < s->count)
398	next_time = s->count;
399	else if (d == s->count)
400	next_time = s->count + 1;
401	else
402	return -1;
403	break;
404	}
405	/* convert to timer units */
406	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
407	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
408	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
409	/* fix potential rounding problems */
410	if (next_time <= current_time)
411	next_time = current_time;
412	/* Add one to next_time; if we don't, integer truncation will cause
413	* the algorithm to think that at the end of each period, it's still
414	* within the first one instead of at the beginning of the next one.
415	*/
416	return next_time + 1;
417	}
418
419	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now)
420	{
421	int64_t expire_time;
422	int irq_level;
423	PPDMDEVINS pDevIns;
424	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
425
426	if (!s->CTX_SUFF(pTimer))
427	return;
428	expire_time = pit_get_next_transition_time(s, current_time);
429	irq_level = pit_get_out1(s, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
430
431	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
432	* but do not modify other aspects of device operation.
433	*/
434	if (!s->pPitR3->fDisabledByHpet)
435	{
436	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
437
438	if (s->mode == 2)
439	{
440	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for years). */
441	PDMDevHlpISASetIrq(pDevIns, s->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
442	} else
443	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
444	}
445
446	if (irq_level)
447	{
448	s->u64ReloadTS = now;
449	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
450	}
451
452	if (expire_time != -1)
453	{
454	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
455	s->u64NextTS = expire_time;
456	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
457	}
458	else
459	{
460	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
461	TMTimerStop(s->CTX_SUFF(pTimer));
462	s->u64NextTS = UINT64_MAX;
463	}
464	s->next_transition_time = expire_time;
465	}
466
467	#endif /* IN_RING3 */
468
469
470	/**
471	* Port I/O Handler for IN operations.
472	*
473	* @returns VBox status code.
474	*
475	* @param pDevIns The device instance.
476	* @param pvUser User argument - ignored.
477	* @param Port Port number used for the IN operation.
478	* @param pu32 Where to store the result.
479	* @param cb Number of bytes read.
480	*/
481	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
482	{
483	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
484	NOREF(pvUser);
485	Port &= 3;
486	if (cb != 1 \|\| Port == 3)
487	{
488	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
489	return VERR_IOM_IOPORT_UNUSED;
490	}
491
492	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
493	int ret;
494	PITChannelState *s = &pit->channels[Port];
495	if (s->status_latched)
496	{
497	s->status_latched = 0;
498	ret = s->status;
499	}
500	else if (s->count_latched)
501	{
502	switch (s->count_latched)
503	{
504	default:
505	case RW_STATE_LSB:
506	ret = s->latched_count & 0xff;
507	s->count_latched = 0;
508	break;
509	case RW_STATE_MSB:
510	ret = s->latched_count >> 8;
511	s->count_latched = 0;
512	break;
513	case RW_STATE_WORD0:
514	ret = s->latched_count & 0xff;
515	s->count_latched = RW_STATE_MSB;
516	break;
517	}
518	}
519	else
520	{
521	int count;
522	switch (s->read_state)
523	{
524	default:
525	case RW_STATE_LSB:
526	count = pit_get_count(s);
527	ret = count & 0xff;
528	break;
529	case RW_STATE_MSB:
530	count = pit_get_count(s);
531	ret = (count >> 8) & 0xff;
532	break;
533	case RW_STATE_WORD0:
534	count = pit_get_count(s);
535	ret = count & 0xff;
536	s->read_state = RW_STATE_WORD1;
537	break;
538	case RW_STATE_WORD1:
539	count = pit_get_count(s);
540	ret = (count >> 8) & 0xff;
541	s->read_state = RW_STATE_WORD0;
542	break;
543	}
544	}
545
546	*pu32 = ret;
547	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
548	return VINF_SUCCESS;
549	}
550
551
552	/**
553	* Port I/O Handler for OUT operations.
554	*
555	* @returns VBox status code.
556	*
557	* @param pDevIns The device instance.
558	* @param pvUser User argument - ignored.
559	* @param Port Port number used for the IN operation.
560	* @param u32 The value to output.
561	* @param cb The value size in bytes.
562	*/
563	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
564	{
565	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
566	NOREF(pvUser);
567	if (cb != 1)
568	return VINF_SUCCESS;
569
570	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
571	Port &= 3;
572	if (Port == 3)
573	{
574	/*
575	* Port 43h - Mode/Command Register.
576	* 7 6 5 4 3 2 1 0
577	* * * . . . . . . Select channel: 0 0 = Channel 0
578	* 0 1 = Channel 1
579	* 1 0 = Channel 2
580	* 1 1 = Read-back command (8254 only)
581	* (Illegal on 8253)
582	* (Illegal on PS/2 {JAM})
583	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
584	* 0 1 = Access mode: lobyte only
585	* 1 0 = Access mode: hibyte only
586	* 1 1 = Access mode: lobyte/hibyte
587	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
588	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
589	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
590	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
591	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
592	*/
593	unsigned channel = u32 >> 6;
594	if (channel == 3)
595	{
596	/* read-back command */
597	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
598	{
599	PITChannelState *s = &pit->channels[channel];
600	if (u32 & (2 << channel)) {
601	if (!(u32 & 0x20))
602	pit_latch_count(s);
603	if (!(u32 & 0x10) && !s->status_latched)
604	{
605	/* status latch */
606	/* XXX: add BCD and null count */
607	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
608	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
609	\| (s->rw_mode << 4)
610	\| (s->mode << 1)
611	\| s->bcd;
612	s->status_latched = 1;
613	}
614	}
615	}
616	}
617	else
618	{
619	PITChannelState *s = &pit->channels[channel];
620	unsigned access = (u32 >> 4) & 3;
621	if (access == 0)
622	pit_latch_count(s);
623	else
624	{
625	s->rw_mode = access;
626	s->read_state = access;
627	s->write_state = access;
628
629	s->mode = (u32 >> 1) & 7;
630	s->bcd = u32 & 1;
631	/* XXX: update irq timer ? */
632	}
633	}
634	}
635	else
636	{
637	#ifndef IN_RING3
638	return VINF_IOM_HC_IOPORT_WRITE;
639	#else /* IN_RING3 */
640	/*
641	* Port 40-42h - Channel Data Ports.
642	*/
643	PITChannelState *s = &pit->channels[Port];
644	switch(s->write_state)
645	{
646	default:
647	case RW_STATE_LSB:
648	pit_load_count(s, u32);
649	break;
650	case RW_STATE_MSB:
651	pit_load_count(s, u32 << 8);
652	break;
653	case RW_STATE_WORD0:
654	s->write_latch = u32;
655	s->write_state = RW_STATE_WORD1;
656	break;
657	case RW_STATE_WORD1:
658	pit_load_count(s, s->write_latch \| (u32 << 8));
659	s->write_state = RW_STATE_WORD0;
660	break;
661	}
662	#endif /* !IN_RING3 */
663	}
664	return VINF_SUCCESS;
665	}
666
667
668	/**
669	* Port I/O Handler for speaker IN operations.
670	*
671	* @returns VBox status code.
672	*
673	* @param pDevIns The device instance.
674	* @param pvUser User argument - ignored.
675	* @param Port Port number used for the IN operation.
676	* @param pu32 Where to store the result.
677	* @param cb Number of bytes read.
678	*/
679	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
680	{
681	NOREF(pvUser);
682	if (cb == 1)
683	{
684	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
685	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
686	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
687
688	/* bit 6,7 Parity error stuff. */
689	/* bit 5 - mirrors timer 2 output condition. */
690	const int fOut = pit_get_out(pThis, 2, u64Now);
691	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
692	ASSUMES ns timer freq, see assertion above. */
693	#ifndef FAKE_REFRESH_CLOCK
694	const int fRefresh = (u64Now / 15085) & 1;
695	#else
696	pThis->dummy_refresh_clock ^= 1;
697	const int fRefresh = pThis->dummy_refresh_clock;
698	#endif
699	/* bit 2,3 NMI / parity status stuff. */
700	/* bit 1 - speaker data status */
701	const int fSpeakerStatus = pThis->speaker_data_on;
702	/* bit 0 - timer 2 clock gate to speaker status. */
703	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
704
705	*pu32 = fTimer2GateStatus
706	\| (fSpeakerStatus << 1)
707	\| (fRefresh << 4)
708	\| (fOut << 5);
709	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
710	return VINF_SUCCESS;
711	}
712	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
713	return VERR_IOM_IOPORT_UNUSED;
714	}
715
716	#ifdef IN_RING3
717
718	/**
719	* Port I/O Handler for speaker OUT operations.
720	*
721	* @returns VBox status code.
722	*
723	* @param pDevIns The device instance.
724	* @param pvUser User argument - ignored.
725	* @param Port Port number used for the IN operation.
726	* @param u32 The value to output.
727	* @param cb The value size in bytes.
728	*/
729	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
730	{
731	NOREF(pvUser);
732	if (cb == 1)
733	{
734	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
735	pThis->speaker_data_on = (u32 >> 1) & 1;
736	pit_set_gate(pThis, 2, u32 & 1);
737	}
738	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
739	return VINF_SUCCESS;
740	}
741
742
743	/**
744	* @copydoc FNSSMDEVLIVEEXEC
745	*/
746	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
747	{
748	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
749	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
750	SSMR3PutU8( pSSM, pThis->channels[0].irq);
751	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
752	return VINF_SSM_DONT_CALL_AGAIN;
753	}
754
755
756	/**
757	* @copydoc FNSSMDEVSAVEEXEC
758	*/
759	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
760	{
761	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
762	unsigned i;
763
764	/* The config. */
765	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
766
767	/* The state. */
768	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
769	{
770	PITChannelState *s = &pThis->channels[i];
771	SSMR3PutU32(pSSM, s->count);
772	SSMR3PutU16(pSSM, s->latched_count);
773	SSMR3PutU8(pSSM, s->count_latched);
774	SSMR3PutU8(pSSM, s->status_latched);
775	SSMR3PutU8(pSSM, s->status);
776	SSMR3PutU8(pSSM, s->read_state);
777	SSMR3PutU8(pSSM, s->write_state);
778	SSMR3PutU8(pSSM, s->write_latch);
779	SSMR3PutU8(pSSM, s->rw_mode);
780	SSMR3PutU8(pSSM, s->mode);
781	SSMR3PutU8(pSSM, s->bcd);
782	SSMR3PutU8(pSSM, s->gate);
783	SSMR3PutU64(pSSM, s->count_load_time);
784	SSMR3PutU64(pSSM, s->u64NextTS);
785	SSMR3PutU64(pSSM, s->u64ReloadTS);
786	SSMR3PutS64(pSSM, s->next_transition_time);
787	if (s->CTX_SUFF(pTimer))
788	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
789	}
790
791	SSMR3PutS32(pSSM, pThis->speaker_data_on);
792	#ifdef FAKE_REFRESH_CLOCK
793	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
794	#else
795	SSMR3PutS32(pSSM, 0);
796	#endif
797
798	return SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
799	}
800
801
802	/**
803	* @copydoc FNSSMDEVLOADEXEC
804	*/
805	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
806	{
807	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
808	int rc;
809
810	if ( uVersion != PIT_SAVED_STATE_VERSION
811	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
812	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
813	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
814
815	/* The config. */
816	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
817	{
818	RTIOPORT IOPortBaseCfg;
819	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
820	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
821	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
822	IOPortBaseCfg, pThis->IOPortBaseCfg);
823
824	uint8_t u8Irq;
825	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
826	if (u8Irq != pThis->channels[0].irq)
827	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
828	u8Irq, pThis->channels[0].irq);
829
830	bool fSpeakerCfg;
831	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
832	if (fSpeakerCfg != pThis->fSpeakerCfg)
833	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
834	fSpeakerCfg, pThis->fSpeakerCfg);
835	}
836
837	if (uPass != SSM_PASS_FINAL)
838	return VINF_SUCCESS;
839
840	/* The state. */
841	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
842	{
843	PITChannelState *s = &pThis->channels[i];
844	SSMR3GetU32(pSSM, &s->count);
845	SSMR3GetU16(pSSM, &s->latched_count);
846	SSMR3GetU8(pSSM, &s->count_latched);
847	SSMR3GetU8(pSSM, &s->status_latched);
848	SSMR3GetU8(pSSM, &s->status);
849	SSMR3GetU8(pSSM, &s->read_state);
850	SSMR3GetU8(pSSM, &s->write_state);
851	SSMR3GetU8(pSSM, &s->write_latch);
852	SSMR3GetU8(pSSM, &s->rw_mode);
853	SSMR3GetU8(pSSM, &s->mode);
854	SSMR3GetU8(pSSM, &s->bcd);
855	SSMR3GetU8(pSSM, &s->gate);
856	SSMR3GetU64(pSSM, &s->count_load_time);
857	SSMR3GetU64(pSSM, &s->u64NextTS);
858	SSMR3GetU64(pSSM, &s->u64ReloadTS);
859	SSMR3GetS64(pSSM, &s->next_transition_time);
860	if (s->CTX_SUFF(pTimer))
861	{
862	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
863	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
864	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
865	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
866	}
867	pThis->channels[i].cRelLogEntries = 0;
868	}
869
870	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
871	#ifdef FAKE_REFRESH_CLOCK
872	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
873	#else
874	int32_t u32Dummy;
875	SSMR3GetS32(pSSM, &u32Dummy);
876	#endif
877	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
878	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
879
880	return VINF_SUCCESS;
881	}
882
883
884	/**
885	* Device timer callback function.
886	*
887	* @param pDevIns Device instance of the device which registered the timer.
888	* @param pTimer The timer handle.
889	* @param pvUser Pointer to the PIT channel state.
890	*/
891	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
892	{
893	PITChannelState s = (PITChannelState )pvUser;
894	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
895	Log(("pitTimer\n"));
896	pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer));
897	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
898	}
899
900
901	/**
902	* Info handler, device version.
903	*
904	* @param pDevIns Device instance which registered the info.
905	* @param pHlp Callback functions for doing output.
906	* @param pszArgs Argument string. Optional and specific to the handler.
907	*/
908	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
909	{
910	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
911	unsigned i;
912	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
913	{
914	const PITChannelState *pCh = &pThis->channels[i];
915
916	pHlp->pfnPrintf(pHlp,
917	"PIT (i8254) channel %d status: irq=%#x\n"
918	" count=%08x" " latched_count=%04x count_latched=%02x\n"
919	" status=%02x status_latched=%02x read_state=%02x\n"
920	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
921	" mode=%02x bcd=%02x gate=%02x\n"
922	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
923	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
924	,
925	i, pCh->irq,
926	pCh->count, pCh->latched_count, pCh->count_latched,
927	pCh->status, pCh->status_latched, pCh->read_state,
928	pCh->write_state, pCh->write_latch, pCh->rw_mode,
929	pCh->mode, pCh->bcd, pCh->gate,
930	pCh->count_load_time, pCh->next_transition_time,
931	pCh->u64ReloadTS, pCh->u64NextTS);
932	}
933	#ifdef FAKE_REFRESH_CLOCK
934	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
935	pThis->speaker_data_on, pThis->dummy_refresh_clock);
936	#else
937	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
938	#endif
939	if (pThis->fDisabledByHpet)
940	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
941	}
942
943
944	/**
945	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
946	*/
947	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
948	{
949	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
950	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
951	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
952	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
953	return NULL;
954	}
955
956
957	/**
958	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
959	*/
960	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
961	{
962	PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IHpetLegacyNotify);
963	pThis->fDisabledByHpet = fActivated;
964	}
965
966
967	/**
968	* Relocation notification.
969	*
970	* @returns VBox status.
971	* @param pDevIns The device instance data.
972	* @param offDelta The delta relative to the old address.
973	*/
974	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
975	{
976	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
977	unsigned i;
978	LogFlow(("pitRelocate: \n"));
979
980	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
981	{
982	PITChannelState *pCh = &pThis->channels[i];
983	if (pCh->pTimerR3)
984	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
985	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
986	}
987	}
988
989
990	/**
991	* Reset notification.
992	*
993	* @returns VBox status.
994	* @param pDevIns The device instance data.
995	*/
996	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
997	{
998	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
999	unsigned i;
1000	LogFlow(("pitReset: \n"));
1001
1002	pThis->fDisabledByHpet = false;
1003
1004	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1005	{
1006	PITChannelState *s = &pThis->channels[i];
1007
1008	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1009	s->latched_count = 0;
1010	s->count_latched = 0;
1011	s->status_latched = 0;
1012	s->status = 0;
1013	s->read_state = 0;
1014	s->write_state = 0;
1015	s->write_latch = 0;
1016	s->rw_mode = 0;
1017	s->bcd = 0;
1018	#endif
1019	s->u64NextTS = UINT64_MAX;
1020	s->cRelLogEntries = 0;
1021	s->mode = 3;
1022	s->gate = (i != 2);
1023	pit_load_count(s, 0);
1024	}
1025	}
1026
1027
1028	/**
1029	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1030	*/
1031	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1032	{
1033	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1034	int rc;
1035	uint8_t u8Irq;
1036	uint16_t u16Base;
1037	bool fSpeaker;
1038	bool fGCEnabled;
1039	bool fR0Enabled;
1040	unsigned i;
1041	Assert(iInstance == 0);
1042
1043	/*
1044	* Validate configuration.
1045	*/
1046	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1047	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1048
1049	/*
1050	* Init the data.
1051	*/
1052	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1053	if (RT_FAILURE(rc))
1054	return PDMDEV_SET_ERROR(pDevIns, rc,
1055	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1056
1057	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1058	if (RT_FAILURE(rc))
1059	return PDMDEV_SET_ERROR(pDevIns, rc,
1060	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1061
1062	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1063	if (RT_FAILURE(rc))
1064	return PDMDEV_SET_ERROR(pDevIns, rc,
1065	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1066
1067	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1068	if (RT_FAILURE(rc))
1069	return PDMDEV_SET_ERROR(pDevIns, rc,
1070	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1071
1072	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1073	if (RT_FAILURE(rc))
1074	return PDMDEV_SET_ERROR(pDevIns, rc,
1075	N_("Configuration error: failed to read R0Enabled as boolean"));
1076
1077	pThis->pDevIns = pDevIns;
1078	pThis->IOPortBaseCfg = u16Base;
1079	pThis->fSpeakerCfg = fSpeaker;
1080	pThis->channels[0].irq = u8Irq;
1081	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1082	{
1083	pThis->channels[i].pPitR3 = pThis;
1084	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1085	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1086	}
1087
1088	/*
1089	* Interfaces
1090	*/
1091	/* IBase */
1092	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1093	/* IHpetLegacyNotify */
1094	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1095
1096	/*
1097	* Create timer, register I/O Ports and save state.
1098	*/
1099	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1100	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1101	&pThis->channels[0].pTimerR3);
1102	if (RT_FAILURE(rc))
1103	return rc;
1104	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1105	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1106
1107	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1108	if (RT_FAILURE(rc))
1109	return rc;
1110	if (fGCEnabled)
1111	{
1112	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1113	if (RT_FAILURE(rc))
1114	return rc;
1115	}
1116	if (fR0Enabled)
1117	{
1118	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1119	if (RT_FAILURE(rc))
1120	return rc;
1121	}
1122
1123	if (fSpeaker)
1124	{
1125	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1126	if (RT_FAILURE(rc))
1127	return rc;
1128	if (fGCEnabled)
1129	{
1130	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1131	if (RT_FAILURE(rc))
1132	return rc;
1133	}
1134	}
1135
1136	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1137	if (RT_FAILURE(rc))
1138	return rc;
1139
1140	/*
1141	* Initialize the device state.
1142	*/
1143	pitReset(pDevIns);
1144
1145	/*
1146	* Register statistics and debug info.
1147	*/
1148	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1149	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1150
1151	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1152
1153	return VINF_SUCCESS;
1154	}
1155
1156
1157	/**
1158	* The device registration structure.
1159	*/
1160	const PDMDEVREG g_DeviceI8254 =
1161	{
1162	/* u32Version */
1163	PDM_DEVREG_VERSION,
1164	/* szName */
1165	"i8254",
1166	/* szRCMod */
1167	"VBoxDDGC.gc",
1168	/* szR0Mod */
1169	"VBoxDDR0.r0",
1170	/* pszDescription */
1171	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1172	/* fFlags */
1173	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1174	/* fClass */
1175	PDM_DEVREG_CLASS_PIT,
1176	/* cMaxInstances */
1177	1,
1178	/* cbInstance */
1179	sizeof(PITState),
1180	/* pfnConstruct */
1181	pitConstruct,
1182	/* pfnDestruct */
1183	NULL,
1184	/* pfnRelocate */
1185	pitRelocate,
1186	/* pfnIOCtl */
1187	NULL,
1188	/* pfnPowerOn */
1189	NULL,
1190	/* pfnReset */
1191	pitReset,
1192	/* pfnSuspend */
1193	NULL,
1194	/* pfnResume */
1195	NULL,
1196	/* pfnAttach */
1197	NULL,
1198	/* pfnDetach */
1199	NULL,
1200	/* pfnQueryInterface */
1201	NULL,
1202	/* pfnInitComplete */
1203	NULL,
1204	/* pfnPowerOff */
1205	NULL,
1206	/* pfnSoftReset */
1207	NULL,
1208	/* u32VersionEnd */
1209	PDM_DEVREG_VERSION
1210	};
1211
1212	#endif /* IN_RING3 */
1213	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 34914

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