DevPit-i8254.cpp@ 37475

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1	/* $Id: DevPit-i8254.cpp 37475 2011-06-15 16:42:55Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PIT
47	#include <VBox/vmm/pdmdev.h>
48	#include <VBox/log.h>
49	#include <VBox/vmm/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm-math.h>
52
53	#ifdef IN_RING3
54	# include <iprt/alloc.h>
55	# include <iprt/string.h>
56	# include <iprt/uuid.h>
57	#endif /* IN_RING3 */
58
59	#include "VBoxDD.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The current saved state version. */
74	#define PIT_SAVED_STATE_VERSION 4
75	/** The saved state version used by VirtualBox 3.1 and earlier.
76	* This did not include disable by HPET flag. */
77	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
78	/** The saved state version used by VirtualBox 3.0 and earlier.
79	* This did not include the config part. */
80	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
81
82	/** @def FAKE_REFRESH_CLOCK
83	* Define this to flip the 15usec refresh bit on every read.
84	* If not defined, it will be flipped correctly. */
85	/* #define FAKE_REFRESH_CLOCK */
86	#ifdef DOXYGEN_RUNNING
87	# define FAKE_REFRESH_CLOCK
88	#endif
89
90	/** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
91	#define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
92
93	/*******************************************************************************
94	* Structures and Typedefs *
95	*******************************************************************************/
96	typedef struct PITChannelState
97	{
98	/** Pointer to the instance data - R3 Ptr. */
99	R3PTRTYPE(struct PITState *) pPitR3;
100	/** The timer - R3 Ptr. */
101	PTMTIMERR3 pTimerR3;
102	/** Pointer to the instance data - R0 Ptr. */
103	R0PTRTYPE(struct PITState *) pPitR0;
104	/** The timer - R0 Ptr. */
105	PTMTIMERR0 pTimerR0;
106	/** Pointer to the instance data - RC Ptr. */
107	RCPTRTYPE(struct PITState *) pPitRC;
108	/** The timer - RC Ptr. */
109	PTMTIMERRC pTimerRC;
110	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
111	uint64_t u64ReloadTS;
112	/** The actual time of the next tick.
113	* As apposed to the next_transition_time which contains the correct time of the next tick. */
114	uint64_t u64NextTS;
115
116	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
117	uint64_t count_load_time;
118	/* irq handling */
119	int64_t next_transition_time;
120	int32_t irq;
121	/** Number of release log entries. Used to prevent flooding. */
122	uint32_t cRelLogEntries;
123
124	uint32_t count; /* can be 65536 */
125	uint16_t latched_count;
126	uint8_t count_latched;
127	uint8_t status_latched;
128
129	uint8_t status;
130	uint8_t read_state;
131	uint8_t write_state;
132	uint8_t write_latch;
133
134	uint8_t rw_mode;
135	uint8_t mode;
136	uint8_t bcd; /* not supported */
137	uint8_t gate; /* timer start */
138
139	} PITChannelState;
140
141	typedef struct PITState
142	{
143	PITChannelState channels[3];
144	/** Speaker data. */
145	int32_t speaker_data_on;
146	#ifdef FAKE_REFRESH_CLOCK
147	/** Speaker dummy. */
148	int32_t dummy_refresh_clock;
149	#else
150	uint32_t Alignment1;
151	#endif
152	/** Config: I/O port base. */
153	RTIOPORT IOPortBaseCfg;
154	/** Config: Speaker enabled. */
155	bool fSpeakerCfg;
156	bool fDisabledByHpet;
157	bool afAlignment0[HC_ARCH_BITS == 32 ? 4 : 4];
158	/** PIT port interface. */
159	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
160	/** Pointer to the device instance. */
161	PPDMDEVINSR3 pDevIns;
162	/** Number of IRQs that's been raised. */
163	STAMCOUNTER StatPITIrq;
164	/** Profiling the timer callback handler. */
165	STAMPROFILEADV StatPITHandler;
166	} PITState;
167
168
169	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
170	/*******************************************************************************
171	* Internal Functions *
172	*******************************************************************************/
173	RT_C_DECLS_BEGIN
174	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
175	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
176	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
177	#ifdef IN_RING3
178	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
179	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now, bool in_timer);
180	#endif
181	RT_C_DECLS_END
182
183
184
185
186	static int pit_get_count(PITChannelState *s)
187	{
188	uint64_t d;
189	int counter;
190	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
191
192	if (EFFECTIVE_MODE(s->mode) == 2)
193	{
194	if (s->u64NextTS == UINT64_MAX)
195	{
196	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
197	return s->count - (d % s->count); /** @todo check this value. */
198	}
199	uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
200	if (!Interval)
201	return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
202	d = TMTimerGet(pTimer);
203	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
204	if (d >= s->count)
205	return 1;
206	return s->count - d;
207	}
208	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
209	switch(EFFECTIVE_MODE(s->mode)) {
210	case 0:
211	case 1:
212	case 4:
213	case 5:
214	counter = (s->count - d) & 0xffff;
215	break;
216	case 3:
217	/* XXX: may be incorrect for odd counts */
218	counter = s->count - ((2 * d) % s->count);
219	break;
220	default:
221	counter = s->count - (d % s->count);
222	break;
223	}
224	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
225	return counter;
226	}
227
228	/* get pit output bit */
229	static int pit_get_out1(PITChannelState *s, int64_t current_time)
230	{
231	uint64_t d;
232	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
233	int out;
234
235	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
236	switch(EFFECTIVE_MODE(s->mode)) {
237	default:
238	case 0:
239	out = (d >= s->count);
240	break;
241	case 1:
242	out = (d < s->count);
243	break;
244	case 2:
245	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
246	if ((d % s->count) == 0 && d != 0)
247	out = 1;
248	else
249	out = 0;
250	break;
251	case 3:
252	out = (d % s->count) < ((s->count + 1) >> 1);
253	break;
254	case 4:
255	case 5:
256	out = (d != s->count);
257	break;
258	}
259	return out;
260	}
261
262
263	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
264	{
265	PITChannelState *s = &pit->channels[channel];
266	return pit_get_out1(s, current_time);
267	}
268
269
270	static int pit_get_gate(PITState *pit, int channel)
271	{
272	PITChannelState *s = &pit->channels[channel];
273	return s->gate;
274	}
275
276
277	/* if already latched, do not latch again */
278	static void pit_latch_count(PITChannelState *s)
279	{
280	if (!s->count_latched) {
281	s->latched_count = pit_get_count(s);
282	s->count_latched = s->rw_mode;
283	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
284	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
285	}
286	}
287
288	#ifdef IN_RING3
289
290	/* val must be 0 or 1 */
291	static void pit_set_gate(PITState *pit, int channel, int val)
292	{
293	PITChannelState *s = &pit->channels[channel];
294	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
295	Assert((val & 1) == val);
296
297	switch(EFFECTIVE_MODE(s->mode)) {
298	default:
299	case 0:
300	case 4:
301	/* XXX: just disable/enable counting */
302	break;
303	case 1:
304	case 5:
305	if (s->gate < val) {
306	/* restart counting on rising edge */
307	Log(("pit_set_gate: restarting mode %d\n", s->mode));
308	s->count_load_time = TMTimerGet(pTimer);
309	pit_irq_timer_update(s, s->count_load_time, s->count_load_time, false);
310	}
311	break;
312	case 2:
313	case 3:
314	if (s->gate < val) {
315	/* restart counting on rising edge */
316	Log(("pit_set_gate: restarting mode %d\n", s->mode));
317	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
318	pit_irq_timer_update(s, s->count_load_time, s->count_load_time, false);
319	}
320	/* XXX: disable/enable counting */
321	break;
322	}
323	s->gate = val;
324	}
325
326	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
327	{
328	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
329	if (val == 0)
330	val = 0x10000;
331	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
332	s->count = val;
333	pit_irq_timer_update(s, s->count_load_time, s->count_load_time, false);
334
335	/* log the new rate (ch 0 only). */
336	if (s->pTimerR3 /* ch 0 */)
337	{
338	if (s->cRelLogEntries++ < 32)
339	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
340	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
341	else
342	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
343	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
344	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
345	}
346	else
347	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
348	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100,
349	s - &s->CTX_SUFF(pPit)->channels[0]));
350	}
351
352	/* return -1 if no transition will occur. */
353	static int64_t pit_get_next_transition_time(PITChannelState *s,
354	uint64_t current_time)
355	{
356	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
357	uint64_t d, next_time, base;
358	uint32_t period2;
359
360	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
361	switch(EFFECTIVE_MODE(s->mode)) {
362	default:
363	case 0:
364	case 1:
365	if (d < s->count)
366	next_time = s->count;
367	else
368	return -1;
369	break;
370	/*
371	* Mode 2: The period is 'count' PIT ticks.
372	* When the counter reaches 1 we set the output low (for channel 0 that
373	* means lowering IRQ0). On the next tick, where we should be decrementing
374	* from 1 to 0, the count is loaded and the output goes high (channel 0
375	* means raising IRQ0 again and triggering timer interrupt).
376	*
377	* In VirtualBox we compress the pulse and flip-flop the IRQ line at the
378	* end of the period, which signals an interrupt at the exact same time.
379	*/
380	case 2:
381	base = (d / s->count) * s->count;
382	#ifndef VBOX /* see above */
383	if ((d - base) == 0 && d != 0)
384	next_time = base + s->count - 1;
385	else
386	#endif
387	next_time = base + s->count;
388	break;
389	case 3:
390	base = (d / s->count) * s->count;
391	period2 = ((s->count + 1) >> 1);
392	if ((d - base) < period2)
393	next_time = base + period2;
394	else
395	next_time = base + s->count;
396	break;
397	/* Modes 4 and 5 generate a short pulse at the end of the time delay. This
398	* is similar to mode 2, except modes 4/5 aren't periodic. We use the same
399	* optimization - only use one timer callback and pulse the IRQ.
400	* Note: Tickless Linux kernels use PIT mode 4 with 'nolapic'.
401	*/
402	case 4:
403	case 5:
404	#ifdef VBOX
405	if (d <= s->count)
406	next_time = s->count;
407	#else
408	if (d < s->count)
409	next_time = s->count;
410	else if (d == s->count)
411	next_time = s->count + 1;
412	#endif
413	else
414	return -1;
415	break;
416	}
417	/* convert to timer units */
418	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
419	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
420	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
421	/* fix potential rounding problems */
422	if (next_time <= current_time)
423	next_time = current_time;
424	/* Add one to next_time; if we don't, integer truncation will cause
425	* the algorithm to think that at the end of each period, it's still
426	* within the first one instead of at the beginning of the next one.
427	*/
428	return next_time + 1;
429	}
430
431	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now, bool in_timer)
432	{
433	int64_t expire_time;
434	int irq_level;
435	PPDMDEVINS pDevIns;
436	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
437
438	if (!s->CTX_SUFF(pTimer))
439	return;
440	expire_time = pit_get_next_transition_time(s, current_time);
441	irq_level = pit_get_out1(s, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
442
443	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
444	* but do not modify other aspects of device operation.
445	*/
446	if (!s->pPitR3->fDisabledByHpet)
447	{
448	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
449
450	switch (EFFECTIVE_MODE(s->mode))
451	{
452	case 2:
453	case 4:
454	case 5:
455	/* We just flip-flop the IRQ line to save an extra timer call,
456	* which isn't generally required. However, the pulse is only
457	* generated when running on the timer callback (and thus on
458	* the trailing edge of the output signal pulse).
459	*/
460	if (in_timer)
461	{
462	PDMDevHlpISASetIrq(pDevIns, s->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
463	break;
464	}
465	/* Else fall through! */
466	default:
467	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
468	break;
469	}
470	}
471
472	if (irq_level)
473	{
474	s->u64ReloadTS = now;
475	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
476	}
477
478	if (expire_time != -1)
479	{
480	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
481	s->u64NextTS = expire_time;
482	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
483	}
484	else
485	{
486	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
487	TMTimerStop(s->CTX_SUFF(pTimer));
488	s->u64NextTS = UINT64_MAX;
489	}
490	s->next_transition_time = expire_time;
491	}
492
493	#endif /* IN_RING3 */
494
495
496	/**
497	* Port I/O Handler for IN operations.
498	*
499	* @returns VBox status code.
500	*
501	* @param pDevIns The device instance.
502	* @param pvUser User argument - ignored.
503	* @param Port Port number used for the IN operation.
504	* @param pu32 Where to store the result.
505	* @param cb Number of bytes read.
506	*/
507	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
508	{
509	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
510	NOREF(pvUser);
511	Port &= 3;
512	if (cb != 1 \|\| Port == 3)
513	{
514	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
515	return VERR_IOM_IOPORT_UNUSED;
516	}
517
518	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
519	int ret;
520	PITChannelState *s = &pit->channels[Port];
521	if (s->status_latched)
522	{
523	s->status_latched = 0;
524	ret = s->status;
525	}
526	else if (s->count_latched)
527	{
528	switch (s->count_latched)
529	{
530	default:
531	case RW_STATE_LSB:
532	ret = s->latched_count & 0xff;
533	s->count_latched = 0;
534	break;
535	case RW_STATE_MSB:
536	ret = s->latched_count >> 8;
537	s->count_latched = 0;
538	break;
539	case RW_STATE_WORD0:
540	ret = s->latched_count & 0xff;
541	s->count_latched = RW_STATE_MSB;
542	break;
543	}
544	}
545	else
546	{
547	int count;
548	switch (s->read_state)
549	{
550	default:
551	case RW_STATE_LSB:
552	count = pit_get_count(s);
553	ret = count & 0xff;
554	break;
555	case RW_STATE_MSB:
556	count = pit_get_count(s);
557	ret = (count >> 8) & 0xff;
558	break;
559	case RW_STATE_WORD0:
560	count = pit_get_count(s);
561	ret = count & 0xff;
562	s->read_state = RW_STATE_WORD1;
563	break;
564	case RW_STATE_WORD1:
565	count = pit_get_count(s);
566	ret = (count >> 8) & 0xff;
567	s->read_state = RW_STATE_WORD0;
568	break;
569	}
570	}
571
572	*pu32 = ret;
573	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
574	return VINF_SUCCESS;
575	}
576
577
578	/**
579	* Port I/O Handler for OUT operations.
580	*
581	* @returns VBox status code.
582	*
583	* @param pDevIns The device instance.
584	* @param pvUser User argument - ignored.
585	* @param Port Port number used for the IN operation.
586	* @param u32 The value to output.
587	* @param cb The value size in bytes.
588	*/
589	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
590	{
591	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
592	NOREF(pvUser);
593	if (cb != 1)
594	return VINF_SUCCESS;
595
596	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
597	Port &= 3;
598	if (Port == 3)
599	{
600	/*
601	* Port 43h - Mode/Command Register.
602	* 7 6 5 4 3 2 1 0
603	* * * . . . . . . Select channel: 0 0 = Channel 0
604	* 0 1 = Channel 1
605	* 1 0 = Channel 2
606	* 1 1 = Read-back command (8254 only)
607	* (Illegal on 8253)
608	* (Illegal on PS/2 {JAM})
609	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
610	* 0 1 = Access mode: lobyte only
611	* 1 0 = Access mode: hibyte only
612	* 1 1 = Access mode: lobyte/hibyte
613	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
614	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
615	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
616	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
617	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
618	*/
619	unsigned channel = u32 >> 6;
620	if (channel == 3)
621	{
622	/* read-back command */
623	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
624	{
625	PITChannelState *s = &pit->channels[channel];
626	if (u32 & (2 << channel)) {
627	if (!(u32 & 0x20))
628	pit_latch_count(s);
629	if (!(u32 & 0x10) && !s->status_latched)
630	{
631	/* status latch */
632	/* XXX: add BCD and null count */
633	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
634	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
635	\| (s->rw_mode << 4)
636	\| (s->mode << 1)
637	\| s->bcd;
638	s->status_latched = 1;
639	}
640	}
641	}
642	}
643	else
644	{
645	PITChannelState *s = &pit->channels[channel];
646	unsigned access = (u32 >> 4) & 3;
647	if (access == 0)
648	pit_latch_count(s);
649	else
650	{
651	s->rw_mode = access;
652	s->read_state = access;
653	s->write_state = access;
654
655	s->mode = (u32 >> 1) & 7;
656	s->bcd = u32 & 1;
657	/* XXX: update irq timer ? */
658	}
659	}
660	}
661	else
662	{
663	#ifndef IN_RING3
664	return VINF_IOM_HC_IOPORT_WRITE;
665	#else /* IN_RING3 */
666	/*
667	* Port 40-42h - Channel Data Ports.
668	*/
669	PITChannelState *s = &pit->channels[Port];
670	switch(s->write_state)
671	{
672	default:
673	case RW_STATE_LSB:
674	pit_load_count(s, u32);
675	break;
676	case RW_STATE_MSB:
677	pit_load_count(s, u32 << 8);
678	break;
679	case RW_STATE_WORD0:
680	s->write_latch = u32;
681	s->write_state = RW_STATE_WORD1;
682	break;
683	case RW_STATE_WORD1:
684	pit_load_count(s, s->write_latch \| (u32 << 8));
685	s->write_state = RW_STATE_WORD0;
686	break;
687	}
688	#endif /* !IN_RING3 */
689	}
690	return VINF_SUCCESS;
691	}
692
693
694	/**
695	* Port I/O Handler for speaker IN operations.
696	*
697	* @returns VBox status code.
698	*
699	* @param pDevIns The device instance.
700	* @param pvUser User argument - ignored.
701	* @param Port Port number used for the IN operation.
702	* @param pu32 Where to store the result.
703	* @param cb Number of bytes read.
704	*/
705	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
706	{
707	NOREF(pvUser);
708	if (cb == 1)
709	{
710	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
711	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
712	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
713
714	/* bit 6,7 Parity error stuff. */
715	/* bit 5 - mirrors timer 2 output condition. */
716	const int fOut = pit_get_out(pThis, 2, u64Now);
717	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
718	ASSUMES ns timer freq, see assertion above. */
719	#ifndef FAKE_REFRESH_CLOCK
720	const int fRefresh = (u64Now / 15085) & 1;
721	#else
722	pThis->dummy_refresh_clock ^= 1;
723	const int fRefresh = pThis->dummy_refresh_clock;
724	#endif
725	/* bit 2,3 NMI / parity status stuff. */
726	/* bit 1 - speaker data status */
727	const int fSpeakerStatus = pThis->speaker_data_on;
728	/* bit 0 - timer 2 clock gate to speaker status. */
729	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
730
731	*pu32 = fTimer2GateStatus
732	\| (fSpeakerStatus << 1)
733	\| (fRefresh << 4)
734	\| (fOut << 5);
735	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
736	return VINF_SUCCESS;
737	}
738	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
739	return VERR_IOM_IOPORT_UNUSED;
740	}
741
742	#ifdef IN_RING3
743
744	/**
745	* Port I/O Handler for speaker OUT operations.
746	*
747	* @returns VBox status code.
748	*
749	* @param pDevIns The device instance.
750	* @param pvUser User argument - ignored.
751	* @param Port Port number used for the IN operation.
752	* @param u32 The value to output.
753	* @param cb The value size in bytes.
754	*/
755	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
756	{
757	NOREF(pvUser);
758	if (cb == 1)
759	{
760	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
761	pThis->speaker_data_on = (u32 >> 1) & 1;
762	pit_set_gate(pThis, 2, u32 & 1);
763	}
764	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
765	return VINF_SUCCESS;
766	}
767
768
769	/**
770	* @copydoc FNSSMDEVLIVEEXEC
771	*/
772	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
773	{
774	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
775	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
776	SSMR3PutU8( pSSM, pThis->channels[0].irq);
777	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
778	return VINF_SSM_DONT_CALL_AGAIN;
779	}
780
781
782	/**
783	* @copydoc FNSSMDEVSAVEEXEC
784	*/
785	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
786	{
787	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
788	unsigned i;
789
790	/* The config. */
791	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
792
793	/* The state. */
794	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
795	{
796	PITChannelState *s = &pThis->channels[i];
797	SSMR3PutU32(pSSM, s->count);
798	SSMR3PutU16(pSSM, s->latched_count);
799	SSMR3PutU8(pSSM, s->count_latched);
800	SSMR3PutU8(pSSM, s->status_latched);
801	SSMR3PutU8(pSSM, s->status);
802	SSMR3PutU8(pSSM, s->read_state);
803	SSMR3PutU8(pSSM, s->write_state);
804	SSMR3PutU8(pSSM, s->write_latch);
805	SSMR3PutU8(pSSM, s->rw_mode);
806	SSMR3PutU8(pSSM, s->mode);
807	SSMR3PutU8(pSSM, s->bcd);
808	SSMR3PutU8(pSSM, s->gate);
809	SSMR3PutU64(pSSM, s->count_load_time);
810	SSMR3PutU64(pSSM, s->u64NextTS);
811	SSMR3PutU64(pSSM, s->u64ReloadTS);
812	SSMR3PutS64(pSSM, s->next_transition_time);
813	if (s->CTX_SUFF(pTimer))
814	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
815	}
816
817	SSMR3PutS32(pSSM, pThis->speaker_data_on);
818	#ifdef FAKE_REFRESH_CLOCK
819	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
820	#else
821	SSMR3PutS32(pSSM, 0);
822	#endif
823
824	return SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
825	}
826
827
828	/**
829	* @copydoc FNSSMDEVLOADEXEC
830	*/
831	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
832	{
833	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
834	int rc;
835
836	if ( uVersion != PIT_SAVED_STATE_VERSION
837	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
838	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
839	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
840
841	/* The config. */
842	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
843	{
844	RTIOPORT IOPortBaseCfg;
845	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
846	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
847	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
848	IOPortBaseCfg, pThis->IOPortBaseCfg);
849
850	uint8_t u8Irq;
851	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
852	if (u8Irq != pThis->channels[0].irq)
853	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
854	u8Irq, pThis->channels[0].irq);
855
856	bool fSpeakerCfg;
857	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
858	if (fSpeakerCfg != pThis->fSpeakerCfg)
859	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
860	fSpeakerCfg, pThis->fSpeakerCfg);
861	}
862
863	if (uPass != SSM_PASS_FINAL)
864	return VINF_SUCCESS;
865
866	/* The state. */
867	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
868	{
869	PITChannelState *s = &pThis->channels[i];
870	SSMR3GetU32(pSSM, &s->count);
871	SSMR3GetU16(pSSM, &s->latched_count);
872	SSMR3GetU8(pSSM, &s->count_latched);
873	SSMR3GetU8(pSSM, &s->status_latched);
874	SSMR3GetU8(pSSM, &s->status);
875	SSMR3GetU8(pSSM, &s->read_state);
876	SSMR3GetU8(pSSM, &s->write_state);
877	SSMR3GetU8(pSSM, &s->write_latch);
878	SSMR3GetU8(pSSM, &s->rw_mode);
879	SSMR3GetU8(pSSM, &s->mode);
880	SSMR3GetU8(pSSM, &s->bcd);
881	SSMR3GetU8(pSSM, &s->gate);
882	SSMR3GetU64(pSSM, &s->count_load_time);
883	SSMR3GetU64(pSSM, &s->u64NextTS);
884	SSMR3GetU64(pSSM, &s->u64ReloadTS);
885	SSMR3GetS64(pSSM, &s->next_transition_time);
886	if (s->CTX_SUFF(pTimer))
887	{
888	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
889	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
890	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
891	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
892	}
893	pThis->channels[i].cRelLogEntries = 0;
894	}
895
896	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
897	#ifdef FAKE_REFRESH_CLOCK
898	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
899	#else
900	int32_t u32Dummy;
901	SSMR3GetS32(pSSM, &u32Dummy);
902	#endif
903	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
904	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
905
906	return VINF_SUCCESS;
907	}
908
909
910	/**
911	* Device timer callback function.
912	*
913	* @param pDevIns Device instance of the device which registered the timer.
914	* @param pTimer The timer handle.
915	* @param pvUser Pointer to the PIT channel state.
916	*/
917	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
918	{
919	PITChannelState s = (PITChannelState )pvUser;
920	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
921	Log(("pitTimer\n"));
922	pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer), true);
923	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
924	}
925
926
927	/**
928	* Info handler, device version.
929	*
930	* @param pDevIns Device instance which registered the info.
931	* @param pHlp Callback functions for doing output.
932	* @param pszArgs Argument string. Optional and specific to the handler.
933	*/
934	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
935	{
936	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
937	unsigned i;
938	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
939	{
940	const PITChannelState *pCh = &pThis->channels[i];
941
942	pHlp->pfnPrintf(pHlp,
943	"PIT (i8254) channel %d status: irq=%#x\n"
944	" count=%08x" " latched_count=%04x count_latched=%02x\n"
945	" status=%02x status_latched=%02x read_state=%02x\n"
946	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
947	" mode=%02x bcd=%02x gate=%02x\n"
948	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
949	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
950	,
951	i, pCh->irq,
952	pCh->count, pCh->latched_count, pCh->count_latched,
953	pCh->status, pCh->status_latched, pCh->read_state,
954	pCh->write_state, pCh->write_latch, pCh->rw_mode,
955	pCh->mode, pCh->bcd, pCh->gate,
956	pCh->count_load_time, pCh->next_transition_time,
957	pCh->u64ReloadTS, pCh->u64NextTS);
958	}
959	#ifdef FAKE_REFRESH_CLOCK
960	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
961	pThis->speaker_data_on, pThis->dummy_refresh_clock);
962	#else
963	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
964	#endif
965	if (pThis->fDisabledByHpet)
966	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
967	}
968
969
970	/**
971	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
972	*/
973	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
974	{
975	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
976	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
977	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
978	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
979	return NULL;
980	}
981
982
983	/**
984	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
985	*/
986	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
987	{
988	PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IHpetLegacyNotify);
989	pThis->fDisabledByHpet = fActivated;
990	}
991
992
993	/**
994	* Relocation notification.
995	*
996	* @returns VBox status.
997	* @param pDevIns The device instance data.
998	* @param offDelta The delta relative to the old address.
999	*/
1000	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1001	{
1002	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1003	unsigned i;
1004	LogFlow(("pitRelocate: \n"));
1005
1006	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1007	{
1008	PITChannelState *pCh = &pThis->channels[i];
1009	if (pCh->pTimerR3)
1010	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
1011	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1012	}
1013	}
1014
1015
1016	/**
1017	* Reset notification.
1018	*
1019	* @returns VBox status.
1020	* @param pDevIns The device instance data.
1021	*/
1022	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
1023	{
1024	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1025	unsigned i;
1026	LogFlow(("pitReset: \n"));
1027
1028	pThis->fDisabledByHpet = false;
1029
1030	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1031	{
1032	PITChannelState *s = &pThis->channels[i];
1033
1034	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1035	s->latched_count = 0;
1036	s->count_latched = 0;
1037	s->status_latched = 0;
1038	s->status = 0;
1039	s->read_state = 0;
1040	s->write_state = 0;
1041	s->write_latch = 0;
1042	s->rw_mode = 0;
1043	s->bcd = 0;
1044	#endif
1045	s->u64NextTS = UINT64_MAX;
1046	s->cRelLogEntries = 0;
1047	s->mode = 3;
1048	s->gate = (i != 2);
1049	pit_load_count(s, 0);
1050	}
1051	}
1052
1053
1054	/**
1055	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1056	*/
1057	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1058	{
1059	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1060	int rc;
1061	uint8_t u8Irq;
1062	uint16_t u16Base;
1063	bool fSpeaker;
1064	bool fGCEnabled;
1065	bool fR0Enabled;
1066	unsigned i;
1067	Assert(iInstance == 0);
1068
1069	/*
1070	* Validate configuration.
1071	*/
1072	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1073	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1074
1075	/*
1076	* Init the data.
1077	*/
1078	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1079	if (RT_FAILURE(rc))
1080	return PDMDEV_SET_ERROR(pDevIns, rc,
1081	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1082
1083	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1084	if (RT_FAILURE(rc))
1085	return PDMDEV_SET_ERROR(pDevIns, rc,
1086	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1087
1088	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1089	if (RT_FAILURE(rc))
1090	return PDMDEV_SET_ERROR(pDevIns, rc,
1091	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1092
1093	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1094	if (RT_FAILURE(rc))
1095	return PDMDEV_SET_ERROR(pDevIns, rc,
1096	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1097
1098	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1099	if (RT_FAILURE(rc))
1100	return PDMDEV_SET_ERROR(pDevIns, rc,
1101	N_("Configuration error: failed to read R0Enabled as boolean"));
1102
1103	pThis->pDevIns = pDevIns;
1104	pThis->IOPortBaseCfg = u16Base;
1105	pThis->fSpeakerCfg = fSpeaker;
1106	pThis->channels[0].irq = u8Irq;
1107	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1108	{
1109	pThis->channels[i].pPitR3 = pThis;
1110	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1111	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1112	}
1113
1114	/*
1115	* Interfaces
1116	*/
1117	/* IBase */
1118	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1119	/* IHpetLegacyNotify */
1120	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1121
1122	/*
1123	* Create timer, register I/O Ports and save state.
1124	*/
1125	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1126	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1127	&pThis->channels[0].pTimerR3);
1128	if (RT_FAILURE(rc))
1129	return rc;
1130	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1131	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1132
1133	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1134	if (RT_FAILURE(rc))
1135	return rc;
1136	if (fGCEnabled)
1137	{
1138	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1139	if (RT_FAILURE(rc))
1140	return rc;
1141	}
1142	if (fR0Enabled)
1143	{
1144	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1145	if (RT_FAILURE(rc))
1146	return rc;
1147	}
1148
1149	if (fSpeaker)
1150	{
1151	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1152	if (RT_FAILURE(rc))
1153	return rc;
1154	if (fGCEnabled)
1155	{
1156	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1157	if (RT_FAILURE(rc))
1158	return rc;
1159	}
1160	}
1161
1162	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1163	if (RT_FAILURE(rc))
1164	return rc;
1165
1166	/*
1167	* Initialize the device state.
1168	*/
1169	pitReset(pDevIns);
1170
1171	/*
1172	* Register statistics and debug info.
1173	*/
1174	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1175	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1176
1177	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1178
1179	return VINF_SUCCESS;
1180	}
1181
1182
1183	/**
1184	* The device registration structure.
1185	*/
1186	const PDMDEVREG g_DeviceI8254 =
1187	{
1188	/* u32Version */
1189	PDM_DEVREG_VERSION,
1190	/* szName */
1191	"i8254",
1192	/* szRCMod */
1193	"VBoxDDGC.gc",
1194	/* szR0Mod */
1195	"VBoxDDR0.r0",
1196	/* pszDescription */
1197	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1198	/* fFlags */
1199	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1200	/* fClass */
1201	PDM_DEVREG_CLASS_PIT,
1202	/* cMaxInstances */
1203	1,
1204	/* cbInstance */
1205	sizeof(PITState),
1206	/* pfnConstruct */
1207	pitConstruct,
1208	/* pfnDestruct */
1209	NULL,
1210	/* pfnRelocate */
1211	pitRelocate,
1212	/* pfnIOCtl */
1213	NULL,
1214	/* pfnPowerOn */
1215	NULL,
1216	/* pfnReset */
1217	pitReset,
1218	/* pfnSuspend */
1219	NULL,
1220	/* pfnResume */
1221	NULL,
1222	/* pfnAttach */
1223	NULL,
1224	/* pfnDetach */
1225	NULL,
1226	/* pfnQueryInterface */
1227	NULL,
1228	/* pfnInitComplete */
1229	NULL,
1230	/* pfnPowerOff */
1231	NULL,
1232	/* pfnSoftReset */
1233	NULL,
1234	/* u32VersionEnd */
1235	PDM_DEVREG_VERSION
1236	};
1237
1238	#endif /* IN_RING3 */
1239	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 37475

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