DevPit-i8254.cpp@ 4071

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1	/** $Id: DevPit-i8254.cpp 4071 2007-08-07 17:07:59Z vboxsync $ */
2	/** @file
3	* Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*******************************************************************************
45	* Header Files *
46	*******************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PIT
48	#include <VBox/pdmdev.h>
49	#include <VBox/log.h>
50	#include <VBox/stam.h>
51	#include <iprt/assert.h>
52	#include <iprt/asm.h>
53
54	#include "Builtins.h"
55
56	/*******************************************************************************
57	* Defined Constants And Macros *
58	*******************************************************************************/
59	/** The PIT frequency. */
60	#define PIT_FREQ 1193182
61
62	#define RW_STATE_LSB 1
63	#define RW_STATE_MSB 2
64	#define RW_STATE_WORD0 3
65	#define RW_STATE_WORD1 4
66
67	/** The version of the saved state. */
68	#define PIT_SAVED_STATE_VERSION 2
69
70
71	/*******************************************************************************
72	* Structures and Typedefs *
73	*******************************************************************************/
74	typedef struct PITChannelState
75	{
76	/** Pointer to the instance data - HCPtr. */
77	HCPTRTYPE(struct PITState *) pPitHC;
78	/** The timer - HCPtr. */
79	PTMTIMERHC pTimerHC;
80	/** Pointer to the instance data - GCPtr. */
81	GCPTRTYPE(struct PITState *) pPitGC;
82	/** The timer - HCPtr. */
83	PTMTIMERGC pTimerGC;
84	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
85	uint64_t u64ReloadTS;
86	/** The actual time of the next tick.
87	* As apposed to the next_transition_time which contains the correct time of the next tick. */
88	uint64_t u64NextTS;
89
90	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
91	uint64_t count_load_time;
92	/* irq handling */
93	int64_t next_transition_time;
94	int32_t irq;
95	/** Number of release log entries. Used to prevent floading. */
96	uint32_t cRelLogEntries;
97
98	uint32_t count; /* can be 65536 */
99	uint16_t latched_count;
100	uint8_t count_latched;
101	uint8_t status_latched;
102
103	uint8_t status;
104	uint8_t read_state;
105	uint8_t write_state;
106	uint8_t write_latch;
107
108	uint8_t rw_mode;
109	uint8_t mode;
110	uint8_t bcd; /* not supported */
111	uint8_t gate; /* timer start */
112
113	} PITChannelState;
114
115	typedef struct PITState
116	{
117	PITChannelState channels[3];
118	/** Speaker data. */
119	int32_t speaker_data_on;
120	/** Speaker dummy. */
121	int32_t dummy_refresh_clock;
122	/** Pointer to the device instance. */
123	HCPTRTYPE(PPDMDEVINS) pDevIns;
124	#if HC_ARCH_BITS == 32
125	uint32_t Alignment0;
126	#endif
127	/** Number of IRQs that's been raised. */
128	STAMCOUNTER StatPITIrq;
129	/** Profiling the timer callback handler. */
130	STAMPROFILEADV StatPITHandler;
131	} PITState;
132
133
134	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
135	/*******************************************************************************
136	* Internal Functions *
137	*******************************************************************************/
138	__BEGIN_DECLS
139	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
140	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
141	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
142	#ifdef IN_RING3
143	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
144	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
145	#endif
146	__END_DECLS
147
148
149
150
151	static int pit_get_count(PITChannelState *s)
152	{
153	uint64_t d;
154	int counter;
155	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
156
157	if (s->mode == 2) /** @todo Implement proper virtual time and get rid of this hack.. */
158	{
159	#if 0
160	d = TMTimerGet(pTimer);
161	d -= s->u64ReloadTS;
162	d = ASMMultU64ByU32DivByU32(d, PIT_FREQ, TMTimerGetFreq(pTimer));
163	#else /* variable time because of catch up */
164	if (s->u64NextTS == UINT64_MAX)
165	return 1; /** @todo check this value. */
166	d = TMTimerGet(pTimer);
167	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
168	#endif
169	if (d >= s->count)
170	return 1;
171	return s->count - d;
172	}
173	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
174	switch(s->mode) {
175	case 0:
176	case 1:
177	case 4:
178	case 5:
179	counter = (s->count - d) & 0xffff;
180	break;
181	case 3:
182	/* XXX: may be incorrect for odd counts */
183	counter = s->count - ((2 * d) % s->count);
184	break;
185	default:
186	counter = s->count - (d % s->count);
187	break;
188	}
189	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
190	return counter;
191	}
192
193	/* get pit output bit */
194	static int pit_get_out1(PITChannelState *s, int64_t current_time)
195	{
196	uint64_t d;
197	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
198	int out;
199
200	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
201	switch(s->mode) {
202	default:
203	case 0:
204	out = (d >= s->count);
205	break;
206	case 1:
207	out = (d < s->count);
208	break;
209	case 2:
210	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
211	if ((d % s->count) == 0 && d != 0)
212	out = 1;
213	else
214	out = 0;
215	break;
216	case 3:
217	out = (d % s->count) < ((s->count + 1) >> 1);
218	break;
219	case 4:
220	case 5:
221	out = (d == s->count);
222	break;
223	}
224	return out;
225	}
226
227
228	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
229	{
230	PITChannelState *s = &pit->channels[channel];
231	return pit_get_out1(s, current_time);
232	}
233
234
235	static int pit_get_gate(PITState *pit, int channel)
236	{
237	PITChannelState *s = &pit->channels[channel];
238	return s->gate;
239	}
240
241
242	/* if already latched, do not latch again */
243	static void pit_latch_count(PITChannelState *s)
244	{
245	if (!s->count_latched) {
246	s->latched_count = pit_get_count(s);
247	s->count_latched = s->rw_mode;
248	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
249	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
250	}
251	}
252
253	#ifdef IN_RING3
254
255	/* val must be 0 or 1 */
256	static void pit_set_gate(PITState *pit, int channel, int val)
257	{
258	PITChannelState *s = &pit->channels[channel];
259	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
260
261	switch(s->mode) {
262	default:
263	case 0:
264	case 4:
265	/* XXX: just disable/enable counting */
266	break;
267	case 1:
268	case 5:
269	if (s->gate < val) {
270	/* restart counting on rising edge */
271	s->count_load_time = TMTimerGet(pTimer);
272	pit_irq_timer_update(s, s->count_load_time);
273	}
274	break;
275	case 2:
276	case 3:
277	if (s->gate < val) {
278	/* restart counting on rising edge */
279	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
280	pit_irq_timer_update(s, s->count_load_time);
281	}
282	/* XXX: disable/enable counting */
283	break;
284	}
285	s->gate = val;
286	}
287
288	static inline void pit_load_count(PITChannelState *s, int val)
289	{
290	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
291	if (val == 0)
292	val = 0x10000;
293	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
294	s->count = val;
295	pit_irq_timer_update(s, s->count_load_time);
296
297	/* log the new rate (ch 0 only). */
298	if ( s->pTimerHC /* ch 0 */
299	&& s->cRelLogEntries++ < 32)
300	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
301	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
302	}
303
304	/* return -1 if no transition will occur. */
305	static int64_t pit_get_next_transition_time(PITChannelState *s,
306	uint64_t current_time)
307	{
308	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
309	uint64_t d, next_time, base;
310	uint32_t period2;
311
312	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
313	switch(s->mode) {
314	default:
315	case 0:
316	case 1:
317	if (d < s->count)
318	next_time = s->count;
319	else
320	return -1;
321	break;
322	/*
323	* Mode 2: The period is count + 1 PIT ticks.
324	* When the counter reaches 1 we sent the output low (for channel 0 that
325	* means raise an irq). On the next tick, where we should be decrementing
326	* from 1 to 0, the count is loaded and the output goes high (channel 0
327	* means clearing the irq).
328	*
329	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
330	* the irq. We also don't set it until we reach 0, which is a tick late - will
331	* try fix that later some day.
332	*/
333	case 2:
334	base = (d / s->count) * s->count;
335	#ifndef VBOX /* see above */
336	if ((d - base) == 0 && d != 0)
337	next_time = base + s->count;
338	else
339	#endif
340	next_time = base + s->count + 1;
341	break;
342	case 3:
343	base = (d / s->count) * s->count;
344	period2 = ((s->count + 1) >> 1);
345	if ((d - base) < period2)
346	next_time = base + period2;
347	else
348	next_time = base + s->count;
349	break;
350	case 4:
351	case 5:
352	if (d < s->count)
353	next_time = s->count;
354	else if (d == s->count)
355	next_time = s->count + 1;
356	else
357	return -1;
358	break;
359	}
360	/* convert to timer units */
361	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
362	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
363	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
364	/* fix potential rounding problems */
365	/* XXX: better solution: use a clock at PIT_FREQ Hz */
366	if (next_time <= current_time)
367	next_time = current_time + 1;
368	return next_time;
369	}
370
371	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
372	{
373	uint64_t now;
374	int64_t expire_time;
375	int irq_level;
376	PPDMDEVINS pDevIns;
377	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
378
379	if (!s->CTXSUFF(pTimer))
380	return;
381	expire_time = pit_get_next_transition_time(s, current_time);
382	irq_level = pit_get_out1(s, current_time);
383
384	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
385	pDevIns = s->CTXSUFF(pPit)->pDevIns;
386	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
387	if (irq_level)
388	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
389	now = TMTimerGet(pTimer);
390	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
391	if (irq_level)
392	{
393	s->u64ReloadTS = now;
394	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITIrq);
395	}
396
397	if (expire_time != -1)
398	{
399	s->u64NextTS = expire_time;
400	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
401	}
402	else
403	{
404	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
405	TMTimerStop(s->CTXSUFF(pTimer));
406	s->u64NextTS = UINT64_MAX;
407	}
408	s->next_transition_time = expire_time;
409	}
410
411	#endif /* IN_RING3 */
412
413
414	/**
415	* Port I/O Handler for IN operations.
416	*
417	* @returns VBox status code.
418	*
419	* @param pDevIns The device instance.
420	* @param pvUser User argument - ignored.
421	* @param Port Port number used for the IN operation.
422	* @param pu32 Where to store the result.
423	* @param cb Number of bytes read.
424	*/
425	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
426	{
427	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
428	NOREF(pvUser);
429	Port &= 3;
430	if (cb != 1 \|\| Port == 3)
431	{
432	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
433	return VERR_IOM_IOPORT_UNUSED;
434	}
435
436	PITState pit = PDMINS2DATA(pDevIns, PITState );
437	int ret;
438	PITChannelState *s = &pit->channels[Port];
439	if (s->status_latched)
440	{
441	s->status_latched = 0;
442	ret = s->status;
443	}
444	else if (s->count_latched)
445	{
446	switch (s->count_latched)
447	{
448	default:
449	case RW_STATE_LSB:
450	ret = s->latched_count & 0xff;
451	s->count_latched = 0;
452	break;
453	case RW_STATE_MSB:
454	ret = s->latched_count >> 8;
455	s->count_latched = 0;
456	break;
457	case RW_STATE_WORD0:
458	ret = s->latched_count & 0xff;
459	s->count_latched = RW_STATE_MSB;
460	break;
461	}
462	}
463	else
464	{
465	int count;
466	switch (s->read_state)
467	{
468	default:
469	case RW_STATE_LSB:
470	count = pit_get_count(s);
471	ret = count & 0xff;
472	break;
473	case RW_STATE_MSB:
474	count = pit_get_count(s);
475	ret = (count >> 8) & 0xff;
476	break;
477	case RW_STATE_WORD0:
478	count = pit_get_count(s);
479	ret = count & 0xff;
480	s->read_state = RW_STATE_WORD1;
481	break;
482	case RW_STATE_WORD1:
483	count = pit_get_count(s);
484	ret = (count >> 8) & 0xff;
485	s->read_state = RW_STATE_WORD0;
486	break;
487	}
488	}
489
490	*pu32 = ret;
491	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
492	return VINF_SUCCESS;
493	}
494
495
496	/**
497	* Port I/O Handler for OUT operations.
498	*
499	* @returns VBox status code.
500	*
501	* @param pDevIns The device instance.
502	* @param pvUser User argument - ignored.
503	* @param Port Port number used for the IN operation.
504	* @param u32 The value to output.
505	* @param cb The value size in bytes.
506	*/
507	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
508	{
509	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
510	NOREF(pvUser);
511	if (cb != 1)
512	return VINF_SUCCESS;
513
514	PITState pit = PDMINS2DATA(pDevIns, PITState );
515	Port &= 3;
516	if (Port == 3)
517	{
518	/*
519	* Port 43h - Mode/Command Register.
520	* 7 6 5 4 3 2 1 0
521	* * * . . . . . . Select channel: 0 0 = Channel 0
522	* 0 1 = Channel 1
523	* 1 0 = Channel 2
524	* 1 1 = Read-back command (8254 only)
525	* (Illegal on 8253)
526	* (Illegal on PS/2 {JAM})
527	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
528	* 0 1 = Access mode: lobyte only
529	* 1 0 = Access mode: hibyte only
530	* 1 1 = Access mode: lobyte/hibyte
531	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
532	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
533	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
534	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
535	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
536	*/
537	unsigned channel = u32 >> 6;
538	if (channel == 3)
539	{
540	/* read-back command */
541	for (channel = 0; channel < ELEMENTS(pit->channels); channel++)
542	{
543	PITChannelState *s = &pit->channels[channel];
544	if (u32 & (2 << channel)) {
545	if (!(u32 & 0x20))
546	pit_latch_count(s);
547	if (!(u32 & 0x10) && !s->status_latched)
548	{
549	/* status latch */
550	/* XXX: add BCD and null count */
551	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
552	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
553	\| (s->rw_mode << 4)
554	\| (s->mode << 1)
555	\| s->bcd;
556	s->status_latched = 1;
557	}
558	}
559	}
560	}
561	else
562	{
563	PITChannelState *s = &pit->channels[channel];
564	unsigned access = (u32 >> 4) & 3;
565	if (access == 0)
566	pit_latch_count(s);
567	else
568	{
569	s->rw_mode = access;
570	s->read_state = access;
571	s->write_state = access;
572
573	s->mode = (u32 >> 1) & 7;
574	s->bcd = u32 & 1;
575	/* XXX: update irq timer ? */
576	}
577	}
578	}
579	else
580	{
581	#ifndef IN_RING3
582	return VINF_IOM_HC_IOPORT_WRITE;
583	#else /* IN_RING3 */
584	/*
585	* Port 40-42h - Channel Data Ports.
586	*/
587	PITChannelState *s = &pit->channels[Port];
588	switch(s->write_state)
589	{
590	default:
591	case RW_STATE_LSB:
592	pit_load_count(s, u32);
593	break;
594	case RW_STATE_MSB:
595	pit_load_count(s, u32 << 8);
596	break;
597	case RW_STATE_WORD0:
598	s->write_latch = u32;
599	s->write_state = RW_STATE_WORD1;
600	break;
601	case RW_STATE_WORD1:
602	pit_load_count(s, s->write_latch \| (u32 << 8));
603	s->write_state = RW_STATE_WORD0;
604	break;
605	}
606	#endif /* !IN_RING3 */
607	}
608	return VINF_SUCCESS;
609	}
610
611
612	/**
613	* Port I/O Handler for speaker IN operations.
614	*
615	* @returns VBox status code.
616	*
617	* @param pDevIns The device instance.
618	* @param pvUser User argument - ignored.
619	* @param Port Port number used for the IN operation.
620	* @param pu32 Where to store the result.
621	* @param cb Number of bytes read.
622	*/
623	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
624	{
625	NOREF(pvUser);
626	if (cb == 1)
627	{
628	PITState pData = PDMINS2DATA(pDevIns, PITState );
629	int out = pit_get_out(pData, 2, TMTimerGet(pData->channels[0].CTXSUFF(pTimer)));
630	pData->dummy_refresh_clock ^= 1;
631	*pu32 = (pData->speaker_data_on << 1) \| pit_get_gate(pData, 2) \| (out << 5) \| (pData->dummy_refresh_clock << 4);
632	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
633	return VINF_SUCCESS;
634	}
635	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
636	return VERR_IOM_IOPORT_UNUSED;
637	}
638
639	#ifdef IN_RING3
640
641	/**
642	* Port I/O Handler for speaker OUT operations.
643	*
644	* @returns VBox status code.
645	*
646	* @param pDevIns The device instance.
647	* @param pvUser User argument - ignored.
648	* @param Port Port number used for the IN operation.
649	* @param u32 The value to output.
650	* @param cb The value size in bytes.
651	*/
652	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
653	{
654	NOREF(pvUser);
655	if (cb == 1)
656	{
657	PITState pData = PDMINS2DATA(pDevIns, PITState );
658	pData->speaker_data_on = (u32 >> 1) & 1;
659	pit_set_gate(pData, 2, u32 & 1);
660	}
661	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
662	return VINF_SUCCESS;
663	}
664
665
666	/**
667	* Saves a state of the programmable interval timer device.
668	*
669	* @returns VBox status code.
670	* @param pDevIns The device instance.
671	* @param pSSMHandle The handle to save the state to.
672	*/
673	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
674	{
675	PITState pData = PDMINS2DATA(pDevIns, PITState );
676	unsigned i;
677
678	for (i = 0; i < ELEMENTS(pData->channels); i++)
679	{
680	PITChannelState *s = &pData->channels[i];
681	SSMR3PutU32(pSSMHandle, s->count);
682	SSMR3PutU16(pSSMHandle, s->latched_count);
683	SSMR3PutU8(pSSMHandle, s->count_latched);
684	SSMR3PutU8(pSSMHandle, s->status_latched);
685	SSMR3PutU8(pSSMHandle, s->status);
686	SSMR3PutU8(pSSMHandle, s->read_state);
687	SSMR3PutU8(pSSMHandle, s->write_state);
688	SSMR3PutU8(pSSMHandle, s->write_latch);
689	SSMR3PutU8(pSSMHandle, s->rw_mode);
690	SSMR3PutU8(pSSMHandle, s->mode);
691	SSMR3PutU8(pSSMHandle, s->bcd);
692	SSMR3PutU8(pSSMHandle, s->gate);
693	SSMR3PutU64(pSSMHandle, s->count_load_time);
694	SSMR3PutU64(pSSMHandle, s->u64NextTS);
695	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
696	SSMR3PutS64(pSSMHandle, s->next_transition_time);
697	if (s->CTXSUFF(pTimer))
698	TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
699	}
700
701	SSMR3PutS32(pSSMHandle, pData->speaker_data_on);
702	return SSMR3PutS32(pSSMHandle, pData->dummy_refresh_clock);
703	}
704
705
706	/**
707	* Loads a saved programmable interval timer device state.
708	*
709	* @returns VBox status code.
710	* @param pDevIns The device instance.
711	* @param pSSMHandle The handle to the saved state.
712	* @param u32Version The data unit version number.
713	*/
714	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
715	{
716	PITState pData = PDMINS2DATA(pDevIns, PITState );
717	unsigned i;
718
719	if (u32Version != PIT_SAVED_STATE_VERSION)
720	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
721
722	for (i = 0; i < ELEMENTS(pData->channels); i++)
723	{
724	PITChannelState *s = &pData->channels[i];
725	SSMR3GetU32(pSSMHandle, &s->count);
726	SSMR3GetU16(pSSMHandle, &s->latched_count);
727	SSMR3GetU8(pSSMHandle, &s->count_latched);
728	SSMR3GetU8(pSSMHandle, &s->status_latched);
729	SSMR3GetU8(pSSMHandle, &s->status);
730	SSMR3GetU8(pSSMHandle, &s->read_state);
731	SSMR3GetU8(pSSMHandle, &s->write_state);
732	SSMR3GetU8(pSSMHandle, &s->write_latch);
733	SSMR3GetU8(pSSMHandle, &s->rw_mode);
734	SSMR3GetU8(pSSMHandle, &s->mode);
735	SSMR3GetU8(pSSMHandle, &s->bcd);
736	SSMR3GetU8(pSSMHandle, &s->gate);
737	SSMR3GetU64(pSSMHandle, &s->count_load_time);
738	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
739	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
740	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
741	if (s->CTXSUFF(pTimer))
742	{
743	TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
744	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
745	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
746	}
747	pData->channels[0].cRelLogEntries = 0;
748	}
749
750	SSMR3GetS32(pSSMHandle, &pData->speaker_data_on);
751	return SSMR3GetS32(pSSMHandle, &pData->dummy_refresh_clock);
752	}
753
754
755	/**
756	* Device timer callback function.
757	*
758	* @param pDevIns Device instance of the device which registered the timer.
759	* @param pTimer The timer handle.
760	*/
761	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
762	{
763	PITState pData = PDMINS2DATA(pDevIns, PITState );
764	PITChannelState *s = &pData->channels[0];
765	STAM_PROFILE_ADV_START(&s->CTXSUFF(pPit)->StatPITHandler, a);
766	pit_irq_timer_update(s, s->next_transition_time);
767	STAM_PROFILE_ADV_STOP(&s->CTXSUFF(pPit)->StatPITHandler, a);
768	}
769
770
771	/**
772	* Relocation notification.
773	*
774	* @returns VBox status.
775	* @param pDevIns The device instance data.
776	* @param offDelta The delta relative to the old address.
777	*/
778	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
779	{
780	PITState pData = PDMINS2DATA(pDevIns, PITState );
781	unsigned i;
782	LogFlow(("pitRelocate: \n"));
783
784	for (i = 0; i < ELEMENTS(pData->channels); i++)
785	{
786	PITChannelState *pCh = &pData->channels[i];
787	if (pCh->pTimerHC)
788	pCh->pTimerGC = TMTimerGCPtr(pCh->pTimerHC);
789	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
790	}
791	}
792
793	/** @todo remove this! */
794	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
795
796	/**
797	* Reset notification.
798	*
799	* @returns VBox status.
800	* @param pDevIns The device instance data.
801	*/
802	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
803	{
804	PITState pData = PDMINS2DATA(pDevIns, PITState );
805	unsigned i;
806	LogFlow(("pitReset: \n"));
807
808	for (i = 0; i < ELEMENTS(pData->channels); i++)
809	{
810	PITChannelState *s = &pData->channels[i];
811
812	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
813	s->latched_count = 0;
814	s->count_latched = 0;
815	s->status_latched = 0;
816	s->status = 0;
817	s->read_state = 0;
818	s->write_state = 0;
819	s->write_latch = 0;
820	s->rw_mode = 0;
821	s->bcd = 0;
822	#endif
823	s->cRelLogEntries = 0;
824	s->mode = 3;
825	s->gate = (i != 2);
826	pit_load_count(s, 0);
827	}
828	}
829
830
831	/**
832	* Info handler, device version.
833	*
834	* @param pDevIns Device instance which registered the info.
835	* @param pHlp Callback functions for doing output.
836	* @param pszArgs Argument string. Optional and specific to the handler.
837	*/
838	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
839	{
840	PITState pData = PDMINS2DATA(pDevIns, PITState );
841	unsigned i;
842	for (i = 0; i < ELEMENTS(pData->channels); i++)
843	{
844	const PITChannelState *pCh = &pData->channels[i];
845
846	pHlp->pfnPrintf(pHlp,
847	"PIT (i8254) channel %d status: irq=%#x\n"
848	" count=%08x" " latched_count=%04x count_latched=%02x\n"
849	" status=%02x status_latched=%02x read_state=%02x\n"
850	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
851	" mode=%02x bcd=%02x gate=%02x\n"
852	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
853	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
854	,
855	i, pCh->irq,
856	pCh->count, pCh->latched_count, pCh->count_latched,
857	pCh->status, pCh->status_latched, pCh->read_state,
858	pCh->write_state, pCh->write_latch, pCh->rw_mode,
859	pCh->mode, pCh->bcd, pCh->gate,
860	pCh->count_load_time, pCh->next_transition_time,
861	pCh->u64ReloadTS, pCh->u64NextTS);
862	}
863	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
864	pData->speaker_data_on, pData->dummy_refresh_clock);
865	}
866
867
868	/**
869	* Construct a device instance for a VM.
870	*
871	* @returns VBox status.
872	* @param pDevIns The device instance data.
873	* If the registration structure is needed, pDevIns->pDevReg points to it.
874	* @param iInstance Instance number. Use this to figure out which registers and such to use.
875	* The device number is also found in pDevIns->iInstance, but since it's
876	* likely to be freqently used PDM passes it as parameter.
877	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
878	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
879	* iInstance it's expected to be used a bit in this function.
880	*/
881	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
882	{
883	PITState pData = PDMINS2DATA(pDevIns, PITState );
884	int rc;
885	uint8_t u8Irq;
886	uint16_t u16Base;
887	bool fSpeaker;
888	bool fGCEnabled;
889	bool fR0Enabled;
890	unsigned i;
891	Assert(iInstance == 0);
892
893	/*
894	* Validate configuration.
895	*/
896	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0Speaker\0GCEnabled\0R0Enabled\0"))
897	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
898
899	/*
900	* Init the data.
901	*/
902	rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
903	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
904	u8Irq = 0;
905	else if (VBOX_FAILURE(rc))
906	return PDMDEV_SET_ERROR(pDevIns, rc,
907	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
908
909	rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
910	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
911	u16Base = 0x40;
912	else if (VBOX_FAILURE(rc))
913	return PDMDEV_SET_ERROR(pDevIns, rc,
914	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
915
916	rc = CFGMR3QueryBool(pCfgHandle, "SpeakerEnabled", &fSpeaker);
917	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
918	fSpeaker = true;
919	else if (VBOX_FAILURE(rc))
920	return PDMDEV_SET_ERROR(pDevIns, rc,
921	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
922
923	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
924	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
925	fGCEnabled = true;
926	else if (VBOX_FAILURE(rc))
927	return PDMDEV_SET_ERROR(pDevIns, rc,
928	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
929
930	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
931	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
932	fR0Enabled = true;
933	else if (VBOX_FAILURE(rc))
934	return PDMDEV_SET_ERROR(pDevIns, rc,
935	N_("Configuration error: failed to read R0Enabled as boolean"));
936
937	pData->pDevIns = pDevIns;
938	pData->channels[0].irq = u8Irq;
939	for (i = 0; i < ELEMENTS(pData->channels); i++)
940	{
941	pData->channels[i].pPitHC = pData;
942	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
943	}
944
945	/*
946	* Create timer, register I/O Ports and save state.
947	*/
948	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, "i8254 Programmable Interval Timer",
949	&pData->channels[0].CTXSUFF(pTimer));
950	if (VBOX_FAILURE(rc))
951	{
952	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
953	return rc;
954	}
955
956	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
957	if (VBOX_FAILURE(rc))
958	return rc;
959	if (fGCEnabled)
960	{
961	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
962	if (VBOX_FAILURE(rc))
963	return rc;
964	}
965	if (fR0Enabled)
966	{
967	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
968	if (VBOX_FAILURE(rc))
969	return rc;
970	}
971
972	if (fSpeaker)
973	{
974	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
975	if (VBOX_FAILURE(rc))
976	return rc;
977	if (fGCEnabled)
978	{
979	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
980	if (VBOX_FAILURE(rc))
981	return rc;
982	}
983	}
984
985	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pData),
986	NULL, pitSaveExec, NULL,
987	NULL, pitLoadExec, NULL);
988	if (VBOX_FAILURE(rc))
989	return rc;
990
991	/*
992	* Initialize the device state.
993	*/
994	pitReset(pDevIns);
995
996	/*
997	* Register statistics and debug info.
998	*/
999	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1000	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1001
1002	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1003
1004	return VINF_SUCCESS;
1005	}
1006
1007
1008	/**
1009	* The device registration structure.
1010	*/
1011	const PDMDEVREG g_DeviceI8254 =
1012	{
1013	/* u32Version */
1014	PDM_DEVREG_VERSION,
1015	/* szDeviceName */
1016	"i8254",
1017	/* szGCMod */
1018	"VBoxDDGC.gc",
1019	/* szR0Mod */
1020	"VBoxDDR0.r0",
1021	/* pszDescription */
1022	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1023	/* fFlags */
1024	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1025	/* fClass */
1026	PDM_DEVREG_CLASS_PIT,
1027	/* cMaxInstances */
1028	1,
1029	/* cbInstance */
1030	sizeof(PITState),
1031	/* pfnConstruct */
1032	pitConstruct,
1033	/* pfnDestruct */
1034	NULL,
1035	/* pfnRelocate */
1036	pitRelocate,
1037	/* pfnIOCtl */
1038	NULL,
1039	/* pfnPowerOn */
1040	NULL,
1041	/* pfnReset */
1042	pitReset,
1043	/* pfnSuspend */
1044	NULL,
1045	/* pfnResume */
1046	NULL,
1047	/* pfnAttach */
1048	NULL,
1049	/* pfnDetach */
1050	NULL,
1051	/* pfnQueryInterface. */
1052	NULL
1053	};
1054
1055	#endif /* IN_RING3 */
1056	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1057

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 4071

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