DevPit-i8254.cpp@ 566

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1	/** @file
2	*
3	* VBox basic PC devices:
4	* Intel 8254 programmable interval timer
5	*/
6
7	/*
8	* Copyright (C) 2006 InnoTek Systemberatung GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* If you received this file as part of a commercial VirtualBox
19	* distribution, then only the terms of your commercial VirtualBox
20	* license agreement apply instead of the previous paragraph.
21	*
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU 8253/8254 interval timer emulation
27	*
28	* Copyright (c) 2003-2004 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49
50	/*******************************************************************************
51	* Header Files *
52	*******************************************************************************/
53	#define LOG_GROUP LOG_GROUP_DEV_PIT
54	#include <VBox/pdm.h>
55
56	#include <VBox/log.h>
57	#include <iprt/assert.h>
58	#include <VBox/stam.h>
59
60	#include "vl_vbox.h"
61
62
63	/*******************************************************************************
64	* Defined Constants And Macros *
65	*******************************************************************************/
66	/** The PIT frequency. */
67	#define PIT_FREQ 1193182
68
69	#define RW_STATE_LSB 1
70	#define RW_STATE_MSB 2
71	#define RW_STATE_WORD0 3
72	#define RW_STATE_WORD1 4
73
74	/** The version of the saved state. */
75	#define PIT_SAVED_STATE_VERSION 2
76
77
78	/*******************************************************************************
79	* Structures and Typedefs *
80	*******************************************************************************/
81	typedef struct PITChannelState
82	{
83	/** Pointer to the instance data - HCPtr. */
84	HCPTRTYPE(struct PITState *) pPitHC;
85	/** The timer - HCPtr. */
86	PTMTIMERHC pTimerHC;
87	/** Pointer to the instance data - GCPtr. */
88	GCPTRTYPE(struct PITState *) pPitGC;
89	/** The timer - HCPtr. */
90	PTMTIMERGC pTimerGC;
91	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
92	uint64_t u64ReloadTS;
93	/** The actual time of the next tick.
94	* As apposed to the next_transition_time which contains the correct time of the next tick. */
95	uint64_t u64NextTS;
96	/** When to give up catching up. (negative number) */
97	int64_t i64MaxCatchupTS;
98
99	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
100	uint64_t count_load_time;
101	/* irq handling */
102	int64_t next_transition_time;
103	int32_t irq;
104	uint32_t padding;
105
106	uint32_t count; /* can be 65536 */
107	uint16_t latched_count;
108	uint8_t count_latched;
109	uint8_t status_latched;
110
111	uint8_t status;
112	uint8_t read_state;
113	uint8_t write_state;
114	uint8_t write_latch;
115
116	uint8_t rw_mode;
117	uint8_t mode;
118	uint8_t bcd; /* not supported */
119	uint8_t gate; /* timer start */
120
121	} PITChannelState;
122
123	typedef struct PITState
124	{
125	PITChannelState channels[3];
126	/** Speaker data. */
127	int32_t speaker_data_on;
128	/** Speaker dummy. */
129	int32_t dummy_refresh_clock;
130	/** Pointer to the device instance. */
131	HCPTRTYPE(PPDMDEVINS) pDevIns;
132	#if HC_ARCH_BITS == 32
133	uint32_t Alignment0;
134	#endif
135	/** Number of IRQs that's been raised. */
136	STAMCOUNTER StatPITIrq;
137	/** Profiling the timer callback handler. */
138	STAMPROFILEADV StatPITHandler;
139	/** The number of times we've had to speed up the time because we lagged too far behind. */
140	STAMCOUNTER StatPITCatchup;
141	/** The number of times we've lagged too far behind for it to be worth trying to catch up. */
142	STAMCOUNTER StatPITGiveup;
143	} PITState;
144
145
146	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
147	/*******************************************************************************
148	* Internal Functions *
149	*******************************************************************************/
150	__BEGIN_DECLS
151	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
152	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
153	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
154	#ifdef IN_RING3
155	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
156	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
157	#endif
158	__END_DECLS
159
160
161
162
163	static int pit_get_count(PITChannelState *s)
164	{
165	uint64_t d;
166	int counter;
167	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
168
169	if (s->mode == 2) /** @todo Implement proper virtual time and get rid of this hack.. */
170	{
171	#if 0
172	d = TMTimerGet(pTimer);
173	d -= s->u64ReloadTS;
174	d = muldiv64(d, PIT_FREQ, TMTimerGetFreq(pTimer));
175	#else /* variable time because of catch up */
176	if (s->u64NextTS == UINT64_MAX)
177	return 1; /** @todo check this value. */
178	d = TMTimerGet(pTimer);
179	d = muldiv64(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
180	#endif
181	if (d >= s->count)
182	return 1;
183	return s->count - d;
184	}
185	d = muldiv64(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
186	switch(s->mode) {
187	case 0:
188	case 1:
189	case 4:
190	case 5:
191	counter = (s->count - d) & 0xffff;
192	break;
193	case 3:
194	/* XXX: may be incorrect for odd counts */
195	counter = s->count - ((2 * d) % s->count);
196	break;
197	default:
198	counter = s->count - (d % s->count);
199	break;
200	}
201	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
202	return counter;
203	}
204
205	/* get pit output bit */
206	static int pit_get_out1(PITChannelState *s, int64_t current_time)
207	{
208	uint64_t d;
209	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
210	int out;
211
212	d = muldiv64(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
213	switch(s->mode) {
214	default:
215	case 0:
216	out = (d >= s->count);
217	break;
218	case 1:
219	out = (d < s->count);
220	break;
221	case 2:
222	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
223	if ((d % s->count) == 0 && d != 0)
224	out = 1;
225	else
226	out = 0;
227	break;
228	case 3:
229	out = (d % s->count) < ((s->count + 1) >> 1);
230	break;
231	case 4:
232	case 5:
233	out = (d == s->count);
234	break;
235	}
236	return out;
237	}
238
239
240	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
241	{
242	PITChannelState *s = &pit->channels[channel];
243	return pit_get_out1(s, current_time);
244	}
245
246
247	static int pit_get_gate(PITState *pit, int channel)
248	{
249	PITChannelState *s = &pit->channels[channel];
250	return s->gate;
251	}
252
253
254	/* if already latched, do not latch again */
255	static void pit_latch_count(PITChannelState *s)
256	{
257	if (!s->count_latched) {
258	s->latched_count = pit_get_count(s);
259	s->count_latched = s->rw_mode;
260	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
261	s->latched_count, muldiv64(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
262	}
263	}
264
265	#ifdef IN_RING3
266
267	/* val must be 0 or 1 */
268	static void pit_set_gate(PITState *pit, int channel, int val)
269	{
270	PITChannelState *s = &pit->channels[channel];
271	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
272
273	switch(s->mode) {
274	default:
275	case 0:
276	case 4:
277	/* XXX: just disable/enable counting */
278	break;
279	case 1:
280	case 5:
281	if (s->gate < val) {
282	/* restart counting on rising edge */
283	s->count_load_time = TMTimerGet(pTimer);
284	pit_irq_timer_update(s, s->count_load_time);
285	}
286	break;
287	case 2:
288	case 3:
289	if (s->gate < val) {
290	/* restart counting on rising edge */
291	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
292	pit_irq_timer_update(s, s->count_load_time);
293	}
294	/* XXX: disable/enable counting */
295	break;
296	}
297	s->gate = val;
298	}
299
300	static inline void pit_load_count(PITChannelState *s, int val)
301	{
302	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
303	if (val == 0)
304	val = 0x10000;
305	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
306	s->count = val;
307	pit_irq_timer_update(s, s->count_load_time);
308	}
309
310	/* return -1 if no transition will occur. */
311	static int64_t pit_get_next_transition_time(PITChannelState *s,
312	uint64_t current_time)
313	{
314	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
315	uint64_t d, next_time, base;
316	uint32_t period2;
317
318	d = muldiv64(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
319	switch(s->mode) {
320	default:
321	case 0:
322	case 1:
323	if (d < s->count)
324	next_time = s->count;
325	else
326	return -1;
327	break;
328	/*
329	* Mode 2: The period is count + 1 PIT ticks.
330	* When the counter reaches 1 we sent the output low (for channel 0 that
331	* means raise an irq). On the next tick, where we should be decrementing
332	* from 1 to 0, the count is loaded and the output goes high (channel 0
333	* means clearing the irq).
334	*
335	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
336	* the irq. We also don't set it until we reach 0, which is a tick late - will
337	* try fix that later some day.
338	*/
339	case 2:
340	base = (d / s->count) * s->count;
341	#ifndef VBOX /* see above */
342	if ((d - base) == 0 && d != 0)
343	next_time = base + s->count;
344	else
345	#endif
346	next_time = base + s->count + 1;
347	break;
348	case 3:
349	base = (d / s->count) * s->count;
350	period2 = ((s->count + 1) >> 1);
351	if ((d - base) < period2)
352	next_time = base + period2;
353	else
354	next_time = base + s->count;
355	break;
356	case 4:
357	case 5:
358	if (d < s->count)
359	next_time = s->count;
360	else if (d == s->count)
361	next_time = s->count + 1;
362	else
363	return -1;
364	break;
365	}
366	/* convert to timer units */
367	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
368	muldiv64(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
369	next_time = s->count_load_time + muldiv64(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
370	/* fix potential rounding problems */
371	/* XXX: better solution: use a clock at PIT_FREQ Hz */
372	if (next_time <= current_time)
373	next_time = current_time + 1;
374	return next_time;
375	}
376
377	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
378	{
379	uint64_t now;
380	int64_t expire_time;
381	int irq_level;
382	PPDMDEVINS pDevIns;
383	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
384
385	if (!s->CTXSUFF(pTimer))
386	return;
387	expire_time = pit_get_next_transition_time(s, current_time);
388	irq_level = pit_get_out1(s, current_time);
389
390	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
391	pDevIns = s->CTXSUFF(pPit)->pDevIns;
392	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
393	if (irq_level)
394	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
395	now = TMTimerGet(pTimer);
396	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
397	if (irq_level)
398	{
399	s->u64ReloadTS = now;
400	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITIrq);
401	}
402
403	/* check if it expires too soon - move at 4x rate if it does. */
404	if (expire_time != -1)
405	{
406	int64_t delta = expire_time - now;
407	const int64_t quarter = (expire_time - s->next_transition_time) >> 2;
408	if (delta <= quarter && s->next_transition_time != -1)
409	{
410	if (delta >= s->i64MaxCatchupTS)
411	{
412	/* If we set the timer to 'expire_time' we could end up with flooding the guest
413	* with timer interrupts because the next interrupt(s) would probably raise
414	* immediately. Therefore we set the timer to 'now + quarter' with quarter>0.
415	* This delays the adaption a little bit. */
416	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITCatchup);
417	s->u64NextTS = now + quarter;
418	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64 delta=%9RI64\n",
419	s->mode, s->count, irq_level, quarter, s->u64NextTS, now, s->count_load_time,
420	muldiv64(s->u64NextTS - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer)), delta));
421	}
422	else
423	{
424	/* We are too far away from the real time. Hard synchronize. */
425	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITGiveup);
426	s->u64NextTS = expire_time = pit_get_next_transition_time(s, now);
427	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64 delta=%9RI64 giving up!\n",
428	s->mode, s->count, irq_level, quarter, s->u64NextTS, now, s->count_load_time,
429	muldiv64(s->u64NextTS - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer)), delta));
430	}
431	}
432	else
433	{
434	/* Everything is fine, just set the timer to the regular next expire_time. */
435	s->u64NextTS = expire_time;
436	LogFlow(("PIT: m=%d cnt=%#4x irq=%#x delay=%8RI64 next=%20RI64 now=%20RI64 load=%20RI64 %9RI64\n",
437	s->mode, s->count, irq_level, expire_time - now, expire_time, now, s->count_load_time,
438	muldiv64(expire_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer))));
439	}
440	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
441	}
442	else
443	{
444	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
445	TMTimerStop(s->CTXSUFF(pTimer));
446	s->u64NextTS = UINT64_MAX;
447	}
448	s->next_transition_time = expire_time;
449	}
450
451	#endif /* IN_RING3 */
452
453
454	/**
455	* Port I/O Handler for IN operations.
456	*
457	* @returns VBox status code.
458	*
459	* @param pDevIns The device instance.
460	* @param pvUser User argument - ignored.
461	* @param Port Port number used for the IN operation.
462	* @param pu32 Where to store the result.
463	* @param cb Number of bytes read.
464	*/
465	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
466	{
467	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
468	NOREF(pvUser);
469	Port &= 3;
470	if (cb != 1 \|\| Port == 3)
471	{
472	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
473	return VERR_IOM_IOPORT_UNUSED;
474	}
475
476	PITState pit = PDMINS2DATA(pDevIns, PITState );
477	int ret;
478	PITChannelState *s = &pit->channels[Port];
479	if (s->status_latched)
480	{
481	s->status_latched = 0;
482	ret = s->status;
483	}
484	else if (s->count_latched)
485	{
486	switch (s->count_latched)
487	{
488	default:
489	case RW_STATE_LSB:
490	ret = s->latched_count & 0xff;
491	s->count_latched = 0;
492	break;
493	case RW_STATE_MSB:
494	ret = s->latched_count >> 8;
495	s->count_latched = 0;
496	break;
497	case RW_STATE_WORD0:
498	ret = s->latched_count & 0xff;
499	s->count_latched = RW_STATE_MSB;
500	break;
501	}
502	}
503	else
504	{
505	int count;
506	switch (s->read_state)
507	{
508	default:
509	case RW_STATE_LSB:
510	count = pit_get_count(s);
511	ret = count & 0xff;
512	break;
513	case RW_STATE_MSB:
514	count = pit_get_count(s);
515	ret = (count >> 8) & 0xff;
516	break;
517	case RW_STATE_WORD0:
518	count = pit_get_count(s);
519	ret = count & 0xff;
520	s->read_state = RW_STATE_WORD1;
521	break;
522	case RW_STATE_WORD1:
523	count = pit_get_count(s);
524	ret = (count >> 8) & 0xff;
525	s->read_state = RW_STATE_WORD0;
526	break;
527	}
528	}
529
530	*pu32 = ret;
531	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
532	return VINF_SUCCESS;
533	}
534
535
536	/**
537	* Port I/O Handler for OUT operations.
538	*
539	* @returns VBox status code.
540	*
541	* @param pDevIns The device instance.
542	* @param pvUser User argument - ignored.
543	* @param Port Port number used for the IN operation.
544	* @param u32 The value to output.
545	* @param cb The value size in bytes.
546	*/
547	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
548	{
549	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
550	NOREF(pvUser);
551	if (cb != 1)
552	return VINF_SUCCESS;
553
554	PITState pit = PDMINS2DATA(pDevIns, PITState );
555	Port &= 3;
556	if (Port == 3)
557	{
558	/*
559	* Port 43h - Mode/Command Register.
560	* 7 6 5 4 3 2 1 0
561	* * * . . . . . . Select channel: 0 0 = Channel 0
562	* 0 1 = Channel 1
563	* 1 0 = Channel 2
564	* 1 1 = Read-back command (8254 only)
565	* (Illegal on 8253)
566	* (Illegal on PS/2 {JAM})
567	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
568	* 0 1 = Access mode: lobyte only
569	* 1 0 = Access mode: hibyte only
570	* 1 1 = Access mode: lobyte/hibyte
571	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
572	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
573	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
574	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
575	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
576	*/
577	unsigned channel = u32 >> 6;
578	if (channel == 3)
579	{
580	/* read-back command */
581	for (channel = 0; channel < ELEMENTS(pit->channels); channel++)
582	{
583	PITChannelState *s = &pit->channels[channel];
584	if (u32 & (2 << channel)) {
585	if (!(u32 & 0x20))
586	pit_latch_count(s);
587	if (!(u32 & 0x10) && !s->status_latched)
588	{
589	/* status latch */
590	/* XXX: add BCD and null count */
591	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
592	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
593	\| (s->rw_mode << 4)
594	\| (s->mode << 1)
595	\| s->bcd;
596	s->status_latched = 1;
597	}
598	}
599	}
600	}
601	else
602	{
603	PITChannelState *s = &pit->channels[channel];
604	unsigned access = (u32 >> 4) & 3;
605	if (access == 0)
606	pit_latch_count(s);
607	else
608	{
609	s->rw_mode = access;
610	s->read_state = access;
611	s->write_state = access;
612
613	s->mode = (u32 >> 1) & 7;
614	s->bcd = u32 & 1;
615	/* XXX: update irq timer ? */
616	}
617	}
618	}
619	else
620	{
621	#ifndef IN_RING3
622	return VINF_IOM_HC_IOPORT_WRITE;
623	#else /* IN_RING3 */
624	/*
625	* Port 40-42h - Channel Data Ports.
626	*/
627	PITChannelState *s = &pit->channels[Port];
628	switch(s->write_state)
629	{
630	default:
631	case RW_STATE_LSB:
632	pit_load_count(s, u32);
633	break;
634	case RW_STATE_MSB:
635	pit_load_count(s, u32 << 8);
636	break;
637	case RW_STATE_WORD0:
638	s->write_latch = u32;
639	s->write_state = RW_STATE_WORD1;
640	break;
641	case RW_STATE_WORD1:
642	pit_load_count(s, s->write_latch \| (u32 << 8));
643	s->write_state = RW_STATE_WORD0;
644	break;
645	}
646	#endif /* !IN_RING3 */
647	}
648	return VINF_SUCCESS;
649	}
650
651
652	/**
653	* Port I/O Handler for speaker IN operations.
654	*
655	* @returns VBox status code.
656	*
657	* @param pDevIns The device instance.
658	* @param pvUser User argument - ignored.
659	* @param Port Port number used for the IN operation.
660	* @param pu32 Where to store the result.
661	* @param cb Number of bytes read.
662	*/
663	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
664	{
665	NOREF(pvUser);
666	if (cb == 1)
667	{
668	PITState pData = PDMINS2DATA(pDevIns, PITState );
669	int out = pit_get_out(pData, 2, TMTimerGet(pData->channels[0].CTXSUFF(pTimer)));
670	pData->dummy_refresh_clock ^= 1;
671	*pu32 = (pData->speaker_data_on << 1) \| pit_get_gate(pData, 2) \| (out << 5) \| (pData->dummy_refresh_clock << 4);
672	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
673	return VINF_SUCCESS;
674	}
675	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
676	return VERR_IOM_IOPORT_UNUSED;
677	}
678
679	#ifdef IN_RING3
680
681	/**
682	* Port I/O Handler for speaker OUT operations.
683	*
684	* @returns VBox status code.
685	*
686	* @param pDevIns The device instance.
687	* @param pvUser User argument - ignored.
688	* @param Port Port number used for the IN operation.
689	* @param u32 The value to output.
690	* @param cb The value size in bytes.
691	*/
692	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
693	{
694	NOREF(pvUser);
695	if (cb == 1)
696	{
697	PITState pData = PDMINS2DATA(pDevIns, PITState );
698	pData->speaker_data_on = (u32 >> 1) & 1;
699	pit_set_gate(pData, 2, u32 & 1);
700	}
701	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
702	return VINF_SUCCESS;
703	}
704
705
706	/**
707	* Saves a state of the programmable interval timer device.
708	*
709	* @returns VBox status code.
710	* @param pDevIns The device instance.
711	* @param pSSMHandle The handle to save the state to.
712	*/
713	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
714	{
715	PITState pData = PDMINS2DATA(pDevIns, PITState );
716	unsigned i;
717
718	for (i = 0; i < ELEMENTS(pData->channels); i++)
719	{
720	PITChannelState *s = &pData->channels[i];
721	SSMR3PutU32(pSSMHandle, s->count);
722	SSMR3PutU16(pSSMHandle, s->latched_count);
723	SSMR3PutU8(pSSMHandle, s->count_latched);
724	SSMR3PutU8(pSSMHandle, s->status_latched);
725	SSMR3PutU8(pSSMHandle, s->status);
726	SSMR3PutU8(pSSMHandle, s->read_state);
727	SSMR3PutU8(pSSMHandle, s->write_state);
728	SSMR3PutU8(pSSMHandle, s->write_latch);
729	SSMR3PutU8(pSSMHandle, s->rw_mode);
730	SSMR3PutU8(pSSMHandle, s->mode);
731	SSMR3PutU8(pSSMHandle, s->bcd);
732	SSMR3PutU8(pSSMHandle, s->gate);
733	SSMR3PutU64(pSSMHandle, s->count_load_time);
734	SSMR3PutU64(pSSMHandle, s->u64NextTS);
735	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
736	SSMR3PutS64(pSSMHandle, s->next_transition_time);
737	if (s->CTXSUFF(pTimer))
738	TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
739	}
740
741	SSMR3PutS32(pSSMHandle, pData->speaker_data_on);
742	return SSMR3PutS32(pSSMHandle, pData->dummy_refresh_clock);
743	}
744
745
746	/**
747	* Loads a saved programmable interval timer device state.
748	*
749	* @returns VBox status code.
750	* @param pDevIns The device instance.
751	* @param pSSMHandle The handle to the saved state.
752	* @param u32Version The data unit version number.
753	*/
754	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
755	{
756	PITState pData = PDMINS2DATA(pDevIns, PITState );
757	unsigned i;
758
759	if (u32Version != PIT_SAVED_STATE_VERSION)
760	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
761
762	for (i = 0; i < ELEMENTS(pData->channels); i++)
763	{
764	PITChannelState *s = &pData->channels[i];
765	SSMR3GetU32(pSSMHandle, &s->count);
766	SSMR3GetU16(pSSMHandle, &s->latched_count);
767	SSMR3GetU8(pSSMHandle, &s->count_latched);
768	SSMR3GetU8(pSSMHandle, &s->status_latched);
769	SSMR3GetU8(pSSMHandle, &s->status);
770	SSMR3GetU8(pSSMHandle, &s->read_state);
771	SSMR3GetU8(pSSMHandle, &s->write_state);
772	SSMR3GetU8(pSSMHandle, &s->write_latch);
773	SSMR3GetU8(pSSMHandle, &s->rw_mode);
774	SSMR3GetU8(pSSMHandle, &s->mode);
775	SSMR3GetU8(pSSMHandle, &s->bcd);
776	SSMR3GetU8(pSSMHandle, &s->gate);
777	SSMR3GetU64(pSSMHandle, &s->count_load_time);
778	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
779	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
780	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
781	if (s->CTXSUFF(pTimer))
782	TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
783	}
784
785	SSMR3GetS32(pSSMHandle, &pData->speaker_data_on);
786	return SSMR3GetS32(pSSMHandle, &pData->dummy_refresh_clock);
787	}
788
789
790	/**
791	* Device timer callback function.
792	*
793	* @param pDevIns Device instance of the device which registered the timer.
794	* @param pTimer The timer handle.
795	*/
796	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
797	{
798	PITState pData = PDMINS2DATA(pDevIns, PITState );
799	PITChannelState *s = &pData->channels[0];
800	STAM_PROFILE_ADV_START(&s->CTXSUFF(pPit)->StatPITHandler, a);
801	pit_irq_timer_update(s, s->next_transition_time);
802	STAM_PROFILE_ADV_STOP(&s->CTXSUFF(pPit)->StatPITHandler, a);
803	}
804
805
806	/**
807	* Relocation notification.
808	*
809	* @returns VBox status.
810	* @param pDevIns The device instance data.
811	* @param offDelta The delta relative to the old address.
812	*/
813	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
814	{
815	PITState pData = PDMINS2DATA(pDevIns, PITState );
816	unsigned i;
817	LogFlow(("pitRelocate: \n"));
818
819	for (i = 0; i < ELEMENTS(pData->channels); i++)
820	{
821	PITChannelState *pCh = &pData->channels[i];
822	if (pCh->pTimerHC)
823	pCh->pTimerGC = TMTimerGCPtr(pCh->pTimerHC);
824	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
825	}
826	}
827
828	/** @todo remove this! */
829	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
830
831	/**
832	* Reset notification.
833	*
834	* @returns VBox status.
835	* @param pDevIns The device instance data.
836	*/
837	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
838	{
839	PITState pData = PDMINS2DATA(pDevIns, PITState );
840	unsigned i;
841	LogFlow(("pitReset: \n"));
842
843	for (i = 0; i < ELEMENTS(pData->channels); i++)
844	{
845	PITChannelState *s = &pData->channels[i];
846
847	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
848	s->latched_count = 0;
849	s->count_latched = 0;
850	s->status_latched = 0;
851	s->status = 0;
852	s->read_state = 0;
853	s->write_state = 0;
854	s->write_latch = 0;
855	s->rw_mode = 0;
856	s->bcd = 0;
857	#endif
858	s->mode = 3;
859	s->gate = (i != 2);
860	pit_load_count(s, 0);
861	}
862	/** @todo remove when #1589 is resolved. */
863	pitInfo(pDevIns, DBGFR3InfoLogRelHlp(), NULL);
864	}
865
866
867	/**
868	* Info handler, device version.
869	*
870	* @param pDevIns Device instance which registered the info.
871	* @param pHlp Callback functions for doing output.
872	* @param pszArgs Argument string. Optional and specific to the handler.
873	*/
874	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
875	{
876	PITState pData = PDMINS2DATA(pDevIns, PITState );
877	unsigned i;
878	for (i = 0; i < ELEMENTS(pData->channels); i++)
879	{
880	const PITChannelState *pCh = &pData->channels[i];
881
882	pHlp->pfnPrintf(pHlp,
883	"PIT (i8254) channel %d status: irq=%#x\n"
884	" count=%08x" " latched_count=%04x count_latched=%02x\n"
885	" status=%02x status_latched=%02x read_state=%02x\n"
886	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
887	" mode=%02x bcd=%02x gate=%02x\n"
888	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
889	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
890	,
891	i, pCh->irq,
892	pCh->count, pCh->latched_count, pCh->count_latched,
893	pCh->status, pCh->status_latched, pCh->read_state,
894	pCh->write_state, pCh->write_latch, pCh->rw_mode,
895	pCh->mode, pCh->bcd, pCh->gate,
896	pCh->count_load_time, pCh->next_transition_time,
897	pCh->u64ReloadTS, pCh->u64NextTS);
898	}
899	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
900	pData->speaker_data_on, pData->dummy_refresh_clock);
901	}
902
903
904	/**
905	* Construct a device instance for a VM.
906	*
907	* @returns VBox status.
908	* @param pDevIns The device instance data.
909	* If the registration structure is needed, pDevIns->pDevReg points to it.
910	* @param iInstance Instance number. Use this to figure out which registers and such to use.
911	* The device number is also found in pDevIns->iInstance, but since it's
912	* likely to be freqently used PDM passes it as parameter.
913	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
914	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
915	* iInstance it's expected to be used a bit in this function.
916	*/
917	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
918	{
919	PITState pData = PDMINS2DATA(pDevIns, PITState );
920	int rc;
921	uint8_t u8Irq;
922	uint16_t u16Base;
923	bool fSpeaker;
924	bool fGCEnabled;
925	bool fR0Enabled;
926	unsigned i;
927	Assert(iInstance == 0);
928
929	/*
930	* Validate configuration.
931	*/
932	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0Speaker\0GCEnabled\0R0Enabled"))
933	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
934
935	/*
936	* Init the data.
937	*/
938	rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
939	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
940	u8Irq = 0;
941	else if (VBOX_FAILURE(rc))
942	return PDMDEV_SET_ERROR(pDevIns, rc,
943	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
944
945	rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
946	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
947	u16Base = 0x40;
948	else if (VBOX_FAILURE(rc))
949	return PDMDEV_SET_ERROR(pDevIns, rc,
950	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
951
952	rc = CFGMR3QueryBool(pCfgHandle, "SpeakerEnabled", &fSpeaker);
953	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
954	fSpeaker = true;
955	else if (VBOX_FAILURE(rc))
956	return PDMDEV_SET_ERROR(pDevIns, rc,
957	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
958
959	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
960	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
961	fGCEnabled = true;
962	else if (VBOX_FAILURE(rc))
963	return PDMDEV_SET_ERROR(pDevIns, rc,
964	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
965
966	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
967	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
968	fR0Enabled = true;
969	else if (VBOX_FAILURE(rc))
970	return PDMDEV_SET_ERROR(pDevIns, rc,
971	N_("Configuration error: failed to read R0Enabled as boolean"));
972
973	pData->pDevIns = pDevIns;
974	pData->channels[0].irq = u8Irq;
975	for (i = 0; i < ELEMENTS(pData->channels); i++)
976	{
977	pData->channels[i].pPitHC = pData;
978	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
979	}
980
981	/*
982	* Create timer, register I/O Ports and save state.
983	*/
984	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pitTimer, "i8254 Programmable Interval Timer",
985	&pData->channels[0].CTXSUFF(pTimer));
986	if (VBOX_FAILURE(rc))
987	{
988	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
989	return rc;
990	}
991
992	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
993	if (VBOX_FAILURE(rc))
994	return rc;
995	if (fGCEnabled)
996	{
997	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
998	if (VBOX_FAILURE(rc))
999	return rc;
1000	}
1001	if (fR0Enabled)
1002	{
1003	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1004	if (VBOX_FAILURE(rc))
1005	return rc;
1006	}
1007
1008	if (fSpeaker)
1009	{
1010	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1011	if (VBOX_FAILURE(rc))
1012	return rc;
1013	if (fGCEnabled)
1014	{
1015	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1016	if (VBOX_FAILURE(rc))
1017	return rc;
1018	}
1019	}
1020
1021	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pData),
1022	NULL, pitSaveExec, NULL,
1023	NULL, pitLoadExec, NULL);
1024	if (VBOX_FAILURE(rc))
1025	return rc;
1026
1027	/*
1028	* Calculate max catchup time.
1029	*/
1030	pData->channels[0].i64MaxCatchupTS = pData->channels[1].i64MaxCatchupTS
1031	= pData->channels[2].i64MaxCatchupTS = -TMTimerFromMilli(pData->channels[0].CTXSUFF(pTimer), 1000602); /* 2 min */
1032
1033	/*
1034	* Initialize the device state.
1035	*/
1036	pitReset(pDevIns);
1037
1038	/*
1039	* Register statistics and debug info.
1040	*/
1041	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1042	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1043	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITCatchup, STAMTYPE_COUNTER, "/TM/PIT/Catchup", STAMUNIT_OCCURENCES, "The number of times we lagged too far behind.");
1044	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITGiveup, STAMTYPE_COUNTER, "/TM/PIT/Giveup", STAMUNIT_OCCURENCES, "The number of times we lagged so far behind that we simply gave up.");
1045
1046	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1047
1048	return VINF_SUCCESS;
1049	}
1050
1051
1052	/**
1053	* The device registration structure.
1054	*/
1055	const PDMDEVREG g_DeviceI8254 =
1056	{
1057	/* u32Version */
1058	PDM_DEVREG_VERSION,
1059	/* szDeviceName */
1060	"i8254",
1061	/* szGCMod */
1062	"VBoxDDGC.gc",
1063	/* szR0Mod */
1064	"VBoxDDR0.r0",
1065	/* pszDescription */
1066	"i8254 Programmable Interval Timer And Dummy Speaker",
1067	/* fFlags */
1068	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1069	/* fClass */
1070	PDM_DEVREG_CLASS_PIT,
1071	/* cMaxInstances */
1072	1,
1073	/* cbInstance */
1074	sizeof(PITState),
1075	/* pfnConstruct */
1076	pitConstruct,
1077	/* pfnDestruct */
1078	NULL,
1079	/* pfnRelocate */
1080	pitRelocate,
1081	/* pfnIOCtl */
1082	NULL,
1083	/* pfnPowerOn */
1084	NULL,
1085	/* pfnReset */
1086	pitReset,
1087	/* pfnSuspend */
1088	NULL,
1089	/* pfnResume */
1090	NULL,
1091	/* pfnAttach */
1092	NULL,
1093	/* pfnDetach */
1094	NULL,
1095	/* pfnQueryInterface. */
1096	NULL
1097	};
1098
1099	#endif /* IN_RING3 */
1100	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1101

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 566

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