DevPit-i8254.cpp@ 7888

Last change on this file since 7888 was 6320, checked in by vboxsync, 17 years ago
Corrected log message, added assertion.
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1	/** $Id: DevPit-i8254.cpp 6320 2008-01-10 10:20:02Z vboxsync $ */
2	/** @file
3	* Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*******************************************************************************
45	* Header Files *
46	*******************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PIT
48	#include <VBox/pdmdev.h>
49	#include <VBox/log.h>
50	#include <VBox/stam.h>
51	#include <iprt/assert.h>
52	#include <iprt/asm.h>
53
54	#include "Builtins.h"
55
56	/*******************************************************************************
57	* Defined Constants And Macros *
58	*******************************************************************************/
59	/** The PIT frequency. */
60	#define PIT_FREQ 1193182
61
62	#define RW_STATE_LSB 1
63	#define RW_STATE_MSB 2
64	#define RW_STATE_WORD0 3
65	#define RW_STATE_WORD1 4
66
67	/** The version of the saved state. */
68	#define PIT_SAVED_STATE_VERSION 2
69
70	/** @def FAKE_REFRESH_CLOCK
71	* Define this to flip the 15usec refresh bit on every read.
72	* If not defined, it will be flipped correctly. */
73	//#define FAKE_REFRESH_CLOCK
74
75	/*******************************************************************************
76	* Structures and Typedefs *
77	*******************************************************************************/
78	typedef struct PITChannelState
79	{
80	/** Pointer to the instance data - HCPtr. */
81	R3R0PTRTYPE(struct PITState *) pPitHC;
82	/** The timer - HCPtr. */
83	R3R0PTRTYPE(PTMTIMER) pTimerHC;
84	/** Pointer to the instance data - GCPtr. */
85	GCPTRTYPE(struct PITState *) pPitGC;
86	/** The timer - HCPtr. */
87	PTMTIMERGC pTimerGC;
88	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
89	uint64_t u64ReloadTS;
90	/** The actual time of the next tick.
91	* As apposed to the next_transition_time which contains the correct time of the next tick. */
92	uint64_t u64NextTS;
93
94	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
95	uint64_t count_load_time;
96	/* irq handling */
97	int64_t next_transition_time;
98	int32_t irq;
99	/** Number of release log entries. Used to prevent floading. */
100	uint32_t cRelLogEntries;
101
102	uint32_t count; /* can be 65536 */
103	uint16_t latched_count;
104	uint8_t count_latched;
105	uint8_t status_latched;
106
107	uint8_t status;
108	uint8_t read_state;
109	uint8_t write_state;
110	uint8_t write_latch;
111
112	uint8_t rw_mode;
113	uint8_t mode;
114	uint8_t bcd; /* not supported */
115	uint8_t gate; /* timer start */
116
117	} PITChannelState;
118
119	typedef struct PITState
120	{
121	PITChannelState channels[3];
122	/** Speaker data. */
123	int32_t speaker_data_on;
124	#ifdef FAKE_REFRESH_CLOCK
125	/** Speaker dummy. */
126	int32_t dummy_refresh_clock;
127	#else
128	uint32_t Alignment1;
129	#endif
130	/** Pointer to the device instance. */
131	R3PTRTYPE(PPDMDEVINS) pDevIns;
132	#if HC_ARCH_BITS == 32
133	uint32_t Alignment0;
134	#endif
135	/** Number of IRQs that's been raised. */
136	STAMCOUNTER StatPITIrq;
137	/** Profiling the timer callback handler. */
138	STAMPROFILEADV StatPITHandler;
139	} PITState;
140
141
142	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
143	/*******************************************************************************
144	* Internal Functions *
145	*******************************************************************************/
146	__BEGIN_DECLS
147	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
148	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
149	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
150	#ifdef IN_RING3
151	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
152	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
153	#endif
154	__END_DECLS
155
156
157
158
159	static int pit_get_count(PITChannelState *s)
160	{
161	uint64_t d;
162	int counter;
163	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
164
165	if (s->mode == 2) /** @todo Implement proper virtual time and get rid of this hack.. */
166	{
167	#if 0
168	d = TMTimerGet(pTimer);
169	d -= s->u64ReloadTS;
170	d = ASMMultU64ByU32DivByU32(d, PIT_FREQ, TMTimerGetFreq(pTimer));
171	#else /* variable time because of catch up */
172	if (s->u64NextTS == UINT64_MAX)
173	return 1; /** @todo check this value. */
174	d = TMTimerGet(pTimer);
175	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
176	#endif
177	if (d >= s->count)
178	return 1;
179	return s->count - d;
180	}
181	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
182	switch(s->mode) {
183	case 0:
184	case 1:
185	case 4:
186	case 5:
187	counter = (s->count - d) & 0xffff;
188	break;
189	case 3:
190	/* XXX: may be incorrect for odd counts */
191	counter = s->count - ((2 * d) % s->count);
192	break;
193	default:
194	counter = s->count - (d % s->count);
195	break;
196	}
197	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
198	return counter;
199	}
200
201	/* get pit output bit */
202	static int pit_get_out1(PITChannelState *s, int64_t current_time)
203	{
204	uint64_t d;
205	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
206	int out;
207
208	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
209	switch(s->mode) {
210	default:
211	case 0:
212	out = (d >= s->count);
213	break;
214	case 1:
215	out = (d < s->count);
216	break;
217	case 2:
218	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
219	if ((d % s->count) == 0 && d != 0)
220	out = 1;
221	else
222	out = 0;
223	break;
224	case 3:
225	out = (d % s->count) < ((s->count + 1) >> 1);
226	break;
227	case 4:
228	case 5:
229	out = (d == s->count);
230	break;
231	}
232	return out;
233	}
234
235
236	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
237	{
238	PITChannelState *s = &pit->channels[channel];
239	return pit_get_out1(s, current_time);
240	}
241
242
243	static int pit_get_gate(PITState *pit, int channel)
244	{
245	PITChannelState *s = &pit->channels[channel];
246	return s->gate;
247	}
248
249
250	/* if already latched, do not latch again */
251	static void pit_latch_count(PITChannelState *s)
252	{
253	if (!s->count_latched) {
254	s->latched_count = pit_get_count(s);
255	s->count_latched = s->rw_mode;
256	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
257	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
258	}
259	}
260
261	#ifdef IN_RING3
262
263	/* val must be 0 or 1 */
264	static void pit_set_gate(PITState *pit, int channel, int val)
265	{
266	PITChannelState *s = &pit->channels[channel];
267	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
268	Assert((val & 1) == val);
269
270	switch(s->mode) {
271	default:
272	case 0:
273	case 4:
274	/* XXX: just disable/enable counting */
275	break;
276	case 1:
277	case 5:
278	if (s->gate < val) {
279	/* restart counting on rising edge */
280	s->count_load_time = TMTimerGet(pTimer);
281	pit_irq_timer_update(s, s->count_load_time);
282	}
283	break;
284	case 2:
285	case 3:
286	if (s->gate < val) {
287	/* restart counting on rising edge */
288	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
289	pit_irq_timer_update(s, s->count_load_time);
290	}
291	/* XXX: disable/enable counting */
292	break;
293	}
294	s->gate = val;
295	}
296
297	static inline void pit_load_count(PITChannelState *s, int val)
298	{
299	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
300	if (val == 0)
301	val = 0x10000;
302	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
303	s->count = val;
304	pit_irq_timer_update(s, s->count_load_time);
305
306	/* log the new rate (ch 0 only). */
307	if ( s->pTimerHC /* ch 0 */
308	&& s->cRelLogEntries++ < 32)
309	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
310	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
311	}
312
313	/* return -1 if no transition will occur. */
314	static int64_t pit_get_next_transition_time(PITChannelState *s,
315	uint64_t current_time)
316	{
317	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
318	uint64_t d, next_time, base;
319	uint32_t period2;
320
321	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
322	switch(s->mode) {
323	default:
324	case 0:
325	case 1:
326	if (d < s->count)
327	next_time = s->count;
328	else
329	return -1;
330	break;
331	/*
332	* Mode 2: The period is count + 1 PIT ticks.
333	* When the counter reaches 1 we sent the output low (for channel 0 that
334	* means raise an irq). On the next tick, where we should be decrementing
335	* from 1 to 0, the count is loaded and the output goes high (channel 0
336	* means clearing the irq).
337	*
338	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
339	* the irq. We also don't set it until we reach 0, which is a tick late - will
340	* try fix that later some day.
341	*/
342	case 2:
343	base = (d / s->count) * s->count;
344	#ifndef VBOX /* see above */
345	if ((d - base) == 0 && d != 0)
346	next_time = base + s->count;
347	else
348	#endif
349	next_time = base + s->count + 1;
350	break;
351	case 3:
352	base = (d / s->count) * s->count;
353	period2 = ((s->count + 1) >> 1);
354	if ((d - base) < period2)
355	next_time = base + period2;
356	else
357	next_time = base + s->count;
358	break;
359	case 4:
360	case 5:
361	if (d < s->count)
362	next_time = s->count;
363	else if (d == s->count)
364	next_time = s->count + 1;
365	else
366	return -1;
367	break;
368	}
369	/* convert to timer units */
370	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
371	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
372	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
373	/* fix potential rounding problems */
374	/* XXX: better solution: use a clock at PIT_FREQ Hz */
375	if (next_time <= current_time)
376	next_time = current_time + 1;
377	return next_time;
378	}
379
380	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
381	{
382	uint64_t now;
383	int64_t expire_time;
384	int irq_level;
385	PPDMDEVINS pDevIns;
386	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
387
388	if (!s->CTXSUFF(pTimer))
389	return;
390	expire_time = pit_get_next_transition_time(s, current_time);
391	irq_level = pit_get_out1(s, current_time);
392
393	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
394	pDevIns = s->CTXSUFF(pPit)->pDevIns;
395	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
396	if (irq_level)
397	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
398	now = TMTimerGet(pTimer);
399	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
400	if (irq_level)
401	{
402	s->u64ReloadTS = now;
403	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITIrq);
404	}
405
406	if (expire_time != -1)
407	{
408	s->u64NextTS = expire_time;
409	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
410	}
411	else
412	{
413	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
414	TMTimerStop(s->CTXSUFF(pTimer));
415	s->u64NextTS = UINT64_MAX;
416	}
417	s->next_transition_time = expire_time;
418	}
419
420	#endif /* IN_RING3 */
421
422
423	/**
424	* Port I/O Handler for IN operations.
425	*
426	* @returns VBox status code.
427	*
428	* @param pDevIns The device instance.
429	* @param pvUser User argument - ignored.
430	* @param Port Port number used for the IN operation.
431	* @param pu32 Where to store the result.
432	* @param cb Number of bytes read.
433	*/
434	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
435	{
436	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
437	NOREF(pvUser);
438	Port &= 3;
439	if (cb != 1 \|\| Port == 3)
440	{
441	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
442	return VERR_IOM_IOPORT_UNUSED;
443	}
444
445	PITState pit = PDMINS2DATA(pDevIns, PITState );
446	int ret;
447	PITChannelState *s = &pit->channels[Port];
448	if (s->status_latched)
449	{
450	s->status_latched = 0;
451	ret = s->status;
452	}
453	else if (s->count_latched)
454	{
455	switch (s->count_latched)
456	{
457	default:
458	case RW_STATE_LSB:
459	ret = s->latched_count & 0xff;
460	s->count_latched = 0;
461	break;
462	case RW_STATE_MSB:
463	ret = s->latched_count >> 8;
464	s->count_latched = 0;
465	break;
466	case RW_STATE_WORD0:
467	ret = s->latched_count & 0xff;
468	s->count_latched = RW_STATE_MSB;
469	break;
470	}
471	}
472	else
473	{
474	int count;
475	switch (s->read_state)
476	{
477	default:
478	case RW_STATE_LSB:
479	count = pit_get_count(s);
480	ret = count & 0xff;
481	break;
482	case RW_STATE_MSB:
483	count = pit_get_count(s);
484	ret = (count >> 8) & 0xff;
485	break;
486	case RW_STATE_WORD0:
487	count = pit_get_count(s);
488	ret = count & 0xff;
489	s->read_state = RW_STATE_WORD1;
490	break;
491	case RW_STATE_WORD1:
492	count = pit_get_count(s);
493	ret = (count >> 8) & 0xff;
494	s->read_state = RW_STATE_WORD0;
495	break;
496	}
497	}
498
499	*pu32 = ret;
500	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
501	return VINF_SUCCESS;
502	}
503
504
505	/**
506	* Port I/O Handler for OUT operations.
507	*
508	* @returns VBox status code.
509	*
510	* @param pDevIns The device instance.
511	* @param pvUser User argument - ignored.
512	* @param Port Port number used for the IN operation.
513	* @param u32 The value to output.
514	* @param cb The value size in bytes.
515	*/
516	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
517	{
518	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
519	NOREF(pvUser);
520	if (cb != 1)
521	return VINF_SUCCESS;
522
523	PITState pit = PDMINS2DATA(pDevIns, PITState );
524	Port &= 3;
525	if (Port == 3)
526	{
527	/*
528	* Port 43h - Mode/Command Register.
529	* 7 6 5 4 3 2 1 0
530	* * * . . . . . . Select channel: 0 0 = Channel 0
531	* 0 1 = Channel 1
532	* 1 0 = Channel 2
533	* 1 1 = Read-back command (8254 only)
534	* (Illegal on 8253)
535	* (Illegal on PS/2 {JAM})
536	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
537	* 0 1 = Access mode: lobyte only
538	* 1 0 = Access mode: hibyte only
539	* 1 1 = Access mode: lobyte/hibyte
540	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
541	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
542	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
543	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
544	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
545	*/
546	unsigned channel = u32 >> 6;
547	if (channel == 3)
548	{
549	/* read-back command */
550	for (channel = 0; channel < ELEMENTS(pit->channels); channel++)
551	{
552	PITChannelState *s = &pit->channels[channel];
553	if (u32 & (2 << channel)) {
554	if (!(u32 & 0x20))
555	pit_latch_count(s);
556	if (!(u32 & 0x10) && !s->status_latched)
557	{
558	/* status latch */
559	/* XXX: add BCD and null count */
560	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
561	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
562	\| (s->rw_mode << 4)
563	\| (s->mode << 1)
564	\| s->bcd;
565	s->status_latched = 1;
566	}
567	}
568	}
569	}
570	else
571	{
572	PITChannelState *s = &pit->channels[channel];
573	unsigned access = (u32 >> 4) & 3;
574	if (access == 0)
575	pit_latch_count(s);
576	else
577	{
578	s->rw_mode = access;
579	s->read_state = access;
580	s->write_state = access;
581
582	s->mode = (u32 >> 1) & 7;
583	s->bcd = u32 & 1;
584	/* XXX: update irq timer ? */
585	}
586	}
587	}
588	else
589	{
590	#ifndef IN_RING3
591	return VINF_IOM_HC_IOPORT_WRITE;
592	#else /* IN_RING3 */
593	/*
594	* Port 40-42h - Channel Data Ports.
595	*/
596	PITChannelState *s = &pit->channels[Port];
597	switch(s->write_state)
598	{
599	default:
600	case RW_STATE_LSB:
601	pit_load_count(s, u32);
602	break;
603	case RW_STATE_MSB:
604	pit_load_count(s, u32 << 8);
605	break;
606	case RW_STATE_WORD0:
607	s->write_latch = u32;
608	s->write_state = RW_STATE_WORD1;
609	break;
610	case RW_STATE_WORD1:
611	pit_load_count(s, s->write_latch \| (u32 << 8));
612	s->write_state = RW_STATE_WORD0;
613	break;
614	}
615	#endif /* !IN_RING3 */
616	}
617	return VINF_SUCCESS;
618	}
619
620
621	/**
622	* Port I/O Handler for speaker IN operations.
623	*
624	* @returns VBox status code.
625	*
626	* @param pDevIns The device instance.
627	* @param pvUser User argument - ignored.
628	* @param Port Port number used for the IN operation.
629	* @param pu32 Where to store the result.
630	* @param cb Number of bytes read.
631	*/
632	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
633	{
634	NOREF(pvUser);
635	if (cb == 1)
636	{
637	PITState pData = PDMINS2DATA(pDevIns, PITState );
638	const uint64_t u64Now = TMTimerGet(pData->channels[0].CTXSUFF(pTimer));
639	Assert(TMTimerGetFreq(pData->channels[0].CTXSUFF(pTimer)) == 1000000000); /* lazy bird. */
640
641	/* bit 6,7 Parity error stuff. */
642	/* bit 5 - mirrors timer 2 output condition. */
643	const int fOut = pit_get_out(pData, 2, u64Now);
644	/* bit 4 - toggled every with each (DRAM?) refresh request, every 15.085 µs. */
645	#ifdef FAKE_REFRESH_CLOCK
646	pData->dummy_refresh_clock ^= 1;
647	const int fRefresh = pData->dummy_refresh_clock;
648	#else
649	const int fRefresh = (u64Now / 15085) & 1;
650	#endif
651	/* bit 2,3 NMI / parity status stuff. */
652	/* bit 1 - speaker data status */
653	const int fSpeakerStatus = pData->speaker_data_on;
654	/* bit 0 - timer 2 clock gate to speaker status. */
655	const int fTimer2GateStatus = pit_get_gate(pData, 2);
656
657	*pu32 = fTimer2GateStatus
658	\| (fSpeakerStatus << 1)
659	\| (fRefresh << 4)
660	\| (fOut << 5);
661	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
662	return VINF_SUCCESS;
663	}
664	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
665	return VERR_IOM_IOPORT_UNUSED;
666	}
667
668	#ifdef IN_RING3
669
670	/**
671	* Port I/O Handler for speaker OUT operations.
672	*
673	* @returns VBox status code.
674	*
675	* @param pDevIns The device instance.
676	* @param pvUser User argument - ignored.
677	* @param Port Port number used for the IN operation.
678	* @param u32 The value to output.
679	* @param cb The value size in bytes.
680	*/
681	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
682	{
683	NOREF(pvUser);
684	if (cb == 1)
685	{
686	PITState pData = PDMINS2DATA(pDevIns, PITState );
687	pData->speaker_data_on = (u32 >> 1) & 1;
688	pit_set_gate(pData, 2, u32 & 1);
689	}
690	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
691	return VINF_SUCCESS;
692	}
693
694
695	/**
696	* Saves a state of the programmable interval timer device.
697	*
698	* @returns VBox status code.
699	* @param pDevIns The device instance.
700	* @param pSSMHandle The handle to save the state to.
701	*/
702	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
703	{
704	PITState pData = PDMINS2DATA(pDevIns, PITState );
705	unsigned i;
706
707	for (i = 0; i < ELEMENTS(pData->channels); i++)
708	{
709	PITChannelState *s = &pData->channels[i];
710	SSMR3PutU32(pSSMHandle, s->count);
711	SSMR3PutU16(pSSMHandle, s->latched_count);
712	SSMR3PutU8(pSSMHandle, s->count_latched);
713	SSMR3PutU8(pSSMHandle, s->status_latched);
714	SSMR3PutU8(pSSMHandle, s->status);
715	SSMR3PutU8(pSSMHandle, s->read_state);
716	SSMR3PutU8(pSSMHandle, s->write_state);
717	SSMR3PutU8(pSSMHandle, s->write_latch);
718	SSMR3PutU8(pSSMHandle, s->rw_mode);
719	SSMR3PutU8(pSSMHandle, s->mode);
720	SSMR3PutU8(pSSMHandle, s->bcd);
721	SSMR3PutU8(pSSMHandle, s->gate);
722	SSMR3PutU64(pSSMHandle, s->count_load_time);
723	SSMR3PutU64(pSSMHandle, s->u64NextTS);
724	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
725	SSMR3PutS64(pSSMHandle, s->next_transition_time);
726	if (s->CTXSUFF(pTimer))
727	TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
728	}
729
730	SSMR3PutS32(pSSMHandle, pData->speaker_data_on);
731	#ifdef FAKE_REFRESH_CLOCK
732	return SSMR3PutS32(pSSMHandle, pData->dummy_refresh_clock);
733	#else
734	return SSMR3PutS32(pSSMHandle, 0);
735	#endif
736	}
737
738
739	/**
740	* Loads a saved programmable interval timer device state.
741	*
742	* @returns VBox status code.
743	* @param pDevIns The device instance.
744	* @param pSSMHandle The handle to the saved state.
745	* @param u32Version The data unit version number.
746	*/
747	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
748	{
749	PITState pData = PDMINS2DATA(pDevIns, PITState );
750	unsigned i;
751
752	if (u32Version != PIT_SAVED_STATE_VERSION)
753	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
754
755	for (i = 0; i < ELEMENTS(pData->channels); i++)
756	{
757	PITChannelState *s = &pData->channels[i];
758	SSMR3GetU32(pSSMHandle, &s->count);
759	SSMR3GetU16(pSSMHandle, &s->latched_count);
760	SSMR3GetU8(pSSMHandle, &s->count_latched);
761	SSMR3GetU8(pSSMHandle, &s->status_latched);
762	SSMR3GetU8(pSSMHandle, &s->status);
763	SSMR3GetU8(pSSMHandle, &s->read_state);
764	SSMR3GetU8(pSSMHandle, &s->write_state);
765	SSMR3GetU8(pSSMHandle, &s->write_latch);
766	SSMR3GetU8(pSSMHandle, &s->rw_mode);
767	SSMR3GetU8(pSSMHandle, &s->mode);
768	SSMR3GetU8(pSSMHandle, &s->bcd);
769	SSMR3GetU8(pSSMHandle, &s->gate);
770	SSMR3GetU64(pSSMHandle, &s->count_load_time);
771	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
772	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
773	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
774	if (s->CTXSUFF(pTimer))
775	{
776	TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
777	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
778	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
779	}
780	pData->channels[0].cRelLogEntries = 0;
781	}
782
783	SSMR3GetS32(pSSMHandle, &pData->speaker_data_on);
784	#ifdef FAKE_REFRESH_CLOCK
785	return SSMR3GetS32(pSSMHandle, &pData->dummy_refresh_clock);
786	#else
787	int32_t u32Dummy;
788	return SSMR3GetS32(pSSMHandle, &u32Dummy);
789	#endif
790	}
791
792
793	/**
794	* Device timer callback function.
795	*
796	* @param pDevIns Device instance of the device which registered the timer.
797	* @param pTimer The timer handle.
798	*/
799	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
800	{
801	PITState pData = PDMINS2DATA(pDevIns, PITState );
802	PITChannelState *s = &pData->channels[0];
803	STAM_PROFILE_ADV_START(&s->CTXSUFF(pPit)->StatPITHandler, a);
804	pit_irq_timer_update(s, s->next_transition_time);
805	STAM_PROFILE_ADV_STOP(&s->CTXSUFF(pPit)->StatPITHandler, a);
806	}
807
808
809	/**
810	* Relocation notification.
811	*
812	* @returns VBox status.
813	* @param pDevIns The device instance data.
814	* @param offDelta The delta relative to the old address.
815	*/
816	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
817	{
818	PITState pData = PDMINS2DATA(pDevIns, PITState );
819	unsigned i;
820	LogFlow(("pitRelocate: \n"));
821
822	for (i = 0; i < ELEMENTS(pData->channels); i++)
823	{
824	PITChannelState *pCh = &pData->channels[i];
825	if (pCh->pTimerHC)
826	pCh->pTimerGC = TMTimerGCPtr(pCh->pTimerHC);
827	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
828	}
829	}
830
831	/** @todo remove this! */
832	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
833
834	/**
835	* Reset notification.
836	*
837	* @returns VBox status.
838	* @param pDevIns The device instance data.
839	*/
840	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
841	{
842	PITState pData = PDMINS2DATA(pDevIns, PITState );
843	unsigned i;
844	LogFlow(("pitReset: \n"));
845
846	for (i = 0; i < ELEMENTS(pData->channels); i++)
847	{
848	PITChannelState *s = &pData->channels[i];
849
850	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
851	s->latched_count = 0;
852	s->count_latched = 0;
853	s->status_latched = 0;
854	s->status = 0;
855	s->read_state = 0;
856	s->write_state = 0;
857	s->write_latch = 0;
858	s->rw_mode = 0;
859	s->bcd = 0;
860	#endif
861	s->cRelLogEntries = 0;
862	s->mode = 3;
863	s->gate = (i != 2);
864	pit_load_count(s, 0);
865	}
866	}
867
868
869	/**
870	* Info handler, device version.
871	*
872	* @param pDevIns Device instance which registered the info.
873	* @param pHlp Callback functions for doing output.
874	* @param pszArgs Argument string. Optional and specific to the handler.
875	*/
876	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
877	{
878	PITState pData = PDMINS2DATA(pDevIns, PITState );
879	unsigned i;
880	for (i = 0; i < ELEMENTS(pData->channels); i++)
881	{
882	const PITChannelState *pCh = &pData->channels[i];
883
884	pHlp->pfnPrintf(pHlp,
885	"PIT (i8254) channel %d status: irq=%#x\n"
886	" count=%08x" " latched_count=%04x count_latched=%02x\n"
887	" status=%02x status_latched=%02x read_state=%02x\n"
888	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
889	" mode=%02x bcd=%02x gate=%02x\n"
890	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
891	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
892	,
893	i, pCh->irq,
894	pCh->count, pCh->latched_count, pCh->count_latched,
895	pCh->status, pCh->status_latched, pCh->read_state,
896	pCh->write_state, pCh->write_latch, pCh->rw_mode,
897	pCh->mode, pCh->bcd, pCh->gate,
898	pCh->count_load_time, pCh->next_transition_time,
899	pCh->u64ReloadTS, pCh->u64NextTS);
900	}
901	#ifdef FAKE_REFRESH_CLOCK
902	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
903	pData->speaker_data_on, pData->dummy_refresh_clock);
904	#else
905	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pData->speaker_data_on);
906	#endif
907	}
908
909
910	/**
911	* Construct a device instance for a VM.
912	*
913	* @returns VBox status.
914	* @param pDevIns The device instance data.
915	* If the registration structure is needed, pDevIns->pDevReg points to it.
916	* @param iInstance Instance number. Use this to figure out which registers and such to use.
917	* The device number is also found in pDevIns->iInstance, but since it's
918	* likely to be freqently used PDM passes it as parameter.
919	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
920	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
921	* iInstance it's expected to be used a bit in this function.
922	*/
923	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
924	{
925	PITState pData = PDMINS2DATA(pDevIns, PITState );
926	int rc;
927	uint8_t u8Irq;
928	uint16_t u16Base;
929	bool fSpeaker;
930	bool fGCEnabled;
931	bool fR0Enabled;
932	unsigned i;
933	Assert(iInstance == 0);
934
935	/*
936	* Validate configuration.
937	*/
938	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0Speaker\0GCEnabled\0R0Enabled\0"))
939	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
940
941	/*
942	* Init the data.
943	*/
944	rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
945	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
946	u8Irq = 0;
947	else if (VBOX_FAILURE(rc))
948	return PDMDEV_SET_ERROR(pDevIns, rc,
949	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
950
951	rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
952	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
953	u16Base = 0x40;
954	else if (VBOX_FAILURE(rc))
955	return PDMDEV_SET_ERROR(pDevIns, rc,
956	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
957
958	rc = CFGMR3QueryBool(pCfgHandle, "SpeakerEnabled", &fSpeaker);
959	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
960	fSpeaker = true;
961	else if (VBOX_FAILURE(rc))
962	return PDMDEV_SET_ERROR(pDevIns, rc,
963	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
964
965	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
966	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
967	fGCEnabled = true;
968	else if (VBOX_FAILURE(rc))
969	return PDMDEV_SET_ERROR(pDevIns, rc,
970	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
971
972	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
973	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
974	fR0Enabled = true;
975	else if (VBOX_FAILURE(rc))
976	return PDMDEV_SET_ERROR(pDevIns, rc,
977	N_("Configuration error: failed to read R0Enabled as boolean"));
978
979	pData->pDevIns = pDevIns;
980	pData->channels[0].irq = u8Irq;
981	for (i = 0; i < ELEMENTS(pData->channels); i++)
982	{
983	pData->channels[i].pPitHC = pData;
984	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
985	}
986
987	/*
988	* Create timer, register I/O Ports and save state.
989	*/
990	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, "i8254 Programmable Interval Timer",
991	&pData->channels[0].CTXSUFF(pTimer));
992	if (VBOX_FAILURE(rc))
993	{
994	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
995	return rc;
996	}
997
998	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
999	if (VBOX_FAILURE(rc))
1000	return rc;
1001	if (fGCEnabled)
1002	{
1003	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1004	if (VBOX_FAILURE(rc))
1005	return rc;
1006	}
1007	if (fR0Enabled)
1008	{
1009	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1010	if (VBOX_FAILURE(rc))
1011	return rc;
1012	}
1013
1014	if (fSpeaker)
1015	{
1016	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1017	if (VBOX_FAILURE(rc))
1018	return rc;
1019	if (fGCEnabled)
1020	{
1021	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1022	if (VBOX_FAILURE(rc))
1023	return rc;
1024	}
1025	}
1026
1027	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pData),
1028	NULL, pitSaveExec, NULL,
1029	NULL, pitLoadExec, NULL);
1030	if (VBOX_FAILURE(rc))
1031	return rc;
1032
1033	/*
1034	* Initialize the device state.
1035	*/
1036	pitReset(pDevIns);
1037
1038	/*
1039	* Register statistics and debug info.
1040	*/
1041	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1042	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1043
1044	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1045
1046	return VINF_SUCCESS;
1047	}
1048
1049
1050	/**
1051	* The device registration structure.
1052	*/
1053	const PDMDEVREG g_DeviceI8254 =
1054	{
1055	/* u32Version */
1056	PDM_DEVREG_VERSION,
1057	/* szDeviceName */
1058	"i8254",
1059	/* szGCMod */
1060	"VBoxDDGC.gc",
1061	/* szR0Mod */
1062	"VBoxDDR0.r0",
1063	/* pszDescription */
1064	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1065	/* fFlags */
1066	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1067	/* fClass */
1068	PDM_DEVREG_CLASS_PIT,
1069	/* cMaxInstances */
1070	1,
1071	/* cbInstance */
1072	sizeof(PITState),
1073	/* pfnConstruct */
1074	pitConstruct,
1075	/* pfnDestruct */
1076	NULL,
1077	/* pfnRelocate */
1078	pitRelocate,
1079	/* pfnIOCtl */
1080	NULL,
1081	/* pfnPowerOn */
1082	NULL,
1083	/* pfnReset */
1084	pitReset,
1085	/* pfnSuspend */
1086	NULL,
1087	/* pfnResume */
1088	NULL,
1089	/* pfnAttach */
1090	NULL,
1091	/* pfnDetach */
1092	NULL,
1093	/* pfnQueryInterface. */
1094	NULL
1095	};
1096
1097	#endif /* IN_RING3 */
1098	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1099

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 7888

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