VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevRTC.cpp@ 56284

Last change on this file since 56284 was 56284, checked in by vboxsync, 9 years ago

s/VMMGC.gc/VMMRC.rc/g s/VBoxDDGC.gc/VBoxDDRC.rc/g s/VBoxDD2GC.gc/VBoxDD2RC.rc/g
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1/* $Id: DevRTC.cpp 56284 2015-06-09 10:46:34Z vboxsync $ */
2/** @file
3 * Motorola MC146818 RTC/CMOS Device with PIIX4 extensions.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is based on:
19 *
20 * QEMU MC146818 RTC emulation
21 *
22 * Copyright (c) 2003-2004 Fabrice Bellard
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 */
42
43/*******************************************************************************
44* Header Files *
45*******************************************************************************/
46#define LOG_GROUP LOG_GROUP_DEV_RTC
47#include <VBox/vmm/pdmdev.h>
48#include <VBox/log.h>
49#include <iprt/asm-math.h>
50#include <iprt/assert.h>
51#include <iprt/string.h>
52
53#ifdef IN_RING3
54# include <iprt/alloc.h>
55# include <iprt/uuid.h>
56#endif /* IN_RING3 */
57
58#include "VBoxDD.h"
59
60
61/*******************************************************************************
62* Defined Constants And Macros *
63*******************************************************************************/
64/*#define DEBUG_CMOS*/
65#define RTC_CRC_START 0x10
66#define RTC_CRC_LAST 0x2d
67#define RTC_CRC_HIGH 0x2e
68#define RTC_CRC_LOW 0x2f
69
70#define RTC_SECONDS 0
71#define RTC_SECONDS_ALARM 1
72#define RTC_MINUTES 2
73#define RTC_MINUTES_ALARM 3
74#define RTC_HOURS 4
75#define RTC_HOURS_ALARM 5
76#define RTC_ALARM_DONT_CARE 0xC0
77
78#define RTC_DAY_OF_WEEK 6
79#define RTC_DAY_OF_MONTH 7
80#define RTC_MONTH 8
81#define RTC_YEAR 9
82
83#define RTC_REG_A 10
84#define RTC_REG_B 11
85#define RTC_REG_C 12
86#define RTC_REG_D 13
87
88#define REG_A_UIP 0x80
89
90#define REG_B_SET 0x80
91#define REG_B_PIE 0x40
92#define REG_B_AIE 0x20
93#define REG_B_UIE 0x10
94
95#define CMOS_BANK_LOWER_LIMIT 0x0E
96#define CMOS_BANK_UPPER_LIMIT 0x7F
97#define CMOS_BANK2_LOWER_LIMIT 0x80
98#define CMOS_BANK2_UPPER_LIMIT 0xFF
99#define CMOS_BANK_SIZE 0x80
100
101/** The saved state version. */
102#define RTC_SAVED_STATE_VERSION 4
103/** The saved state version used by VirtualBox pre-3.2.
104 * This does not include the second 128-byte bank. */
105#define RTC_SAVED_STATE_VERSION_VBOX_32PRE 3
106/** The saved state version used by VirtualBox 3.1 and earlier.
107 * This does not include disabled by HPET state. */
108#define RTC_SAVED_STATE_VERSION_VBOX_31 2
109/** The saved state version used by VirtualBox 3.0 and earlier.
110 * This does not include the configuration. */
111#define RTC_SAVED_STATE_VERSION_VBOX_30 1
112
113
114/*******************************************************************************
115* Structures and Typedefs *
116*******************************************************************************/
117/** @todo Replace struct my_tm with RTTIME. */
118struct my_tm
119{
120 int32_t tm_sec;
121 int32_t tm_min;
122 int32_t tm_hour;
123 int32_t tm_mday;
124 int32_t tm_mon;
125 int32_t tm_year;
126 int32_t tm_wday;
127 int32_t tm_yday;
128};
129
130
131typedef struct RTCSTATE
132{
133 uint8_t cmos_data[256];
134 uint8_t cmos_index[2];
135 uint8_t Alignment0[6];
136 struct my_tm current_tm;
137 /** The configured IRQ. */
138 int32_t irq;
139 /** The configured I/O port base. */
140 RTIOPORT IOPortBase;
141 /** Use UTC or local time initially. */
142 bool fUTC;
143 /** Disabled by HPET legacy mode. */
144 bool fDisabledByHpet;
145 /* periodic timer */
146 int64_t next_periodic_time;
147 /* second update */
148 int64_t next_second_time;
149
150 /** Pointer to the device instance - R3 Ptr. */
151 PPDMDEVINSR3 pDevInsR3;
152 /** The periodic timer (rtcTimerPeriodic) - R3 Ptr. */
153 PTMTIMERR3 pPeriodicTimerR3;
154 /** The second timer (rtcTimerSecond) - R3 Ptr. */
155 PTMTIMERR3 pSecondTimerR3;
156 /** The second second timer (rtcTimerSecond2) - R3 Ptr. */
157 PTMTIMERR3 pSecondTimer2R3;
158
159 /** Pointer to the device instance - R0 Ptr. */
160 PPDMDEVINSR0 pDevInsR0;
161 /** The periodic timer (rtcTimerPeriodic) - R0 Ptr. */
162 PTMTIMERR0 pPeriodicTimerR0;
163 /** The second timer (rtcTimerSecond) - R0 Ptr. */
164 PTMTIMERR0 pSecondTimerR0;
165 /** The second second timer (rtcTimerSecond2) - R0 Ptr. */
166 PTMTIMERR0 pSecondTimer2R0;
167
168 /** Pointer to the device instance - RC Ptr. */
169 PPDMDEVINSRC pDevInsRC;
170 /** The periodic timer (rtcTimerPeriodic) - RC Ptr. */
171 PTMTIMERRC pPeriodicTimerRC;
172 /** The second timer (rtcTimerSecond) - RC Ptr. */
173 PTMTIMERRC pSecondTimerRC;
174 /** The second second timer (rtcTimerSecond2) - RC Ptr. */
175 PTMTIMERRC pSecondTimer2RC;
176
177 /** The RTC registration structure. */
178 PDMRTCREG RtcReg;
179 /** The RTC device helpers. */
180 R3PTRTYPE(PCPDMRTCHLP) pRtcHlpR3;
181 /** Number of release log entries. Used to prevent flooding. */
182 uint32_t cRelLogEntries;
183 /** The current/previous logged timer period. */
184 int32_t CurLogPeriod;
185 /** The current/previous hinted timer period. */
186 int32_t CurHintPeriod;
187 /** How many consecutive times the UIP has been seen. */
188 int32_t cUipSeen;
189
190 /** HPET legacy mode notification interface. */
191 PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
192
193 /** Number of IRQs that's been raised. */
194 STAMCOUNTER StatRTCIrq;
195 /** Number of times the timer callback handler ran. */
196 STAMCOUNTER StatRTCTimerCB;
197} RTCSTATE;
198/** Pointer to the RTC device state. */
199typedef RTCSTATE *PRTCSTATE;
200
201#ifndef VBOX_DEVICE_STRUCT_TESTCASE
202
203static void rtc_timer_update(PRTCSTATE pThis, int64_t current_time)
204{
205 int period_code, period;
206 uint64_t cur_clock, next_irq_clock;
207 uint32_t freq;
208
209 Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPeriodicTimer)));
210 Assert(PDMCritSectIsOwner(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo)));
211
212 period_code = pThis->cmos_data[RTC_REG_A] & 0x0f;
213 if ( period_code != 0
214 && (pThis->cmos_data[RTC_REG_B] & REG_B_PIE))
215 {
216 if (period_code <= 2)
217 period_code += 7;
218 /* period in 32 kHz cycles */
219 period = 1 << (period_code - 1);
220 /* compute 32 kHz clock */
221 freq = TMTimerGetFreq(pThis->CTX_SUFF(pPeriodicTimer));
222
223 cur_clock = ASMMultU64ByU32DivByU32(current_time, 32768, freq);
224 next_irq_clock = (cur_clock & ~(uint64_t)(period - 1)) + period;
225 pThis->next_periodic_time = ASMMultU64ByU32DivByU32(next_irq_clock, freq, 32768) + 1;
226 TMTimerSet(pThis->CTX_SUFF(pPeriodicTimer), pThis->next_periodic_time);
227
228#ifdef IN_RING3
229 if (RT_UNLIKELY(period != pThis->CurLogPeriod))
230#else
231 if (RT_UNLIKELY(period != pThis->CurHintPeriod))
232#endif
233 {
234#ifdef IN_RING3
235 if (pThis->cRelLogEntries++ < 64)
236 LogRel(("RTC: period=%#x (%d) %u Hz\n", period, period, _32K / period));
237 pThis->CurLogPeriod = period;
238#endif
239 pThis->CurHintPeriod = period;
240 TMTimerSetFrequencyHint(pThis->CTX_SUFF(pPeriodicTimer), _32K / period);
241 }
242 }
243 else
244 {
245#ifdef IN_RING3
246 if (TMTimerIsActive(pThis->CTX_SUFF(pPeriodicTimer)) && pThis->cRelLogEntries++ < 64)
247 LogRel(("RTC: stopped the periodic timer\n"));
248#endif
249 TMTimerStop(pThis->CTX_SUFF(pPeriodicTimer));
250 }
251}
252
253
254static void rtc_raise_irq(PRTCSTATE pThis, uint32_t iLevel)
255{
256 if (!pThis->fDisabledByHpet)
257 {
258 PDMDevHlpISASetIrq(pThis->CTX_SUFF(pDevIns), pThis->irq, iLevel);
259 if (iLevel)
260 STAM_COUNTER_INC(&pThis->StatRTCIrq);
261 }
262}
263
264
265DECLINLINE(int) to_bcd(PRTCSTATE pThis, int a)
266{
267 if (pThis->cmos_data[RTC_REG_B] & 0x04)
268 return a;
269 return ((a / 10) << 4) | (a % 10);
270}
271
272
273DECLINLINE(int) from_bcd(PRTCSTATE pThis, int a)
274{
275 if (pThis->cmos_data[RTC_REG_B] & 0x04)
276 return a;
277 return ((a >> 4) * 10) + (a & 0x0f);
278}
279
280
281static void rtc_set_time(PRTCSTATE pThis)
282{
283 struct my_tm *tm = &pThis->current_tm;
284
285 tm->tm_sec = from_bcd(pThis, pThis->cmos_data[RTC_SECONDS]);
286 tm->tm_min = from_bcd(pThis, pThis->cmos_data[RTC_MINUTES]);
287 tm->tm_hour = from_bcd(pThis, pThis->cmos_data[RTC_HOURS] & 0x7f);
288 if (!(pThis->cmos_data[RTC_REG_B] & 0x02))
289 {
290 tm->tm_hour %= 12;
291 if (pThis->cmos_data[RTC_HOURS] & 0x80)
292 tm->tm_hour += 12;
293 }
294 tm->tm_wday = from_bcd(pThis, pThis->cmos_data[RTC_DAY_OF_WEEK]);
295 tm->tm_mday = from_bcd(pThis, pThis->cmos_data[RTC_DAY_OF_MONTH]);
296 tm->tm_mon = from_bcd(pThis, pThis->cmos_data[RTC_MONTH]) - 1;
297 tm->tm_year = from_bcd(pThis, pThis->cmos_data[RTC_YEAR]) + 100;
298}
299
300
301/* -=-=-=-=-=- I/O Port Handlers -=-=-=-=-=- */
302
303
304/**
305 * @callback_method_impl{FNIOMIOPORTIN}
306 */
307PDMBOTHCBDECL(int) rtcIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
308{
309 NOREF(pvUser);
310 if (cb != 1)
311 return VERR_IOM_IOPORT_UNUSED;
312
313 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
314 if ((Port & 1) == 0)
315 *pu32 = 0xff;
316 else
317 {
318 unsigned bank = (Port >> 1) & 1;
319 switch (pThis->cmos_index[bank])
320 {
321 case RTC_SECONDS:
322 case RTC_MINUTES:
323 case RTC_HOURS:
324 case RTC_DAY_OF_WEEK:
325 case RTC_DAY_OF_MONTH:
326 case RTC_MONTH:
327 case RTC_YEAR:
328 *pu32 = pThis->cmos_data[pThis->cmos_index[0]];
329 break;
330
331 case RTC_REG_A:
332 if (pThis->cmos_data[RTC_REG_A] & REG_A_UIP)
333 ++pThis->cUipSeen;
334 else
335 pThis->cUipSeen = 0;
336 if (pThis->cUipSeen >= 250)
337 {
338 pThis->cmos_data[pThis->cmos_index[0]] &= ~REG_A_UIP;
339 pThis->cUipSeen = 0;
340 }
341 *pu32 = pThis->cmos_data[pThis->cmos_index[0]];
342 break;
343
344 case RTC_REG_C:
345 *pu32 = pThis->cmos_data[pThis->cmos_index[0]];
346 rtc_raise_irq(pThis, 0);
347 pThis->cmos_data[RTC_REG_C] = 0x00;
348 break;
349
350 default:
351 *pu32 = pThis->cmos_data[pThis->cmos_index[bank]];
352 break;
353 }
354
355 Log(("CMOS: Read bank %d idx %#04x: %#04x\n", bank, pThis->cmos_index[bank], *pu32));
356 }
357
358 return VINF_SUCCESS;
359}
360
361
362/**
363 * @callback_method_impl{FNIOMIOPORTOUT}
364 */
365PDMBOTHCBDECL(int) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
366{
367 NOREF(pvUser);
368 if (cb != 1)
369 return VINF_SUCCESS;
370
371 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
372 uint32_t bank = (Port >> 1) & 1;
373 if ((Port & 1) == 0)
374 {
375 pThis->cmos_index[bank] = (u32 & 0x7f) + (bank * CMOS_BANK_SIZE);
376
377 /* HACK ALERT! Attempt to trigger VM_FF_TIMER and/or VM_FF_TM_VIRTUAL_SYNC
378 for forcing the pSecondTimer2 timer to run be run and clear UIP in
379 a timely fashion. */
380 if (u32 == RTC_REG_A)
381 TMTimerGet(pThis->CTX_SUFF(pSecondTimer));
382 }
383 else
384 {
385 Log(("CMOS: Write bank %d idx %#04x: %#04x (old %#04x)\n", bank,
386 pThis->cmos_index[bank], u32, pThis->cmos_data[pThis->cmos_index[bank]]));
387
388 int const idx = pThis->cmos_index[bank];
389 switch (idx)
390 {
391 case RTC_SECONDS_ALARM:
392 case RTC_MINUTES_ALARM:
393 case RTC_HOURS_ALARM:
394 pThis->cmos_data[pThis->cmos_index[0]] = u32;
395 break;
396
397 case RTC_SECONDS:
398 case RTC_MINUTES:
399 case RTC_HOURS:
400 case RTC_DAY_OF_WEEK:
401 case RTC_DAY_OF_MONTH:
402 case RTC_MONTH:
403 case RTC_YEAR:
404 pThis->cmos_data[pThis->cmos_index[0]] = u32;
405 /* if in set mode, do not update the time */
406 if (!(pThis->cmos_data[RTC_REG_B] & REG_B_SET))
407 rtc_set_time(pThis);
408 break;
409
410 case RTC_REG_A:
411 case RTC_REG_B:
412 {
413 /* We need to acquire the clock lock, because of lock ordering
414 issues this means having to release the device lock. Since
415 we're letting IOM do the locking, we must not return without
416 holding the device lock.*/
417 PDMCritSectLeave(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo));
418 int rc1 = TMTimerLock(pThis->CTX_SUFF(pPeriodicTimer), VINF_SUCCESS /* must get it */);
419 int rc2 = PDMCritSectEnter(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS /* must get it */);
420 AssertRCReturn(rc1, rc1);
421 AssertRCReturnStmt(rc2, TMTimerUnlock(pThis->CTX_SUFF(pPeriodicTimer)), rc2);
422
423 if (idx == RTC_REG_A)
424 {
425 /* UIP bit is read only */
426 pThis->cmos_data[RTC_REG_A] = (u32 & ~REG_A_UIP)
427 | (pThis->cmos_data[RTC_REG_A] & REG_A_UIP);
428 }
429 else
430 {
431 if (u32 & REG_B_SET)
432 {
433 /* set mode: reset UIP mode */
434 pThis->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
435#if 0 /* This is probably wrong as it breaks changing the time/date in OS/2. */
436 u32 &= ~REG_B_UIE;
437#endif
438 }
439 else
440 {
441 /* if disabling set mode, update the time */
442 if (pThis->cmos_data[RTC_REG_B] & REG_B_SET)
443 rtc_set_time(pThis);
444 }
445 pThis->cmos_data[RTC_REG_B] = u32;
446 }
447
448 rtc_timer_update(pThis, TMTimerGet(pThis->CTX_SUFF(pPeriodicTimer)));
449
450 TMTimerUnlock(pThis->CTX_SUFF(pPeriodicTimer));
451 /* the caller leaves the other lock. */
452 break;
453 }
454
455 case RTC_REG_C:
456 case RTC_REG_D:
457 /* cannot write to them */
458 break;
459
460 default:
461 pThis->cmos_data[pThis->cmos_index[bank]] = u32;
462 break;
463 }
464 }
465
466 return VINF_SUCCESS;
467}
468
469#ifdef IN_RING3
470
471/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
472
473/**
474 * @callback_method_impl{FNDBGFHANDLERDEV,
475 * Dumps the cmos Bank Info.}
476 */
477static DECLCALLBACK(void) rtcCmosBankInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
478{
479 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
480
481 pHlp->pfnPrintf(pHlp,
482 "First CMOS bank, offsets 0x0E - 0x7F\n"
483 "Offset %02x : --- use 'info rtc' to show CMOS clock ---", 0);
484 for (unsigned iCmos = CMOS_BANK_LOWER_LIMIT; iCmos <= CMOS_BANK_UPPER_LIMIT; iCmos++)
485 {
486 if ((iCmos & 15) == 0)
487 pHlp->pfnPrintf(pHlp, "Offset %02x : %02x", iCmos, pThis->cmos_data[iCmos]);
488 else if ((iCmos & 15) == 8)
489 pHlp->pfnPrintf(pHlp, "-%02x", pThis->cmos_data[iCmos]);
490 else if ((iCmos & 15) == 15)
491 pHlp->pfnPrintf(pHlp, " %02x\n", pThis->cmos_data[iCmos]);
492 else
493 pHlp->pfnPrintf(pHlp, " %02x", pThis->cmos_data[iCmos]);
494 }
495}
496
497/**
498 * @callback_method_impl{FNDBGFHANDLERDEV,
499 * Dumps the cmos Bank2 Info.}
500 */
501static DECLCALLBACK(void) rtcCmosBank2Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
502{
503 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
504
505 pHlp->pfnPrintf(pHlp, "Second CMOS bank, offsets 0x80 - 0xFF\n");
506 for (uint16_t iCmos = CMOS_BANK2_LOWER_LIMIT; iCmos <= CMOS_BANK2_UPPER_LIMIT; iCmos++)
507 {
508 if ((iCmos & 15) == 0)
509 pHlp->pfnPrintf(pHlp, "Offset %02x : %02x", iCmos, pThis->cmos_data[iCmos]);
510 else if ((iCmos & 15) == 8)
511 pHlp->pfnPrintf(pHlp, "-%02x", pThis->cmos_data[iCmos]);
512 else if ((iCmos & 15) == 15)
513 pHlp->pfnPrintf(pHlp, " %02x\n", pThis->cmos_data[iCmos]);
514 else
515 pHlp->pfnPrintf(pHlp, " %02x", pThis->cmos_data[iCmos]);
516 }
517}
518
519/**
520 * @callback_method_impl{FNDBGFHANDLERDEV,
521 * Dumps the cmos RTC Info.}
522 */
523static DECLCALLBACK(void) rtcCmosClockInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
524{
525 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
526 uint8_t u8Sec = from_bcd(pThis, pThis->cmos_data[RTC_SECONDS]);
527 uint8_t u8Min = from_bcd(pThis, pThis->cmos_data[RTC_MINUTES]);
528 uint8_t u8Hr = from_bcd(pThis, pThis->cmos_data[RTC_HOURS] & 0x7f);
529 if ( !(pThis->cmos_data[RTC_REG_B] & 0x02)
530 && (pThis->cmos_data[RTC_HOURS] & 0x80))
531 u8Hr += 12;
532 uint8_t u8Day = from_bcd(pThis, pThis->cmos_data[RTC_DAY_OF_MONTH]);
533 uint8_t u8Month = from_bcd(pThis, pThis->cmos_data[RTC_MONTH]) ;
534 uint8_t u8Year = from_bcd(pThis, pThis->cmos_data[RTC_YEAR]);
535 pHlp->pfnPrintf(pHlp, "Time: %02u:%02u:%02u Date: %02u-%02u-%02u\n",
536 u8Hr, u8Min, u8Sec, u8Year, u8Month, u8Day);
537 pHlp->pfnPrintf(pHlp, "REG A=%02x B=%02x C=%02x D=%02x\n",
538 pThis->cmos_data[RTC_REG_A], pThis->cmos_data[RTC_REG_B],
539 pThis->cmos_data[RTC_REG_C], pThis->cmos_data[RTC_REG_D]);
540}
541
542
543
544/* -=-=-=-=-=- Timers and their support code -=-=-=-=-=- */
545
546
547/**
548 * @callback_method_impl{FNTMTIMERDEV, periodic}
549 */
550static DECLCALLBACK(void) rtcTimerPeriodic(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
551{
552 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
553 Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPeriodicTimer)));
554 Assert(PDMCritSectIsOwner(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo)));
555
556 rtc_timer_update(pThis, pThis->next_periodic_time);
557 STAM_COUNTER_INC(&pThis->StatRTCTimerCB);
558 pThis->cmos_data[RTC_REG_C] |= 0xc0;
559
560 rtc_raise_irq(pThis, 1);
561}
562
563
564/* month is between 0 and 11. */
565static int get_days_in_month(int month, int year)
566{
567 static const int days_tab[12] =
568 {
569 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
570 };
571 int d;
572
573 if ((unsigned )month >= 12)
574 return 31;
575
576 d = days_tab[month];
577 if (month == 1)
578 {
579 if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
580 d++;
581 }
582 return d;
583}
584
585
586/* update 'tm' to the next second */
587static void rtc_next_second(struct my_tm *tm)
588{
589 int days_in_month;
590
591 tm->tm_sec++;
592 if ((unsigned)tm->tm_sec >= 60)
593 {
594 tm->tm_sec = 0;
595 tm->tm_min++;
596 if ((unsigned)tm->tm_min >= 60)
597 {
598 tm->tm_min = 0;
599 tm->tm_hour++;
600 if ((unsigned)tm->tm_hour >= 24)
601 {
602 tm->tm_hour = 0;
603 /* next day */
604 tm->tm_wday++;
605 if ((unsigned)tm->tm_wday >= 7)
606 tm->tm_wday = 0;
607 days_in_month = get_days_in_month(tm->tm_mon,
608 tm->tm_year + 1900);
609 tm->tm_mday++;
610 if (tm->tm_mday < 1)
611 tm->tm_mday = 1;
612 else if (tm->tm_mday > days_in_month)
613 {
614 tm->tm_mday = 1;
615 tm->tm_mon++;
616 if (tm->tm_mon >= 12)
617 {
618 tm->tm_mon = 0;
619 tm->tm_year++;
620 }
621 }
622 }
623 }
624 }
625}
626
627
628/**
629 * @callback_method_impl{FNTMTIMERDEV, Second timer.}
630 */
631static DECLCALLBACK(void) rtcTimerSecond(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
632{
633 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
634 Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPeriodicTimer)));
635 Assert(PDMCritSectIsOwner(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo)));
636
637 /* if the oscillator is not in normal operation, we do not update */
638 if ((pThis->cmos_data[RTC_REG_A] & 0x70) != 0x20)
639 {
640 pThis->next_second_time += TMTimerGetFreq(pThis->CTX_SUFF(pSecondTimer));
641 TMTimerSet(pThis->CTX_SUFF(pSecondTimer), pThis->next_second_time);
642 }
643 else
644 {
645 rtc_next_second(&pThis->current_tm);
646
647 if (!(pThis->cmos_data[RTC_REG_B] & REG_B_SET))
648 {
649 /* update in progress bit */
650 Log2(("RTC: UIP %x -> 1\n", !!(pThis->cmos_data[RTC_REG_A] & REG_A_UIP)));
651 pThis->cmos_data[RTC_REG_A] |= REG_A_UIP;
652 }
653
654 /* 244140 ns = 8 / 32768 seconds */
655 uint64_t delay = TMTimerFromNano(pThis->CTX_SUFF(pSecondTimer2), 244140);
656 TMTimerSet(pThis->CTX_SUFF(pSecondTimer2), pThis->next_second_time + delay);
657 }
658}
659
660
661/* Used by rtc_set_date and rtcTimerSecond2. */
662static void rtc_copy_date(PRTCSTATE pThis)
663{
664 const struct my_tm *tm = &pThis->current_tm;
665
666 pThis->cmos_data[RTC_SECONDS] = to_bcd(pThis, tm->tm_sec);
667 pThis->cmos_data[RTC_MINUTES] = to_bcd(pThis, tm->tm_min);
668 if (pThis->cmos_data[RTC_REG_B] & 0x02)
669 {
670 /* 24 hour format */
671 pThis->cmos_data[RTC_HOURS] = to_bcd(pThis, tm->tm_hour);
672 }
673 else
674 {
675 /* 12 hour format */
676 int h = tm->tm_hour % 12;
677 pThis->cmos_data[RTC_HOURS] = to_bcd(pThis, h ? h : 12);
678 if (tm->tm_hour >= 12)
679 pThis->cmos_data[RTC_HOURS] |= 0x80;
680 }
681 pThis->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(pThis, tm->tm_wday);
682 pThis->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(pThis, tm->tm_mday);
683 pThis->cmos_data[RTC_MONTH] = to_bcd(pThis, tm->tm_mon + 1);
684 pThis->cmos_data[RTC_YEAR] = to_bcd(pThis, tm->tm_year % 100);
685}
686
687
688/**
689 * @callback_method_impl{FNTMTIMERDEV, Second2 timer.}
690 */
691static DECLCALLBACK(void) rtcTimerSecond2(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
692{
693 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
694 Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPeriodicTimer)));
695 Assert(PDMCritSectIsOwner(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo)));
696
697 if (!(pThis->cmos_data[RTC_REG_B] & REG_B_SET))
698 rtc_copy_date(pThis);
699
700 /* check alarm */
701 if (pThis->cmos_data[RTC_REG_B] & REG_B_AIE)
702 {
703 if ( ( (pThis->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0
704 || from_bcd(pThis, pThis->cmos_data[RTC_SECONDS_ALARM]) == pThis->current_tm.tm_sec)
705 && ( (pThis->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0
706 || from_bcd(pThis, pThis->cmos_data[RTC_MINUTES_ALARM]) == pThis->current_tm.tm_min)
707 && ( (pThis->cmos_data[RTC_HOURS_ALARM ] & 0xc0) == 0xc0
708 || from_bcd(pThis, pThis->cmos_data[RTC_HOURS_ALARM ]) == pThis->current_tm.tm_hour)
709 )
710 {
711 pThis->cmos_data[RTC_REG_C] |= 0xa0;
712 rtc_raise_irq(pThis, 1);
713 }
714 }
715
716 /* update ended interrupt */
717 if (pThis->cmos_data[RTC_REG_B] & REG_B_UIE)
718 {
719 pThis->cmos_data[RTC_REG_C] |= 0x90;
720 rtc_raise_irq(pThis, 1);
721 }
722
723 /* clear update in progress bit */
724 Log2(("RTC: UIP %x -> 0\n", !!(pThis->cmos_data[RTC_REG_A] & REG_A_UIP)));
725 pThis->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
726
727 pThis->next_second_time += TMTimerGetFreq(pThis->CTX_SUFF(pSecondTimer));
728 TMTimerSet(pThis->CTX_SUFF(pSecondTimer), pThis->next_second_time);
729}
730
731
732/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
733
734
735/**
736 * @callback_method_impl{FNSSMDEVLIVEEXEC}
737 */
738static DECLCALLBACK(int) rtcLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
739{
740 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
741
742 SSMR3PutU8( pSSM, pThis->irq);
743 SSMR3PutIOPort(pSSM, pThis->IOPortBase);
744 SSMR3PutBool( pSSM, pThis->fUTC);
745
746 return VINF_SSM_DONT_CALL_AGAIN;
747}
748
749
750/**
751 * @callback_method_impl{FNSSMDEVSAVEEXEC}
752 */
753static DECLCALLBACK(int) rtcSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
754{
755 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
756
757 /* The config. */
758 rtcLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
759
760 /* The state. */
761 SSMR3PutMem(pSSM, pThis->cmos_data, CMOS_BANK_SIZE);
762 SSMR3PutU8(pSSM, pThis->cmos_index[0]);
763
764 SSMR3PutS32(pSSM, pThis->current_tm.tm_sec);
765 SSMR3PutS32(pSSM, pThis->current_tm.tm_min);
766 SSMR3PutS32(pSSM, pThis->current_tm.tm_hour);
767 SSMR3PutS32(pSSM, pThis->current_tm.tm_wday);
768 SSMR3PutS32(pSSM, pThis->current_tm.tm_mday);
769 SSMR3PutS32(pSSM, pThis->current_tm.tm_mon);
770 SSMR3PutS32(pSSM, pThis->current_tm.tm_year);
771
772 TMR3TimerSave(pThis->CTX_SUFF(pPeriodicTimer), pSSM);
773
774 SSMR3PutS64(pSSM, pThis->next_periodic_time);
775
776 SSMR3PutS64(pSSM, pThis->next_second_time);
777 TMR3TimerSave(pThis->CTX_SUFF(pSecondTimer), pSSM);
778 TMR3TimerSave(pThis->CTX_SUFF(pSecondTimer2), pSSM);
779
780 SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
781
782 SSMR3PutMem(pSSM, &pThis->cmos_data[CMOS_BANK_SIZE], CMOS_BANK_SIZE);
783 return SSMR3PutU8(pSSM, pThis->cmos_index[1]);
784}
785
786
787/**
788 * @callback_method_impl{FNSSMDEVLOADEXEC}
789 */
790static DECLCALLBACK(int) rtcLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
791{
792 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
793 int rc;
794
795 if ( uVersion != RTC_SAVED_STATE_VERSION
796 && uVersion != RTC_SAVED_STATE_VERSION_VBOX_32PRE
797 && uVersion != RTC_SAVED_STATE_VERSION_VBOX_31
798 && uVersion != RTC_SAVED_STATE_VERSION_VBOX_30)
799 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
800
801 /* The config. */
802 if (uVersion > RTC_SAVED_STATE_VERSION_VBOX_30)
803 {
804 uint8_t u8Irq;
805 rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
806 if (u8Irq != pThis->irq)
807 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"), u8Irq, pThis->irq);
808
809 RTIOPORT IOPortBase;
810 rc = SSMR3GetIOPort(pSSM, &IOPortBase); AssertRCReturn(rc, rc);
811 if (IOPortBase != pThis->IOPortBase)
812 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBase: saved=%RTiop config=%RTiop"), IOPortBase, pThis->IOPortBase);
813
814 bool fUTC;
815 rc = SSMR3GetBool(pSSM, &fUTC); AssertRCReturn(rc, rc);
816 if (fUTC != pThis->fUTC)
817 LogRel(("RTC: Config mismatch - fUTC: saved=%RTbool config=%RTbool\n", fUTC, pThis->fUTC));
818 }
819
820 if (uPass != SSM_PASS_FINAL)
821 return VINF_SUCCESS;
822
823 /* The state. */
824 SSMR3GetMem(pSSM, pThis->cmos_data, CMOS_BANK_SIZE);
825 SSMR3GetU8(pSSM, &pThis->cmos_index[0]);
826
827 SSMR3GetS32(pSSM, &pThis->current_tm.tm_sec);
828 SSMR3GetS32(pSSM, &pThis->current_tm.tm_min);
829 SSMR3GetS32(pSSM, &pThis->current_tm.tm_hour);
830 SSMR3GetS32(pSSM, &pThis->current_tm.tm_wday);
831 SSMR3GetS32(pSSM, &pThis->current_tm.tm_mday);
832 SSMR3GetS32(pSSM, &pThis->current_tm.tm_mon);
833 SSMR3GetS32(pSSM, &pThis->current_tm.tm_year);
834
835 TMR3TimerLoad(pThis->CTX_SUFF(pPeriodicTimer), pSSM);
836
837 SSMR3GetS64(pSSM, &pThis->next_periodic_time);
838
839 SSMR3GetS64(pSSM, &pThis->next_second_time);
840 TMR3TimerLoad(pThis->CTX_SUFF(pSecondTimer), pSSM);
841 TMR3TimerLoad(pThis->CTX_SUFF(pSecondTimer2), pSSM);
842
843 if (uVersion > RTC_SAVED_STATE_VERSION_VBOX_31)
844 SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
845
846 if (uVersion > RTC_SAVED_STATE_VERSION_VBOX_32PRE)
847 {
848 /* Second CMOS bank. */
849 SSMR3GetMem(pSSM, &pThis->cmos_data[CMOS_BANK_SIZE], CMOS_BANK_SIZE);
850 SSMR3GetU8(pSSM, &pThis->cmos_index[1]);
851 }
852
853 int period_code = pThis->cmos_data[RTC_REG_A] & 0x0f;
854 if ( period_code != 0
855 && (pThis->cmos_data[RTC_REG_B] & REG_B_PIE))
856 {
857 if (period_code <= 2)
858 period_code += 7;
859 int period = 1 << (period_code - 1);
860 LogRel(("RTC: period=%#x (%d) %u Hz (restore)\n", period, period, _32K / period));
861 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VINF_SUCCESS);
862 TMTimerSetFrequencyHint(pThis->CTX_SUFF(pPeriodicTimer), _32K / period);
863 PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
864 pThis->CurLogPeriod = period;
865 pThis->CurHintPeriod = period;
866 }
867 else
868 {
869 LogRel(("RTC: stopped the periodic timer (restore)\n"));
870 pThis->CurLogPeriod = 0;
871 pThis->CurHintPeriod = 0;
872 }
873 pThis->cRelLogEntries = 0;
874
875 return VINF_SUCCESS;
876}
877
878
879/* -=-=-=-=-=- PDM Interface provided by the RTC device -=-=-=-=-=- */
880
881/**
882 * Calculate and update the standard CMOS checksum.
883 *
884 * @param pThis Pointer to the RTC state data.
885 */
886static void rtcCalcCRC(PRTCSTATE pThis)
887{
888 uint16_t u16 = 0;
889 for (unsigned i = RTC_CRC_START; i <= RTC_CRC_LAST; i++)
890 u16 += pThis->cmos_data[i];
891
892 pThis->cmos_data[RTC_CRC_LOW] = u16 & 0xff;
893 pThis->cmos_data[RTC_CRC_HIGH] = (u16 >> 8) & 0xff;
894}
895
896
897/**
898 * @interface_method_impl{PDMRTCREG,pfnWrite}
899 */
900static DECLCALLBACK(int) rtcCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
901{
902 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
903 Assert(PDMCritSectIsOwner(pDevIns->pCritSectRoR3));
904 if (iReg < RT_ELEMENTS(pThis->cmos_data))
905 {
906 pThis->cmos_data[iReg] = u8Value;
907
908 /* does it require checksum update? */
909 if ( iReg >= RTC_CRC_START
910 && iReg <= RTC_CRC_LAST)
911 rtcCalcCRC(pThis);
912
913 return VINF_SUCCESS;
914 }
915
916 AssertMsgFailed(("iReg=%d\n", iReg));
917 return VERR_INVALID_PARAMETER;
918}
919
920
921/**
922 * @interface_method_impl{PDMRTCREG,pfnRead}
923 */
924static DECLCALLBACK(int) rtcCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
925{
926 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
927 Assert(PDMCritSectIsOwner(pDevIns->pCritSectRoR3));
928
929 if (iReg < RT_ELEMENTS(pThis->cmos_data))
930 {
931 *pu8Value = pThis->cmos_data[iReg];
932 return VINF_SUCCESS;
933 }
934 AssertMsgFailed(("iReg=%d\n", iReg));
935 return VERR_INVALID_PARAMETER;
936}
937
938
939/**
940 * @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
941 */
942static DECLCALLBACK(void) rtcHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
943{
944 PRTCSTATE pThis = RT_FROM_MEMBER(pInterface, RTCSTATE, IHpetLegacyNotify);
945 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VERR_IGNORED);
946
947 pThis->fDisabledByHpet = fActivated;
948
949 PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
950}
951
952
953
954/* -=-=-=-=-=- IBase -=-=-=-=-=- */
955
956/**
957 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
958 */
959static DECLCALLBACK(void *) rtcQueryInterface(PPDMIBASE pInterface, const char *pszIID)
960{
961 PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
962 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
963 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
964 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
965 return NULL;
966}
967
968
969/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
970
971static void rtc_set_memory(PRTCSTATE pThis, int addr, int val)
972{
973 if (addr >= 0 && addr <= 127)
974 pThis->cmos_data[addr] = val;
975}
976
977
978static void rtc_set_date(PRTCSTATE pThis, const struct my_tm *tm)
979{
980 pThis->current_tm = *tm;
981 rtc_copy_date(pThis);
982}
983
984
985/**
986 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
987 *
988 * Used to set the clock.
989 */
990static DECLCALLBACK(int) rtcInitComplete(PPDMDEVINS pDevIns)
991{
992 /** @todo this should be (re)done at power on if we didn't load a state... */
993 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
994
995 /*
996 * Set the CMOS date/time.
997 */
998 RTTIMESPEC Now;
999 PDMDevHlpTMUtcNow(pDevIns, &Now);
1000 RTTIME Time;
1001 if (pThis->fUTC)
1002 RTTimeExplode(&Time, &Now);
1003 else
1004 RTTimeLocalExplode(&Time, &Now);
1005
1006 struct my_tm Tm;
1007 memset(&Tm, 0, sizeof(Tm));
1008 Tm.tm_year = Time.i32Year - 1900;
1009 Tm.tm_mon = Time.u8Month - 1;
1010 Tm.tm_mday = Time.u8MonthDay;
1011 Tm.tm_wday = (Time.u8WeekDay + 1 + 7) % 7; /* 0 = Monday -> Sunday */
1012 Tm.tm_yday = Time.u16YearDay - 1;
1013 Tm.tm_hour = Time.u8Hour;
1014 Tm.tm_min = Time.u8Minute;
1015 Tm.tm_sec = Time.u8Second;
1016
1017 rtc_set_date(pThis, &Tm);
1018
1019 int iYear = to_bcd(pThis, (Tm.tm_year / 100) + 19); /* tm_year is 1900 based */
1020 rtc_set_memory(pThis, 0x32, iYear); /* 32h - Century Byte (BCD value for the century */
1021 rtc_set_memory(pThis, 0x37, iYear); /* 37h - (IBM PS/2) Date Century Byte */
1022
1023 /*
1024 * Recalculate the checksum just in case.
1025 */
1026 rtcCalcCRC(pThis);
1027
1028 Log(("CMOS bank 0: \n%16.128Rhxd\n", &pThis->cmos_data[0]));
1029 Log(("CMOS bank 1: \n%16.128Rhxd\n", &pThis->cmos_data[CMOS_BANK_SIZE]));
1030 return VINF_SUCCESS;
1031}
1032
1033
1034/**
1035 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1036 */
1037static DECLCALLBACK(void) rtcRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1038{
1039 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
1040
1041 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1042 pThis->pPeriodicTimerRC = TMTimerRCPtr(pThis->pPeriodicTimerR3);
1043 pThis->pSecondTimerRC = TMTimerRCPtr(pThis->pSecondTimerR3);
1044 pThis->pSecondTimer2RC = TMTimerRCPtr(pThis->pSecondTimer2R3);
1045}
1046
1047
1048/**
1049 * @interface_method_impl{PDMDEVREG,pfnReset}
1050 */
1051static DECLCALLBACK(void) rtcReset(PPDMDEVINS pDevIns)
1052{
1053 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
1054
1055 /* If shutdown status is non-zero, log its value. */
1056 if (pThis->cmos_data[0xF])
1057 {
1058 LogRel(("CMOS shutdown status byte is %02X\n", pThis->cmos_data[0xF]));
1059
1060#if 0 /* It would be nice to log the warm reboot vector but alas, we already trashed it. */
1061 uint32_t u32WarmVector;
1062 int rc;
1063 rc = PDMDevHlpPhysRead(pDevIns, 0x467, &u32WarmVector, sizeof(u32WarmVector));
1064 AssertRC(rc);
1065 LogRel((", 40:67 contains %04X:%04X\n", u32WarmVector >> 16, u32WarmVector & 0xFFFF));
1066#endif
1067 /* If we're going to trash the VM's memory, we also have to clear this. */
1068 pThis->cmos_data[0xF] = 0;
1069 }
1070
1071 /* Reset index values (important for second bank). */
1072 pThis->cmos_index[0] = 0;
1073 pThis->cmos_index[1] = CMOS_BANK_SIZE; /* Point to start of second bank. */
1074}
1075
1076
1077/**
1078 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1079 */
1080static DECLCALLBACK(int) rtcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1081{
1082 PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
1083 int rc;
1084 Assert(iInstance == 0);
1085
1086 /*
1087 * Validate configuration.
1088 */
1089 if (!CFGMR3AreValuesValid(pCfg,
1090 "Irq\0"
1091 "Base\0"
1092 "UseUTC\0"
1093 "GCEnabled\0"
1094 "R0Enabled\0"))
1095 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1096
1097 /*
1098 * Init the data.
1099 */
1100 uint8_t u8Irq;
1101 rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 8);
1102 if (RT_FAILURE(rc))
1103 return PDMDEV_SET_ERROR(pDevIns, rc,
1104 N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1105 pThis->irq = u8Irq;
1106
1107 rc = CFGMR3QueryPortDef(pCfg, "Base", &pThis->IOPortBase, 0x70);
1108 if (RT_FAILURE(rc))
1109 return PDMDEV_SET_ERROR(pDevIns, rc,
1110 N_("Configuration error: Querying \"Base\" as a RTIOPORT failed"));
1111
1112 rc = CFGMR3QueryBoolDef(pCfg, "UseUTC", &pThis->fUTC, false);
1113 if (RT_FAILURE(rc))
1114 return PDMDEV_SET_ERROR(pDevIns, rc,
1115 N_("Configuration error: Querying \"UseUTC\" as a bool failed"));
1116
1117 bool fGCEnabled;
1118 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1119 if (RT_FAILURE(rc))
1120 return PDMDEV_SET_ERROR(pDevIns, rc,
1121 N_("Configuration error: failed to read GCEnabled as boolean"));
1122
1123 bool fR0Enabled;
1124 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1125 if (RT_FAILURE(rc))
1126 return PDMDEV_SET_ERROR(pDevIns, rc,
1127 N_("Configuration error: failed to read R0Enabled as boolean"));
1128
1129 Log(("RTC: Irq=%#x Base=%#x fGCEnabled=%RTbool fR0Enabled=%RTbool\n",
1130 u8Irq, pThis->IOPortBase, fGCEnabled, fR0Enabled));
1131
1132
1133 pThis->pDevInsR3 = pDevIns;
1134 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1135 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1136 pThis->cmos_data[RTC_REG_A] = 0x26;
1137 pThis->cmos_data[RTC_REG_B] = 0x02;
1138 pThis->cmos_data[RTC_REG_C] = 0x00;
1139 pThis->cmos_data[RTC_REG_D] = 0x80;
1140 pThis->RtcReg.u32Version = PDM_RTCREG_VERSION;
1141 pThis->RtcReg.pfnRead = rtcCMOSRead;
1142 pThis->RtcReg.pfnWrite = rtcCMOSWrite;
1143 pThis->fDisabledByHpet = false;
1144 pThis->cmos_index[1] = CMOS_BANK_SIZE; /* Point to start of second bank. */
1145
1146
1147 /* IBase */
1148 pDevIns->IBase.pfnQueryInterface = rtcQueryInterface;
1149 /* IHpetLegacyNotify */
1150 pThis->IHpetLegacyNotify.pfnModeChanged = rtcHpetLegacyNotify_ModeChanged;
1151
1152 /*
1153 * Create timers.
1154 */
1155 PTMTIMER pTimer;
1156 /* Periodic timer. */
1157 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerPeriodic, pThis,
1158 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "MC146818 RTC/CMOS - Periodic",
1159 &pTimer);
1160 if (RT_FAILURE(rc))
1161 return rc;
1162 pThis->pPeriodicTimerR3 = pTimer;
1163 pThis->pPeriodicTimerR0 = TMTimerR0Ptr(pTimer);
1164 pThis->pPeriodicTimerRC = TMTimerRCPtr(pTimer);
1165
1166 /* Seconds timer. */
1167 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerSecond, pThis,
1168 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "MC146818 RTC/CMOS - Second",
1169 &pTimer);
1170 if (RT_FAILURE(rc))
1171 return rc;
1172 pThis->pSecondTimerR3 = pTimer;
1173 pThis->pSecondTimerR0 = TMTimerR0Ptr(pTimer);
1174 pThis->pSecondTimerRC = TMTimerRCPtr(pTimer);
1175
1176 /* The second2 timer, this is always active. */
1177 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerSecond2, pThis,
1178 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "MC146818 RTC/CMOS - Second2",
1179 &pTimer);
1180 if (RT_FAILURE(rc))
1181 return rc;
1182 pThis->pSecondTimer2R3 = pTimer;
1183 pThis->pSecondTimer2R0 = TMTimerR0Ptr(pTimer);
1184 pThis->pSecondTimer2RC = TMTimerRCPtr(pTimer);
1185 pThis->next_second_time = TMTimerGet(pTimer)
1186 + (TMTimerGetFreq(pTimer) * 99) / 100;
1187 rc = TMTimerLock(pTimer, VERR_IGNORED);
1188 AssertRCReturn(rc, rc);
1189 rc = TMTimerSet(pTimer, pThis->next_second_time);
1190 TMTimerUnlock(pTimer);
1191 AssertRCReturn(rc, rc);
1192
1193 /*
1194 * Register I/O ports.
1195 */
1196 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase, 4, NULL,
1197 rtcIOPortWrite, rtcIOPortRead, NULL, NULL, "MC146818 RTC/CMOS");
1198 if (RT_FAILURE(rc))
1199 return rc;
1200 if (fGCEnabled)
1201 {
1202 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase, 4, NIL_RTRCPTR,
1203 "rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS");
1204 if (RT_FAILURE(rc))
1205 return rc;
1206 }
1207 if (fR0Enabled)
1208 {
1209 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase, 4, NIL_RTR0PTR,
1210 "rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS");
1211 if (RT_FAILURE(rc))
1212 return rc;
1213 }
1214
1215 /*
1216 * Register the saved state.
1217 */
1218 rc = PDMDevHlpSSMRegister3(pDevIns, RTC_SAVED_STATE_VERSION, sizeof(*pThis), rtcLiveExec, rtcSaveExec, rtcLoadExec);
1219 if (RT_FAILURE(rc))
1220 return rc;
1221
1222 /*
1223 * Register ourselves as the RTC/CMOS with PDM.
1224 */
1225 rc = PDMDevHlpRTCRegister(pDevIns, &pThis->RtcReg, &pThis->pRtcHlpR3);
1226 if (RT_FAILURE(rc))
1227 return rc;
1228
1229 /*
1230 * Register debugger info callback.
1231 */
1232 PDMDevHlpDBGFInfoRegister(pDevIns, "cmos1", "Display CMOS Bank 1 Info (0x0e-0x7f). No arguments. See also rtc.", rtcCmosBankInfo);
1233 PDMDevHlpDBGFInfoRegister(pDevIns, "cmos2", "Display CMOS Bank 2 Info (0x0e-0x7f). No arguments.", rtcCmosBank2Info);
1234 PDMDevHlpDBGFInfoRegister(pDevIns, "rtc", "Display CMOS RTC (0x00-0x0d). No arguments. See also cmos1 & cmos2", rtcCmosClockInfo);
1235
1236 /*
1237 * Register statistics.
1238 */
1239 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRTCIrq, STAMTYPE_COUNTER, "/TM/RTC/Irq", STAMUNIT_OCCURENCES, "The number of times a RTC interrupt was triggered.");
1240 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRTCTimerCB, STAMTYPE_COUNTER, "/TM/RTC/TimerCB", STAMUNIT_OCCURENCES, "The number of times the RTC timer callback ran.");
1241
1242 return VINF_SUCCESS;
1243}
1244
1245
1246/**
1247 * The device registration structure.
1248 */
1249const PDMDEVREG g_DeviceMC146818 =
1250{
1251 /* u32Version */
1252 PDM_DEVREG_VERSION,
1253 /* szName */
1254 "mc146818",
1255 /* szRCMod */
1256 "VBoxDDRC.rc",
1257 /* szR0Mod */
1258 "VBoxDDR0.r0",
1259 /* pszDescription */
1260 "Motorola MC146818 RTC/CMOS Device.",
1261 /* fFlags */
1262 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1263 /* fClass */
1264 PDM_DEVREG_CLASS_RTC,
1265 /* cMaxInstances */
1266 1,
1267 /* cbInstance */
1268 sizeof(RTCSTATE),
1269 /* pfnConstruct */
1270 rtcConstruct,
1271 /* pfnDestruct */
1272 NULL,
1273 /* pfnRelocate */
1274 rtcRelocate,
1275 /* pfnMemSetup */
1276 NULL,
1277 /* pfnPowerOn */
1278 NULL,
1279 /* pfnReset */
1280 rtcReset,
1281 /* pfnSuspend */
1282 NULL,
1283 /* pfnResume */
1284 NULL,
1285 /* pfnAttach */
1286 NULL,
1287 /* pfnDetach */
1288 NULL,
1289 /* pfnQueryInterface */
1290 NULL,
1291 /* pfnInitComplete */
1292 rtcInitComplete,
1293 /* pfnPowerOff */
1294 NULL,
1295 /* pfnSoftReset */
1296 NULL,
1297 /* u32VersionEnd */
1298 PDM_DEVREG_VERSION
1299};
1300
1301#endif /* IN_RING3 */
1302#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1303
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