DevRTC.cpp@ 64808

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1	/* $Id: DevRTC.cpp 64369 2016-10-22 18:19:08Z vboxsync $ */
2	/** @file
3	* Motorola MC146818 RTC/CMOS Device with PIIX4 extensions.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU MC146818 RTC emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_RTC
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/log.h>
50	#include <iprt/asm-math.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#ifdef IN_RING3
55	# include <iprt/alloc.h>
56	# include <iprt/uuid.h>
57	#endif /* IN_RING3 */
58
59	#include "VBoxDD.h"
60
61
62	/*********************************************************************************************************************************
63	* Defined Constants And Macros *
64	*********************************************************************************************************************************/
65	/#define DEBUG_CMOS/
66	#define RTC_CRC_START 0x10
67	#define RTC_CRC_LAST 0x2d
68	#define RTC_CRC_HIGH 0x2e
69	#define RTC_CRC_LOW 0x2f
70
71	#define RTC_SECONDS 0
72	#define RTC_SECONDS_ALARM 1
73	#define RTC_MINUTES 2
74	#define RTC_MINUTES_ALARM 3
75	#define RTC_HOURS 4
76	#define RTC_HOURS_ALARM 5
77	#define RTC_ALARM_DONT_CARE 0xC0
78
79	#define RTC_DAY_OF_WEEK 6
80	#define RTC_DAY_OF_MONTH 7
81	#define RTC_MONTH 8
82	#define RTC_YEAR 9
83
84	#define RTC_REG_A 10
85	#define RTC_REG_B 11
86	#define RTC_REG_C 12
87	#define RTC_REG_D 13
88
89	#define REG_A_UIP 0x80
90
91	#define REG_B_SET 0x80
92	#define REG_B_PIE 0x40
93	#define REG_B_AIE 0x20
94	#define REG_B_UIE 0x10
95
96	#define CMOS_BANK_LOWER_LIMIT 0x0E
97	#define CMOS_BANK_UPPER_LIMIT 0x7F
98	#define CMOS_BANK2_LOWER_LIMIT 0x80
99	#define CMOS_BANK2_UPPER_LIMIT 0xFF
100	#define CMOS_BANK_SIZE 0x80
101
102	/** The saved state version. */
103	#define RTC_SAVED_STATE_VERSION 4
104	/** The saved state version used by VirtualBox pre-3.2.
105	* This does not include the second 128-byte bank. */
106	#define RTC_SAVED_STATE_VERSION_VBOX_32PRE 3
107	/** The saved state version used by VirtualBox 3.1 and earlier.
108	* This does not include disabled by HPET state. */
109	#define RTC_SAVED_STATE_VERSION_VBOX_31 2
110	/** The saved state version used by VirtualBox 3.0 and earlier.
111	* This does not include the configuration. */
112	#define RTC_SAVED_STATE_VERSION_VBOX_30 1
113
114
115	/*********************************************************************************************************************************
116	* Structures and Typedefs *
117	*********************************************************************************************************************************/
118	/** @todo Replace struct my_tm with RTTIME. */
119	struct my_tm
120	{
121	int32_t tm_sec;
122	int32_t tm_min;
123	int32_t tm_hour;
124	int32_t tm_mday;
125	int32_t tm_mon;
126	int32_t tm_year;
127	int32_t tm_wday;
128	int32_t tm_yday;
129	};
130
131
132	typedef struct RTCSTATE
133	{
134	uint8_t cmos_data[256];
135	uint8_t cmos_index[2];
136	uint8_t Alignment0[6];
137	struct my_tm current_tm;
138	/** The configured IRQ. */
139	int32_t irq;
140	/** The configured I/O port base. */
141	RTIOPORT IOPortBase;
142	/** Use UTC or local time initially. */
143	bool fUTC;
144	/** Disabled by HPET legacy mode. */
145	bool fDisabledByHpet;
146	/* periodic timer */
147	int64_t next_periodic_time;
148	/* second update */
149	int64_t next_second_time;
150
151	/** Pointer to the device instance - R3 Ptr. */
152	PPDMDEVINSR3 pDevInsR3;
153	/** The periodic timer (rtcTimerPeriodic) - R3 Ptr. */
154	PTMTIMERR3 pPeriodicTimerR3;
155	/** The second timer (rtcTimerSecond) - R3 Ptr. */
156	PTMTIMERR3 pSecondTimerR3;
157	/** The second second timer (rtcTimerSecond2) - R3 Ptr. */
158	PTMTIMERR3 pSecondTimer2R3;
159
160	/** Pointer to the device instance - R0 Ptr. */
161	PPDMDEVINSR0 pDevInsR0;
162	/** The periodic timer (rtcTimerPeriodic) - R0 Ptr. */
163	PTMTIMERR0 pPeriodicTimerR0;
164	/** The second timer (rtcTimerSecond) - R0 Ptr. */
165	PTMTIMERR0 pSecondTimerR0;
166	/** The second second timer (rtcTimerSecond2) - R0 Ptr. */
167	PTMTIMERR0 pSecondTimer2R0;
168
169	/** Pointer to the device instance - RC Ptr. */
170	PPDMDEVINSRC pDevInsRC;
171	/** The periodic timer (rtcTimerPeriodic) - RC Ptr. */
172	PTMTIMERRC pPeriodicTimerRC;
173	/** The second timer (rtcTimerSecond) - RC Ptr. */
174	PTMTIMERRC pSecondTimerRC;
175	/** The second second timer (rtcTimerSecond2) - RC Ptr. */
176	PTMTIMERRC pSecondTimer2RC;
177
178	/** The RTC registration structure. */
179	PDMRTCREG RtcReg;
180	/** The RTC device helpers. */
181	R3PTRTYPE(PCPDMRTCHLP) pRtcHlpR3;
182	/** Number of release log entries. Used to prevent flooding. */
183	uint32_t cRelLogEntries;
184	/** The current/previous logged timer period. */
185	int32_t CurLogPeriod;
186	/** The current/previous hinted timer period. */
187	int32_t CurHintPeriod;
188	/** How many consecutive times the UIP has been seen. */
189	int32_t cUipSeen;
190
191	/** HPET legacy mode notification interface. */
192	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
193
194	/** Number of IRQs that's been raised. */
195	STAMCOUNTER StatRTCIrq;
196	/** Number of times the timer callback handler ran. */
197	STAMCOUNTER StatRTCTimerCB;
198	} RTCSTATE;
199	/** Pointer to the RTC device state. */
200	typedef RTCSTATE *PRTCSTATE;
201
202	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
203
204	static void rtc_timer_update(PRTCSTATE pThis, int64_t current_time)
205	{
206	int period_code, period;
207	uint64_t cur_clock, next_irq_clock;
208	uint32_t freq;
209
210	Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPeriodicTimer)));
211	Assert(PDMCritSectIsOwner(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo)));
212
213	period_code = pThis->cmos_data[RTC_REG_A] & 0x0f;
214	if ( period_code != 0
215	&& (pThis->cmos_data[RTC_REG_B] & REG_B_PIE))
216	{
217	if (period_code <= 2)
218	period_code += 7;
219	/* period in 32 kHz cycles */
220	period = 1 << (period_code - 1);
221	/* compute 32 kHz clock */
222	freq = TMTimerGetFreq(pThis->CTX_SUFF(pPeriodicTimer));
223
224	cur_clock = ASMMultU64ByU32DivByU32(current_time, 32768, freq);
225	next_irq_clock = (cur_clock & ~(uint64_t)(period - 1)) + period;
226	pThis->next_periodic_time = ASMMultU64ByU32DivByU32(next_irq_clock, freq, 32768) + 1;
227	TMTimerSet(pThis->CTX_SUFF(pPeriodicTimer), pThis->next_periodic_time);
228
229	#ifdef IN_RING3
230	if (RT_UNLIKELY(period != pThis->CurLogPeriod))
231	#else
232	if (RT_UNLIKELY(period != pThis->CurHintPeriod))
233	#endif
234	{
235	#ifdef IN_RING3
236	if (pThis->cRelLogEntries++ < 64)
237	LogRel(("RTC: period=%#x (%d) %u Hz\n", period, period, _32K / period));
238	pThis->CurLogPeriod = period;
239	#endif
240	pThis->CurHintPeriod = period;
241	TMTimerSetFrequencyHint(pThis->CTX_SUFF(pPeriodicTimer), _32K / period);
242	}
243	}
244	else
245	{
246	#ifdef IN_RING3
247	if (TMTimerIsActive(pThis->CTX_SUFF(pPeriodicTimer)) && pThis->cRelLogEntries++ < 64)
248	LogRel(("RTC: stopped the periodic timer\n"));
249	#endif
250	TMTimerStop(pThis->CTX_SUFF(pPeriodicTimer));
251	}
252	}
253
254
255	static void rtc_raise_irq(PRTCSTATE pThis, uint32_t iLevel)
256	{
257	if (!pThis->fDisabledByHpet)
258	{
259	PDMDevHlpISASetIrq(pThis->CTX_SUFF(pDevIns), pThis->irq, iLevel);
260	if (iLevel)
261	STAM_COUNTER_INC(&pThis->StatRTCIrq);
262	}
263	}
264
265
266	#ifdef IN_RING3
267	DECLINLINE(int) to_bcd(PRTCSTATE pThis, int a)
268	{
269	if (pThis->cmos_data[RTC_REG_B] & 0x04)
270	return a;
271	return ((a / 10) << 4) \| (a % 10);
272	}
273	#endif
274
275
276	DECLINLINE(int) from_bcd(PRTCSTATE pThis, int a)
277	{
278	if (pThis->cmos_data[RTC_REG_B] & 0x04)
279	return a;
280	return ((a >> 4) * 10) + (a & 0x0f);
281	}
282
283
284	static void rtc_set_time(PRTCSTATE pThis)
285	{
286	struct my_tm *tm = &pThis->current_tm;
287
288	tm->tm_sec = from_bcd(pThis, pThis->cmos_data[RTC_SECONDS]);
289	tm->tm_min = from_bcd(pThis, pThis->cmos_data[RTC_MINUTES]);
290	tm->tm_hour = from_bcd(pThis, pThis->cmos_data[RTC_HOURS] & 0x7f);
291	if (!(pThis->cmos_data[RTC_REG_B] & 0x02))
292	{
293	tm->tm_hour %= 12;
294	if (pThis->cmos_data[RTC_HOURS] & 0x80)
295	tm->tm_hour += 12;
296	}
297	tm->tm_wday = from_bcd(pThis, pThis->cmos_data[RTC_DAY_OF_WEEK]);
298	tm->tm_mday = from_bcd(pThis, pThis->cmos_data[RTC_DAY_OF_MONTH]);
299	tm->tm_mon = from_bcd(pThis, pThis->cmos_data[RTC_MONTH]) - 1;
300	tm->tm_year = from_bcd(pThis, pThis->cmos_data[RTC_YEAR]) + 100;
301	}
302
303
304	/* -=-=-=-=-=- I/O Port Handlers -=-=-=-=-=- */
305
306
307	/**
308	* @callback_method_impl{FNIOMIOPORTIN}
309	*/
310	PDMBOTHCBDECL(int) rtcIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
311	{
312	NOREF(pvUser);
313	if (cb != 1)
314	return VERR_IOM_IOPORT_UNUSED;
315
316	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
317	if ((uPort & 1) == 0)
318	*pu32 = 0xff;
319	else
320	{
321	unsigned bank = (uPort >> 1) & 1;
322	switch (pThis->cmos_index[bank])
323	{
324	case RTC_SECONDS:
325	case RTC_MINUTES:
326	case RTC_HOURS:
327	case RTC_DAY_OF_WEEK:
328	case RTC_DAY_OF_MONTH:
329	case RTC_MONTH:
330	case RTC_YEAR:
331	*pu32 = pThis->cmos_data[pThis->cmos_index[0]];
332	break;
333
334	case RTC_REG_A:
335	if (pThis->cmos_data[RTC_REG_A] & REG_A_UIP)
336	++pThis->cUipSeen;
337	else
338	pThis->cUipSeen = 0;
339	if (pThis->cUipSeen >= 250)
340	{
341	pThis->cmos_data[pThis->cmos_index[0]] &= ~REG_A_UIP;
342	pThis->cUipSeen = 0;
343	}
344	*pu32 = pThis->cmos_data[pThis->cmos_index[0]];
345	break;
346
347	case RTC_REG_C:
348	*pu32 = pThis->cmos_data[pThis->cmos_index[0]];
349	rtc_raise_irq(pThis, 0);
350	pThis->cmos_data[RTC_REG_C] = 0x00;
351	break;
352
353	default:
354	*pu32 = pThis->cmos_data[pThis->cmos_index[bank]];
355	break;
356	}
357
358	Log(("CMOS: Read bank %d idx %#04x: %#04x\n", bank, pThis->cmos_index[bank], *pu32));
359	}
360
361	return VINF_SUCCESS;
362	}
363
364
365	/**
366	* @callback_method_impl{FNIOMIOPORTOUT}
367	*/
368	PDMBOTHCBDECL(int) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
369	{
370	NOREF(pvUser);
371	if (cb != 1)
372	return VINF_SUCCESS;
373
374	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
375	uint32_t bank = (uPort >> 1) & 1;
376	if ((uPort & 1) == 0)
377	{
378	pThis->cmos_index[bank] = (u32 & 0x7f) + (bank * CMOS_BANK_SIZE);
379
380	/* HACK ALERT! Attempt to trigger VM_FF_TIMER and/or VM_FF_TM_VIRTUAL_SYNC
381	for forcing the pSecondTimer2 timer to run be run and clear UIP in
382	a timely fashion. */
383	if (u32 == RTC_REG_A)
384	TMTimerGet(pThis->CTX_SUFF(pSecondTimer));
385	}
386	else
387	{
388	Log(("CMOS: Write bank %d idx %#04x: %#04x (old %#04x)\n", bank,
389	pThis->cmos_index[bank], u32, pThis->cmos_data[pThis->cmos_index[bank]]));
390
391	int const idx = pThis->cmos_index[bank];
392	switch (idx)
393	{
394	case RTC_SECONDS_ALARM:
395	case RTC_MINUTES_ALARM:
396	case RTC_HOURS_ALARM:
397	pThis->cmos_data[pThis->cmos_index[0]] = u32;
398	break;
399
400	case RTC_SECONDS:
401	case RTC_MINUTES:
402	case RTC_HOURS:
403	case RTC_DAY_OF_WEEK:
404	case RTC_DAY_OF_MONTH:
405	case RTC_MONTH:
406	case RTC_YEAR:
407	pThis->cmos_data[pThis->cmos_index[0]] = u32;
408	/* if in set mode, do not update the time */
409	if (!(pThis->cmos_data[RTC_REG_B] & REG_B_SET))
410	rtc_set_time(pThis);
411	break;
412
413	case RTC_REG_A:
414	case RTC_REG_B:
415	{
416	/* We need to acquire the clock lock, because of lock ordering
417	issues this means having to release the device lock. Since
418	we're letting IOM do the locking, we must not return without
419	holding the device lock.*/
420	PDMCritSectLeave(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo));
421	int rc1 = TMTimerLock(pThis->CTX_SUFF(pPeriodicTimer), VINF_SUCCESS /* must get it */);
422	int rc2 = PDMCritSectEnter(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS /* must get it */);
423	AssertRCReturn(rc1, rc1);
424	AssertRCReturnStmt(rc2, TMTimerUnlock(pThis->CTX_SUFF(pPeriodicTimer)), rc2);
425
426	if (idx == RTC_REG_A)
427	{
428	/* UIP bit is read only */
429	pThis->cmos_data[RTC_REG_A] = (u32 & ~REG_A_UIP)
430	\| (pThis->cmos_data[RTC_REG_A] & REG_A_UIP);
431	}
432	else
433	{
434	if (u32 & REG_B_SET)
435	{
436	/* set mode: reset UIP mode */
437	pThis->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
438	#if 0 /* This is probably wrong as it breaks changing the time/date in OS/2. */
439	u32 &= ~REG_B_UIE;
440	#endif
441	}
442	else
443	{
444	/* if disabling set mode, update the time */
445	if (pThis->cmos_data[RTC_REG_B] & REG_B_SET)
446	rtc_set_time(pThis);
447	}
448	pThis->cmos_data[RTC_REG_B] = u32;
449	}
450
451	rtc_timer_update(pThis, TMTimerGet(pThis->CTX_SUFF(pPeriodicTimer)));
452
453	TMTimerUnlock(pThis->CTX_SUFF(pPeriodicTimer));
454	/* the caller leaves the other lock. */
455	break;
456	}
457
458	case RTC_REG_C:
459	case RTC_REG_D:
460	/* cannot write to them */
461	break;
462
463	default:
464	pThis->cmos_data[pThis->cmos_index[bank]] = u32;
465	break;
466	}
467	}
468
469	return VINF_SUCCESS;
470	}
471
472	#ifdef IN_RING3
473
474	/* -=-=-=-=-=- Debug Info Handlers -=-=-=-=-=- */
475
476	/**
477	* @callback_method_impl{FNDBGFHANDLERDEV,
478	* Dumps the cmos Bank Info.}
479	*/
480	static DECLCALLBACK(void) rtcCmosBankInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
481	{
482	RT_NOREF1(pszArgs);
483	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
484
485	pHlp->pfnPrintf(pHlp,
486	"First CMOS bank, offsets 0x0E - 0x7F\n"
487	"Offset %02x : --- use 'info rtc' to show CMOS clock ---", 0);
488	for (unsigned iCmos = CMOS_BANK_LOWER_LIMIT; iCmos <= CMOS_BANK_UPPER_LIMIT; iCmos++)
489	{
490	if ((iCmos & 15) == 0)
491	pHlp->pfnPrintf(pHlp, "Offset %02x : %02x", iCmos, pThis->cmos_data[iCmos]);
492	else if ((iCmos & 15) == 8)
493	pHlp->pfnPrintf(pHlp, "-%02x", pThis->cmos_data[iCmos]);
494	else if ((iCmos & 15) == 15)
495	pHlp->pfnPrintf(pHlp, " %02x\n", pThis->cmos_data[iCmos]);
496	else
497	pHlp->pfnPrintf(pHlp, " %02x", pThis->cmos_data[iCmos]);
498	}
499	}
500
501	/**
502	* @callback_method_impl{FNDBGFHANDLERDEV,
503	* Dumps the cmos Bank2 Info.}
504	*/
505	static DECLCALLBACK(void) rtcCmosBank2Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
506	{
507	RT_NOREF1(pszArgs);
508	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
509
510	pHlp->pfnPrintf(pHlp, "Second CMOS bank, offsets 0x80 - 0xFF\n");
511	for (uint16_t iCmos = CMOS_BANK2_LOWER_LIMIT; iCmos <= CMOS_BANK2_UPPER_LIMIT; iCmos++)
512	{
513	if ((iCmos & 15) == 0)
514	pHlp->pfnPrintf(pHlp, "Offset %02x : %02x", iCmos, pThis->cmos_data[iCmos]);
515	else if ((iCmos & 15) == 8)
516	pHlp->pfnPrintf(pHlp, "-%02x", pThis->cmos_data[iCmos]);
517	else if ((iCmos & 15) == 15)
518	pHlp->pfnPrintf(pHlp, " %02x\n", pThis->cmos_data[iCmos]);
519	else
520	pHlp->pfnPrintf(pHlp, " %02x", pThis->cmos_data[iCmos]);
521	}
522	}
523
524	/**
525	* @callback_method_impl{FNDBGFHANDLERDEV,
526	* Dumps the cmos RTC Info.}
527	*/
528	static DECLCALLBACK(void) rtcCmosClockInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
529	{
530	RT_NOREF1(pszArgs);
531	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
532	uint8_t u8Sec = from_bcd(pThis, pThis->cmos_data[RTC_SECONDS]);
533	uint8_t u8Min = from_bcd(pThis, pThis->cmos_data[RTC_MINUTES]);
534	uint8_t u8Hr = from_bcd(pThis, pThis->cmos_data[RTC_HOURS] & 0x7f);
535	if ( !(pThis->cmos_data[RTC_REG_B] & 0x02)
536	&& (pThis->cmos_data[RTC_HOURS] & 0x80))
537	u8Hr += 12;
538	uint8_t u8Day = from_bcd(pThis, pThis->cmos_data[RTC_DAY_OF_MONTH]);
539	uint8_t u8Month = from_bcd(pThis, pThis->cmos_data[RTC_MONTH]) ;
540	uint8_t u8Year = from_bcd(pThis, pThis->cmos_data[RTC_YEAR]);
541	pHlp->pfnPrintf(pHlp, "Time: %02u:%02u:%02u Date: %02u-%02u-%02u\n",
542	u8Hr, u8Min, u8Sec, u8Year, u8Month, u8Day);
543	pHlp->pfnPrintf(pHlp, "REG A=%02x B=%02x C=%02x D=%02x\n",
544	pThis->cmos_data[RTC_REG_A], pThis->cmos_data[RTC_REG_B],
545	pThis->cmos_data[RTC_REG_C], pThis->cmos_data[RTC_REG_D]);
546	}
547
548
549
550	/* -=-=-=-=-=- Timers and their support code -=-=-=-=-=- */
551
552
553	/**
554	* @callback_method_impl{FNTMTIMERDEV, periodic}
555	*/
556	static DECLCALLBACK(void) rtcTimerPeriodic(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
557	{
558	RT_NOREF2(pTimer, pvUser);
559	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
560	Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPeriodicTimer)));
561	Assert(PDMCritSectIsOwner(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo)));
562
563	rtc_timer_update(pThis, pThis->next_periodic_time);
564	STAM_COUNTER_INC(&pThis->StatRTCTimerCB);
565	pThis->cmos_data[RTC_REG_C] \|= 0xc0;
566
567	rtc_raise_irq(pThis, 1);
568	}
569
570
571	/* month is between 0 and 11. */
572	static int get_days_in_month(int month, int year)
573	{
574	static const int days_tab[12] =
575	{
576	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
577	};
578	int d;
579
580	if ((unsigned )month >= 12)
581	return 31;
582
583	d = days_tab[month];
584	if (month == 1)
585	{
586	if ((year % 4) == 0 && ((year % 100) != 0 \|\| (year % 400) == 0))
587	d++;
588	}
589	return d;
590	}
591
592
593	/* update 'tm' to the next second */
594	static void rtc_next_second(struct my_tm *tm)
595	{
596	int days_in_month;
597
598	tm->tm_sec++;
599	if ((unsigned)tm->tm_sec >= 60)
600	{
601	tm->tm_sec = 0;
602	tm->tm_min++;
603	if ((unsigned)tm->tm_min >= 60)
604	{
605	tm->tm_min = 0;
606	tm->tm_hour++;
607	if ((unsigned)tm->tm_hour >= 24)
608	{
609	tm->tm_hour = 0;
610	/* next day */
611	tm->tm_wday++;
612	if ((unsigned)tm->tm_wday >= 7)
613	tm->tm_wday = 0;
614	days_in_month = get_days_in_month(tm->tm_mon,
615	tm->tm_year + 1900);
616	tm->tm_mday++;
617	if (tm->tm_mday < 1)
618	tm->tm_mday = 1;
619	else if (tm->tm_mday > days_in_month)
620	{
621	tm->tm_mday = 1;
622	tm->tm_mon++;
623	if (tm->tm_mon >= 12)
624	{
625	tm->tm_mon = 0;
626	tm->tm_year++;
627	}
628	}
629	}
630	}
631	}
632	}
633
634
635	/**
636	* @callback_method_impl{FNTMTIMERDEV, Second timer.}
637	*/
638	static DECLCALLBACK(void) rtcTimerSecond(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
639	{
640	RT_NOREF2(pTimer, pvUser);
641	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
642	Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPeriodicTimer)));
643	Assert(PDMCritSectIsOwner(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo)));
644
645	/* if the oscillator is not in normal operation, we do not update */
646	if ((pThis->cmos_data[RTC_REG_A] & 0x70) != 0x20)
647	{
648	pThis->next_second_time += TMTimerGetFreq(pThis->CTX_SUFF(pSecondTimer));
649	TMTimerSet(pThis->CTX_SUFF(pSecondTimer), pThis->next_second_time);
650	}
651	else
652	{
653	rtc_next_second(&pThis->current_tm);
654
655	if (!(pThis->cmos_data[RTC_REG_B] & REG_B_SET))
656	{
657	/* update in progress bit */
658	Log2(("RTC: UIP %x -> 1\n", !!(pThis->cmos_data[RTC_REG_A] & REG_A_UIP)));
659	pThis->cmos_data[RTC_REG_A] \|= REG_A_UIP;
660	}
661
662	/* 244140 ns = 8 / 32768 seconds */
663	uint64_t delay = TMTimerFromNano(pThis->CTX_SUFF(pSecondTimer2), 244140);
664	TMTimerSet(pThis->CTX_SUFF(pSecondTimer2), pThis->next_second_time + delay);
665	}
666	}
667
668
669	/* Used by rtc_set_date and rtcTimerSecond2. */
670	static void rtc_copy_date(PRTCSTATE pThis)
671	{
672	const struct my_tm *tm = &pThis->current_tm;
673
674	pThis->cmos_data[RTC_SECONDS] = to_bcd(pThis, tm->tm_sec);
675	pThis->cmos_data[RTC_MINUTES] = to_bcd(pThis, tm->tm_min);
676	if (pThis->cmos_data[RTC_REG_B] & 0x02)
677	{
678	/* 24 hour format */
679	pThis->cmos_data[RTC_HOURS] = to_bcd(pThis, tm->tm_hour);
680	}
681	else
682	{
683	/* 12 hour format */
684	int h = tm->tm_hour % 12;
685	pThis->cmos_data[RTC_HOURS] = to_bcd(pThis, h ? h : 12);
686	if (tm->tm_hour >= 12)
687	pThis->cmos_data[RTC_HOURS] \|= 0x80;
688	}
689	pThis->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(pThis, tm->tm_wday);
690	pThis->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(pThis, tm->tm_mday);
691	pThis->cmos_data[RTC_MONTH] = to_bcd(pThis, tm->tm_mon + 1);
692	pThis->cmos_data[RTC_YEAR] = to_bcd(pThis, tm->tm_year % 100);
693	}
694
695
696	/**
697	* @callback_method_impl{FNTMTIMERDEV, Second2 timer.}
698	*/
699	static DECLCALLBACK(void) rtcTimerSecond2(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
700	{
701	RT_NOREF2(pTimer, pvUser);
702	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
703	Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPeriodicTimer)));
704	Assert(PDMCritSectIsOwner(pThis->CTX_SUFF(pDevIns)->CTX_SUFF(pCritSectRo)));
705
706	if (!(pThis->cmos_data[RTC_REG_B] & REG_B_SET))
707	rtc_copy_date(pThis);
708
709	/* check alarm */
710	if (pThis->cmos_data[RTC_REG_B] & REG_B_AIE)
711	{
712	if ( ( (pThis->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0
713	\|\| from_bcd(pThis, pThis->cmos_data[RTC_SECONDS_ALARM]) == pThis->current_tm.tm_sec)
714	&& ( (pThis->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0
715	\|\| from_bcd(pThis, pThis->cmos_data[RTC_MINUTES_ALARM]) == pThis->current_tm.tm_min)
716	&& ( (pThis->cmos_data[RTC_HOURS_ALARM ] & 0xc0) == 0xc0
717	\|\| from_bcd(pThis, pThis->cmos_data[RTC_HOURS_ALARM ]) == pThis->current_tm.tm_hour)
718	)
719	{
720	pThis->cmos_data[RTC_REG_C] \|= 0xa0;
721	rtc_raise_irq(pThis, 1);
722	}
723	}
724
725	/* update ended interrupt */
726	if (pThis->cmos_data[RTC_REG_B] & REG_B_UIE)
727	{
728	pThis->cmos_data[RTC_REG_C] \|= 0x90;
729	rtc_raise_irq(pThis, 1);
730	}
731
732	/* clear update in progress bit */
733	Log2(("RTC: UIP %x -> 0\n", !!(pThis->cmos_data[RTC_REG_A] & REG_A_UIP)));
734	pThis->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
735
736	pThis->next_second_time += TMTimerGetFreq(pThis->CTX_SUFF(pSecondTimer));
737	TMTimerSet(pThis->CTX_SUFF(pSecondTimer), pThis->next_second_time);
738	}
739
740
741	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
742
743
744	/**
745	* @callback_method_impl{FNSSMDEVLIVEEXEC}
746	*/
747	static DECLCALLBACK(int) rtcLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
748	{
749	RT_NOREF1(uPass);
750	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
751
752	SSMR3PutU8( pSSM, pThis->irq);
753	SSMR3PutIOPort(pSSM, pThis->IOPortBase);
754	SSMR3PutBool( pSSM, pThis->fUTC);
755
756	return VINF_SSM_DONT_CALL_AGAIN;
757	}
758
759
760	/**
761	* @callback_method_impl{FNSSMDEVSAVEEXEC}
762	*/
763	static DECLCALLBACK(int) rtcSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
764	{
765	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
766
767	/* The config. */
768	rtcLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
769
770	/* The state. */
771	SSMR3PutMem(pSSM, pThis->cmos_data, CMOS_BANK_SIZE);
772	SSMR3PutU8(pSSM, pThis->cmos_index[0]);
773
774	SSMR3PutS32(pSSM, pThis->current_tm.tm_sec);
775	SSMR3PutS32(pSSM, pThis->current_tm.tm_min);
776	SSMR3PutS32(pSSM, pThis->current_tm.tm_hour);
777	SSMR3PutS32(pSSM, pThis->current_tm.tm_wday);
778	SSMR3PutS32(pSSM, pThis->current_tm.tm_mday);
779	SSMR3PutS32(pSSM, pThis->current_tm.tm_mon);
780	SSMR3PutS32(pSSM, pThis->current_tm.tm_year);
781
782	TMR3TimerSave(pThis->CTX_SUFF(pPeriodicTimer), pSSM);
783
784	SSMR3PutS64(pSSM, pThis->next_periodic_time);
785
786	SSMR3PutS64(pSSM, pThis->next_second_time);
787	TMR3TimerSave(pThis->CTX_SUFF(pSecondTimer), pSSM);
788	TMR3TimerSave(pThis->CTX_SUFF(pSecondTimer2), pSSM);
789
790	SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
791
792	SSMR3PutMem(pSSM, &pThis->cmos_data[CMOS_BANK_SIZE], CMOS_BANK_SIZE);
793	return SSMR3PutU8(pSSM, pThis->cmos_index[1]);
794	}
795
796
797	/**
798	* @callback_method_impl{FNSSMDEVLOADEXEC}
799	*/
800	static DECLCALLBACK(int) rtcLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
801	{
802	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
803	int rc;
804
805	if ( uVersion != RTC_SAVED_STATE_VERSION
806	&& uVersion != RTC_SAVED_STATE_VERSION_VBOX_32PRE
807	&& uVersion != RTC_SAVED_STATE_VERSION_VBOX_31
808	&& uVersion != RTC_SAVED_STATE_VERSION_VBOX_30)
809	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
810
811	/* The config. */
812	if (uVersion > RTC_SAVED_STATE_VERSION_VBOX_30)
813	{
814	uint8_t u8Irq;
815	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
816	if (u8Irq != pThis->irq)
817	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"), u8Irq, pThis->irq);
818
819	RTIOPORT IOPortBase;
820	rc = SSMR3GetIOPort(pSSM, &IOPortBase); AssertRCReturn(rc, rc);
821	if (IOPortBase != pThis->IOPortBase)
822	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBase: saved=%RTiop config=%RTiop"), IOPortBase, pThis->IOPortBase);
823
824	bool fUTC;
825	rc = SSMR3GetBool(pSSM, &fUTC); AssertRCReturn(rc, rc);
826	if (fUTC != pThis->fUTC)
827	LogRel(("RTC: Config mismatch - fUTC: saved=%RTbool config=%RTbool\n", fUTC, pThis->fUTC));
828	}
829
830	if (uPass != SSM_PASS_FINAL)
831	return VINF_SUCCESS;
832
833	/* The state. */
834	SSMR3GetMem(pSSM, pThis->cmos_data, CMOS_BANK_SIZE);
835	SSMR3GetU8(pSSM, &pThis->cmos_index[0]);
836
837	SSMR3GetS32(pSSM, &pThis->current_tm.tm_sec);
838	SSMR3GetS32(pSSM, &pThis->current_tm.tm_min);
839	SSMR3GetS32(pSSM, &pThis->current_tm.tm_hour);
840	SSMR3GetS32(pSSM, &pThis->current_tm.tm_wday);
841	SSMR3GetS32(pSSM, &pThis->current_tm.tm_mday);
842	SSMR3GetS32(pSSM, &pThis->current_tm.tm_mon);
843	SSMR3GetS32(pSSM, &pThis->current_tm.tm_year);
844
845	TMR3TimerLoad(pThis->CTX_SUFF(pPeriodicTimer), pSSM);
846
847	SSMR3GetS64(pSSM, &pThis->next_periodic_time);
848
849	SSMR3GetS64(pSSM, &pThis->next_second_time);
850	TMR3TimerLoad(pThis->CTX_SUFF(pSecondTimer), pSSM);
851	TMR3TimerLoad(pThis->CTX_SUFF(pSecondTimer2), pSSM);
852
853	if (uVersion > RTC_SAVED_STATE_VERSION_VBOX_31)
854	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
855
856	if (uVersion > RTC_SAVED_STATE_VERSION_VBOX_32PRE)
857	{
858	/* Second CMOS bank. */
859	SSMR3GetMem(pSSM, &pThis->cmos_data[CMOS_BANK_SIZE], CMOS_BANK_SIZE);
860	SSMR3GetU8(pSSM, &pThis->cmos_index[1]);
861	}
862
863	int period_code = pThis->cmos_data[RTC_REG_A] & 0x0f;
864	if ( period_code != 0
865	&& (pThis->cmos_data[RTC_REG_B] & REG_B_PIE))
866	{
867	if (period_code <= 2)
868	period_code += 7;
869	int period = 1 << (period_code - 1);
870	LogRel(("RTC: period=%#x (%d) %u Hz (restore)\n", period, period, _32K / period));
871	PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VINF_SUCCESS);
872	TMTimerSetFrequencyHint(pThis->CTX_SUFF(pPeriodicTimer), _32K / period);
873	PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
874	pThis->CurLogPeriod = period;
875	pThis->CurHintPeriod = period;
876	}
877	else
878	{
879	LogRel(("RTC: stopped the periodic timer (restore)\n"));
880	pThis->CurLogPeriod = 0;
881	pThis->CurHintPeriod = 0;
882	}
883	pThis->cRelLogEntries = 0;
884
885	return VINF_SUCCESS;
886	}
887
888
889	/* -=-=-=-=-=- PDM Interface provided by the RTC device -=-=-=-=-=- */
890
891	/**
892	* Calculate and update the standard CMOS checksum.
893	*
894	* @param pThis Pointer to the RTC state data.
895	*/
896	static void rtcCalcCRC(PRTCSTATE pThis)
897	{
898	uint16_t u16 = 0;
899	for (unsigned i = RTC_CRC_START; i <= RTC_CRC_LAST; i++)
900	u16 += pThis->cmos_data[i];
901
902	pThis->cmos_data[RTC_CRC_LOW] = u16 & 0xff;
903	pThis->cmos_data[RTC_CRC_HIGH] = (u16 >> 8) & 0xff;
904	}
905
906
907	/**
908	* @interface_method_impl{PDMRTCREG,pfnWrite}
909	*/
910	static DECLCALLBACK(int) rtcCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
911	{
912	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
913	Assert(PDMCritSectIsOwner(pDevIns->pCritSectRoR3));
914	if (iReg < RT_ELEMENTS(pThis->cmos_data))
915	{
916	pThis->cmos_data[iReg] = u8Value;
917
918	/* does it require checksum update? */
919	if ( iReg >= RTC_CRC_START
920	&& iReg <= RTC_CRC_LAST)
921	rtcCalcCRC(pThis);
922
923	return VINF_SUCCESS;
924	}
925
926	AssertMsgFailed(("iReg=%d\n", iReg));
927	return VERR_INVALID_PARAMETER;
928	}
929
930
931	/**
932	* @interface_method_impl{PDMRTCREG,pfnRead}
933	*/
934	static DECLCALLBACK(int) rtcCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
935	{
936	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
937	Assert(PDMCritSectIsOwner(pDevIns->pCritSectRoR3));
938
939	if (iReg < RT_ELEMENTS(pThis->cmos_data))
940	{
941	*pu8Value = pThis->cmos_data[iReg];
942	return VINF_SUCCESS;
943	}
944	AssertMsgFailed(("iReg=%d\n", iReg));
945	return VERR_INVALID_PARAMETER;
946	}
947
948
949	/**
950	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
951	*/
952	static DECLCALLBACK(void) rtcHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
953	{
954	PRTCSTATE pThis = RT_FROM_MEMBER(pInterface, RTCSTATE, IHpetLegacyNotify);
955	PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VERR_IGNORED);
956
957	pThis->fDisabledByHpet = fActivated;
958
959	PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
960	}
961
962
963
964	/* -=-=-=-=-=- IBase -=-=-=-=-=- */
965
966	/**
967	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
968	*/
969	static DECLCALLBACK(void ) rtcQueryInterface(PPDMIBASE pInterface, const char pszIID)
970	{
971	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
972	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
973	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
974	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
975	return NULL;
976	}
977
978
979	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
980
981	static void rtc_set_memory(PRTCSTATE pThis, int addr, int val)
982	{
983	if (addr >= 0 && addr <= 127)
984	pThis->cmos_data[addr] = val;
985	}
986
987
988	static void rtc_set_date(PRTCSTATE pThis, const struct my_tm *tm)
989	{
990	pThis->current_tm = *tm;
991	rtc_copy_date(pThis);
992	}
993
994
995	/**
996	* @interface_method_impl{PDMDEVREG,pfnInitComplete}
997	*
998	* Used to set the clock.
999	*/
1000	static DECLCALLBACK(int) rtcInitComplete(PPDMDEVINS pDevIns)
1001	{
1002	/** @todo this should be (re)done at power on if we didn't load a state... */
1003	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
1004
1005	/*
1006	* Set the CMOS date/time.
1007	*/
1008	RTTIMESPEC Now;
1009	PDMDevHlpTMUtcNow(pDevIns, &Now);
1010	RTTIME Time;
1011	if (pThis->fUTC)
1012	RTTimeExplode(&Time, &Now);
1013	else
1014	RTTimeLocalExplode(&Time, &Now);
1015
1016	struct my_tm Tm;
1017	memset(&Tm, 0, sizeof(Tm));
1018	Tm.tm_year = Time.i32Year - 1900;
1019	Tm.tm_mon = Time.u8Month - 1;
1020	Tm.tm_mday = Time.u8MonthDay;
1021	Tm.tm_wday = (Time.u8WeekDay + 1 + 7) % 7; /* 0 = Monday -> Sunday */
1022	Tm.tm_yday = Time.u16YearDay - 1;
1023	Tm.tm_hour = Time.u8Hour;
1024	Tm.tm_min = Time.u8Minute;
1025	Tm.tm_sec = Time.u8Second;
1026
1027	rtc_set_date(pThis, &Tm);
1028
1029	int iYear = to_bcd(pThis, (Tm.tm_year / 100) + 19); /* tm_year is 1900 based */
1030	rtc_set_memory(pThis, 0x32, iYear); /* 32h - Century Byte (BCD value for the century */
1031	rtc_set_memory(pThis, 0x37, iYear); /* 37h - (IBM PS/2) Date Century Byte */
1032
1033	/*
1034	* Recalculate the checksum just in case.
1035	*/
1036	rtcCalcCRC(pThis);
1037
1038	Log(("CMOS bank 0: \n%16.128Rhxd\n", &pThis->cmos_data[0]));
1039	Log(("CMOS bank 1: \n%16.128Rhxd\n", &pThis->cmos_data[CMOS_BANK_SIZE]));
1040	return VINF_SUCCESS;
1041	}
1042
1043
1044	/**
1045	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1046	*/
1047	static DECLCALLBACK(void) rtcRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1048	{
1049	RT_NOREF1(offDelta);
1050	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
1051
1052	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1053	pThis->pPeriodicTimerRC = TMTimerRCPtr(pThis->pPeriodicTimerR3);
1054	pThis->pSecondTimerRC = TMTimerRCPtr(pThis->pSecondTimerR3);
1055	pThis->pSecondTimer2RC = TMTimerRCPtr(pThis->pSecondTimer2R3);
1056	}
1057
1058
1059	/**
1060	* @interface_method_impl{PDMDEVREG,pfnReset}
1061	*/
1062	static DECLCALLBACK(void) rtcReset(PPDMDEVINS pDevIns)
1063	{
1064	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
1065
1066	/* Reset index values (important for second bank). */
1067	pThis->cmos_index[0] = 0;
1068	pThis->cmos_index[1] = CMOS_BANK_SIZE; /* Point to start of second bank. */
1069	}
1070
1071
1072	/**
1073	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1074	*/
1075	static DECLCALLBACK(int) rtcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1076	{
1077	RT_NOREF1(iInstance);
1078	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1079	PRTCSTATE pThis = PDMINS_2_DATA(pDevIns, PRTCSTATE);
1080	int rc;
1081	Assert(iInstance == 0);
1082
1083	/*
1084	* Validate configuration.
1085	*/
1086	if (!CFGMR3AreValuesValid(pCfg,
1087	"Irq\0"
1088	"Base\0"
1089	"UseUTC\0"
1090	"RCEnabled\0"
1091	"R0Enabled\0"))
1092	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1093
1094	/*
1095	* Init the data.
1096	*/
1097	uint8_t u8Irq;
1098	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 8);
1099	if (RT_FAILURE(rc))
1100	return PDMDEV_SET_ERROR(pDevIns, rc,
1101	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1102	pThis->irq = u8Irq;
1103
1104	rc = CFGMR3QueryPortDef(pCfg, "Base", &pThis->IOPortBase, 0x70);
1105	if (RT_FAILURE(rc))
1106	return PDMDEV_SET_ERROR(pDevIns, rc,
1107	N_("Configuration error: Querying \"Base\" as a RTIOPORT failed"));
1108
1109	rc = CFGMR3QueryBoolDef(pCfg, "UseUTC", &pThis->fUTC, false);
1110	if (RT_FAILURE(rc))
1111	return PDMDEV_SET_ERROR(pDevIns, rc,
1112	N_("Configuration error: Querying \"UseUTC\" as a bool failed"));
1113
1114	bool fRCEnabled;
1115	rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &fRCEnabled, true);
1116	if (RT_FAILURE(rc))
1117	return PDMDEV_SET_ERROR(pDevIns, rc,
1118	N_("Configuration error: failed to read GCEnabled as boolean"));
1119
1120	bool fR0Enabled;
1121	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1122	if (RT_FAILURE(rc))
1123	return PDMDEV_SET_ERROR(pDevIns, rc,
1124	N_("Configuration error: failed to read R0Enabled as boolean"));
1125
1126	Log(("RTC: Irq=%#x Base=%#x fRCEnabled=%RTbool fR0Enabled=%RTbool\n",
1127	u8Irq, pThis->IOPortBase, fRCEnabled, fR0Enabled));
1128
1129
1130	pThis->pDevInsR3 = pDevIns;
1131	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1132	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1133	pThis->cmos_data[RTC_REG_A] = 0x26;
1134	pThis->cmos_data[RTC_REG_B] = 0x02;
1135	pThis->cmos_data[RTC_REG_C] = 0x00;
1136	pThis->cmos_data[RTC_REG_D] = 0x80;
1137	pThis->RtcReg.u32Version = PDM_RTCREG_VERSION;
1138	pThis->RtcReg.pfnRead = rtcCMOSRead;
1139	pThis->RtcReg.pfnWrite = rtcCMOSWrite;
1140	pThis->fDisabledByHpet = false;
1141	pThis->cmos_index[1] = CMOS_BANK_SIZE; /* Point to start of second bank. */
1142
1143
1144	/* IBase */
1145	pDevIns->IBase.pfnQueryInterface = rtcQueryInterface;
1146	/* IHpetLegacyNotify */
1147	pThis->IHpetLegacyNotify.pfnModeChanged = rtcHpetLegacyNotify_ModeChanged;
1148
1149	/*
1150	* Create timers.
1151	*/
1152	PTMTIMER pTimer;
1153	/* Periodic timer. */
1154	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerPeriodic, pThis,
1155	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "MC146818 RTC/CMOS - Periodic",
1156	&pTimer);
1157	if (RT_FAILURE(rc))
1158	return rc;
1159	pThis->pPeriodicTimerR3 = pTimer;
1160	pThis->pPeriodicTimerR0 = TMTimerR0Ptr(pTimer);
1161	pThis->pPeriodicTimerRC = TMTimerRCPtr(pTimer);
1162
1163	/* Seconds timer. */
1164	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerSecond, pThis,
1165	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "MC146818 RTC/CMOS - Second",
1166	&pTimer);
1167	if (RT_FAILURE(rc))
1168	return rc;
1169	pThis->pSecondTimerR3 = pTimer;
1170	pThis->pSecondTimerR0 = TMTimerR0Ptr(pTimer);
1171	pThis->pSecondTimerRC = TMTimerRCPtr(pTimer);
1172
1173	/* The second2 timer, this is always active. */
1174	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerSecond2, pThis,
1175	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "MC146818 RTC/CMOS - Second2",
1176	&pTimer);
1177	if (RT_FAILURE(rc))
1178	return rc;
1179	pThis->pSecondTimer2R3 = pTimer;
1180	pThis->pSecondTimer2R0 = TMTimerR0Ptr(pTimer);
1181	pThis->pSecondTimer2RC = TMTimerRCPtr(pTimer);
1182	pThis->next_second_time = TMTimerGet(pTimer)
1183	+ (TMTimerGetFreq(pTimer) * 99) / 100;
1184	rc = TMTimerLock(pTimer, VERR_IGNORED);
1185	AssertRCReturn(rc, rc);
1186	rc = TMTimerSet(pTimer, pThis->next_second_time);
1187	TMTimerUnlock(pTimer);
1188	AssertRCReturn(rc, rc);
1189
1190	/*
1191	* Register I/O ports.
1192	*/
1193	rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase, 4, NULL,
1194	rtcIOPortWrite, rtcIOPortRead, NULL, NULL, "MC146818 RTC/CMOS");
1195	if (RT_FAILURE(rc))
1196	return rc;
1197	if (fRCEnabled)
1198	{
1199	rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase, 4, NIL_RTRCPTR,
1200	"rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS");
1201	if (RT_FAILURE(rc))
1202	return rc;
1203	}
1204	if (fR0Enabled)
1205	{
1206	rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase, 4, NIL_RTR0PTR,
1207	"rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS");
1208	if (RT_FAILURE(rc))
1209	return rc;
1210	}
1211
1212	/*
1213	* Register the saved state.
1214	*/
1215	rc = PDMDevHlpSSMRegister3(pDevIns, RTC_SAVED_STATE_VERSION, sizeof(*pThis), rtcLiveExec, rtcSaveExec, rtcLoadExec);
1216	if (RT_FAILURE(rc))
1217	return rc;
1218
1219	/*
1220	* Register ourselves as the RTC/CMOS with PDM.
1221	*/
1222	rc = PDMDevHlpRTCRegister(pDevIns, &pThis->RtcReg, &pThis->pRtcHlpR3);
1223	if (RT_FAILURE(rc))
1224	return rc;
1225
1226	/*
1227	* Register debugger info callback.
1228	*/
1229	PDMDevHlpDBGFInfoRegister(pDevIns, "cmos1", "Display CMOS Bank 1 Info (0x0e-0x7f). No arguments. See also rtc.", rtcCmosBankInfo);
1230	PDMDevHlpDBGFInfoRegister(pDevIns, "cmos2", "Display CMOS Bank 2 Info (0x0e-0x7f). No arguments.", rtcCmosBank2Info);
1231	PDMDevHlpDBGFInfoRegister(pDevIns, "rtc", "Display CMOS RTC (0x00-0x0d). No arguments. See also cmos1 & cmos2", rtcCmosClockInfo);
1232
1233	/*
1234	* Register statistics.
1235	*/
1236	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRTCIrq, STAMTYPE_COUNTER, "/TM/RTC/Irq", STAMUNIT_OCCURENCES, "The number of times a RTC interrupt was triggered.");
1237	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRTCTimerCB, STAMTYPE_COUNTER, "/TM/RTC/TimerCB", STAMUNIT_OCCURENCES, "The number of times the RTC timer callback ran.");
1238
1239	return VINF_SUCCESS;
1240	}
1241
1242
1243	/**
1244	* The device registration structure.
1245	*/
1246	const PDMDEVREG g_DeviceMC146818 =
1247	{
1248	/* u32Version */
1249	PDM_DEVREG_VERSION,
1250	/* szName */
1251	"mc146818",
1252	/* szRCMod */
1253	"VBoxDDRC.rc",
1254	/* szR0Mod */
1255	"VBoxDDR0.r0",
1256	/* pszDescription */
1257	"Motorola MC146818 RTC/CMOS Device.",
1258	/* fFlags */
1259	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1260	/* fClass */
1261	PDM_DEVREG_CLASS_RTC,
1262	/* cMaxInstances */
1263	1,
1264	/* cbInstance */
1265	sizeof(RTCSTATE),
1266	/* pfnConstruct */
1267	rtcConstruct,
1268	/* pfnDestruct */
1269	NULL,
1270	/* pfnRelocate */
1271	rtcRelocate,
1272	/* pfnMemSetup */
1273	NULL,
1274	/* pfnPowerOn */
1275	NULL,
1276	/* pfnReset */
1277	rtcReset,
1278	/* pfnSuspend */
1279	NULL,
1280	/* pfnResume */
1281	NULL,
1282	/* pfnAttach */
1283	NULL,
1284	/* pfnDetach */
1285	NULL,
1286	/* pfnQueryInterface */
1287	NULL,
1288	/* pfnInitComplete */
1289	rtcInitComplete,
1290	/* pfnPowerOff */
1291	NULL,
1292	/* pfnSoftReset */
1293	NULL,
1294	/* u32VersionEnd */
1295	PDM_DEVREG_VERSION
1296	};
1297
1298	#endif /* IN_RING3 */
1299	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1300

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source: vbox/trunk/src/VBox/Devices/PC/DevRTC.cpp@ 64808

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