3c90x.c@ 1300

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1	/*
2	* 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
3	* by Greg Beeley, [email protected]. Modified by Steve Smith,
4	* [email protected]. Alignment bug fix Neil Newell ([email protected]).
5	*
6	* This program Copyright (C) 1999 LightSys Technology Services, Inc.
7	* Portions Copyright (C) 1999 Steve Smith
8	*
9	* This program may be re-distributed in source or binary form, modified,
10	* sold, or copied for any purpose, provided that the above copyright message
11	* and this text are included with all source copies or derivative works, and
12	* provided that the above copyright message and this text are included in the
13	* documentation of any binary-only distributions. This program is distributed
14	* WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
15	* PURPOSE or MERCHANTABILITY. Please read the associated documentation
16	* "3c90x.txt" before compiling and using this driver.
17	*
18	* --------
19	*
20	* Program written with the assistance of the 3com documentation for
21	* the 3c905B-TX card, as well as with some assistance from the 3c59x
22	* driver Donald Becker wrote for the Linux kernel, and with some assistance
23	* from the remainder of the Etherboot distribution.
24	*
25	* REVISION HISTORY:
26	*
27	* v0.10 1-26-1998 GRB Initial implementation.
28	* v0.90 1-27-1998 GRB System works.
29	* v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
30	* v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
31	* Re-wrote poll and transmit for
32	* better error recovery and heavy
33	* network traffic operation
34	* v2.01 5-26-2003 NN Fixed driver alignment issue which
35	* caused system lockups if driver structures
36	* not 8-byte aligned.
37	*
38	*/
39
40	#include "etherboot.h"
41	#include "nic.h"
42	#include "pci.h"
43	#include "timer.h"
44
45	#define XCVR_MAGIC (0x5A00)
46	/** any single transmission fails after 16 collisions or other errors
47	** this is the number of times to retry the transmission -- this should
48	** be plenty
49	**/
50	#define XMIT_RETRIES 250
51
52	/* Register definitions for the 3c905 */
53	enum Registers
54	{
55	regPowerMgmtCtrl_w = 0x7c, / 905B Revision Only /
56	regUpMaxBurst_w = 0x7a, / 905B Revision Only /
57	regDnMaxBurst_w = 0x78, / 905B Revision Only /
58	regDebugControl_w = 0x74, / 905B Revision Only /
59	regDebugData_l = 0x70, / 905B Revision Only /
60	regRealTimeCnt_l = 0x40, / Universal /
61	regUpBurstThresh_b = 0x3e, / 905B Revision Only /
62	regUpPoll_b = 0x3d, / 905B Revision Only /
63	regUpPriorityThresh_b = 0x3c, / 905B Revision Only /
64	regUpListPtr_l = 0x38, / Universal /
65	regCountdown_w = 0x36, / Universal /
66	regFreeTimer_w = 0x34, / Universal /
67	regUpPktStatus_l = 0x30, / Universal with Exception, pg 130 /
68	regTxFreeThresh_b = 0x2f, / 90X Revision Only /
69	regDnPoll_b = 0x2d, / 905B Revision Only /
70	regDnPriorityThresh_b = 0x2c, / 905B Revision Only /
71	regDnBurstThresh_b = 0x2a, / 905B Revision Only /
72	regDnListPtr_l = 0x24, / Universal with Exception, pg 107 /
73	regDmaCtrl_l = 0x20, / Universal with Exception, pg 106 /
74	/ /
75	regIntStatusAuto_w = 0x1e, / 905B Revision Only /
76	regTxStatus_b = 0x1b, / Universal with Exception, pg 113 /
77	regTimer_b = 0x1a, / Universal /
78	regTxPktId_b = 0x18, / 905B Revision Only /
79	regCommandIntStatus_w = 0x0e, / Universal (Command Variations) /
80	};
81
82	/ following are windowed registers /
83	enum Registers7
84	{
85	regPowerMgmtEvent_7_w = 0x0c, / 905B Revision Only /
86	regVlanEtherType_7_w = 0x04, / 905B Revision Only /
87	regVlanMask_7_w = 0x00, / 905B Revision Only /
88	};
89
90	enum Registers6
91	{
92	regBytesXmittedOk_6_w = 0x0c, / Universal /
93	regBytesRcvdOk_6_w = 0x0a, / Universal /
94	regUpperFramesOk_6_b = 0x09, / Universal /
95	regFramesDeferred_6_b = 0x08, / Universal /
96	regFramesRecdOk_6_b = 0x07, / Universal with Exceptions, pg 142 /
97	regFramesXmittedOk_6_b = 0x06, / Universal /
98	regRxOverruns_6_b = 0x05, / Universal /
99	regLateCollisions_6_b = 0x04, / Universal /
100	regSingleCollisions_6_b = 0x03, / Universal /
101	regMultipleCollisions_6_b = 0x02, / Universal /
102	regSqeErrors_6_b = 0x01, / Universal /
103	regCarrierLost_6_b = 0x00, / Universal /
104	};
105
106	enum Registers5
107	{
108	regIndicationEnable_5_w = 0x0c, / Universal /
109	regInterruptEnable_5_w = 0x0a, / Universal /
110	regTxReclaimThresh_5_b = 0x09, / 905B Revision Only /
111	regRxFilter_5_b = 0x08, / Universal /
112	regRxEarlyThresh_5_w = 0x06, / Universal /
113	regTxStartThresh_5_w = 0x00, / Universal /
114	};
115
116	enum Registers4
117	{
118	regUpperBytesOk_4_b = 0x0d, / Universal /
119	regBadSSD_4_b = 0x0c, / Universal /
120	regMediaStatus_4_w = 0x0a, / Universal with Exceptions, pg 201 /
121	regPhysicalMgmt_4_w = 0x08, / Universal /
122	regNetworkDiagnostic_4_w = 0x06, / Universal with Exceptions, pg 203 /
123	regFifoDiagnostic_4_w = 0x04, / Universal with Exceptions, pg 196 /
124	regVcoDiagnostic_4_w = 0x02, / Undocumented? /
125	};
126
127	enum Registers3
128	{
129	regTxFree_3_w = 0x0c, / Universal /
130	regRxFree_3_w = 0x0a, / Universal with Exceptions, pg 125 /
131	regResetMediaOptions_3_w = 0x08, / Media Options on B Revision, /
132	/ Reset Options on Non-B Revision /
133	regMacControl_3_w = 0x06, / Universal with Exceptions, pg 199 /
134	regMaxPktSize_3_w = 0x04, / 905B Revision Only /
135	regInternalConfig_3_l = 0x00, / Universal, different bit /
136	/ definitions, pg 59 /
137	};
138
139	enum Registers2
140	{
141	regResetOptions_2_w = 0x0c, / 905B Revision Only /
142	regStationMask_2_3w = 0x06, / Universal with Exceptions, pg 127 /
143	regStationAddress_2_3w = 0x00, / Universal with Exceptions, pg 127 /
144	};
145
146	enum Registers1
147	{
148	regRxStatus_1_w = 0x0a, / 90X Revision Only, Pg 126 /
149	};
150
151	enum Registers0
152	{
153	regEepromData_0_w = 0x0c, / Universal /
154	regEepromCommand_0_w = 0x0a, / Universal /
155	regBiosRomData_0_b = 0x08, / 905B Revision Only /
156	regBiosRomAddr_0_l = 0x04, / 905B Revision Only /
157	};
158
159
160	/* The names for the eight register windows */
161	enum Windows
162	{
163	winPowerVlan7 = 0x07,
164	winStatistics6 = 0x06,
165	winTxRxControl5 = 0x05,
166	winDiagnostics4 = 0x04,
167	winTxRxOptions3 = 0x03,
168	winAddressing2 = 0x02,
169	winUnused1 = 0x01,
170	winEepromBios0 = 0x00,
171	};
172
173
174	/* Command definitions for the 3c90X */
175	enum Commands
176	{
177	cmdGlobalReset = 0x00, / Universal with Exceptions, pg 151 /
178	cmdSelectRegisterWindow = 0x01, / Universal /
179	cmdEnableDcConverter = 0x02, / /
180	cmdRxDisable = 0x03, / /
181	cmdRxEnable = 0x04, / Universal /
182	cmdRxReset = 0x05, / Universal /
183	cmdStallCtl = 0x06, / Universal /
184	cmdTxEnable = 0x09, / Universal /
185	cmdTxDisable = 0x0A, / /
186	cmdTxReset = 0x0B, / Universal /
187	cmdRequestInterrupt = 0x0C, / /
188	cmdAcknowledgeInterrupt = 0x0D, / Universal /
189	cmdSetInterruptEnable = 0x0E, / Universal /
190	cmdSetIndicationEnable = 0x0F, / Universal /
191	cmdSetRxFilter = 0x10, / Universal /
192	cmdSetRxEarlyThresh = 0x11, / /
193	cmdSetTxStartThresh = 0x13, / /
194	cmdStatisticsEnable = 0x15, / /
195	cmdStatisticsDisable = 0x16, / /
196	cmdDisableDcConverter = 0x17, / /
197	cmdSetTxReclaimThresh = 0x18, / /
198	cmdSetHashFilterBit = 0x19, / /
199	};
200
201
202	/* Values for int status register bitmask /
203	#define INT_INTERRUPTLATCH (1<<0)
204	#define INT_HOSTERROR (1<<1)
205	#define INT_TXCOMPLETE (1<<2)
206	#define INT_RXCOMPLETE (1<<4)
207	#define INT_RXEARLY (1<<5)
208	#define INT_INTREQUESTED (1<<6)
209	#define INT_UPDATESTATS (1<<7)
210	#define INT_LINKEVENT (1<<8)
211	#define INT_DNCOMPLETE (1<<9)
212	#define INT_UPCOMPLETE (1<<10)
213	#define INT_CMDINPROGRESS (1<<12)
214	#define INT_WINDOWNUMBER (7<<13)
215
216
217	/* TX descriptor */
218	typedef struct
219	{
220	unsigned int DnNextPtr;
221	unsigned int FrameStartHeader;
222	unsigned int HdrAddr;
223	unsigned int HdrLength;
224	unsigned int DataAddr;
225	unsigned int DataLength;
226	}
227	TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
228
229	/* RX descriptor */
230	typedef struct
231	{
232	unsigned int UpNextPtr;
233	unsigned int UpPktStatus;
234	unsigned int DataAddr;
235	unsigned int DataLength;
236	}
237	RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
238
239	/* Global variables */
240	static struct
241	{
242	unsigned int is3c556;
243	unsigned char isBrev;
244	unsigned char CurrentWindow;
245	unsigned int IOAddr;
246	unsigned char HWAddr[ETH_ALEN];
247	TXD TransmitDPD;
248	RXD ReceiveUPD;
249	}
250	INF_3C90X;
251
252
253	/*** a3c90x_internal_IssueCommand: sends a command to the 3c90x card
254	***/
255	static int
256	a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param)
257	{
258	unsigned int val;
259
260	/ Build the cmd. /
261	val = cmd;
262	val <<= 11;
263	val \|= param;
264
265	/ Send the cmd to the cmd register /
266	outw(val, ioaddr + regCommandIntStatus_w);
267
268	/ Wait for the cmd to complete, if necessary /
269	while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
270
271	return 0;
272	}
273
274
275	/*** a3c90x_internal_SetWindow: selects a register window set.
276	***/
277	static int
278	a3c90x_internal_SetWindow(int ioaddr, int window)
279	{
280
281	/ Window already as set? /
282	if (INF_3C90X.CurrentWindow == window) return 0;
283
284	/ Issue the window command. /
285	a3c90x_internal_IssueCommand(ioaddr, cmdSelectRegisterWindow, window);
286	INF_3C90X.CurrentWindow = window;
287
288	return 0;
289	}
290
291
292	/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
293	***/
294	static unsigned short
295	a3c90x_internal_ReadEeprom(int ioaddr, int address)
296	{
297	unsigned short val;
298
299	/ Select correct window /
300	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winEepromBios0);
301
302	/ Make sure the eeprom isn't busy /
303	while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
304
305	/ Read the value. /
306	if (INF_3C90X.is3c556)
307	{
308	outw(address + (0x230), ioaddr + regEepromCommand_0_w);
309	}
310	else
311	{
312	outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w);
313	}
314
315	while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
316	val = inw(ioaddr + regEepromData_0_w);
317
318	return val;
319	}
320
321
322	#ifdef CFG_3C90X_BOOTROM_FIX
323	/*** a3c90x_internal_WriteEepromWord - write a physical word of
324	*** data to the onboard serial eeprom (not the BIOS prom, but the
325	*** nvram in the card that stores, among other things, the MAC
326	*** address).
327	***/
328	static int
329	a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
330	{
331	/ Select register window /
332	a3c90x_internal_SetWindow(ioaddr, winEepromBios0);
333
334	/ Verify Eeprom not busy /
335	while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
336
337	/ Issue WriteEnable, and wait for completion. /
338	outw(0x30, ioaddr + regEepromCommand_0_w);
339	while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
340
341	/ Issue EraseRegister, and wait for completion. /
342	outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
343	while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
344
345	/ Send the new data to the eeprom, and wait for completion. /
346	outw(value, ioaddr + regEepromData_0_w);
347	outw(0x30, ioaddr + regEepromCommand_0_w);
348	while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
349
350	/ Burn the new data into the eeprom, and wait for completion. /
351	outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
352	while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
353
354	return 0;
355	}
356	#endif
357
358	#ifdef CFG_3C90X_BOOTROM_FIX
359	/*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
360	*** and re-compute the eeprom checksum.
361	***/
362	static int
363	a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
364	{
365	int cksum = 0,v;
366	int i;
367	int maxAddress, cksumAddress;
368
369	if (INF_3C90X.isBrev)
370	{
371	maxAddress=0x1f;
372	cksumAddress=0x20;
373	}
374	else
375	{
376	maxAddress=0x16;
377	cksumAddress=0x17;
378	}
379
380	/ Write the value. /
381	if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
382	return -1;
383
384	/ Recompute the checksum. /
385	for(i=0;i<=maxAddress;i++)
386	{
387	v = a3c90x_internal_ReadEeprom(ioaddr, i);
388	cksum ^= (v & 0xFF);
389	cksum ^= ((v>>8) & 0xFF);
390	}
391	/ Write the checksum to the location in the eeprom /
392	if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
393	return -1;
394
395	return 0;
396	}
397	#endif
398
399	/*** a3c90x_reset: exported function that resets the card to its default
400	*** state. This is so the Linux driver can re-set the card up the way
401	*** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
402	*** not alter the selected transceiver that we used to download the boot
403	*** image.
404	***/
405	static void a3c90x_reset(void)
406	{
407	#ifdef CFG_3C90X_PRESERVE_XCVR
408	int cfg;
409	/ Read the current InternalConfig value. /
410	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
411	cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
412	#endif
413
414	/ Send the reset command to the card /
415	printf("Issuing RESET:\n");
416	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdGlobalReset, 0);
417
418	/ wait for reset command to complete /
419	while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
420
421	/** global reset command resets station mask, non-B revision cards
422	** require explicit reset of values
423	**/
424	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
425	outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
426	outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
427	outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
428
429	#ifdef CFG_3C90X_PRESERVE_XCVR
430	/ Re-set the original InternalConfig value from before reset /
431	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
432	outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
433
434	/ enable DC converter for 10-Base-T /
435	if ((cfg&0x0300) == 0x0300)
436	{
437	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
438	}
439	#endif
440
441	/ Issue transmit reset, wait for command completion /
442	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0);
443	while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
444	;
445	if (! INF_3C90X.isBrev)
446	outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
447	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
448
449	/**
450	** reset of the receiver on B-revision cards re-negotiates the link
451	** takes several seconds (a computer eternity)
452	**/
453	if (INF_3C90X.isBrev)
454	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
455	else
456	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
457	while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
458	;
459	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
460
461	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
462	cmdSetInterruptEnable, 0);
463	/ enable rxComplete and txComplete /
464	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
465	cmdSetIndicationEnable, 0x0014);
466	/ acknowledge any pending status flags /
467	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
468	cmdAcknowledgeInterrupt, 0x661);
469
470	return;
471	}
472
473
474
475	/*** a3c90x_transmit: exported function that transmits a packet. Does not
476	*** return any particular status. Parameters are:
477	*** d[6] - destination address, ethernet;
478	*** t - protocol type (ARP, IP, etc);
479	*** s - size of the non-header part of the packet that needs transmitted;
480	*** p - the pointer to the packet data itself.
481	***/
482	static void
483	a3c90x_transmit(struct nic nic __unused, const char d, unsigned int t,
484	unsigned int s, const char *p)
485	{
486
487	struct eth_hdr
488	{
489	unsigned char dst_addr[ETH_ALEN];
490	unsigned char src_addr[ETH_ALEN];
491	unsigned short type;
492	} hdr;
493
494	unsigned char status;
495	unsigned i, retries;
496
497	for (retries=0; retries < XMIT_RETRIES ; retries++)
498	{
499	/ Stall the download engine /
500	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 2);
501
502	/ Make sure the card is not waiting on us /
503	inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
504	inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
505
506	while (inw(INF_3C90X.IOAddr+regCommandIntStatus_w) &
507	INT_CMDINPROGRESS)
508	;
509
510	/ Set the ethernet packet type /
511	hdr.type = htons(t);
512
513	/ Copy the destination address /
514	memcpy(hdr.dst_addr, d, ETH_ALEN);
515
516	/ Copy our MAC address /
517	memcpy(hdr.src_addr, INF_3C90X.HWAddr, ETH_ALEN);
518
519	/ Setup the DPD (download descriptor) /
520	INF_3C90X.TransmitDPD.DnNextPtr = 0;
521	/ set notification for transmission completion (bit 15) /
522	INF_3C90X.TransmitDPD.FrameStartHeader = (s + sizeof(hdr)) \| 0x8000;
523	INF_3C90X.TransmitDPD.HdrAddr = virt_to_bus(&hdr);
524	INF_3C90X.TransmitDPD.HdrLength = sizeof(hdr);
525	INF_3C90X.TransmitDPD.DataAddr = virt_to_bus(p);
526	INF_3C90X.TransmitDPD.DataLength = s + (1<<31);
527
528	/ Send the packet /
529	outl(virt_to_bus(&(INF_3C90X.TransmitDPD)),
530	INF_3C90X.IOAddr + regDnListPtr_l);
531
532	/ End Stall and Wait for upload to complete. /
533	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 3);
534	while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
535	;
536
537	/ Wait for NIC Transmit to Complete /
538	load_timer2(10TICKS_PER_MS); / Give it 10 ms */
539	while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004) &&
540	timer2_running())
541	;
542
543	if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004))
544	{
545	printf("3C90X: Tx Timeout\n");
546	continue;
547	}
548
549	status = inb(INF_3C90X.IOAddr + regTxStatus_b);
550
551	/ acknowledge transmit interrupt by writing status /
552	outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
553
554	/ successful completion (sans "interrupt Requested" bit) /
555	if ((status & 0xbf) == 0x80)
556	return;
557
558	printf("3C90X: Status (%hhX)\n", status);
559	/ check error codes /
560	if (status & 0x02)
561	{
562	printf("3C90X: Tx Reclaim Error (%hhX)\n", status);
563	a3c90x_reset();
564	}
565	else if (status & 0x04)
566	{
567	printf("3C90X: Tx Status Overflow (%hhX)\n", status);
568	for (i=0; i<32; i++)
569	outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
570	/ must re-enable after max collisions before re-issuing tx /
571	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
572	}
573	else if (status & 0x08)
574	{
575	printf("3C90X: Tx Max Collisions (%hhX)\n", status);
576	/ must re-enable after max collisions before re-issuing tx /
577	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
578	}
579	else if (status & 0x10)
580	{
581	printf("3C90X: Tx Underrun (%hhX)\n", status);
582	a3c90x_reset();
583	}
584	else if (status & 0x20)
585	{
586	printf("3C90X: Tx Jabber (%hhX)\n", status);
587	a3c90x_reset();
588	}
589	else if ((status & 0x80) != 0x80)
590	{
591	printf("3C90X: Internal Error - Incomplete Transmission (%hhX)\n",
592	status);
593	a3c90x_reset();
594	}
595	}
596
597	/ failed after RETRY attempts /
598	printf("Failed to send after %d retries\n", retries);
599	return;
600
601	}
602
603
604
605	/*** a3c90x_poll: exported routine that waits for a certain length of time
606	*** for a packet, and if it sees none, returns 0. This routine should
607	*** copy the packet to nic->packet if it gets a packet and set the size
608	*** in nic->packetlen. Return 1 if a packet was found.
609	***/
610	static int
611	a3c90x_poll(struct nic *nic, int retrieve)
612	{
613	int i, errcode;
614
615	if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
616	{
617	return 0;
618	}
619
620	if ( ! retrieve ) return 1;
621
622	/** we don't need to acknowledge rxComplete -- the upload engine
623	** does it for us.
624	**/
625
626	/ Build the up-load descriptor /
627	INF_3C90X.ReceiveUPD.UpNextPtr = 0;
628	INF_3C90X.ReceiveUPD.UpPktStatus = 0;
629	INF_3C90X.ReceiveUPD.DataAddr = virt_to_bus(nic->packet);
630	INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
631
632	/ Submit the upload descriptor to the NIC /
633	outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)),
634	INF_3C90X.IOAddr + regUpListPtr_l);
635
636	/ Wait for upload completion (upComplete(15) or upError (14)) /
637	for(i=0;i<40000;i++);
638	while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) \| (1<<15))) == 0)
639	for(i=0;i<40000;i++);
640
641	/ Check for Error (else we have good packet) /
642	if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
643	{
644	errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
645	if (errcode & (1<<16))
646	printf("3C90X: Rx Overrun (%hX)\n",errcode>>16);
647	else if (errcode & (1<<17))
648	printf("3C90X: Runt Frame (%hX)\n",errcode>>16);
649	else if (errcode & (1<<18))
650	printf("3C90X: Alignment Error (%hX)\n",errcode>>16);
651	else if (errcode & (1<<19))
652	printf("3C90X: CRC Error (%hX)\n",errcode>>16);
653	else if (errcode & (1<<20))
654	printf("3C90X: Oversized Frame (%hX)\n",errcode>>16);
655	else
656	printf("3C90X: Packet error (%hX)\n",errcode>>16);
657	return 0;
658	}
659
660	/ Ok, got packet. Set length in nic->packetlen. /
661	nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
662
663	return 1;
664	}
665
666
667
668	/*** a3c90x_disable: exported routine to disable the card. What's this for?
669	*** the eepro100.c driver didn't have one, so I just left this one empty too.
670	*** Ideas anyone?
671	*** Must turn off receiver at least so stray packets will not corrupt memory
672	*** [Ken]
673	***/
674	static void
675	a3c90x_disable(struct dev *dev __unused)
676	{
677	/* reset and disable merge */
678	a3c90x_reset();
679	/* Disable the receiver and transmitter. */
680	outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
681	outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
682	}
683
684	static void a3c90x_irq(struct nic *nic __unused, irq_action_t action __unused)
685	{
686	switch ( action ) {
687	case DISABLE :
688	break;
689	case ENABLE :
690	break;
691	case FORCE :
692	break;
693	}
694	}
695
696	/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
697	*** initialization. If this routine is called, the pci functions did find the
698	*** card. We just have to init it here.
699	***/
700	static int a3c90x_probe(struct dev dev, struct pci_device pci)
701	{
702	struct nic nic = (struct nic )dev;
703	INF_3C90X.is3c556 = (pci->dev_id == 0x6055);
704
705	int i, c;
706	unsigned short eeprom[0x21];
707	unsigned int cfg;
708	unsigned int mopt;
709	unsigned int mstat;
710	unsigned short linktype;
711	#define HWADDR_OFFSET 10
712
713	if (pci->ioaddr == 0)
714	return 0;
715
716	adjust_pci_device(pci);
717
718	nic->ioaddr = pci->ioaddr & ~3;
719	nic->irqno = 0;
720
721	INF_3C90X.IOAddr = pci->ioaddr & ~3;
722	INF_3C90X.CurrentWindow = 255;
723	switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
724	{
725	case 0x9000: / 10 Base TPO /
726	case 0x9001: / 10/100 T4 /
727	case 0x9050: / 10/100 TPO /
728	case 0x9051: / 10 Base Combo /
729	INF_3C90X.isBrev = 0;
730	break;
731
732	case 0x9004: / 10 Base TPO /
733	case 0x9005: / 10 Base Combo /
734	case 0x9006: / 10 Base TPO and Base2 /
735	case 0x900A: / 10 Base FL /
736	case 0x9055: / 10/100 TPO /
737	case 0x9056: / 10/100 T4 /
738	case 0x905A: / 10 Base FX /
739	default:
740	INF_3C90X.isBrev = 1;
741	break;
742	}
743
744	/ Load the EEPROM contents /
745	if (INF_3C90X.isBrev)
746	{
747	for(i=0;i<=0x20;i++)
748	{
749	eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
750	}
751
752	#ifdef CFG_3C90X_BOOTROM_FIX
753	/ Set xcvrSelect in InternalConfig in eeprom. /
754	/* only necessary for 3c905b revision cards with boot PROM bug!!! */
755	a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
756	#endif
757
758	#ifdef CFG_3C90X_XCVR
759	if (CFG_3C90X_XCVR == 255)
760	{
761	/ Clear the LanWorks register /
762	a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
763	}
764	else
765	{
766	/** Set the selected permanent-xcvrSelect in the
767	** LanWorks register
768	**/
769	a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
770	XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
771	}
772	#endif
773	}
774	else
775	{
776	for(i=0;i<=0x17;i++)
777	{
778	eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
779	}
780	}
781
782	/ Print identification message /
783	printf("\n\n3C90X Driver 2.00 "
784	"Copyright 1999 LightSys Technology Services, Inc.\n"
785	"Portions Copyright 1999 Steve Smith\n");
786	printf("Provided with ABSOLUTELY NO WARRANTY.\n");
787	#ifdef CFG_3C90X_BOOTROM_FIX
788	if (INF_3C90X.isBrev)
789	{
790	printf("NOTE: 3c905b bootrom fix enabled; has side "
791	"effects. See 3c90x.txt for info.\n");
792	}
793	#endif
794	printf("-------------------------------------------------------"
795	"------------------------\n");
796
797	/ Retrieve the Hardware address and print it on the screen. /
798	INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
799	INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
800	INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
801	INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
802	INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
803	INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
804	printf("MAC Address = %!\n", INF_3C90X.HWAddr);
805
806	/ 3C556: Invert MII power /
807	if (INF_3C90X.is3c556) {
808	unsigned int tmp;
809	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
810	tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
811	tmp \|= 0x4000;
812	outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
813	}
814
815	/* Test if the link is good, if not continue */
816	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winDiagnostics4);
817	mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
818	if((mstat & (1<<11)) == 0) {
819	printf("Valid link not established\n");
820	return 0;
821	}
822
823	/ Program the MAC address into the station address registers /
824	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
825	outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
826	outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
827	outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
828	outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
829	outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
830	outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
831
832	/ Fill in our entry in the etherboot arp table /
833	for(i=0;i<ETH_ALEN;i++)
834	nic->node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
835
836	/** Read the media options register, print a message and set default
837	** xcvr.
838	**
839	** Uses Media Option command on B revision, Reset Option on non-B
840	** revision cards -- same register address
841	**/
842	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
843	mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
844
845	/ mask out VCO bit that is defined as 10baseFL bit on B-rev cards /
846	if (! INF_3C90X.isBrev)
847	{
848	mopt &= 0x7F;
849	}
850
851	printf("Connectors present: ");
852	c = 0;
853	linktype = 0x0008;
854	if (mopt & 0x01)
855	{
856	printf("%s100Base-T4",(c++)?", ":"");
857	linktype = 0x0006;
858	}
859	if (mopt & 0x04)
860	{
861	printf("%s100Base-FX",(c++)?", ":"");
862	linktype = 0x0005;
863	}
864	if (mopt & 0x10)
865	{
866	printf("%s10Base-2",(c++)?", ":"");
867	linktype = 0x0003;
868	}
869	if (mopt & 0x20)
870	{
871	printf("%sAUI",(c++)?", ":"");
872	linktype = 0x0001;
873	}
874	if (mopt & 0x40)
875	{
876	printf("%sMII",(c++)?", ":"");
877	linktype = 0x0006;
878	}
879	if ((mopt & 0xA) == 0xA)
880	{
881	printf("%s10Base-T / 100Base-TX",(c++)?", ":"");
882	linktype = 0x0008;
883	}
884	else if ((mopt & 0xA) == 0x2)
885	{
886	printf("%s100Base-TX",(c++)?", ":"");
887	linktype = 0x0008;
888	}
889	else if ((mopt & 0xA) == 0x8)
890	{
891	printf("%s10Base-T",(c++)?", ":"");
892	linktype = 0x0008;
893	}
894	printf(".\n");
895
896	/** Determine transceiver type to use, depending on value stored in
897	** eeprom 0x16
898	**/
899	if (INF_3C90X.isBrev)
900	{
901	if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
902	{
903	/ User-defined /
904	linktype = eeprom[0x16] & 0x000F;
905	}
906	}
907	else
908	{
909	#ifdef CFG_3C90X_XCVR
910	if (CFG_3C90X_XCVR != 255)
911	linktype = CFG_3C90X_XCVR;
912	#endif /* CFG_3C90X_XCVR */
913
914	/ I don't know what MII MAC only mode is!!! /
915	if (linktype == 0x0009)
916	{
917	if (INF_3C90X.isBrev)
918	printf("WARNING: MII External MAC Mode only supported on B-revision "
919	"cards!!!!\nFalling Back to MII Mode\n");
920	linktype = 0x0006;
921	}
922	}
923
924	/ enable DC converter for 10-Base-T /
925	if (linktype == 0x0003)
926	{
927	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
928	}
929
930	/ Set the link to the type we just determined. /
931	a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
932	cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
933	cfg &= ~(0xF<<20);
934	cfg \|= (linktype<<20);
935	outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
936
937	/ Now that we set the xcvr type, reset the Tx and Rx, re-enable. /
938	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0x00);
939	while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
940	;
941
942	if (!INF_3C90X.isBrev)
943	outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
944
945	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
946
947	/**
948	** reset of the receiver on B-revision cards re-negotiates the link
949	** takes several seconds (a computer eternity)
950	**/
951	if (INF_3C90X.isBrev)
952	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
953	else
954	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
955	while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
956	;
957
958	/ Set the RX filter = receive only individual pkts & multicast & bcast. /
959	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
960	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
961
962
963	/**
964	** set Indication and Interrupt flags , acknowledge any IRQ's
965	**/
966	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
967	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
968	cmdSetIndicationEnable, 0x0014);
969	a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
970	cmdAcknowledgeInterrupt, 0x661);
971
972	/ Set our exported functions /
973	dev->disable = a3c90x_disable;
974	nic->poll = a3c90x_poll;
975	nic->transmit = a3c90x_transmit;
976	nic->irq = a3c90x_irq;
977
978	return 1;
979	}
980
981
982	static struct pci_id a3c90x_nics[] = {
983	/* Original 90x revisions: */
984	PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
985	PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
986	PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
987	PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
988	PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
989	/* Newer 90xB revisions: */
990	PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
991	PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
992	PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
993	PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
994	PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
995	PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
996	PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
997	PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
998	/* Newer 90xC revision: */
999	PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
1000	PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
1001	PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
1002	PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
1003	PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
1004	PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
1005	PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
1006	PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
1007	PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
1008	};
1009
1010	static struct pci_driver a3c90x_driver __pci_driver = {
1011	.type = NIC_DRIVER,
1012	.name = "3C90X",
1013	.probe = a3c90x_probe,
1014	.ids = a3c90x_nics,
1015	.id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
1016	.class = 0,
1017	};

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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/3c90x.c@ 1300

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