depca.c@ 1

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1	/* Not fixed for relocation yet. Probably won't work relocated above 16MB */
2	#ifdef ALLMULTI
3	#error multicast support is not yet implemented
4	#endif
5	/* Etherboot: depca.h merged, comments from Linux driver retained */
6	/* depca.c: A DIGITAL DEPCA & EtherWORKS ethernet driver for linux.
7
8	Written 1994, 1995 by David C. Davies.
9
10
11	Copyright 1994 David C. Davies
12	and
13	United States Government
14	(as represented by the Director, National Security Agency).
15
16	Copyright 1995 Digital Equipment Corporation.
17
18
19	This software may be used and distributed according to the terms of
20	the GNU Public License, incorporated herein by reference.
21
22	This driver is written for the Digital Equipment Corporation series
23	of DEPCA and EtherWORKS ethernet cards:
24
25	DEPCA (the original)
26	DE100
27	DE101
28	DE200 Turbo
29	DE201 Turbo
30	DE202 Turbo (TP BNC)
31	DE210
32	DE422 (EISA)
33
34	The driver has been tested on DE100, DE200 and DE202 cards in a
35	relatively busy network. The DE422 has been tested a little.
36
37	This driver will NOT work for the DE203, DE204 and DE205 series of
38	cards, since they have a new custom ASIC in place of the AMD LANCE
39	chip. See the 'ewrk3.c' driver in the Linux source tree for running
40	those cards.
41
42	I have benchmarked the driver with a DE100 at 595kB/s to (542kB/s from)
43	a DECstation 5000/200.
44
45	The author may be reached at [email protected]
46
47	=========================================================================
48
49	The driver was originally based on the 'lance.c' driver from Donald
50	Becker which is included with the standard driver distribution for
51	linux. V0.4 is a complete re-write with only the kernel interface
52	remaining from the original code.
53
54	1) Lance.c code in /linux/drivers/net/
55	2) "Ethernet/IEEE 802.3 Family. 1992 World Network Data Book/Handbook",
56	AMD, 1992 [(800) 222-9323].
57	3) "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)",
58	AMD, Pub. #17881, May 1993.
59	4) "Am79C960 PCnet-ISA(tm), Single-Chip Ethernet Controller for ISA",
60	AMD, Pub. #16907, May 1992
61	5) "DEC EtherWORKS LC Ethernet Controller Owners Manual",
62	Digital Equipment corporation, 1990, Pub. #EK-DE100-OM.003
63	6) "DEC EtherWORKS Turbo Ethernet Controller Owners Manual",
64	Digital Equipment corporation, 1990, Pub. #EK-DE200-OM.003
65	7) "DEPCA Hardware Reference Manual", Pub. #EK-DEPCA-PR
66	Digital Equipment Corporation, 1989
67	8) "DEC EtherWORKS Turbo_(TP BNC) Ethernet Controller Owners Manual",
68	Digital Equipment corporation, 1991, Pub. #EK-DE202-OM.001
69
70
71	Peter Bauer's depca.c (V0.5) was referred to when debugging V0.1 of this
72	driver.
73
74	The original DEPCA card requires that the ethernet ROM address counter
75	be enabled to count and has an 8 bit NICSR. The ROM counter enabling is
76	only done when a 0x08 is read as the first address octet (to minimise
77	the chances of writing over some other hardware's I/O register). The
78	NICSR accesses have been changed to byte accesses for all the cards
79	supported by this driver, since there is only one useful bit in the MSB
80	(remote boot timeout) and it is not used. Also, there is a maximum of
81	only 48kB network RAM for this card. My thanks to Torbjorn Lindh for
82	help debugging all this (and holding my feet to the fire until I got it
83	right).
84
85	The DE200 series boards have on-board 64kB RAM for use as a shared
86	memory network buffer. Only the DE100 cards make use of a 2kB buffer
87	mode which has not been implemented in this driver (only the 32kB and
88	64kB modes are supported [16kB/48kB for the original DEPCA]).
89
90	At the most only 2 DEPCA cards can be supported on the ISA bus because
91	there is only provision for two I/O base addresses on each card (0x300
92	and 0x200). The I/O address is detected by searching for a byte sequence
93	in the Ethernet station address PROM at the expected I/O address for the
94	Ethernet PROM. The shared memory base address is 'autoprobed' by
95	looking for the self test PROM and detecting the card name. When a
96	second DEPCA is detected, information is placed in the base_addr
97	variable of the next device structure (which is created if necessary),
98	thus enabling ethif_probe initialization for the device. More than 2
99	EISA cards can be supported, but care will be needed assigning the
100	shared memory to ensure that each slot has the correct IRQ, I/O address
101	and shared memory address assigned.
102
103	************************************************************************
104
105	NOTE: If you are using two ISA DEPCAs, it is important that you assign
106	the base memory addresses correctly. The driver autoprobes I/O 0x300
107	then 0x200. The base memory address for the first device must be less
108	than that of the second so that the auto probe will correctly assign the
109	I/O and memory addresses on the same card. I can't think of a way to do
110	this unambiguously at the moment, since there is nothing on the cards to
111	tie I/O and memory information together.
112
113	I am unable to test 2 cards together for now, so this code is
114	unchecked. All reports, good or bad, are welcome.
115
116	************************************************************************
117
118	The board IRQ setting must be at an unused IRQ which is auto-probed
119	using Donald Becker's autoprobe routines. DEPCA and DE100 board IRQs are
120	{2,3,4,5,7}, whereas the DE200 is at {5,9,10,11,15}. Note that IRQ2 is
121	really IRQ9 in machines with 16 IRQ lines.
122
123	No 16MB memory limitation should exist with this driver as DMA is not
124	used and the common memory area is in low memory on the network card (my
125	current system has 20MB and I've not had problems yet).
126
127	The ability to load this driver as a loadable module has been added. To
128	utilise this ability, you have to do <8 things:
129
130	0) have a copy of the loadable modules code installed on your system.
131	1) copy depca.c from the /linux/drivers/net directory to your favourite
132	temporary directory.
133	2) if you wish, edit the source code near line 1530 to reflect the I/O
134	address and IRQ you're using (see also 5).
135	3) compile depca.c, but include -DMODULE in the command line to ensure
136	that the correct bits are compiled (see end of source code).
137	4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
138	kernel with the depca configuration turned off and reboot.
139	5) insmod depca.o [irq=7] [io=0x200] [mem=0xd0000] [adapter_name=DE100]
140	[Alan Cox: Changed the code to allow command line irq/io assignments]
141	[Dave Davies: Changed the code to allow command line mem/name
142	assignments]
143	6) run the net startup bits for your eth?? interface manually
144	(usually /etc/rc.inet[12] at boot time).
145	7) enjoy!
146
147	Note that autoprobing is not allowed in loadable modules - the system is
148	already up and running and you're messing with interrupts.
149
150	To unload a module, turn off the associated interface
151	'ifconfig eth?? down' then 'rmmod depca'.
152
153	To assign a base memory address for the shared memory when running as a
154	loadable module, see 5 above. To include the adapter name (if you have
155	no PROM but know the card name) also see 5 above. Note that this last
156	option will not work with kernel built-in depca's.
157
158	The shared memory assignment for a loadable module makes sense to avoid
159	the 'memory autoprobe' picking the wrong shared memory (for the case of
160	2 depca's in a PC).
161
162	************************************************************************
163	Support for MCA EtherWORKS cards added 11-3-98.
164	Verified to work with up to 2 DE212 cards in a system (although not
165	fully stress-tested).
166
167	Currently known bugs/limitations:
168
169	Note: with the MCA stuff as a module, it trusts the MCA configuration,
170	not the command line for IRQ and memory address. You can
171	specify them if you want, but it will throw your values out.
172	You still have to pass the IO address it was configured as
173	though.
174
175	************************************************************************
176	TO DO:
177	------
178
179
180	Revision History
181	----------------
182
183	Version Date Description
184
185	0.1 25-jan-94 Initial writing.
186	0.2 27-jan-94 Added LANCE TX hardware buffer chaining.
187	0.3 1-feb-94 Added multiple DEPCA support.
188	0.31 4-feb-94 Added DE202 recognition.
189	0.32 19-feb-94 Tidy up. Improve multi-DEPCA support.
190	0.33 25-feb-94 Fix DEPCA ethernet ROM counter enable.
191	Add jabber packet fix from [email protected]
192	and [email protected]
193	0.34 7-mar-94 Fix DEPCA max network memory RAM & NICSR access.
194	0.35 8-mar-94 Added DE201 recognition. Tidied up.
195	0.351 30-apr-94 Added EISA support. Added DE422 recognition.
196	0.36 16-may-94 DE422 fix released.
197	0.37 22-jul-94 Added MODULE support
198	0.38 15-aug-94 Added DBR ROM switch in depca_close().
199	Multi DEPCA bug fix.
200	0.38axp 15-sep-94 Special version for Alpha AXP Linux V1.0.
201	0.381 12-dec-94 Added DE101 recognition, fix multicast bug.
202	0.382 9-feb-95 Fix recognition bug reported by <[email protected]>.
203	0.383 22-feb-95 Fix for conflict with VESA SCSI reported by
204	<[email protected]>
205	0.384 17-mar-95 Fix a ring full bug reported by <[email protected]>
206	0.385 3-apr-95 Fix a recognition bug reported by
207	<[email protected]>
208	0.386 21-apr-95 Fix the last fix...sorry, must be galloping senility
209	0.40 25-May-95 Rewrite for portability & updated.
210	ALPHA support from <[email protected]>
211	0.41 26-Jun-95 Added verify_area() calls in depca_ioctl() from
212	suggestion by <[email protected]>
213	0.42 27-Dec-95 Add 'mem' shared memory assignment for loadable
214	modules.
215	Add 'adapter_name' for loadable modules when no PROM.
216	Both above from a suggestion by
217	<[email protected]>.
218	Add new multicasting code.
219	0.421 22-Apr-96 Fix alloc_device() bug <[email protected]>
220	0.422 29-Apr-96 Fix depca_hw_init() bug <[email protected]>
221	0.423 7-Jun-96 Fix module load bug <[email protected]>
222	0.43 16-Aug-96 Update alloc_device() to conform to de4x5.c
223	0.44 1-Sep-97 Fix *_probe() to test check_region() first - bug
224	reported by <[email protected]>
225	0.45 3-Nov-98 Added support for MCA EtherWORKS (DE210/DE212) cards
226	by <[email protected]>
227	0.451 5-Nov-98 Fixed mca stuff cuz I'm a dummy. <[email protected]>
228	0.5 14-Nov-98 Re-spin for 2.1.x kernels.
229	0.51 27-Jun-99 Correct received packet length for CRC from
230	report by <[email protected]>
231
232	=========================================================================
233	*/
234
235	#include "etherboot.h"
236	#include "nic.h"
237	#include "isa.h"
238
239	/*
240	** I/O addresses. Note that the 2k buffer option is not supported in
241	** this driver.
242	*/
243	#define DEPCA_NICSR ioaddr+0x00 /* Network interface CSR */
244	#define DEPCA_RBI ioaddr+0x02 /* RAM buffer index (2k buffer mode) */
245	#define DEPCA_DATA ioaddr+0x04 /* LANCE registers' data port */
246	#define DEPCA_ADDR ioaddr+0x06 /* LANCE registers' address port */
247	#define DEPCA_HBASE ioaddr+0x08 /* EISA high memory base address reg. */
248	#define DEPCA_PROM ioaddr+0x0c /* Ethernet address ROM data port */
249	#define DEPCA_CNFG ioaddr+0x0c /* EISA Configuration port */
250	#define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */
251
252	/*
253	** These are LANCE registers addressable through DEPCA_ADDR
254	*/
255	#define CSR0 0
256	#define CSR1 1
257	#define CSR2 2
258	#define CSR3 3
259
260	/*
261	** NETWORK INTERFACE CSR (NI_CSR) bit definitions
262	*/
263
264	#define TO 0x0100 /* Time Out for remote boot */
265	#define SHE 0x0080 /* SHadow memory Enable */
266	#define BS 0x0040 /* Bank Select */
267	#define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */
268	#define RBE 0x0010 /* Remote Boot Enable (1->net boot) */
269	#define AAC 0x0008 /* Address ROM Address Counter (1->enable) */
270	#define _128KB 0x0008 /* 128kB Network RAM (1->enable) */
271	#define IM 0x0004 /* Interrupt Mask (1->mask) */
272	#define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */
273	#define LED 0x0001 /* LED control */
274
275	/*
276	** Control and Status Register 0 (CSR0) bit definitions
277	*/
278
279	#define ERR 0x8000 /* Error summary */
280	#define BABL 0x4000 /* Babble transmitter timeout error */
281	#define CERR 0x2000 /* Collision Error */
282	#define MISS 0x1000 /* Missed packet */
283	#define MERR 0x0800 /* Memory Error */
284	#define RINT 0x0400 /* Receiver Interrupt */
285	#define TINT 0x0200 /* Transmit Interrupt */
286	#define IDON 0x0100 /* Initialization Done */
287	#define INTR 0x0080 /* Interrupt Flag */
288	#define INEA 0x0040 /* Interrupt Enable */
289	#define RXON 0x0020 /* Receiver on */
290	#define TXON 0x0010 /* Transmitter on */
291	#define TDMD 0x0008 /* Transmit Demand */
292	#define STOP 0x0004 /* Stop */
293	#define STRT 0x0002 /* Start */
294	#define INIT 0x0001 /* Initialize */
295	#define INTM 0xff00 /* Interrupt Mask */
296	#define INTE 0xfff0 /* Interrupt Enable */
297
298	/*
299	** CONTROL AND STATUS REGISTER 3 (CSR3)
300	*/
301
302	#define BSWP 0x0004 /* Byte SWaP */
303	#define ACON 0x0002 /* ALE control */
304	#define BCON 0x0001 /* Byte CONtrol */
305
306	/*
307	** Initialization Block Mode Register
308	*/
309
310	#define PROM 0x8000 /* Promiscuous Mode */
311	#define EMBA 0x0080 /* Enable Modified Back-off Algorithm */
312	#define INTL 0x0040 /* Internal Loopback */
313	#define DRTY 0x0020 /* Disable Retry */
314	#define COLL 0x0010 /* Force Collision */
315	#define DTCR 0x0008 /* Disable Transmit CRC */
316	#define LOOP 0x0004 /* Loopback */
317	#define DTX 0x0002 /* Disable the Transmitter */
318	#define DRX 0x0001 /* Disable the Receiver */
319
320	/*
321	** Receive Message Descriptor 1 (RMD1) bit definitions.
322	*/
323
324	#define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
325	#define R_ERR 0x4000 /* Error Summary */
326	#define R_FRAM 0x2000 /* Framing Error */
327	#define R_OFLO 0x1000 /* Overflow Error */
328	#define R_CRC 0x0800 /* CRC Error */
329	#define R_BUFF 0x0400 /* Buffer Error */
330	#define R_STP 0x0200 /* Start of Packet */
331	#define R_ENP 0x0100 /* End of Packet */
332
333	/*
334	** Transmit Message Descriptor 1 (TMD1) bit definitions.
335	*/
336
337	#define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
338	#define T_ERR 0x4000 /* Error Summary */
339	#define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */
340	#define T_MORE 0x1000 /* >1 retry to transmit packet */
341	#define T_ONE 0x0800 /* 1 try needed to transmit the packet */
342	#define T_DEF 0x0400 /* Deferred */
343	#define T_STP 0x02000000 /* Start of Packet */
344	#define T_ENP 0x01000000 /* End of Packet */
345	#define T_FLAGS 0xff000000 /* TX Flags Field */
346
347	/*
348	** Transmit Message Descriptor 3 (TMD3) bit definitions.
349	*/
350
351	#define TMD3_BUFF 0x8000 /* BUFFer error */
352	#define TMD3_UFLO 0x4000 /* UnderFLOw error */
353	#define TMD3_RES 0x2000 /* REServed */
354	#define TMD3_LCOL 0x1000 /* Late COLlision */
355	#define TMD3_LCAR 0x0800 /* Loss of CARrier */
356	#define TMD3_RTRY 0x0400 /* ReTRY error */
357
358	/*
359	** Ethernet PROM defines
360	*/
361	#define PROBE_LENGTH 32
362
363	/*
364	** Set the number of Tx and Rx buffers. Ensure that the memory requested
365	** here is <= to the amount of shared memory set up by the board switches.
366	** The number of descriptors MUST BE A POWER OF 2.
367	**
368	** total_memory = NUM_RX_DESC(8+RX_BUFF_SZ) + NUM_TX_DESC(8+TX_BUFF_SZ)
369	*/
370	#define NUM_RX_DESC 2 /* Number of RX descriptors */
371	#define NUM_TX_DESC 2 /* Number of TX descriptors */
372	#define RX_BUFF_SZ 1536 /* Buffer size for each Rx buffer */
373	#define TX_BUFF_SZ 1536 /* Buffer size for each Tx buffer */
374
375	/*
376	** ISA Bus defines
377	*/
378	#define DEPCA_IO_PORTS {0x300, 0x200, 0}
379
380	#ifndef DEPCA_MODEL
381	#define DEPCA_MODEL DEPCA
382	#endif
383
384	static enum {
385	DEPCA, DE100, DE101, DE200, DE201, DE202, DE210, DE212, DE422, unknown
386	} adapter = DEPCA_MODEL;
387
388	/*
389	** Name <-> Adapter mapping
390	*/
391
392	static char *adapter_name[] = {
393	"DEPCA",
394	"DE100","DE101",
395	"DE200","DE201","DE202",
396	"DE210","DE212",
397	"DE422",
398	""
399	};
400
401	#ifndef DEPCA_RAM_BASE
402	#define DEPCA_RAM_BASE 0xd0000
403	#endif
404
405	/*
406	** Memory Alignment. Each descriptor is 4 longwords long. To force a
407	** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
408	** DESC_ALIGN. ALIGN aligns the start address of the private memory area
409	** and hence the RX descriptor ring's first entry.
410	*/
411	#define ALIGN4 ((u32)4 - 1) /* 1 longword align */
412	#define ALIGN8 ((u32)8 - 1) /* 2 longword (quadword) align */
413	#define ALIGN ALIGN8 /* Keep the LANCE happy... */
414
415	/*
416	** The DEPCA Rx and Tx ring descriptors.
417	*/
418	struct depca_rx_desc {
419	volatile s32 base;
420	s16 buf_length; /* This length is negative 2's complement! */
421	s16 msg_length; /* This length is "normal". */
422	};
423
424	struct depca_tx_desc {
425	volatile s32 base;
426	s16 length; /* This length is negative 2's complement! */
427	s16 misc; /* Errors and TDR info */
428	};
429
430	#define LA_MASK 0x0000ffff /* LANCE address mask for mapping network RAM
431	to LANCE memory address space */
432
433	/*
434	** The Lance initialization block, described in databook, in common memory.
435	*/
436	struct depca_init {
437	u16 mode; /* Mode register */
438	u8 phys_addr[ETH_ALEN]; /* Physical ethernet address */
439	u8 mcast_table[8]; /* Multicast Hash Table. */
440	u32 rx_ring; /* Rx ring base pointer & ring length */
441	u32 tx_ring; /* Tx ring base pointer & ring length */
442	};
443
444	struct depca_private {
445	struct depca_rx_desc *rx_ring;
446	struct depca_tx_desc *tx_ring;
447	struct depca_init init_block; /* Shadow init block */
448	char *rx_memcpy[NUM_RX_DESC];
449	char *tx_memcpy[NUM_TX_DESC];
450	u32 bus_offset; /* ISA bus address offset */
451	u32 sh_mem; /* address of shared mem */
452	u32 dma_buffs; /* Rx & Tx buffer start */
453	int rx_cur, tx_cur; /* Next free ring entry */
454	int txRingMask, rxRingMask;
455	s32 rx_rlen, tx_rlen;
456	/* log2([rt]xRingMask+1) for the descriptors */
457	};
458
459	static Address mem_start = DEPCA_RAM_BASE;
460	static Address mem_len, offset;
461	static unsigned short ioaddr = 0;
462	static struct depca_private lp;
463
464	/*
465	** Miscellaneous defines...
466	*/
467	#define STOP_DEPCA \
468	outw(CSR0, DEPCA_ADDR);\
469	outw(STOP, DEPCA_DATA)
470
471	/* Initialize the lance Rx and Tx descriptor rings. */
472	static void depca_init_ring(struct nic *nic)
473	{
474	int i;
475	u32 p;
476
477	lp.rx_cur = lp.tx_cur = 0;
478	/* Initialize the base addresses and length of each buffer in the ring */
479	for (i = 0; i <= lp.rxRingMask; i++) {
480	writel((p = lp.dma_buffs + i * RX_BUFF_SZ) \| R_OWN, &lp.rx_ring[i].base);
481	writew(-RX_BUFF_SZ, &lp.rx_ring[i].buf_length);
482	lp.rx_memcpy[i] = (char *) (p + lp.bus_offset);
483	}
484	for (i = 0; i <= lp.txRingMask; i++) {
485	writel((p = lp.dma_buffs + (i + lp.txRingMask + 1) * TX_BUFF_SZ) & 0x00ffffff, &lp.tx_ring[i].base);
486	lp.tx_memcpy[i] = (char *) (p + lp.bus_offset);
487	}
488
489	/* Set up the initialization block */
490	lp.init_block.rx_ring = ((u32) ((u32) lp.rx_ring) & LA_MASK) \| lp.rx_rlen;
491	lp.init_block.tx_ring = ((u32) ((u32) lp.tx_ring) & LA_MASK) \| lp.tx_rlen;
492	for (i = 0; i < ETH_ALEN; i++)
493	lp.init_block.phys_addr[i] = nic->node_addr[i];
494	lp.init_block.mode = 0x0000; /* Enable the Tx and Rx */
495	memset(lp.init_block.mcast_table, 0, sizeof(lp.init_block.mcast_table));
496	}
497
498	static void LoadCSRs(void)
499	{
500	outw(CSR1, DEPCA_ADDR); /* initialisation block address LSW */
501	outw((u16) (lp.sh_mem & LA_MASK), DEPCA_DATA);
502	outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */
503	outw((u16) ((lp.sh_mem & LA_MASK) >> 16), DEPCA_DATA);
504	outw(CSR3, DEPCA_ADDR); /* ALE control */
505	outw(ACON, DEPCA_DATA);
506	outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */
507	}
508
509	static int InitRestartDepca(void)
510	{
511	int i;
512
513	/* Copy the shadow init_block to shared memory */
514	memcpy_toio((char *)lp.sh_mem, &lp.init_block, sizeof(struct depca_init));
515	outw(CSR0, DEPCA_ADDR); /* point back to CSR0 */
516	outw(INIT, DEPCA_DATA); /* initialise DEPCA */
517
518	for (i = 0; i < 100 && !(inw(DEPCA_DATA) & IDON); i++)
519	;
520	if (i < 100) {
521	/* clear IDON by writing a 1, and start LANCE */
522	outw(IDON \| STRT, DEPCA_DATA);
523	} else {
524	printf("DEPCA not initialised\n");
525	return (1);
526	}
527	return (0);
528	}
529
530	/**************************************************************************
531	RESET - Reset adapter
532	***************************************************************************/
533	static void depca_reset(struct nic *nic)
534	{
535	s16 nicsr;
536	int i, j;
537
538	STOP_DEPCA;
539	nicsr = inb(DEPCA_NICSR);
540	nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) \| IM);
541	outb(nicsr, DEPCA_NICSR);
542	if (inw(DEPCA_DATA) != STOP)
543	{
544	printf("depca: Cannot stop NIC\n");
545	return;
546	}
547
548	/* Initialisation block */
549	lp.sh_mem = mem_start;
550	mem_start += sizeof(struct depca_init);
551	/* Tx & Rx descriptors (aligned to a quadword boundary) */
552	mem_start = (mem_start + ALIGN) & ~ALIGN;
553	lp.rx_ring = (struct depca_rx_desc *) mem_start;
554	mem_start += (sizeof(struct depca_rx_desc) * NUM_RX_DESC);
555	lp.tx_ring = (struct depca_tx_desc *) mem_start;
556	mem_start += (sizeof(struct depca_tx_desc) * NUM_TX_DESC);
557
558	lp.bus_offset = mem_start & 0x00ff0000;
559	/* LANCE re-mapped start address */
560	lp.dma_buffs = mem_start & LA_MASK;
561
562	/* Finish initialising the ring information. */
563	lp.rxRingMask = NUM_RX_DESC - 1;
564	lp.txRingMask = NUM_TX_DESC - 1;
565
566	/* Calculate Tx/Rx RLEN size for the descriptors. */
567	for (i = 0, j = lp.rxRingMask; j > 0; i++) {
568	j >>= 1;
569	}
570	lp.rx_rlen = (s32) (i << 29);
571	for (i = 0, j = lp.txRingMask; j > 0; i++) {
572	j >>= 1;
573	}
574	lp.tx_rlen = (s32) (i << 29);
575
576	/* Load the initialisation block */
577	depca_init_ring(nic);
578	LoadCSRs();
579	InitRestartDepca();
580	}
581
582	/**************************************************************************
583	POLL - Wait for a frame
584	***************************************************************************/
585	static int depca_poll(struct nic *nic, int retrieve)
586	{
587	int entry;
588	u32 status;
589
590	entry = lp.rx_cur;
591	if ((status = readl(&lp.rx_ring[entry].base) & R_OWN))
592	return (0);
593
594	if ( ! retrieve ) return 1;
595
596	memcpy(nic->packet, lp.rx_memcpy[entry], nic->packetlen = lp.rx_ring[entry].msg_length);
597	lp.rx_ring[entry].base \|= R_OWN;
598	lp.rx_cur = (++lp.rx_cur) & lp.rxRingMask;
599	return (1);
600	}
601
602	/**************************************************************************
603	TRANSMIT - Transmit a frame
604	***************************************************************************/
605	static void depca_transmit(
606	struct nic *nic,
607	const char d, / Destination */
608	unsigned int t, /* Type */
609	unsigned int s, /* size */
610	const char p) / Packet */
611	{
612	int entry, len;
613	char *mem;
614
615	/* send the packet to destination */
616	/*
617	** Caution: the right order is important here... dont
618	** setup the ownership rights until all the other
619	** information is in place
620	*/
621	mem = lp.tx_memcpy[entry = lp.tx_cur];
622	memcpy_toio(mem, d, ETH_ALEN);
623	memcpy_toio(mem + ETH_ALEN, nic->node_addr, ETH_ALEN);
624	mem[ETH_ALEN * 2] = t >> 8;
625	mem[ETH_ALEN * 2 + 1] = t;
626	memcpy_toio(mem + ETH_HLEN, p, s);
627	s += ETH_HLEN;
628	len = (s < ETH_ZLEN ? ETH_ZLEN : s);
629	/* clean out flags */
630	writel(readl(&lp.tx_ring[entry].base) & ~T_FLAGS, &lp.tx_ring[entry].base);
631	/* clears other error flags */
632	writew(0x0000, &lp.tx_ring[entry].misc);
633	/* packet length in buffer */
634	writew(-len, &lp.tx_ring[entry].length);
635	/* start and end of packet, ownership */
636	writel(readl(&lp.tx_ring[entry].base) \| (T_STP\|T_ENP\|T_OWN), &lp.tx_ring[entry].base);
637	/* update current pointers */
638	lp.tx_cur = (++lp.tx_cur) & lp.txRingMask;
639	}
640
641	/**************************************************************************
642	DISABLE - Turn off ethernet interface
643	***************************************************************************/
644	static void depca_disable(struct dev *dev)
645	{
646	struct nic nic = (struct nic )dev;
647	/* reset and disable merge */
648	depca_reset(nic);
649
650	STOP_DEPCA;
651	}
652
653	/**************************************************************************
654	IRQ - Interrupt Control
655	***************************************************************************/
656	static void depca_irq(struct nic *nic __unused, irq_action_t action __unused)
657	{
658	switch ( action ) {
659	case DISABLE :
660	break;
661	case ENABLE :
662	break;
663	case FORCE :
664	break;
665	}
666	}
667
668	/*
669	** Look for a special sequence in the Ethernet station address PROM that
670	** is common across all DEPCA products. Note that the original DEPCA needs
671	** its ROM address counter to be initialized and enabled. Only enable
672	** if the first address octet is a 0x08 - this minimises the chances of
673	** messing around with some other hardware, but it assumes that this DEPCA
674	** card initialized itself correctly.
675	**
676	** Search the Ethernet address ROM for the signature. Since the ROM address
677	** counter can start at an arbitrary point, the search must include the entire
678	** probe sequence length plus the (length_of_the_signature - 1).
679	** Stop the search IMMEDIATELY after the signature is found so that the
680	** PROM address counter is correctly positioned at the start of the
681	** ethernet address for later read out.
682	*/
683	static int depca_probe1(struct nic *nic)
684	{
685	u8 data, nicsr;
686	/* This is only correct for little endian machines, but then
687	Etherboot doesn't work on anything but a PC */
688	u8 sig[] = { 0xFF, 0x00, 0x55, 0xAA, 0xFF, 0x00, 0x55, 0xAA };
689	int i, j;
690	long sum, chksum;
691
692	data = inb(DEPCA_PROM); /* clear counter on DEPCA */
693	data = inb(DEPCA_PROM); /* read data */
694	if (data == 0x8) {
695	nicsr = inb(DEPCA_NICSR);
696	nicsr \|= AAC;
697	outb(nicsr, DEPCA_NICSR);
698	}
699	for (i = 0, j = 0; j < (int)sizeof(sig) && i < PROBE_LENGTH+((int)sizeof(sig))-1; ++i) {
700	data = inb(DEPCA_PROM);
701	if (data == sig[j]) /* track signature */
702	++j;
703	else
704	j = (data == sig[0]) ? 1 : 0;
705	}
706	if (j != sizeof(sig))
707	return (0);
708	/* put the card in its initial state */
709	STOP_DEPCA;
710	nicsr = ((inb(DEPCA_NICSR) & ~SHE & ~RBE & ~IEN) \| IM);
711	outb(nicsr, DEPCA_NICSR);
712	if (inw(DEPCA_DATA) != STOP)
713	return (0);
714	memcpy((char *)mem_start, sig, sizeof(sig));
715	if (memcmp((char *)mem_start, sig, sizeof(sig)) != 0)
716	return (0);
717	for (i = 0, j = 0, sum = 0; j < 3; j++) {
718	sum <<= 1;
719	if (sum > 0xFFFF)
720	sum -= 0xFFFF;
721	sum += (u8)(nic->node_addr[i++] = inb(DEPCA_PROM));
722	sum += (u16)((nic->node_addr[i++] = inb(DEPCA_PROM)) << 8);
723	if (sum > 0xFFFF)
724	sum -= 0xFFFF;
725	}
726	if (sum == 0xFFFF)
727	sum = 0;
728	chksum = (u8)inb(DEPCA_PROM);
729	chksum \|= (u16)(inb(DEPCA_PROM) << 8);
730	mem_len = (adapter == DEPCA) ? (48 << 10) : (64 << 10);
731	offset = 0;
732	if (nicsr & BUF) {
733	offset = 0x8000;
734	nicsr &= ~BS;
735	mem_len -= (32 << 10);
736	}
737	if (adapter != DEPCA) /* enable shadow RAM */
738	outb(nicsr \|= SHE, DEPCA_NICSR);
739	printf("%s base %#hX, memory [%#hX-%#hX], addr %!",
740	adapter_name[adapter], ioaddr, mem_start, mem_start + mem_len,
741	nic->node_addr);
742	if (sum != chksum)
743	printf(" (bad checksum)");
744	putchar('\n');
745	return (1);
746	}
747
748	/**************************************************************************
749	PROBE - Look for an adapter, this routine's visible to the outside
750	***************************************************************************/
751	static int depca_probe(struct dev dev, unsigned short probe_addrs)
752	{
753	struct nic nic = (struct nic )dev;
754	static unsigned short base[] = DEPCA_IO_PORTS;
755	int i;
756
757	if (probe_addrs == 0 \|\| probe_addrs[0] == 0)
758	probe_addrs = base; /* Use defaults */
759	for (i = 0; (ioaddr = base[i]) != 0; ++i) {
760	if (depca_probe1(nic))
761	break;
762	}
763	if (ioaddr == 0)
764	return (0);
765
766	nic->irqno = 0;
767	nic->ioaddr = ioaddr & ~3;
768
769	depca_reset(nic);
770	/* point to NIC specific routines */
771	dev->disable = depca_disable;
772	nic->poll = depca_poll;
773	nic->transmit = depca_transmit;
774	nic->irq = depca_irq;
775
776	/* Based on PnP ISA map */
777	dev->devid.vendor_id = htons(GENERIC_ISAPNP_VENDOR);
778	dev->devid.device_id = htons(0x80f7);
779	return 1;
780	}
781
782	static struct isa_driver depca_driver __isa_driver = {
783	.type = NIC_DRIVER,
784	.name = "DEPCA",
785	.probe = depca_probe,
786	.ioaddrs = 0,
787	};

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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/depca.c@ 1

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