e1000.c@ 1300

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1	/**************************************************************************
2	Etherboot - BOOTP/TFTP Bootstrap Program
3	Inter Pro 1000 for Etherboot
4	Drivers are port from Intel's Linux driver e1000-4.3.15
5
6	***************************************************************************/
7	/*******************************************************************************
8
9
10	Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
11
12	This program is free software; you can redistribute it and/or modify it
13	under the terms of the GNU General Public License as published by the Free
14	Software Foundation; either version 2 of the License, or (at your option)
15	any later version.
16
17	This program is distributed in the hope that it will be useful, but WITHOUT
18	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20	more details.
21
22	You should have received a copy of the GNU General Public License along with
23	this program; if not, write to the Free Software Foundation, Inc., 59
24	Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25
26	The full GNU General Public License is included in this distribution in the
27	file called LICENSE.
28
29	Contact Information:
30	Linux NICS <[email protected]>
31	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33	*******************************************************************************/
34	/*
35	* Copyright (C) Archway Digital Solutions.
36	*
37	* written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38	* 2/9/2002
39	*
40	* Copyright (C) Linux Networx.
41	* Massive upgrade to work with the new intel gigabit NICs.
42	* <ebiederman at lnxi dot com>
43	*
44	* Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
45	* Georg Baum <[email protected]>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
46	*
47	* 01/2004: Updated to Linux driver 5.2.22 by Georg Baum <[email protected]>
48	*/
49
50	/* to get some global routines like printf */
51	#include "etherboot.h"
52	/* to get the interface to the body of the program */
53	#include "nic.h"
54	/* to get the PCI support functions, if this is a PCI NIC */
55	#include "pci.h"
56	#include "timer.h"
57
58	typedef unsigned char *dma_addr_t;
59
60	typedef enum {
61	FALSE = 0,
62	TRUE = 1
63	} boolean_t;
64
65	#define DEBUG 0
66
67
68	/* Some pieces of code are disabled with #if 0 ... #endif.
69	* They are not deleted to show where the etherboot driver differs
70	* from the linux driver below the function level.
71	* Some member variables of the hw struct have been eliminated
72	* and the corresponding inplace checks inserted instead.
73	* Pieces such as LED handling that we definitely don't need are deleted.
74	*
75	* Please keep the function ordering so that it is easy to produce diffs
76	* against the linux driver.
77	*
78	* The following defines should not be needed normally,
79	* but may be helpful for debugging purposes. */
80
81	/* Define this if you want to program the transmission control register
82	* the way the Linux driver does it. */
83	#undef LINUX_DRIVER_TCTL
84
85	/* Define this to behave more like the Linux driver. */
86	#undef LINUX_DRIVER
87
88	#include "e1000_hw.h"
89
90	#define RX_BUFS 8
91	#define MAX_PACKET 2096
92
93	/* NIC specific static variables go here */
94	static struct e1000_hw hw;
95	static char tx_pool[128 + 16];
96	static char rx_pool[128 + 16];
97	static char packets[MAX_PACKET * RX_BUFS];
98
99	static struct e1000_tx_desc *tx_base;
100	static struct e1000_rx_desc *rx_base;
101
102	static int tx_tail;
103	static int rx_tail, rx_last;
104
105	/* Function forward declarations */
106	static int e1000_setup_link(struct e1000_hw *hw);
107	static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
108	static int e1000_setup_copper_link(struct e1000_hw *hw);
109	static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
110	static void e1000_config_collision_dist(struct e1000_hw *hw);
111	static int e1000_config_mac_to_phy(struct e1000_hw *hw);
112	static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
113	static int e1000_check_for_link(struct e1000_hw *hw);
114	static int e1000_wait_autoneg(struct e1000_hw *hw);
115	static void e1000_get_speed_and_duplex(struct e1000_hw hw, uint16_t speed, uint16_t *duplex);
116	static int e1000_read_phy_reg(struct e1000_hw hw, uint32_t reg_addr, uint16_t phy_data);
117	static int e1000_read_phy_reg_ex(struct e1000_hw hw, uint32_t reg_addr, uint16_t phy_data);
118	static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
119	static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
120	static void e1000_phy_hw_reset(struct e1000_hw *hw);
121	static int e1000_phy_reset(struct e1000_hw *hw);
122	static int e1000_detect_gig_phy(struct e1000_hw *hw);
123	static int e1000_read_eeprom(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
124	static void e1000_init_rx_addrs(struct e1000_hw *hw);
125	static void e1000_clear_vfta(struct e1000_hw *hw);
126	static void e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value);
127	static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
128
129	/* Printing macros... */
130
131	#define E1000_ERR(args...) printf("e1000: " args)
132
133	#if DEBUG >= 3
134	#define E1000_DBG(args...) printf("e1000: " args)
135	#else
136	#define E1000_DBG(args...)
137	#endif
138
139	#define MSGOUT(S, A, B) printk(S "\n", A, B)
140	#if DEBUG >= 2
141	#define DEBUGFUNC(F) DEBUGOUT(F "\n");
142	#else
143	#define DEBUGFUNC(F)
144	#endif
145	#if DEBUG >= 1
146	#define DEBUGOUT(S) printf(S)
147	#define DEBUGOUT1(S,A) printf(S,A)
148	#define DEBUGOUT2(S,A,B) printf(S,A,B)
149	#define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
150	#define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
151	#else
152	#define DEBUGOUT(S)
153	#define DEBUGOUT1(S,A)
154	#define DEBUGOUT2(S,A,B)
155	#define DEBUGOUT3(S,A,B,C)
156	#define DEBUGOUT7(S,A,B,C,D,E,F,G)
157	#endif
158
159	#define E1000_WRITE_REG(a, reg, value) ( \
160	((a)->mac_type >= e1000_82543) ? \
161	(writel((value), ((a)->hw_addr + E1000_##reg))) : \
162	(writel((value), ((a)->hw_addr + E1000_82542_##reg))))
163
164	#define E1000_READ_REG(a, reg) ( \
165	((a)->mac_type >= e1000_82543) ? \
166	readl((a)->hw_addr + E1000_##reg) : \
167	readl((a)->hw_addr + E1000_82542_##reg))
168
169	#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
170	((a)->mac_type >= e1000_82543) ? \
171	writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
172	writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
173
174	#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
175	((a)->mac_type >= e1000_82543) ? \
176	readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
177	readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
178
179	#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
180
181
182	/******************************************************************************
183	* Inline functions from e1000_main.c of the linux driver
184	******************************************************************************/
185
186	static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
187	{
188	pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
189	}
190
191	static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
192	{
193	pci_write_config_word(hw->pdev, PCI_COMMAND,
194	hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
195	}
196
197
198	/******************************************************************************
199	* Functions from e1000_hw.c of the linux driver
200	******************************************************************************/
201
202	/******************************************************************************
203	* Set the phy type member in the hw struct.
204	*
205	* hw - Struct containing variables accessed by shared code
206	*****************************************************************************/
207	static int32_t
208	e1000_set_phy_type(struct e1000_hw *hw)
209	{
210	DEBUGFUNC("e1000_set_phy_type");
211
212	switch(hw->phy_id) {
213	case M88E1000_E_PHY_ID:
214	case M88E1000_I_PHY_ID:
215	case M88E1011_I_PHY_ID:
216	hw->phy_type = e1000_phy_m88;
217	break;
218	case IGP01E1000_I_PHY_ID:
219	hw->phy_type = e1000_phy_igp;
220	break;
221	case GG82563_E_PHY_ID:
222	if (hw->mac_type == e1000_80003es2lan) {
223	hw->phy_type = e1000_phy_gg82563;
224	break;
225	}
226	default:
227	/* Should never have loaded on this device */
228	hw->phy_type = e1000_phy_undefined;
229	return -E1000_ERR_PHY_TYPE;
230	}
231
232	return E1000_SUCCESS;
233	}
234
235	/******************************************************************************
236	* IGP phy init script - initializes the GbE PHY
237	*
238	* hw - Struct containing variables accessed by shared code
239	*****************************************************************************/
240	static void
241	e1000_phy_init_script(struct e1000_hw *hw)
242	{
243	DEBUGFUNC("e1000_phy_init_script");
244
245	#if 0
246	/* See e1000_sw_init() of the Linux driver */
247	if(hw->phy_init_script) {
248	#else
249	if((hw->mac_type == e1000_82541) \|\|
250	(hw->mac_type == e1000_82547) \|\|
251	(hw->mac_type == e1000_82541_rev_2) \|\|
252	(hw->mac_type == e1000_82547_rev_2)) {
253	#endif
254	mdelay(20);
255
256	e1000_write_phy_reg(hw,0x0000,0x0140);
257
258	mdelay(5);
259
260	if(hw->mac_type == e1000_82541 \|\| hw->mac_type == e1000_82547) {
261	e1000_write_phy_reg(hw, 0x1F95, 0x0001);
262
263	e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
264
265	e1000_write_phy_reg(hw, 0x1F79, 0x0018);
266
267	e1000_write_phy_reg(hw, 0x1F30, 0x1600);
268
269	e1000_write_phy_reg(hw, 0x1F31, 0x0014);
270
271	e1000_write_phy_reg(hw, 0x1F32, 0x161C);
272
273	e1000_write_phy_reg(hw, 0x1F94, 0x0003);
274
275	e1000_write_phy_reg(hw, 0x1F96, 0x003F);
276
277	e1000_write_phy_reg(hw, 0x2010, 0x0008);
278	} else {
279	e1000_write_phy_reg(hw, 0x1F73, 0x0099);
280	}
281
282	e1000_write_phy_reg(hw, 0x0000, 0x3300);
283
284
285	if(hw->mac_type == e1000_82547) {
286	uint16_t fused, fine, coarse;
287
288	/* Move to analog registers page */
289	e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
290
291	if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
292	e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
293
294	fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
295	coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
296
297	if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
298	coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
299	fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
300	} else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
301	fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
302
303	fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) \|
304	(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) \|
305	(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
306
307	e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
308	e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
309	IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
310	}
311	}
312	}
313	}
314
315	/******************************************************************************
316	* Set the mac type member in the hw struct.
317	*
318	* hw - Struct containing variables accessed by shared code
319	*****************************************************************************/
320	static int
321	e1000_set_mac_type(struct e1000_hw *hw)
322	{
323	DEBUGFUNC("e1000_set_mac_type");
324
325	switch (hw->device_id) {
326	case E1000_DEV_ID_82542:
327	switch (hw->revision_id) {
328	case E1000_82542_2_0_REV_ID:
329	hw->mac_type = e1000_82542_rev2_0;
330	break;
331	case E1000_82542_2_1_REV_ID:
332	hw->mac_type = e1000_82542_rev2_1;
333	break;
334	default:
335	/* Invalid 82542 revision ID */
336	return -E1000_ERR_MAC_TYPE;
337	}
338	break;
339	case E1000_DEV_ID_82543GC_FIBER:
340	case E1000_DEV_ID_82543GC_COPPER:
341	hw->mac_type = e1000_82543;
342	break;
343	case E1000_DEV_ID_82544EI_COPPER:
344	case E1000_DEV_ID_82544EI_FIBER:
345	case E1000_DEV_ID_82544GC_COPPER:
346	case E1000_DEV_ID_82544GC_LOM:
347	hw->mac_type = e1000_82544;
348	break;
349	case E1000_DEV_ID_82540EM:
350	case E1000_DEV_ID_82540EM_LOM:
351	case E1000_DEV_ID_82540EP:
352	case E1000_DEV_ID_82540EP_LOM:
353	case E1000_DEV_ID_82540EP_LP:
354	hw->mac_type = e1000_82540;
355	break;
356	case E1000_DEV_ID_82545EM_COPPER:
357	case E1000_DEV_ID_82545EM_FIBER:
358	hw->mac_type = e1000_82545;
359	break;
360	case E1000_DEV_ID_82545GM_COPPER:
361	case E1000_DEV_ID_82545GM_FIBER:
362	case E1000_DEV_ID_82545GM_SERDES:
363	hw->mac_type = e1000_82545_rev_3;
364	break;
365	case E1000_DEV_ID_82546EB_COPPER:
366	case E1000_DEV_ID_82546EB_FIBER:
367	case E1000_DEV_ID_82546EB_QUAD_COPPER:
368	hw->mac_type = e1000_82546;
369	break;
370	case E1000_DEV_ID_82546GB_COPPER:
371	case E1000_DEV_ID_82546GB_FIBER:
372	case E1000_DEV_ID_82546GB_SERDES:
373	hw->mac_type = e1000_82546_rev_3;
374	break;
375	case E1000_DEV_ID_82541EI:
376	case E1000_DEV_ID_82541EI_MOBILE:
377	hw->mac_type = e1000_82541;
378	break;
379	case E1000_DEV_ID_82541ER:
380	case E1000_DEV_ID_82541GI:
381	case E1000_DEV_ID_82541GI_MOBILE:
382	hw->mac_type = e1000_82541_rev_2;
383	break;
384	case E1000_DEV_ID_82547EI:
385	hw->mac_type = e1000_82547;
386	break;
387	case E1000_DEV_ID_82547GI:
388	hw->mac_type = e1000_82547_rev_2;
389	break;
390	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
391	hw->mac_type = e1000_80003es2lan;
392	break;
393	default:
394	/* Should never have loaded on this device */
395	return -E1000_ERR_MAC_TYPE;
396	}
397
398	return E1000_SUCCESS;
399	}
400
401	/*****************************************************************************
402	* Set media type and TBI compatibility.
403	*
404	* hw - Struct containing variables accessed by shared code
405	* **************************************************************************/
406	static void
407	e1000_set_media_type(struct e1000_hw *hw)
408	{
409	uint32_t status;
410
411	DEBUGFUNC("e1000_set_media_type");
412
413	if(hw->mac_type != e1000_82543) {
414	/* tbi_compatibility is only valid on 82543 */
415	hw->tbi_compatibility_en = FALSE;
416	}
417
418	switch (hw->device_id) {
419	case E1000_DEV_ID_82545GM_SERDES:
420	case E1000_DEV_ID_82546GB_SERDES:
421	hw->media_type = e1000_media_type_internal_serdes;
422	break;
423	default:
424	if(hw->mac_type >= e1000_82543) {
425	status = E1000_READ_REG(hw, STATUS);
426	if(status & E1000_STATUS_TBIMODE) {
427	hw->media_type = e1000_media_type_fiber;
428	/* tbi_compatibility not valid on fiber */
429	hw->tbi_compatibility_en = FALSE;
430	} else {
431	hw->media_type = e1000_media_type_copper;
432	}
433	} else {
434	/* This is an 82542 (fiber only) */
435	hw->media_type = e1000_media_type_fiber;
436	}
437	}
438	}
439
440	/******************************************************************************
441	* Reset the transmit and receive units; mask and clear all interrupts.
442	*
443	* hw - Struct containing variables accessed by shared code
444	*****************************************************************************/
445	static void
446	e1000_reset_hw(struct e1000_hw *hw)
447	{
448	uint32_t ctrl;
449	uint32_t ctrl_ext;
450	uint32_t icr;
451	uint32_t manc;
452
453	DEBUGFUNC("e1000_reset_hw");
454
455	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
456	if(hw->mac_type == e1000_82542_rev2_0) {
457	DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
458	e1000_pci_clear_mwi(hw);
459	}
460
461	/* Clear interrupt mask to stop board from generating interrupts */
462	DEBUGOUT("Masking off all interrupts\n");
463	E1000_WRITE_REG(hw, IMC, 0xffffffff);
464
465	/* Disable the Transmit and Receive units. Then delay to allow
466	* any pending transactions to complete before we hit the MAC with
467	* the global reset.
468	*/
469	E1000_WRITE_REG(hw, RCTL, 0);
470	E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
471	E1000_WRITE_FLUSH(hw);
472
473	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
474	hw->tbi_compatibility_on = FALSE;
475
476	/* Delay to allow any outstanding PCI transactions to complete before
477	* resetting the device
478	*/
479	mdelay(10);
480
481	ctrl = E1000_READ_REG(hw, CTRL);
482
483	/* Must reset the PHY before resetting the MAC */
484	if((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
485	E1000_WRITE_REG_IO(hw, CTRL, (ctrl \| E1000_CTRL_PHY_RST));
486	mdelay(5);
487	}
488
489	/* Issue a global reset to the MAC. This will reset the chip's
490	* transmit, receive, DMA, and link units. It will not effect
491	* the current PCI configuration. The global reset bit is self-
492	* clearing, and should clear within a microsecond.
493	*/
494	DEBUGOUT("Issuing a global reset to MAC\n");
495
496	switch(hw->mac_type) {
497	case e1000_82544:
498	case e1000_82540:
499	case e1000_82545:
500	case e1000_82546:
501	case e1000_82541:
502	case e1000_82541_rev_2:
503	/* These controllers can't ack the 64-bit write when issuing the
504	* reset, so use IO-mapping as a workaround to issue the reset */
505	E1000_WRITE_REG_IO(hw, CTRL, (ctrl \| E1000_CTRL_RST));
506	break;
507	case e1000_82545_rev_3:
508	case e1000_82546_rev_3:
509	/* Reset is performed on a shadow of the control register */
510	E1000_WRITE_REG(hw, CTRL_DUP, (ctrl \| E1000_CTRL_RST));
511	break;
512	default:
513	E1000_WRITE_REG(hw, CTRL, (ctrl \| E1000_CTRL_RST));
514	break;
515	}
516
517	/* After MAC reset, force reload of EEPROM to restore power-on settings to
518	* device. Later controllers reload the EEPROM automatically, so just wait
519	* for reload to complete.
520	*/
521	switch(hw->mac_type) {
522	case e1000_82542_rev2_0:
523	case e1000_82542_rev2_1:
524	case e1000_82543:
525	case e1000_82544:
526	/* Wait for reset to complete */
527	udelay(10);
528	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
529	ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
530	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
531	E1000_WRITE_FLUSH(hw);
532	/* Wait for EEPROM reload */
533	mdelay(2);
534	break;
535	case e1000_82541:
536	case e1000_82541_rev_2:
537	case e1000_82547:
538	case e1000_82547_rev_2:
539	/* Wait for EEPROM reload */
540	mdelay(20);
541	break;
542	default:
543	/* Wait for EEPROM reload (it happens automatically) */
544	mdelay(5);
545	break;
546	}
547
548	/* Disable HW ARPs on ASF enabled adapters */
549	if(hw->mac_type >= e1000_82540) {
550	manc = E1000_READ_REG(hw, MANC);
551	manc &= ~(E1000_MANC_ARP_EN);
552	E1000_WRITE_REG(hw, MANC, manc);
553	}
554
555	if((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
556	e1000_phy_init_script(hw);
557	}
558
559	/* Clear interrupt mask to stop board from generating interrupts */
560	DEBUGOUT("Masking off all interrupts\n");
561	E1000_WRITE_REG(hw, IMC, 0xffffffff);
562
563	/* Clear any pending interrupt events. */
564	icr = E1000_READ_REG(hw, ICR);
565
566	/* If MWI was previously enabled, reenable it. */
567	if(hw->mac_type == e1000_82542_rev2_0) {
568	#ifdef LINUX_DRIVER
569	if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
570	#endif
571	e1000_pci_set_mwi(hw);
572	}
573	}
574
575	/******************************************************************************
576	* Performs basic configuration of the adapter.
577	*
578	* hw - Struct containing variables accessed by shared code
579	*
580	* Assumes that the controller has previously been reset and is in a
581	* post-reset uninitialized state. Initializes the receive address registers,
582	* multicast table, and VLAN filter table. Calls routines to setup link
583	* configuration and flow control settings. Clears all on-chip counters. Leaves
584	* the transmit and receive units disabled and uninitialized.
585	*****************************************************************************/
586	static int
587	e1000_init_hw(struct e1000_hw *hw)
588	{
589	uint32_t ctrl, status;
590	uint32_t i;
591	int32_t ret_val;
592	uint16_t pcix_cmd_word;
593	uint16_t pcix_stat_hi_word;
594	uint16_t cmd_mmrbc;
595	uint16_t stat_mmrbc;
596	e1000_bus_type bus_type = e1000_bus_type_unknown;
597
598	DEBUGFUNC("e1000_init_hw");
599
600	/* Set the media type and TBI compatibility */
601	e1000_set_media_type(hw);
602
603	/* Disabling VLAN filtering. */
604	DEBUGOUT("Initializing the IEEE VLAN\n");
605	E1000_WRITE_REG(hw, VET, 0);
606
607	e1000_clear_vfta(hw);
608
609	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
610	if(hw->mac_type == e1000_82542_rev2_0) {
611	DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
612	e1000_pci_clear_mwi(hw);
613	E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
614	E1000_WRITE_FLUSH(hw);
615	mdelay(5);
616	}
617
618	/* Setup the receive address. This involves initializing all of the Receive
619	* Address Registers (RARs 0 - 15).
620	*/
621	e1000_init_rx_addrs(hw);
622
623	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
624	if(hw->mac_type == e1000_82542_rev2_0) {
625	E1000_WRITE_REG(hw, RCTL, 0);
626	E1000_WRITE_FLUSH(hw);
627	mdelay(1);
628	#ifdef LINUX_DRIVER
629	if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
630	#endif
631	e1000_pci_set_mwi(hw);
632	}
633
634	/* Zero out the Multicast HASH table */
635	DEBUGOUT("Zeroing the MTA\n");
636	for(i = 0; i < E1000_MC_TBL_SIZE; i++)
637	E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
638
639	#if 0
640	/* Set the PCI priority bit correctly in the CTRL register. This
641	* determines if the adapter gives priority to receives, or if it
642	* gives equal priority to transmits and receives.
643	*/
644	if(hw->dma_fairness) {
645	ctrl = E1000_READ_REG(hw, CTRL);
646	E1000_WRITE_REG(hw, CTRL, ctrl \| E1000_CTRL_PRIOR);
647	}
648	#endif
649
650	switch(hw->mac_type) {
651	case e1000_82545_rev_3:
652	case e1000_82546_rev_3:
653	break;
654	case e1000_80003es2lan:
655	{
656	int32_t timeout = 200;
657	while(timeout) {
658	if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
659	break;
660	else mdelay(10);
661	timeout--;
662	}
663	if(!timeout) {
664	/* We don't want to continue accessing MAC registers. */
665	return -E1000_ERR_RESET;
666	}
667	break;
668	}
669	default:
670	if (hw->mac_type >= e1000_82543) {
671	/* See e1000_get_bus_info() of the Linux driver */
672	status = E1000_READ_REG(hw, STATUS);
673	bus_type = (status & E1000_STATUS_PCIX_MODE) ?
674	e1000_bus_type_pcix : e1000_bus_type_pci;
675	}
676
677	/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
678	if(bus_type == e1000_bus_type_pcix) {
679	pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
680	pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
681	cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
682	PCIX_COMMAND_MMRBC_SHIFT;
683	stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
684	PCIX_STATUS_HI_MMRBC_SHIFT;
685	if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
686	stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
687	if(cmd_mmrbc > stat_mmrbc) {
688	pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
689	pcix_cmd_word \|= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
690	pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
691	}
692	}
693	break;
694	}
695
696	/* Call a subroutine to configure the link and setup flow control. */
697	ret_val = e1000_setup_link(hw);
698
699	/* Set the transmit descriptor write-back policy */
700	if(hw->mac_type > e1000_82544) {
701	ctrl = E1000_READ_REG(hw, TXDCTL);
702	ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) \| E1000_TXDCTL_FULL_TX_DESC_WB;
703	E1000_WRITE_REG(hw, TXDCTL, ctrl);
704	}
705
706	#if 0
707	/* Clear all of the statistics registers (clear on read). It is
708	* important that we do this after we have tried to establish link
709	* because the symbol error count will increment wildly if there
710	* is no link.
711	*/
712	e1000_clear_hw_cntrs(hw);
713	#endif
714
715	return ret_val;
716	}
717
718	/******************************************************************************
719	* Adjust SERDES output amplitude based on EEPROM setting.
720	*
721	* hw - Struct containing variables accessed by shared code.
722	*****************************************************************************/
723	static int32_t
724	e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
725	{
726	uint16_t eeprom_data;
727	int32_t ret_val;
728
729	DEBUGFUNC("e1000_adjust_serdes_amplitude");
730
731	if(hw->media_type != e1000_media_type_internal_serdes)
732	return E1000_SUCCESS;
733
734	switch(hw->mac_type) {
735	case e1000_82545_rev_3:
736	case e1000_82546_rev_3:
737	break;
738	default:
739	return E1000_SUCCESS;
740	}
741
742	if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
743	&eeprom_data))) {
744	return ret_val;
745	}
746
747	if(eeprom_data != EEPROM_RESERVED_WORD) {
748	/* Adjust SERDES output amplitude only. */
749	eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
750	if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
751	eeprom_data)))
752	return ret_val;
753	}
754
755	return E1000_SUCCESS;
756	}
757
758	/******************************************************************************
759	* Configures flow control and link settings.
760	*
761	* hw - Struct containing variables accessed by shared code
762	*
763	* Determines which flow control settings to use. Calls the apropriate media-
764	* specific link configuration function. Configures the flow control settings.
765	* Assuming the adapter has a valid link partner, a valid link should be
766	* established. Assumes the hardware has previously been reset and the
767	* transmitter and receiver are not enabled.
768	*****************************************************************************/
769	static int
770	e1000_setup_link(struct e1000_hw *hw)
771	{
772	uint32_t ctrl_ext;
773	int32_t ret_val;
774	uint16_t eeprom_data;
775
776	DEBUGFUNC("e1000_setup_link");
777
778	/* Read and store word 0x0F of the EEPROM. This word contains bits
779	* that determine the hardware's default PAUSE (flow control) mode,
780	* a bit that determines whether the HW defaults to enabling or
781	* disabling auto-negotiation, and the direction of the
782	* SW defined pins. If there is no SW over-ride of the flow
783	* control setting, then the variable hw->fc will
784	* be initialized based on a value in the EEPROM.
785	*/
786	if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
787	DEBUGOUT("EEPROM Read Error\n");
788	return -E1000_ERR_EEPROM;
789	}
790
791	if(hw->fc == e1000_fc_default) {
792	if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
793	hw->fc = e1000_fc_none;
794	else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
795	EEPROM_WORD0F_ASM_DIR)
796	hw->fc = e1000_fc_tx_pause;
797	else
798	hw->fc = e1000_fc_full;
799	}
800
801	/* We want to save off the original Flow Control configuration just
802	* in case we get disconnected and then reconnected into a different
803	* hub or switch with different Flow Control capabilities.
804	*/
805	if(hw->mac_type == e1000_82542_rev2_0)
806	hw->fc &= (~e1000_fc_tx_pause);
807
808	#if 0
809	/* See e1000_sw_init() of the Linux driver */
810	if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
811	#else
812	if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
813	#endif
814	hw->fc &= (~e1000_fc_rx_pause);
815
816	#if 0
817	hw->original_fc = hw->fc;
818	#endif
819
820	DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
821
822	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
823	* polarity value for the SW controlled pins, and setup the
824	* Extended Device Control reg with that info.
825	* This is needed because one of the SW controlled pins is used for
826	* signal detection. So this should be done before e1000_setup_pcs_link()
827	* or e1000_phy_setup() is called.
828	*/
829	if(hw->mac_type == e1000_82543) {
830	ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
831	SWDPIO__EXT_SHIFT);
832	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
833	}
834
835	/* Call the necessary subroutine to configure the link. */
836	ret_val = (hw->media_type == e1000_media_type_copper) ?
837	e1000_setup_copper_link(hw) :
838	e1000_setup_fiber_serdes_link(hw);
839	if (ret_val < 0) {
840	return ret_val;
841	}
842
843	/* Initialize the flow control address, type, and PAUSE timer
844	* registers to their default values. This is done even if flow
845	* control is disabled, because it does not hurt anything to
846	* initialize these registers.
847	*/
848	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
849
850	E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
851	E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
852	E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
853	#if 0
854	E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
855	#else
856	E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
857	#endif
858
859	/* Set the flow control receive threshold registers. Normally,
860	* these registers will be set to a default threshold that may be
861	* adjusted later by the driver's runtime code. However, if the
862	* ability to transmit pause frames in not enabled, then these
863	* registers will be set to 0.
864	*/
865	if(!(hw->fc & e1000_fc_tx_pause)) {
866	E1000_WRITE_REG(hw, FCRTL, 0);
867	E1000_WRITE_REG(hw, FCRTH, 0);
868	} else {
869	/* We need to set up the Receive Threshold high and low water marks
870	* as well as (optionally) enabling the transmission of XON frames.
871	*/
872	#if 0
873	if(hw->fc_send_xon) {
874	E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water \| E1000_FCRTL_XONE));
875	E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
876	} else {
877	E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
878	E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
879	}
880	#else
881	E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH \| E1000_FCRTL_XONE));
882	E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
883	#endif
884	}
885	return ret_val;
886	}
887
888	/******************************************************************************
889	* Sets up link for a fiber based or serdes based adapter
890	*
891	* hw - Struct containing variables accessed by shared code
892	*
893	* Manipulates Physical Coding Sublayer functions in order to configure
894	* link. Assumes the hardware has been previously reset and the transmitter
895	* and receiver are not enabled.
896	*****************************************************************************/
897	static int
898	e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
899	{
900	uint32_t ctrl;
901	uint32_t status;
902	uint32_t txcw = 0;
903	uint32_t i;
904	uint32_t signal = 0;
905	int32_t ret_val;
906
907	DEBUGFUNC("e1000_setup_fiber_serdes_link");
908
909	/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
910	* set when the optics detect a signal. On older adapters, it will be
911	* cleared when there is a signal. This applies to fiber media only.
912	* If we're on serdes media, adjust the output amplitude to value set in
913	* the EEPROM.
914	*/
915	ctrl = E1000_READ_REG(hw, CTRL);
916	if(hw->media_type == e1000_media_type_fiber)
917	signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
918
919	if((ret_val = e1000_adjust_serdes_amplitude(hw)))
920	return ret_val;
921
922	/* Take the link out of reset */
923	ctrl &= ~(E1000_CTRL_LRST);
924
925	#if 0
926	/* Adjust VCO speed to improve BER performance */
927	if((ret_val = e1000_set_vco_speed(hw)))
928	return ret_val;
929	#endif
930
931	e1000_config_collision_dist(hw);
932
933	/* Check for a software override of the flow control settings, and setup
934	* the device accordingly. If auto-negotiation is enabled, then software
935	* will have to set the "PAUSE" bits to the correct value in the Tranmsit
936	* Config Word Register (TXCW) and re-start auto-negotiation. However, if
937	* auto-negotiation is disabled, then software will have to manually
938	* configure the two flow control enable bits in the CTRL register.
939	*
940	* The possible values of the "fc" parameter are:
941	* 0: Flow control is completely disabled
942	* 1: Rx flow control is enabled (we can receive pause frames, but
943	* not send pause frames).
944	* 2: Tx flow control is enabled (we can send pause frames but we do
945	* not support receiving pause frames).
946	* 3: Both Rx and TX flow control (symmetric) are enabled.
947	*/
948	switch (hw->fc) {
949	case e1000_fc_none:
950	/* Flow control is completely disabled by a software over-ride. */
951	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD);
952	break;
953	case e1000_fc_rx_pause:
954	/* RX Flow control is enabled and TX Flow control is disabled by a
955	* software over-ride. Since there really isn't a way to advertise
956	* that we are capable of RX Pause ONLY, we will advertise that we
957	* support both symmetric and asymmetric RX PAUSE. Later, we will
958	* disable the adapter's ability to send PAUSE frames.
959	*/
960	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_PAUSE_MASK);
961	break;
962	case e1000_fc_tx_pause:
963	/* TX Flow control is enabled, and RX Flow control is disabled, by a
964	* software over-ride.
965	*/
966	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_ASM_DIR);
967	break;
968	case e1000_fc_full:
969	/* Flow control (both RX and TX) is enabled by a software over-ride. */
970	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_PAUSE_MASK);
971	break;
972	default:
973	DEBUGOUT("Flow control param set incorrectly\n");
974	return -E1000_ERR_CONFIG;
975	break;
976	}
977
978	/* Since auto-negotiation is enabled, take the link out of reset (the link
979	* will be in reset, because we previously reset the chip). This will
980	* restart auto-negotiation. If auto-neogtiation is successful then the
981	* link-up status bit will be set and the flow control enable bits (RFCE
982	* and TFCE) will be set according to their negotiated value.
983	*/
984	DEBUGOUT("Auto-negotiation enabled\n");
985
986	E1000_WRITE_REG(hw, TXCW, txcw);
987	E1000_WRITE_REG(hw, CTRL, ctrl);
988	E1000_WRITE_FLUSH(hw);
989
990	hw->txcw = txcw;
991	mdelay(1);
992
993	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
994	* indication in the Device Status Register. Time-out if a link isn't
995	* seen in 500 milliseconds seconds (Auto-negotiation should complete in
996	* less than 500 milliseconds even if the other end is doing it in SW).
997	* For internal serdes, we just assume a signal is present, then poll.
998	*/
999	if(hw->media_type == e1000_media_type_internal_serdes \|\|
1000	(E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1001	DEBUGOUT("Looking for Link\n");
1002	for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1003	mdelay(10);
1004	status = E1000_READ_REG(hw, STATUS);
1005	if(status & E1000_STATUS_LU) break;
1006	}
1007	if(i == (LINK_UP_TIMEOUT / 10)) {
1008	DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1009	hw->autoneg_failed = 1;
1010	/* AutoNeg failed to achieve a link, so we'll call
1011	* e1000_check_for_link. This routine will force the link up if
1012	* we detect a signal. This will allow us to communicate with
1013	* non-autonegotiating link partners.
1014	*/
1015	if((ret_val = e1000_check_for_link(hw))) {
1016	DEBUGOUT("Error while checking for link\n");
1017	return ret_val;
1018	}
1019	hw->autoneg_failed = 0;
1020	} else {
1021	hw->autoneg_failed = 0;
1022	DEBUGOUT("Valid Link Found\n");
1023	}
1024	} else {
1025	DEBUGOUT("No Signal Detected\n");
1026	}
1027	return E1000_SUCCESS;
1028	}
1029
1030	int32_t
1031	e1000_read_kmrn_reg(struct e1000_hw *hw,
1032	uint32_t reg_addr,
1033	uint16_t *data)
1034	{
1035	uint32_t reg_val;
1036	DEBUGFUNC("e1000_read_kmrn_reg");
1037
1038	/* Write register address */
1039	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
1040	E1000_KUMCTRLSTA_OFFSET) \|
1041	E1000_KUMCTRLSTA_REN;
1042	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
1043	udelay(2);
1044
1045	/* Read the data returned */
1046	reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
1047	*data = (uint16_t)reg_val;
1048
1049	return E1000_SUCCESS;
1050	}
1051
1052	int32_t
1053	e1000_write_kmrn_reg(struct e1000_hw *hw,
1054	uint32_t reg_addr,
1055	uint16_t data)
1056	{
1057	uint32_t reg_val;
1058	DEBUGFUNC("e1000_write_kmrn_reg");
1059
1060	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
1061	E1000_KUMCTRLSTA_OFFSET) \| data;
1062	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
1063	udelay(2);
1064
1065	return E1000_SUCCESS;
1066	}
1067
1068	/********************************************************************
1069	* Copper link setup for e1000_phy_gg82563 series.
1070	*
1071	* hw - Struct containing variables accessed by shared code
1072	*********************************************************************/
1073
1074	static int32_t
1075	e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1076	{
1077	int32_t ret_val;
1078	uint16_t phy_data;
1079	uint32_t reg_data;
1080
1081	DEBUGFUNC("e1000_copper_link_ggp_setup\n");
1082
1083	/* Enable CRS on TX for half-duplex operation. */
1084	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1085	&phy_data);
1086	if(ret_val)
1087	return ret_val;
1088
1089	phy_data \|= GG82563_MSCR_ASSERT_CRS_ON_TX;
1090	/* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1091	phy_data \|= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1092
1093	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1094	phy_data);
1095	if(ret_val)
1096	return ret_val;
1097	/* Options:
1098	* MDI/MDI-X = 0 (default)
1099	* 0 - Auto for all speeds
1100	* 1 - MDI mode
1101	* 2 - MDI-X mode
1102	* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1103	*/
1104	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1105	if(ret_val)
1106	return ret_val;
1107
1108	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1109
1110	phy_data \|= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1111
1112	/* Options:
1113	* disable_polarity_correction = 0 (default)
1114	* Automatic Correction for Reversed Cable Polarity
1115	* 0 - Disabled
1116	* 1 - Enabled
1117	*/
1118	phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1119	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1120
1121	if(ret_val)
1122	return ret_val;
1123
1124	/* SW Reset the PHY so all changes take effect */
1125	ret_val = e1000_phy_reset(hw);
1126	if (ret_val) {
1127	DEBUGOUT("Error Resetting the PHY\n");
1128	return ret_val;
1129	}
1130
1131	if (hw->mac_type == e1000_80003es2lan) {
1132	/* Bypass RX and TX FIFO's */
1133	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1134	E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS \|
1135	E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1136	if (ret_val)
1137	return ret_val;
1138
1139	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1140	if (ret_val)
1141	ret_val;
1142
1143	phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1144	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1145
1146	if (ret_val)
1147	return ret_val;
1148
1149	reg_data = E1000_READ_REG(hw, CTRL_EXT);
1150	reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1151	E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1152
1153	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1154	&phy_data);
1155	if (ret_val)
1156	return ret_val;
1157
1158	/* Enable Electrical Idle on the PHY */
1159	phy_data \|= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1160	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1161	phy_data);
1162
1163	if (ret_val)
1164	return ret_val;
1165
1166	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1167	&phy_data);
1168	if (ret_val)
1169	return ret_val;
1170
1171	/* Disable Pass False Carrier on the PHY */
1172	phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1173
1174	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1175	phy_data);
1176	if (ret_val)
1177	return ret_val;
1178	}
1179
1180	return E1000_SUCCESS;
1181	}
1182
1183	/******************************************************************************
1184	* Detects which PHY is present and the speed and duplex
1185	*
1186	* hw - Struct containing variables accessed by shared code
1187	******************************************************************************/
1188	static int
1189	e1000_setup_copper_link(struct e1000_hw *hw)
1190	{
1191	uint32_t ctrl;
1192	int32_t ret_val;
1193	uint16_t i;
1194	uint16_t phy_data;
1195
1196	DEBUGFUNC("e1000_setup_copper_link");
1197
1198	ctrl = E1000_READ_REG(hw, CTRL);
1199
1200	if(hw->mac_type == e1000_80003es2lan) {
1201	uint16_t reg_data;
1202	/* Set the mac to wait the maximum time between each
1203	* iteration and increase the max iterations when
1204	* polling the phy; this fixes erroneous timeouts at 10Mbps. */
1205	ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1206	if (ret_val)
1207	return ret_val;
1208	ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1209	if (ret_val)
1210	return ret_val;
1211	reg_data \|= 0x3F;
1212	ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1213	if (ret_val)
1214	return ret_val;
1215	ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1216	&reg_data);
1217	if (ret_val)
1218	return ret_val;
1219	reg_data \|= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1220	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1221	reg_data);
1222	if (ret_val)
1223	return ret_val;
1224	}
1225
1226	/* With 82543, we need to force speed and duplex on the MAC equal to what
1227	* the PHY speed and duplex configuration is. In addition, we need to
1228	* perform a hardware reset on the PHY to take it out of reset.
1229	*/
1230	if(hw->mac_type > e1000_82543) {
1231	ctrl \|= E1000_CTRL_SLU;
1232	ctrl &= ~(E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
1233	E1000_WRITE_REG(hw, CTRL, ctrl);
1234	} else {
1235	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX \| E1000_CTRL_SLU);
1236	E1000_WRITE_REG(hw, CTRL, ctrl);
1237	e1000_phy_hw_reset(hw);
1238	}
1239
1240	/* Make sure we have a valid PHY */
1241	if((ret_val = e1000_detect_gig_phy(hw))) {
1242	DEBUGOUT("Error, did not detect valid phy.\n");
1243	return ret_val;
1244	}
1245	DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1246
1247	if (hw->phy_type == e1000_phy_gg82563) {
1248	ret_val = e1000_copper_link_ggp_setup(hw);
1249	if(ret_val)
1250	return ret_val;
1251	}
1252
1253	if(hw->mac_type <= e1000_82543 \|\|
1254	hw->mac_type == e1000_82541 \|\| hw->mac_type == e1000_82547 \|\|
1255	#if 0
1256	hw->mac_type == e1000_82541_rev_2 \|\| hw->mac_type == e1000_82547_rev_2)
1257	hw->phy_reset_disable = FALSE;
1258
1259	if(!hw->phy_reset_disable) {
1260	#else
1261	hw->mac_type == e1000_82541_rev_2 \|\| hw->mac_type == e1000_82547_rev_2 \|\|
1262	hw->mac_type == e1000_80003es2lan) {
1263	#endif
1264	if (hw->phy_type == e1000_phy_igp \|\| hw->phy_type == e1000_phy_gg82563) {
1265
1266	if((ret_val = e1000_phy_reset(hw))) {
1267	DEBUGOUT("Error Resetting the PHY\n");
1268	return ret_val;
1269	}
1270
1271	/* Wait 10ms for MAC to configure PHY from eeprom settings */
1272	mdelay(15);
1273
1274	#if 0
1275	/* disable lplu d3 during driver init */
1276	if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1277	DEBUGOUT("Error Disabling LPLU D3\n");
1278	return ret_val;
1279	}
1280
1281	/* Configure mdi-mdix settings */
1282	if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1283	&phy_data)))
1284	return ret_val;
1285
1286	if((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
1287	hw->dsp_config_state = e1000_dsp_config_disabled;
1288	/* Force MDI for IGP B-0 PHY */
1289	phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX \|
1290	IGP01E1000_PSCR_FORCE_MDI_MDIX);
1291	hw->mdix = 1;
1292
1293	} else {
1294	hw->dsp_config_state = e1000_dsp_config_enabled;
1295	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1296
1297	switch (hw->mdix) {
1298	case 1:
1299	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1300	break;
1301	case 2:
1302	phy_data \|= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1303	break;
1304	case 0:
1305	default:
1306	phy_data \|= IGP01E1000_PSCR_AUTO_MDIX;
1307	break;
1308	}
1309	}
1310	if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1311	phy_data)))
1312	return ret_val;
1313
1314	/* set auto-master slave resolution settings */
1315	e1000_ms_type phy_ms_setting = hw->master_slave;
1316
1317	if(hw->ffe_config_state == e1000_ffe_config_active)
1318	hw->ffe_config_state = e1000_ffe_config_enabled;
1319
1320	if(hw->dsp_config_state == e1000_dsp_config_activated)
1321	hw->dsp_config_state = e1000_dsp_config_enabled;
1322	#endif
1323
1324	/* when autonegotiation advertisment is only 1000Mbps then we
1325	* should disable SmartSpeed and enable Auto MasterSlave
1326	* resolution as hardware default. */
1327	if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1328	/* Disable SmartSpeed */
1329	if((ret_val = e1000_read_phy_reg(hw,
1330	IGP01E1000_PHY_PORT_CONFIG,
1331	&phy_data)))
1332	return ret_val;
1333	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1334	if((ret_val = e1000_write_phy_reg(hw,
1335	IGP01E1000_PHY_PORT_CONFIG,
1336	phy_data)))
1337	return ret_val;
1338	/* Set auto Master/Slave resolution process */
1339	if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1340	&phy_data)))
1341	return ret_val;
1342	phy_data &= ~CR_1000T_MS_ENABLE;
1343	if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1344	phy_data)))
1345	return ret_val;
1346	}
1347
1348	if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1349	&phy_data)))
1350	return ret_val;
1351
1352	#if 0
1353	/* load defaults for future use */
1354	hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1355	((phy_data & CR_1000T_MS_VALUE) ?
1356	e1000_ms_force_master :
1357	e1000_ms_force_slave) :
1358	e1000_ms_auto;
1359
1360	switch (phy_ms_setting) {
1361	case e1000_ms_force_master:
1362	phy_data \|= (CR_1000T_MS_ENABLE \| CR_1000T_MS_VALUE);
1363	break;
1364	case e1000_ms_force_slave:
1365	phy_data \|= CR_1000T_MS_ENABLE;
1366	phy_data &= ~(CR_1000T_MS_VALUE);
1367	break;
1368	case e1000_ms_auto:
1369	phy_data &= ~CR_1000T_MS_ENABLE;
1370	default:
1371	break;
1372	}
1373	#endif
1374
1375	if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1376	phy_data)))
1377	return ret_val;
1378	} else {
1379	/* Enable CRS on TX. This must be set for half-duplex operation. */
1380	if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1381	&phy_data)))
1382	return ret_val;
1383
1384	phy_data \|= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1385
1386	/* Options:
1387	* MDI/MDI-X = 0 (default)
1388	* 0 - Auto for all speeds
1389	* 1 - MDI mode
1390	* 2 - MDI-X mode
1391	* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1392	*/
1393	#if 0
1394	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1395
1396	switch (hw->mdix) {
1397	case 1:
1398	phy_data \|= M88E1000_PSCR_MDI_MANUAL_MODE;
1399	break;
1400	case 2:
1401	phy_data \|= M88E1000_PSCR_MDIX_MANUAL_MODE;
1402	break;
1403	case 3:
1404	phy_data \|= M88E1000_PSCR_AUTO_X_1000T;
1405	break;
1406	case 0:
1407	default:
1408	#endif
1409	phy_data \|= M88E1000_PSCR_AUTO_X_MODE;
1410	#if 0
1411	break;
1412	}
1413	#endif
1414
1415	/* Options:
1416	* disable_polarity_correction = 0 (default)
1417	* Automatic Correction for Reversed Cable Polarity
1418	* 0 - Disabled
1419	* 1 - Enabled
1420	*/
1421	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1422	if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1423	phy_data)))
1424	return ret_val;
1425
1426	/* Force TX_CLK in the Extended PHY Specific Control Register
1427	* to 25MHz clock.
1428	*/
1429	if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1430	&phy_data)))
1431	return ret_val;
1432
1433	phy_data \|= M88E1000_EPSCR_TX_CLK_25;
1434
1435	#ifdef LINUX_DRIVER
1436	if (hw->phy_revision < M88E1011_I_REV_4) {
1437	#endif
1438	/* Configure Master and Slave downshift values */
1439	phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK \|
1440	M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1441	phy_data \|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X \|
1442	M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1443	if((ret_val = e1000_write_phy_reg(hw,
1444	M88E1000_EXT_PHY_SPEC_CTRL,
1445	phy_data)))
1446	return ret_val;
1447	}
1448
1449	/* SW Reset the PHY so all changes take effect */
1450	if((ret_val = e1000_phy_reset(hw))) {
1451	DEBUGOUT("Error Resetting the PHY\n");
1452	return ret_val;
1453	#ifdef LINUX_DRIVER
1454	}
1455	#endif
1456	}
1457
1458	/* Options:
1459	* autoneg = 1 (default)
1460	* PHY will advertise value(s) parsed from
1461	* autoneg_advertised and fc
1462	* autoneg = 0
1463	* PHY will be set to 10H, 10F, 100H, or 100F
1464	* depending on value parsed from forced_speed_duplex.
1465	*/
1466
1467	/* Is autoneg enabled? This is enabled by default or by software
1468	* override. If so, call e1000_phy_setup_autoneg routine to parse the
1469	* autoneg_advertised and fc options. If autoneg is NOT enabled, then
1470	* the user should have provided a speed/duplex override. If so, then
1471	* call e1000_phy_force_speed_duplex to parse and set this up.
1472	*/
1473	/* Perform some bounds checking on the hw->autoneg_advertised
1474	* parameter. If this variable is zero, then set it to the default.
1475	*/
1476	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1477
1478	/* If autoneg_advertised is zero, we assume it was not defaulted
1479	* by the calling code so we set to advertise full capability.
1480	*/
1481	if(hw->autoneg_advertised == 0)
1482	hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1483
1484	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1485	if((ret_val = e1000_phy_setup_autoneg(hw))) {
1486	DEBUGOUT("Error Setting up Auto-Negotiation\n");
1487	return ret_val;
1488	}
1489	DEBUGOUT("Restarting Auto-Neg\n");
1490
1491	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
1492	* the Auto Neg Restart bit in the PHY control register.
1493	*/
1494	if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1495	return ret_val;
1496
1497	phy_data \|= (MII_CR_AUTO_NEG_EN \| MII_CR_RESTART_AUTO_NEG);
1498	if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1499	return ret_val;
1500
1501	#if 0
1502	/* Does the user want to wait for Auto-Neg to complete here, or
1503	* check at a later time (for example, callback routine).
1504	*/
1505	if(hw->wait_autoneg_complete) {
1506	if((ret_val = e1000_wait_autoneg(hw))) {
1507	DEBUGOUT("Error while waiting for autoneg to complete\n");
1508	return ret_val;
1509	}
1510	}
1511	#else
1512	/* If we do not wait for autonegotiation to complete I
1513	* do not see a valid link status.
1514	*/
1515	if((ret_val = e1000_wait_autoneg(hw))) {
1516	DEBUGOUT("Error while waiting for autoneg to complete\n");
1517	return ret_val;
1518	}
1519	#endif
1520	} /* !hw->phy_reset_disable */
1521
1522	/* Check link status. Wait up to 100 microseconds for link to become
1523	* valid.
1524	*/
1525	for(i = 0; i < 10; i++) {
1526	if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1527	return ret_val;
1528	if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1529	return ret_val;
1530
1531	if(phy_data & MII_SR_LINK_STATUS) {
1532	/* We have link, so we need to finish the config process:
1533	* 1) Set up the MAC to the current PHY speed/duplex
1534	* if we are on 82543. If we
1535	* are on newer silicon, we only need to configure
1536	* collision distance in the Transmit Control Register.
1537	* 2) Set up flow control on the MAC to that established with
1538	* the link partner.
1539	*/
1540	if(hw->mac_type >= e1000_82544) {
1541	e1000_config_collision_dist(hw);
1542	} else {
1543	if((ret_val = e1000_config_mac_to_phy(hw))) {
1544	DEBUGOUT("Error configuring MAC to PHY settings\n");
1545	return ret_val;
1546	}
1547	}
1548	if((ret_val = e1000_config_fc_after_link_up(hw))) {
1549	DEBUGOUT("Error Configuring Flow Control\n");
1550	return ret_val;
1551	}
1552	#if 0
1553	if(hw->phy_type == e1000_phy_igp) {
1554	if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1555	DEBUGOUT("Error Configuring DSP after link up\n");
1556	return ret_val;
1557	}
1558	}
1559	#endif
1560	DEBUGOUT("Valid link established!!!\n");
1561	return E1000_SUCCESS;
1562	}
1563	udelay(10);
1564	}
1565
1566	DEBUGOUT("Unable to establish link!!!\n");
1567	return -E1000_ERR_NOLINK;
1568	}
1569
1570	/******************************************************************************
1571	* Configures PHY autoneg and flow control advertisement settings
1572	*
1573	* hw - Struct containing variables accessed by shared code
1574	******************************************************************************/
1575	static int
1576	e1000_phy_setup_autoneg(struct e1000_hw *hw)
1577	{
1578	int32_t ret_val;
1579	uint16_t mii_autoneg_adv_reg;
1580	uint16_t mii_1000t_ctrl_reg;
1581
1582	DEBUGFUNC("e1000_phy_setup_autoneg");
1583
1584	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
1585	if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1586	&mii_autoneg_adv_reg)))
1587	return ret_val;
1588
1589	/* Read the MII 1000Base-T Control Register (Address 9). */
1590	if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1591	return ret_val;
1592
1593	/* Need to parse both autoneg_advertised and fc and set up
1594	* the appropriate PHY registers. First we will parse for
1595	* autoneg_advertised software override. Since we can advertise
1596	* a plethora of combinations, we need to check each bit
1597	* individually.
1598	*/
1599
1600	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
1601	* Advertisement Register (Address 4) and the 1000 mb speed bits in
1602	* the 1000Base-T Control Register (Address 9).
1603	*/
1604	mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1605	mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1606
1607	DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1608
1609	/* Do we want to advertise 10 Mb Half Duplex? */
1610	if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1611	DEBUGOUT("Advertise 10mb Half duplex\n");
1612	mii_autoneg_adv_reg \|= NWAY_AR_10T_HD_CAPS;
1613	}
1614
1615	/* Do we want to advertise 10 Mb Full Duplex? */
1616	if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1617	DEBUGOUT("Advertise 10mb Full duplex\n");
1618	mii_autoneg_adv_reg \|= NWAY_AR_10T_FD_CAPS;
1619	}
1620
1621	/* Do we want to advertise 100 Mb Half Duplex? */
1622	if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1623	DEBUGOUT("Advertise 100mb Half duplex\n");
1624	mii_autoneg_adv_reg \|= NWAY_AR_100TX_HD_CAPS;
1625	}
1626
1627	/* Do we want to advertise 100 Mb Full Duplex? */
1628	if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1629	DEBUGOUT("Advertise 100mb Full duplex\n");
1630	mii_autoneg_adv_reg \|= NWAY_AR_100TX_FD_CAPS;
1631	}
1632
1633	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1634	if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1635	DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1636	}
1637
1638	/* Do we want to advertise 1000 Mb Full Duplex? */
1639	if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1640	DEBUGOUT("Advertise 1000mb Full duplex\n");
1641	mii_1000t_ctrl_reg \|= CR_1000T_FD_CAPS;
1642	}
1643
1644	/* Check for a software override of the flow control settings, and
1645	* setup the PHY advertisement registers accordingly. If
1646	* auto-negotiation is enabled, then software will have to set the
1647	* "PAUSE" bits to the correct value in the Auto-Negotiation
1648	* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1649	*
1650	* The possible values of the "fc" parameter are:
1651	* 0: Flow control is completely disabled
1652	* 1: Rx flow control is enabled (we can receive pause frames
1653	* but not send pause frames).
1654	* 2: Tx flow control is enabled (we can send pause frames
1655	* but we do not support receiving pause frames).
1656	* 3: Both Rx and TX flow control (symmetric) are enabled.
1657	* other: No software override. The flow control configuration
1658	* in the EEPROM is used.
1659	*/
1660	switch (hw->fc) {
1661	case e1000_fc_none: /* 0 */
1662	/* Flow control (RX & TX) is completely disabled by a
1663	* software over-ride.
1664	*/
1665	mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
1666	break;
1667	case e1000_fc_rx_pause: /* 1 */
1668	/* RX Flow control is enabled, and TX Flow control is
1669	* disabled, by a software over-ride.
1670	*/
1671	/* Since there really isn't a way to advertise that we are
1672	* capable of RX Pause ONLY, we will advertise that we
1673	* support both symmetric and asymmetric RX PAUSE. Later
1674	* (in e1000_config_fc_after_link_up) we will disable the
1675	*hw's ability to send PAUSE frames.
1676	*/
1677	mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
1678	break;
1679	case e1000_fc_tx_pause: /* 2 */
1680	/* TX Flow control is enabled, and RX Flow control is
1681	* disabled, by a software over-ride.
1682	*/
1683	mii_autoneg_adv_reg \|= NWAY_AR_ASM_DIR;
1684	mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1685	break;
1686	case e1000_fc_full: /* 3 */
1687	/* Flow control (both RX and TX) is enabled by a software
1688	* over-ride.
1689	*/
1690	mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
1691	break;
1692	default:
1693	DEBUGOUT("Flow control param set incorrectly\n");
1694	return -E1000_ERR_CONFIG;
1695	}
1696
1697	if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
1698	mii_autoneg_adv_reg)))
1699	return ret_val;
1700
1701	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1702
1703	if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
1704	return ret_val;
1705
1706	return E1000_SUCCESS;
1707	}
1708
1709	/******************************************************************************
1710	* Sets the collision distance in the Transmit Control register
1711	*
1712	* hw - Struct containing variables accessed by shared code
1713	*
1714	* Link should have been established previously. Reads the speed and duplex
1715	* information from the Device Status register.
1716	******************************************************************************/
1717	static void
1718	e1000_config_collision_dist(struct e1000_hw *hw)
1719	{
1720	uint32_t tctl;
1721
1722	tctl = E1000_READ_REG(hw, TCTL);
1723
1724	tctl &= ~E1000_TCTL_COLD;
1725	tctl \|= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1726
1727	E1000_WRITE_REG(hw, TCTL, tctl);
1728	E1000_WRITE_FLUSH(hw);
1729	}
1730
1731	/******************************************************************************
1732	* Sets MAC speed and duplex settings to reflect the those in the PHY
1733	*
1734	* hw - Struct containing variables accessed by shared code
1735	* mii_reg - data to write to the MII control register
1736	*
1737	* The contents of the PHY register containing the needed information need to
1738	* be passed in.
1739	******************************************************************************/
1740	static int
1741	e1000_config_mac_to_phy(struct e1000_hw *hw)
1742	{
1743	uint32_t ctrl;
1744	int32_t ret_val;
1745	uint16_t phy_data;
1746
1747	DEBUGFUNC("e1000_config_mac_to_phy");
1748
1749	/* Read the Device Control Register and set the bits to Force Speed
1750	* and Duplex.
1751	*/
1752	ctrl = E1000_READ_REG(hw, CTRL);
1753	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
1754	ctrl &= ~(E1000_CTRL_SPD_SEL \| E1000_CTRL_ILOS);
1755
1756	/* Set up duplex in the Device Control and Transmit Control
1757	* registers depending on negotiated values.
1758	*/
1759	if (hw->phy_type == e1000_phy_igp) {
1760	if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1761	&phy_data)))
1762	return ret_val;
1763
1764	if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl \|= E1000_CTRL_FD;
1765	else ctrl &= ~E1000_CTRL_FD;
1766
1767	e1000_config_collision_dist(hw);
1768
1769	/* Set up speed in the Device Control register depending on
1770	* negotiated values.
1771	*/
1772	if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1773	IGP01E1000_PSSR_SPEED_1000MBPS)
1774	ctrl \|= E1000_CTRL_SPD_1000;
1775	else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1776	IGP01E1000_PSSR_SPEED_100MBPS)
1777	ctrl \|= E1000_CTRL_SPD_100;
1778	} else {
1779	if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1780	&phy_data)))
1781	return ret_val;
1782
1783	if(phy_data & M88E1000_PSSR_DPLX) ctrl \|= E1000_CTRL_FD;
1784	else ctrl &= ~E1000_CTRL_FD;
1785
1786	e1000_config_collision_dist(hw);
1787
1788	/* Set up speed in the Device Control register depending on
1789	* negotiated values.
1790	*/
1791	if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1792	ctrl \|= E1000_CTRL_SPD_1000;
1793	else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1794	ctrl \|= E1000_CTRL_SPD_100;
1795	}
1796	/* Write the configured values back to the Device Control Reg. */
1797	E1000_WRITE_REG(hw, CTRL, ctrl);
1798	return E1000_SUCCESS;
1799	}
1800
1801	/******************************************************************************
1802	* Forces the MAC's flow control settings.
1803	*
1804	* hw - Struct containing variables accessed by shared code
1805	*
1806	* Sets the TFCE and RFCE bits in the device control register to reflect
1807	* the adapter settings. TFCE and RFCE need to be explicitly set by
1808	* software when a Copper PHY is used because autonegotiation is managed
1809	* by the PHY rather than the MAC. Software must also configure these
1810	* bits when link is forced on a fiber connection.
1811	*****************************************************************************/
1812	static int
1813	e1000_force_mac_fc(struct e1000_hw *hw)
1814	{
1815	uint32_t ctrl;
1816
1817	DEBUGFUNC("e1000_force_mac_fc");
1818
1819	/* Get the current configuration of the Device Control Register */
1820	ctrl = E1000_READ_REG(hw, CTRL);
1821
1822	/* Because we didn't get link via the internal auto-negotiation
1823	* mechanism (we either forced link or we got link via PHY
1824	* auto-neg), we have to manually enable/disable transmit an
1825	* receive flow control.
1826	*
1827	* The "Case" statement below enables/disable flow control
1828	* according to the "hw->fc" parameter.
1829	*
1830	* The possible values of the "fc" parameter are:
1831	* 0: Flow control is completely disabled
1832	* 1: Rx flow control is enabled (we can receive pause
1833	* frames but not send pause frames).
1834	* 2: Tx flow control is enabled (we can send pause frames
1835	* frames but we do not receive pause frames).
1836	* 3: Both Rx and TX flow control (symmetric) is enabled.
1837	* other: No other values should be possible at this point.
1838	*/
1839
1840	switch (hw->fc) {
1841	case e1000_fc_none:
1842	ctrl &= (~(E1000_CTRL_TFCE \| E1000_CTRL_RFCE));
1843	break;
1844	case e1000_fc_rx_pause:
1845	ctrl &= (~E1000_CTRL_TFCE);
1846	ctrl \|= E1000_CTRL_RFCE;
1847	break;
1848	case e1000_fc_tx_pause:
1849	ctrl &= (~E1000_CTRL_RFCE);
1850	ctrl \|= E1000_CTRL_TFCE;
1851	break;
1852	case e1000_fc_full:
1853	ctrl \|= (E1000_CTRL_TFCE \| E1000_CTRL_RFCE);
1854	break;
1855	default:
1856	DEBUGOUT("Flow control param set incorrectly\n");
1857	return -E1000_ERR_CONFIG;
1858	}
1859
1860	/* Disable TX Flow Control for 82542 (rev 2.0) */
1861	if(hw->mac_type == e1000_82542_rev2_0)
1862	ctrl &= (~E1000_CTRL_TFCE);
1863
1864	E1000_WRITE_REG(hw, CTRL, ctrl);
1865	return E1000_SUCCESS;
1866	}
1867
1868	/******************************************************************************
1869	* Configures flow control settings after link is established
1870	*
1871	* hw - Struct containing variables accessed by shared code
1872	*
1873	* Should be called immediately after a valid link has been established.
1874	* Forces MAC flow control settings if link was forced. When in MII/GMII mode
1875	* and autonegotiation is enabled, the MAC flow control settings will be set
1876	* based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1877	* and RFCE bits will be automaticaly set to the negotiated flow control mode.
1878	*****************************************************************************/
1879	static int
1880	e1000_config_fc_after_link_up(struct e1000_hw *hw)
1881	{
1882	int32_t ret_val;
1883	uint16_t mii_status_reg;
1884	uint16_t mii_nway_adv_reg;
1885	uint16_t mii_nway_lp_ability_reg;
1886	uint16_t speed;
1887	uint16_t duplex;
1888
1889	DEBUGFUNC("e1000_config_fc_after_link_up");
1890
1891	/* Check for the case where we have fiber media and auto-neg failed
1892	* so we had to force link. In this case, we need to force the
1893	* configuration of the MAC to match the "fc" parameter.
1894	*/
1895	if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) \|\|
1896	((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) {
1897	if((ret_val = e1000_force_mac_fc(hw))) {
1898	DEBUGOUT("Error forcing flow control settings\n");
1899	return ret_val;
1900	}
1901	}
1902
1903	/* Check for the case where we have copper media and auto-neg is
1904	* enabled. In this case, we need to check and see if Auto-Neg
1905	* has completed, and if so, how the PHY and link partner has
1906	* flow control configured.
1907	*/
1908	if(hw->media_type == e1000_media_type_copper) {
1909	/* Read the MII Status Register and check to see if AutoNeg
1910	* has completed. We read this twice because this reg has
1911	* some "sticky" (latched) bits.
1912	*/
1913	if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1914	return ret_val;
1915	if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1916	return ret_val;
1917
1918	if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1919	/* The AutoNeg process has completed, so we now need to
1920	* read both the Auto Negotiation Advertisement Register
1921	* (Address 4) and the Auto_Negotiation Base Page Ability
1922	* Register (Address 5) to determine how flow control was
1923	* negotiated.
1924	*/
1925	if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1926	&mii_nway_adv_reg)))
1927	return ret_val;
1928	if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1929	&mii_nway_lp_ability_reg)))
1930	return ret_val;
1931
1932	/* Two bits in the Auto Negotiation Advertisement Register
1933	* (Address 4) and two bits in the Auto Negotiation Base
1934	* Page Ability Register (Address 5) determine flow control
1935	* for both the PHY and the link partner. The following
1936	* table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1937	* 1999, describes these PAUSE resolution bits and how flow
1938	* control is determined based upon these settings.
1939	* NOTE: DC = Don't Care
1940	*
1941	* LOCAL DEVICE \| LINK PARTNER
1942	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| NIC Resolution
1943	*-------\|---------\|-------\|---------\|--------------------
1944	* 0 \| 0 \| DC \| DC \| e1000_fc_none
1945	* 0 \| 1 \| 0 \| DC \| e1000_fc_none
1946	* 0 \| 1 \| 1 \| 0 \| e1000_fc_none
1947	* 0 \| 1 \| 1 \| 1 \| e1000_fc_tx_pause
1948	* 1 \| 0 \| 0 \| DC \| e1000_fc_none
1949	* 1 \| DC \| 1 \| DC \| e1000_fc_full
1950	* 1 \| 1 \| 0 \| 0 \| e1000_fc_none
1951	* 1 \| 1 \| 0 \| 1 \| e1000_fc_rx_pause
1952	*
1953	*/
1954	/* Are both PAUSE bits set to 1? If so, this implies
1955	* Symmetric Flow Control is enabled at both ends. The
1956	* ASM_DIR bits are irrelevant per the spec.
1957	*
1958	* For Symmetric Flow Control:
1959	*
1960	* LOCAL DEVICE \| LINK PARTNER
1961	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
1962	*-------\|---------\|-------\|---------\|--------------------
1963	* 1 \| DC \| 1 \| DC \| e1000_fc_full
1964	*
1965	*/
1966	if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1967	(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1968	/* Now we need to check if the user selected RX ONLY
1969	* of pause frames. In this case, we had to advertise
1970	* FULL flow control because we could not advertise RX
1971	* ONLY. Hence, we must now check to see if we need to
1972	* turn OFF the TRANSMISSION of PAUSE frames.
1973	*/
1974	#if 0
1975	if(hw->original_fc == e1000_fc_full) {
1976	hw->fc = e1000_fc_full;
1977	#else
1978	if(hw->fc == e1000_fc_full) {
1979	#endif
1980	DEBUGOUT("Flow Control = FULL.\r\n");
1981	} else {
1982	hw->fc = e1000_fc_rx_pause;
1983	DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1984	}
1985	}
1986	/* For receiving PAUSE frames ONLY.
1987	*
1988	* LOCAL DEVICE \| LINK PARTNER
1989	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
1990	*-------\|---------\|-------\|---------\|--------------------
1991	* 0 \| 1 \| 1 \| 1 \| e1000_fc_tx_pause
1992	*
1993	*/
1994	else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1995	(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1996	(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1997	(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1998	hw->fc = e1000_fc_tx_pause;
1999	DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2000	}
2001	/* For transmitting PAUSE frames ONLY.
2002	*
2003	* LOCAL DEVICE \| LINK PARTNER
2004	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
2005	*-------\|---------\|-------\|---------\|--------------------
2006	* 1 \| 1 \| 0 \| 1 \| e1000_fc_rx_pause
2007	*
2008	*/
2009	else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2010	(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2011	!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2012	(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2013	hw->fc = e1000_fc_rx_pause;
2014	DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2015	}
2016	/* Per the IEEE spec, at this point flow control should be
2017	* disabled. However, we want to consider that we could
2018	* be connected to a legacy switch that doesn't advertise
2019	* desired flow control, but can be forced on the link
2020	* partner. So if we advertised no flow control, that is
2021	* what we will resolve to. If we advertised some kind of
2022	* receive capability (Rx Pause Only or Full Flow Control)
2023	* and the link partner advertised none, we will configure
2024	* ourselves to enable Rx Flow Control only. We can do
2025	* this safely for two reasons: If the link partner really
2026	* didn't want flow control enabled, and we enable Rx, no
2027	* harm done since we won't be receiving any PAUSE frames
2028	* anyway. If the intent on the link partner was to have
2029	* flow control enabled, then by us enabling RX only, we
2030	* can at least receive pause frames and process them.
2031	* This is a good idea because in most cases, since we are
2032	* predominantly a server NIC, more times than not we will
2033	* be asked to delay transmission of packets than asking
2034	* our link partner to pause transmission of frames.
2035	*/
2036	#if 0
2037	else if(hw->original_fc == e1000_fc_none \|\|
2038	hw->original_fc == e1000_fc_tx_pause) {
2039	#else
2040	else if(hw->fc == e1000_fc_none)
2041	DEBUGOUT("Flow Control = NONE.\r\n");
2042	else if(hw->fc == e1000_fc_tx_pause) {
2043	#endif
2044	hw->fc = e1000_fc_none;
2045	DEBUGOUT("Flow Control = NONE.\r\n");
2046	} else {
2047	hw->fc = e1000_fc_rx_pause;
2048	DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2049	}
2050
2051	/* Now we need to do one last check... If we auto-
2052	* negotiated to HALF DUPLEX, flow control should not be
2053	* enabled per IEEE 802.3 spec.
2054	*/
2055	e1000_get_speed_and_duplex(hw, &speed, &duplex);
2056
2057	if(duplex == HALF_DUPLEX)
2058	hw->fc = e1000_fc_none;
2059
2060	/* Now we call a subroutine to actually force the MAC
2061	* controller to use the correct flow control settings.
2062	*/
2063	if((ret_val = e1000_force_mac_fc(hw))) {
2064	DEBUGOUT("Error forcing flow control settings\n");
2065	return ret_val;
2066	}
2067	} else {
2068	DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2069	}
2070	}
2071	return E1000_SUCCESS;
2072	}
2073
2074	/******************************************************************************
2075	* Checks to see if the link status of the hardware has changed.
2076	*
2077	* hw - Struct containing variables accessed by shared code
2078	*
2079	* Called by any function that needs to check the link status of the adapter.
2080	*****************************************************************************/
2081	static int
2082	e1000_check_for_link(struct e1000_hw *hw)
2083	{
2084	uint32_t rxcw;
2085	uint32_t ctrl;
2086	uint32_t status;
2087	uint32_t rctl;
2088	uint32_t signal = 0;
2089	int32_t ret_val;
2090	uint16_t phy_data;
2091	uint16_t lp_capability;
2092
2093	DEBUGFUNC("e1000_check_for_link");
2094
2095	/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2096	* set when the optics detect a signal. On older adapters, it will be
2097	* cleared when there is a signal. This applies to fiber media only.
2098	*/
2099	if(hw->media_type == e1000_media_type_fiber)
2100	signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2101
2102	ctrl = E1000_READ_REG(hw, CTRL);
2103	status = E1000_READ_REG(hw, STATUS);
2104	rxcw = E1000_READ_REG(hw, RXCW);
2105
2106	/* If we have a copper PHY then we only want to go out to the PHY
2107	* registers to see if Auto-Neg has completed and/or if our link
2108	* status has changed. The get_link_status flag will be set if we
2109	* receive a Link Status Change interrupt or we have Rx Sequence
2110	* Errors.
2111	*/
2112	#if 0
2113	if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2114	#else
2115	if(hw->media_type == e1000_media_type_copper) {
2116	#endif
2117	/* First we want to see if the MII Status Register reports
2118	* link. If so, then we want to get the current speed/duplex
2119	* of the PHY.
2120	* Read the register twice since the link bit is sticky.
2121	*/
2122	if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2123	return ret_val;
2124	if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2125	return ret_val;
2126
2127	if(phy_data & MII_SR_LINK_STATUS) {
2128	#if 0
2129	hw->get_link_status = FALSE;
2130	#endif
2131	} else {
2132	/* No link detected */
2133	return -E1000_ERR_NOLINK;
2134	}
2135
2136	/* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2137	* have Si on board that is 82544 or newer, Auto
2138	* Speed Detection takes care of MAC speed/duplex
2139	* configuration. So we only need to configure Collision
2140	* Distance in the MAC. Otherwise, we need to force
2141	* speed/duplex on the MAC to the current PHY speed/duplex
2142	* settings.
2143	*/
2144	if(hw->mac_type >= e1000_82544)
2145	e1000_config_collision_dist(hw);
2146	else {
2147	if((ret_val = e1000_config_mac_to_phy(hw))) {
2148	DEBUGOUT("Error configuring MAC to PHY settings\n");
2149	return ret_val;
2150	}
2151	}
2152
2153	/* Configure Flow Control now that Auto-Neg has completed. First, we
2154	* need to restore the desired flow control settings because we may
2155	* have had to re-autoneg with a different link partner.
2156	*/
2157	if((ret_val = e1000_config_fc_after_link_up(hw))) {
2158	DEBUGOUT("Error configuring flow control\n");
2159	return ret_val;
2160	}
2161
2162	/* At this point we know that we are on copper and we have
2163	* auto-negotiated link. These are conditions for checking the link
2164	* parter capability register. We use the link partner capability to
2165	* determine if TBI Compatibility needs to be turned on or off. If
2166	* the link partner advertises any speed in addition to Gigabit, then
2167	* we assume that they are GMII-based, and TBI compatibility is not
2168	* needed. If no other speeds are advertised, we assume the link
2169	* partner is TBI-based, and we turn on TBI Compatibility.
2170	*/
2171	if(hw->tbi_compatibility_en) {
2172	if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2173	&lp_capability)))
2174	return ret_val;
2175	if(lp_capability & (NWAY_LPAR_10T_HD_CAPS \|
2176	NWAY_LPAR_10T_FD_CAPS \|
2177	NWAY_LPAR_100TX_HD_CAPS \|
2178	NWAY_LPAR_100TX_FD_CAPS \|
2179	NWAY_LPAR_100T4_CAPS)) {
2180	/* If our link partner advertises anything in addition to
2181	* gigabit, we do not need to enable TBI compatibility.
2182	*/
2183	if(hw->tbi_compatibility_on) {
2184	/* If we previously were in the mode, turn it off. */
2185	rctl = E1000_READ_REG(hw, RCTL);
2186	rctl &= ~E1000_RCTL_SBP;
2187	E1000_WRITE_REG(hw, RCTL, rctl);
2188	hw->tbi_compatibility_on = FALSE;
2189	}
2190	} else {
2191	/* If TBI compatibility is was previously off, turn it on. For
2192	* compatibility with a TBI link partner, we will store bad
2193	* packets. Some frames have an additional byte on the end and
2194	* will look like CRC errors to to the hardware.
2195	*/
2196	if(!hw->tbi_compatibility_on) {
2197	hw->tbi_compatibility_on = TRUE;
2198	rctl = E1000_READ_REG(hw, RCTL);
2199	rctl \|= E1000_RCTL_SBP;
2200	E1000_WRITE_REG(hw, RCTL, rctl);
2201	}
2202	}
2203	}
2204	}
2205	/* If we don't have link (auto-negotiation failed or link partner cannot
2206	* auto-negotiate), the cable is plugged in (we have signal), and our
2207	* link partner is not trying to auto-negotiate with us (we are receiving
2208	* idles or data), we need to force link up. We also need to give
2209	* auto-negotiation time to complete, in case the cable was just plugged
2210	* in. The autoneg_failed flag does this.
2211	*/
2212	else if((((hw->media_type == e1000_media_type_fiber) &&
2213	((ctrl & E1000_CTRL_SWDPIN1) == signal)) \|\|
2214	(hw->media_type == e1000_media_type_internal_serdes)) &&
2215	(!(status & E1000_STATUS_LU)) &&
2216	(!(rxcw & E1000_RXCW_C))) {
2217	if(hw->autoneg_failed == 0) {
2218	hw->autoneg_failed = 1;
2219	return 0;
2220	}
2221	DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2222
2223	/* Disable auto-negotiation in the TXCW register */
2224	E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2225
2226	/* Force link-up and also force full-duplex. */
2227	ctrl = E1000_READ_REG(hw, CTRL);
2228	ctrl \|= (E1000_CTRL_SLU \| E1000_CTRL_FD);
2229	E1000_WRITE_REG(hw, CTRL, ctrl);
2230
2231	/* Configure Flow Control after forcing link up. */
2232	if((ret_val = e1000_config_fc_after_link_up(hw))) {
2233	DEBUGOUT("Error configuring flow control\n");
2234	return ret_val;
2235	}
2236	}
2237	/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2238	* auto-negotiation in the TXCW register and disable forced link in the
2239	* Device Control register in an attempt to auto-negotiate with our link
2240	* partner.
2241	*/
2242	else if(((hw->media_type == e1000_media_type_fiber) \|\|
2243	(hw->media_type == e1000_media_type_internal_serdes)) &&
2244	(ctrl & E1000_CTRL_SLU) &&
2245	(rxcw & E1000_RXCW_C)) {
2246	DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2247	E1000_WRITE_REG(hw, TXCW, hw->txcw);
2248	E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2249	}
2250	#if 0
2251	/* If we force link for non-auto-negotiation switch, check link status
2252	* based on MAC synchronization for internal serdes media type.
2253	*/
2254	else if((hw->media_type == e1000_media_type_internal_serdes) &&
2255	!(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2256	/* SYNCH bit and IV bit are sticky. */
2257	udelay(10);
2258	if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2259	if(!(rxcw & E1000_RXCW_IV)) {
2260	hw->serdes_link_down = FALSE;
2261	DEBUGOUT("SERDES: Link is up.\n");
2262	}
2263	} else {
2264	hw->serdes_link_down = TRUE;
2265	DEBUGOUT("SERDES: Link is down.\n");
2266	}
2267	}
2268	#endif
2269	return E1000_SUCCESS;
2270	}
2271
2272	/******************************************************************************
2273	* Detects the current speed and duplex settings of the hardware.
2274	*
2275	* hw - Struct containing variables accessed by shared code
2276	* speed - Speed of the connection
2277	* duplex - Duplex setting of the connection
2278	*****************************************************************************/
2279	static void
2280	e1000_get_speed_and_duplex(struct e1000_hw *hw,
2281	uint16_t *speed,
2282	uint16_t *duplex)
2283	{
2284	uint32_t status;
2285
2286	DEBUGFUNC("e1000_get_speed_and_duplex");
2287
2288	if(hw->mac_type >= e1000_82543) {
2289	status = E1000_READ_REG(hw, STATUS);
2290	if(status & E1000_STATUS_SPEED_1000) {
2291	*speed = SPEED_1000;
2292	DEBUGOUT("1000 Mbs, ");
2293	} else if(status & E1000_STATUS_SPEED_100) {
2294	*speed = SPEED_100;
2295	DEBUGOUT("100 Mbs, ");
2296	} else {
2297	*speed = SPEED_10;
2298	DEBUGOUT("10 Mbs, ");
2299	}
2300
2301	if(status & E1000_STATUS_FD) {
2302	*duplex = FULL_DUPLEX;
2303	DEBUGOUT("Full Duplex\r\n");
2304	} else {
2305	*duplex = HALF_DUPLEX;
2306	DEBUGOUT(" Half Duplex\r\n");
2307	}
2308	} else {
2309	DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2310	*speed = SPEED_1000;
2311	*duplex = FULL_DUPLEX;
2312	}
2313	}
2314
2315	/******************************************************************************
2316	* Blocks until autoneg completes or times out (~4.5 seconds)
2317	*
2318	* hw - Struct containing variables accessed by shared code
2319	******************************************************************************/
2320	static int
2321	e1000_wait_autoneg(struct e1000_hw *hw)
2322	{
2323	int32_t ret_val;
2324	uint16_t i;
2325	uint16_t phy_data;
2326
2327	DEBUGFUNC("e1000_wait_autoneg");
2328	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2329
2330	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
2331	for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2332	/* Read the MII Status Register and wait for Auto-Neg
2333	* Complete bit to be set.
2334	*/
2335	if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2336	return ret_val;
2337	if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2338	return ret_val;
2339	if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2340	DEBUGOUT("Auto-Neg complete.\n");
2341	return E1000_SUCCESS;
2342	}
2343	mdelay(100);
2344	}
2345	DEBUGOUT("Auto-Neg timedout.\n");
2346	return -E1000_ERR_TIMEOUT;
2347	}
2348
2349	/******************************************************************************
2350	* Raises the Management Data Clock
2351	*
2352	* hw - Struct containing variables accessed by shared code
2353	* ctrl - Device control register's current value
2354	******************************************************************************/
2355	static void
2356	e1000_raise_mdi_clk(struct e1000_hw *hw,
2357	uint32_t *ctrl)
2358	{
2359	/* Raise the clock input to the Management Data Clock (by setting the MDC
2360	* bit), and then delay 10 microseconds.
2361	*/
2362	E1000_WRITE_REG(hw, CTRL, (*ctrl \| E1000_CTRL_MDC));
2363	E1000_WRITE_FLUSH(hw);
2364	udelay(10);
2365	}
2366
2367	/******************************************************************************
2368	* Lowers the Management Data Clock
2369	*
2370	* hw - Struct containing variables accessed by shared code
2371	* ctrl - Device control register's current value
2372	******************************************************************************/
2373	static void
2374	e1000_lower_mdi_clk(struct e1000_hw *hw,
2375	uint32_t *ctrl)
2376	{
2377	/* Lower the clock input to the Management Data Clock (by clearing the MDC
2378	* bit), and then delay 10 microseconds.
2379	*/
2380	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2381	E1000_WRITE_FLUSH(hw);
2382	udelay(10);
2383	}
2384
2385	/******************************************************************************
2386	* Shifts data bits out to the PHY
2387	*
2388	* hw - Struct containing variables accessed by shared code
2389	* data - Data to send out to the PHY
2390	* count - Number of bits to shift out
2391	*
2392	* Bits are shifted out in MSB to LSB order.
2393	******************************************************************************/
2394	static void
2395	e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2396	uint32_t data,
2397	uint16_t count)
2398	{
2399	uint32_t ctrl;
2400	uint32_t mask;
2401
2402	/* We need to shift "count" number of bits out to the PHY. So, the value
2403	* in the "data" parameter will be shifted out to the PHY one bit at a
2404	* time. In order to do this, "data" must be broken down into bits.
2405	*/
2406	mask = 0x01;
2407	mask <<= (count - 1);
2408
2409	ctrl = E1000_READ_REG(hw, CTRL);
2410
2411	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2412	ctrl \|= (E1000_CTRL_MDIO_DIR \| E1000_CTRL_MDC_DIR);
2413
2414	while(mask) {
2415	/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2416	* then raising and lowering the Management Data Clock. A "0" is
2417	* shifted out to the PHY by setting the MDIO bit to "0" and then
2418	* raising and lowering the clock.
2419	*/
2420	if(data & mask) ctrl \|= E1000_CTRL_MDIO;
2421	else ctrl &= ~E1000_CTRL_MDIO;
2422
2423	E1000_WRITE_REG(hw, CTRL, ctrl);
2424	E1000_WRITE_FLUSH(hw);
2425
2426	udelay(10);
2427
2428	e1000_raise_mdi_clk(hw, &ctrl);
2429	e1000_lower_mdi_clk(hw, &ctrl);
2430
2431	mask = mask >> 1;
2432	}
2433	}
2434
2435	/******************************************************************************
2436	* Shifts data bits in from the PHY
2437	*
2438	* hw - Struct containing variables accessed by shared code
2439	*
2440	* Bits are shifted in in MSB to LSB order.
2441	******************************************************************************/
2442	static uint16_t
2443	e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2444	{
2445	uint32_t ctrl;
2446	uint16_t data = 0;
2447	uint8_t i;
2448
2449	/* In order to read a register from the PHY, we need to shift in a total
2450	* of 18 bits from the PHY. The first two bit (turnaround) times are used
2451	* to avoid contention on the MDIO pin when a read operation is performed.
2452	* These two bits are ignored by us and thrown away. Bits are "shifted in"
2453	* by raising the input to the Management Data Clock (setting the MDC bit),
2454	* and then reading the value of the MDIO bit.
2455	*/
2456	ctrl = E1000_READ_REG(hw, CTRL);
2457
2458	/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2459	ctrl &= ~E1000_CTRL_MDIO_DIR;
2460	ctrl &= ~E1000_CTRL_MDIO;
2461
2462	E1000_WRITE_REG(hw, CTRL, ctrl);
2463	E1000_WRITE_FLUSH(hw);
2464
2465	/* Raise and Lower the clock before reading in the data. This accounts for
2466	* the turnaround bits. The first clock occurred when we clocked out the
2467	* last bit of the Register Address.
2468	*/
2469	e1000_raise_mdi_clk(hw, &ctrl);
2470	e1000_lower_mdi_clk(hw, &ctrl);
2471
2472	for(data = 0, i = 0; i < 16; i++) {
2473	data = data << 1;
2474	e1000_raise_mdi_clk(hw, &ctrl);
2475	ctrl = E1000_READ_REG(hw, CTRL);
2476	/* Check to see if we shifted in a "1". */
2477	if(ctrl & E1000_CTRL_MDIO) data \|= 1;
2478	e1000_lower_mdi_clk(hw, &ctrl);
2479	}
2480
2481	e1000_raise_mdi_clk(hw, &ctrl);
2482	e1000_lower_mdi_clk(hw, &ctrl);
2483
2484	return data;
2485	}
2486
2487	/*****************************************************************************
2488	* Reads the value from a PHY register, if the value is on a specific non zero
2489	* page, sets the page first.
2490	*
2491	* hw - Struct containing variables accessed by shared code
2492	* reg_addr - address of the PHY register to read
2493	******************************************************************************/
2494	static int
2495	e1000_read_phy_reg(struct e1000_hw *hw,
2496	uint32_t reg_addr,
2497	uint16_t *phy_data)
2498	{
2499	uint32_t ret_val;
2500
2501	DEBUGFUNC("e1000_read_phy_reg");
2502
2503	if(hw->phy_type == e1000_phy_igp &&
2504	(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2505	if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2506	(uint16_t)reg_addr)))
2507	return ret_val;
2508	}
2509
2510	ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2511	phy_data);
2512
2513	return ret_val;
2514	}
2515
2516	static int
2517	e1000_read_phy_reg_ex(struct e1000_hw *hw,
2518	uint32_t reg_addr,
2519	uint16_t *phy_data)
2520	{
2521	uint32_t i;
2522	uint32_t mdic = 0;
2523	const uint32_t phy_addr = 1;
2524
2525	DEBUGFUNC("e1000_read_phy_reg_ex");
2526
2527	if(reg_addr > MAX_PHY_REG_ADDRESS) {
2528	DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2529	return -E1000_ERR_PARAM;
2530	}
2531
2532	if(hw->mac_type > e1000_82543) {
2533	/* Set up Op-code, Phy Address, and register address in the MDI
2534	* Control register. The MAC will take care of interfacing with the
2535	* PHY to retrieve the desired data.
2536	*/
2537	mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) \|
2538	(phy_addr << E1000_MDIC_PHY_SHIFT) \|
2539	(E1000_MDIC_OP_READ));
2540
2541	E1000_WRITE_REG(hw, MDIC, mdic);
2542
2543	/* Poll the ready bit to see if the MDI read completed */
2544	for(i = 0; i < 64; i++) {
2545	udelay(50);
2546	mdic = E1000_READ_REG(hw, MDIC);
2547	if(mdic & E1000_MDIC_READY) break;
2548	}
2549	if(!(mdic & E1000_MDIC_READY)) {
2550	DEBUGOUT("MDI Read did not complete\n");
2551	return -E1000_ERR_PHY;
2552	}
2553	if(mdic & E1000_MDIC_ERROR) {
2554	DEBUGOUT("MDI Error\n");
2555	return -E1000_ERR_PHY;
2556	}
2557	*phy_data = (uint16_t) mdic;
2558	} else {
2559	/* We must first send a preamble through the MDIO pin to signal the
2560	* beginning of an MII instruction. This is done by sending 32
2561	* consecutive "1" bits.
2562	*/
2563	e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2564
2565	/* Now combine the next few fields that are required for a read
2566	* operation. We use this method instead of calling the
2567	* e1000_shift_out_mdi_bits routine five different times. The format of
2568	* a MII read instruction consists of a shift out of 14 bits and is
2569	* defined as follows:
2570	* <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2571	* followed by a shift in of 18 bits. This first two bits shifted in
2572	* are TurnAround bits used to avoid contention on the MDIO pin when a
2573	* READ operation is performed. These two bits are thrown away
2574	* followed by a shift in of 16 bits which contains the desired data.
2575	*/
2576	mdic = ((reg_addr) \| (phy_addr << 5) \|
2577	(PHY_OP_READ << 10) \| (PHY_SOF << 12));
2578
2579	e1000_shift_out_mdi_bits(hw, mdic, 14);
2580
2581	/* Now that we've shifted out the read command to the MII, we need to
2582	* "shift in" the 16-bit value (18 total bits) of the requested PHY
2583	* register address.
2584	*/
2585	*phy_data = e1000_shift_in_mdi_bits(hw);
2586	}
2587	return E1000_SUCCESS;
2588	}
2589
2590	/******************************************************************************
2591	* Writes a value to a PHY register
2592	*
2593	* hw - Struct containing variables accessed by shared code
2594	* reg_addr - address of the PHY register to write
2595	* data - data to write to the PHY
2596	******************************************************************************/
2597	static int
2598	e1000_write_phy_reg(struct e1000_hw *hw,
2599	uint32_t reg_addr,
2600	uint16_t phy_data)
2601	{
2602	uint32_t ret_val;
2603
2604	DEBUGFUNC("e1000_write_phy_reg");
2605
2606	if(hw->phy_type == e1000_phy_igp &&
2607	(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2608	if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2609	(uint16_t)reg_addr)))
2610	return ret_val;
2611	}
2612
2613	ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2614	phy_data);
2615
2616	return ret_val;
2617	}
2618
2619	static int
2620	e1000_write_phy_reg_ex(struct e1000_hw *hw,
2621	uint32_t reg_addr,
2622	uint16_t phy_data)
2623	{
2624	uint32_t i;
2625	uint32_t mdic = 0;
2626	const uint32_t phy_addr = 1;
2627
2628	DEBUGFUNC("e1000_write_phy_reg_ex");
2629
2630	if(reg_addr > MAX_PHY_REG_ADDRESS) {
2631	DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2632	return -E1000_ERR_PARAM;
2633	}
2634
2635	if(hw->mac_type > e1000_82543) {
2636	/* Set up Op-code, Phy Address, register address, and data intended
2637	* for the PHY register in the MDI Control register. The MAC will take
2638	* care of interfacing with the PHY to send the desired data.
2639	*/
2640	mdic = (((uint32_t) phy_data) \|
2641	(reg_addr << E1000_MDIC_REG_SHIFT) \|
2642	(phy_addr << E1000_MDIC_PHY_SHIFT) \|
2643	(E1000_MDIC_OP_WRITE));
2644
2645	E1000_WRITE_REG(hw, MDIC, mdic);
2646
2647	/* Poll the ready bit to see if the MDI read completed */
2648	for(i = 0; i < 640; i++) {
2649	udelay(5);
2650	mdic = E1000_READ_REG(hw, MDIC);
2651	if(mdic & E1000_MDIC_READY) break;
2652	}
2653	if(!(mdic & E1000_MDIC_READY)) {
2654	DEBUGOUT("MDI Write did not complete\n");
2655	return -E1000_ERR_PHY;
2656	}
2657	} else {
2658	/* We'll need to use the SW defined pins to shift the write command
2659	* out to the PHY. We first send a preamble to the PHY to signal the
2660	* beginning of the MII instruction. This is done by sending 32
2661	* consecutive "1" bits.
2662	*/
2663	e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2664
2665	/* Now combine the remaining required fields that will indicate a
2666	* write operation. We use this method instead of calling the
2667	* e1000_shift_out_mdi_bits routine for each field in the command. The
2668	* format of a MII write instruction is as follows:
2669	* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2670	*/
2671	mdic = ((PHY_TURNAROUND) \| (reg_addr << 2) \| (phy_addr << 7) \|
2672	(PHY_OP_WRITE << 12) \| (PHY_SOF << 14));
2673	mdic <<= 16;
2674	mdic \|= (uint32_t) phy_data;
2675
2676	e1000_shift_out_mdi_bits(hw, mdic, 32);
2677	}
2678
2679	return E1000_SUCCESS;
2680	}
2681
2682	/******************************************************************************
2683	* Returns the PHY to the power-on reset state
2684	*
2685	* hw - Struct containing variables accessed by shared code
2686	******************************************************************************/
2687	static void
2688	e1000_phy_hw_reset(struct e1000_hw *hw)
2689	{
2690	uint32_t ctrl, ctrl_ext;
2691
2692	DEBUGFUNC("e1000_phy_hw_reset");
2693
2694	DEBUGOUT("Resetting Phy...\n");
2695
2696	if(hw->mac_type > e1000_82543) {
2697	/* Read the device control register and assert the E1000_CTRL_PHY_RST
2698	* bit. Then, take it out of reset.
2699	*/
2700	ctrl = E1000_READ_REG(hw, CTRL);
2701	E1000_WRITE_REG(hw, CTRL, ctrl \| E1000_CTRL_PHY_RST);
2702	E1000_WRITE_FLUSH(hw);
2703	mdelay(10);
2704	E1000_WRITE_REG(hw, CTRL, ctrl);
2705	E1000_WRITE_FLUSH(hw);
2706	} else {
2707	/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2708	* bit to put the PHY into reset. Then, take it out of reset.
2709	*/
2710	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2711	ctrl_ext \|= E1000_CTRL_EXT_SDP4_DIR;
2712	ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2713	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2714	E1000_WRITE_FLUSH(hw);
2715	mdelay(10);
2716	ctrl_ext \|= E1000_CTRL_EXT_SDP4_DATA;
2717	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2718	E1000_WRITE_FLUSH(hw);
2719	}
2720	udelay(150);
2721	}
2722
2723	/******************************************************************************
2724	* Resets the PHY
2725	*
2726	* hw - Struct containing variables accessed by shared code
2727	*
2728	* Sets bit 15 of the MII Control regiser
2729	******************************************************************************/
2730	static int
2731	e1000_phy_reset(struct e1000_hw *hw)
2732	{
2733	int32_t ret_val;
2734	uint16_t phy_data;
2735
2736	DEBUGFUNC("e1000_phy_reset");
2737
2738	if(hw->mac_type != e1000_82541_rev_2) {
2739	if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
2740	return ret_val;
2741
2742	phy_data \|= MII_CR_RESET;
2743	if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
2744	return ret_val;
2745
2746	udelay(1);
2747	} else e1000_phy_hw_reset(hw);
2748
2749	if(hw->phy_type == e1000_phy_igp)
2750	e1000_phy_init_script(hw);
2751
2752	return E1000_SUCCESS;
2753	}
2754
2755	/******************************************************************************
2756	* Probes the expected PHY address for known PHY IDs
2757	*
2758	* hw - Struct containing variables accessed by shared code
2759	******************************************************************************/
2760	static int
2761	e1000_detect_gig_phy(struct e1000_hw *hw)
2762	{
2763	int32_t phy_init_status, ret_val;
2764	uint16_t phy_id_high, phy_id_low;
2765	boolean_t match = FALSE;
2766
2767	DEBUGFUNC("e1000_detect_gig_phy");
2768
2769	/* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
2770	* around that forces PHY page 0 to be set or the reads fail. The rest of
2771	* the code in this routine uses e1000_read_phy_reg to read the PHY ID.
2772	* So for ESB-2 we need to have this set so our reads won't fail. If the
2773	* attached PHY is not a e1000_phy_gg82563, the routines below will figure
2774	* this out as well. */
2775	if (hw->mac_type == e1000_80003es2lan)
2776	hw->phy_type = e1000_phy_gg82563;
2777
2778	/* Read the PHY ID Registers to identify which PHY is onboard. */
2779	if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
2780	return ret_val;
2781
2782	hw->phy_id = (uint32_t) (phy_id_high << 16);
2783	udelay(20);
2784	if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
2785	return ret_val;
2786
2787	hw->phy_id \|= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2788	#ifdef LINUX_DRIVER
2789	hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2790	#endif
2791
2792	switch(hw->mac_type) {
2793	case e1000_82543:
2794	if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2795	break;
2796	case e1000_82544:
2797	if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2798	break;
2799	case e1000_82540:
2800	case e1000_82545:
2801	case e1000_82545_rev_3:
2802	case e1000_82546:
2803	case e1000_82546_rev_3:
2804	if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2805	break;
2806	case e1000_82541:
2807	case e1000_82541_rev_2:
2808	case e1000_82547:
2809	case e1000_82547_rev_2:
2810	if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2811	break;
2812	case e1000_80003es2lan:
2813	if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
2814	break;
2815	default:
2816	DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2817	return -E1000_ERR_CONFIG;
2818	}
2819	phy_init_status = e1000_set_phy_type(hw);
2820
2821	if ((match) && (phy_init_status == E1000_SUCCESS)) {
2822	DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2823	return E1000_SUCCESS;
2824	}
2825	DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2826	return -E1000_ERR_PHY;
2827	}
2828
2829	/******************************************************************************
2830	* Sets up eeprom variables in the hw struct. Must be called after mac_type
2831	* is configured.
2832	*
2833	* hw - Struct containing variables accessed by shared code
2834	*****************************************************************************/
2835	static void
2836	e1000_init_eeprom_params(struct e1000_hw *hw)
2837	{
2838	struct e1000_eeprom_info *eeprom = &hw->eeprom;
2839	uint32_t eecd = E1000_READ_REG(hw, EECD);
2840	uint16_t eeprom_size;
2841
2842	DEBUGFUNC("e1000_init_eeprom_params");
2843
2844	switch (hw->mac_type) {
2845	case e1000_82542_rev2_0:
2846	case e1000_82542_rev2_1:
2847	case e1000_82543:
2848	case e1000_82544:
2849	eeprom->type = e1000_eeprom_microwire;
2850	eeprom->word_size = 64;
2851	eeprom->opcode_bits = 3;
2852	eeprom->address_bits = 6;
2853	eeprom->delay_usec = 50;
2854	break;
2855	case e1000_82540:
2856	case e1000_82545:
2857	case e1000_82545_rev_3:
2858	case e1000_82546:
2859	case e1000_82546_rev_3:
2860	eeprom->type = e1000_eeprom_microwire;
2861	eeprom->opcode_bits = 3;
2862	eeprom->delay_usec = 50;
2863	if(eecd & E1000_EECD_SIZE) {
2864	eeprom->word_size = 256;
2865	eeprom->address_bits = 8;
2866	} else {
2867	eeprom->word_size = 64;
2868	eeprom->address_bits = 6;
2869	}
2870	break;
2871	case e1000_82541:
2872	case e1000_82541_rev_2:
2873	case e1000_82547:
2874	case e1000_82547_rev_2:
2875	if (eecd & E1000_EECD_TYPE) {
2876	eeprom->type = e1000_eeprom_spi;
2877	if (eecd & E1000_EECD_ADDR_BITS) {
2878	eeprom->page_size = 32;
2879	eeprom->address_bits = 16;
2880	} else {
2881	eeprom->page_size = 8;
2882	eeprom->address_bits = 8;
2883	}
2884	} else {
2885	eeprom->type = e1000_eeprom_microwire;
2886	eeprom->opcode_bits = 3;
2887	eeprom->delay_usec = 50;
2888	if (eecd & E1000_EECD_ADDR_BITS) {
2889	eeprom->word_size = 256;
2890	eeprom->address_bits = 8;
2891	} else {
2892	eeprom->word_size = 64;
2893	eeprom->address_bits = 6;
2894	}
2895	}
2896	break;
2897	default:
2898	eeprom->type = e1000_eeprom_spi;
2899	if (eecd & E1000_EECD_ADDR_BITS) {
2900	eeprom->page_size = 32;
2901	eeprom->address_bits = 16;
2902	} else {
2903	eeprom->page_size = 8;
2904	eeprom->address_bits = 8;
2905	}
2906	break;
2907	}
2908
2909	if (eeprom->type == e1000_eeprom_spi) {
2910	eeprom->opcode_bits = 8;
2911	eeprom->delay_usec = 1;
2912	eeprom->word_size = 64;
2913	if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
2914	eeprom_size &= EEPROM_SIZE_MASK;
2915
2916	switch (eeprom_size) {
2917	case EEPROM_SIZE_16KB:
2918	eeprom->word_size = 8192;
2919	break;
2920	case EEPROM_SIZE_8KB:
2921	eeprom->word_size = 4096;
2922	break;
2923	case EEPROM_SIZE_4KB:
2924	eeprom->word_size = 2048;
2925	break;
2926	case EEPROM_SIZE_2KB:
2927	eeprom->word_size = 1024;
2928	break;
2929	case EEPROM_SIZE_1KB:
2930	eeprom->word_size = 512;
2931	break;
2932	case EEPROM_SIZE_512B:
2933	eeprom->word_size = 256;
2934	break;
2935	case EEPROM_SIZE_128B:
2936	default:
2937	break;
2938	}
2939	}
2940	}
2941	}
2942
2943	/******************************************************************************
2944	* Raises the EEPROM's clock input.
2945	*
2946	* hw - Struct containing variables accessed by shared code
2947	* eecd - EECD's current value
2948	*****************************************************************************/
2949	static void
2950	e1000_raise_ee_clk(struct e1000_hw *hw,
2951	uint32_t *eecd)
2952	{
2953	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
2954	* wait <delay> microseconds.
2955	*/
2956	eecd = eecd \| E1000_EECD_SK;
2957	E1000_WRITE_REG(hw, EECD, *eecd);
2958	E1000_WRITE_FLUSH(hw);
2959	udelay(hw->eeprom.delay_usec);
2960	}
2961
2962	/******************************************************************************
2963	* Lowers the EEPROM's clock input.
2964	*
2965	* hw - Struct containing variables accessed by shared code
2966	* eecd - EECD's current value
2967	*****************************************************************************/
2968	static void
2969	e1000_lower_ee_clk(struct e1000_hw *hw,
2970	uint32_t *eecd)
2971	{
2972	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
2973	* wait 50 microseconds.
2974	*/
2975	eecd = eecd & ~E1000_EECD_SK;
2976	E1000_WRITE_REG(hw, EECD, *eecd);
2977	E1000_WRITE_FLUSH(hw);
2978	udelay(hw->eeprom.delay_usec);
2979	}
2980
2981	/******************************************************************************
2982	* Shift data bits out to the EEPROM.
2983	*
2984	* hw - Struct containing variables accessed by shared code
2985	* data - data to send to the EEPROM
2986	* count - number of bits to shift out
2987	*****************************************************************************/
2988	static void
2989	e1000_shift_out_ee_bits(struct e1000_hw *hw,
2990	uint16_t data,
2991	uint16_t count)
2992	{
2993	struct e1000_eeprom_info *eeprom = &hw->eeprom;
2994	uint32_t eecd;
2995	uint32_t mask;
2996
2997	/* We need to shift "count" bits out to the EEPROM. So, value in the
2998	* "data" parameter will be shifted out to the EEPROM one bit at a time.
2999	* In order to do this, "data" must be broken down into bits.
3000	*/
3001	mask = 0x01 << (count - 1);
3002	eecd = E1000_READ_REG(hw, EECD);
3003	if (eeprom->type == e1000_eeprom_microwire) {
3004	eecd &= ~E1000_EECD_DO;
3005	} else if (eeprom->type == e1000_eeprom_spi) {
3006	eecd \|= E1000_EECD_DO;
3007	}
3008	do {
3009	/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3010	* and then raising and then lowering the clock (the SK bit controls
3011	* the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3012	* by setting "DI" to "0" and then raising and then lowering the clock.
3013	*/
3014	eecd &= ~E1000_EECD_DI;
3015
3016	if(data & mask)
3017	eecd \|= E1000_EECD_DI;
3018
3019	E1000_WRITE_REG(hw, EECD, eecd);
3020	E1000_WRITE_FLUSH(hw);
3021
3022	udelay(eeprom->delay_usec);
3023
3024	e1000_raise_ee_clk(hw, &eecd);
3025	e1000_lower_ee_clk(hw, &eecd);
3026
3027	mask = mask >> 1;
3028
3029	} while(mask);
3030
3031	/* We leave the "DI" bit set to "0" when we leave this routine. */
3032	eecd &= ~E1000_EECD_DI;
3033	E1000_WRITE_REG(hw, EECD, eecd);
3034	}
3035
3036	/******************************************************************************
3037	* Shift data bits in from the EEPROM
3038	*
3039	* hw - Struct containing variables accessed by shared code
3040	*****************************************************************************/
3041	static uint16_t
3042	e1000_shift_in_ee_bits(struct e1000_hw *hw,
3043	uint16_t count)
3044	{
3045	uint32_t eecd;
3046	uint32_t i;
3047	uint16_t data;
3048
3049	/* In order to read a register from the EEPROM, we need to shift 'count'
3050	* bits in from the EEPROM. Bits are "shifted in" by raising the clock
3051	* input to the EEPROM (setting the SK bit), and then reading the value of
3052	* the "DO" bit. During this "shifting in" process the "DI" bit should
3053	* always be clear.
3054	*/
3055
3056	eecd = E1000_READ_REG(hw, EECD);
3057
3058	eecd &= ~(E1000_EECD_DO \| E1000_EECD_DI);
3059	data = 0;
3060
3061	for(i = 0; i < count; i++) {
3062	data = data << 1;
3063	e1000_raise_ee_clk(hw, &eecd);
3064
3065	eecd = E1000_READ_REG(hw, EECD);
3066
3067	eecd &= ~(E1000_EECD_DI);
3068	if(eecd & E1000_EECD_DO)
3069	data \|= 1;
3070
3071	e1000_lower_ee_clk(hw, &eecd);
3072	}
3073
3074	return data;
3075	}
3076
3077	/******************************************************************************
3078	* Prepares EEPROM for access
3079	*
3080	* hw - Struct containing variables accessed by shared code
3081	*
3082	* Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3083	* function should be called before issuing a command to the EEPROM.
3084	*****************************************************************************/
3085	static int32_t
3086	e1000_acquire_eeprom(struct e1000_hw *hw)
3087	{
3088	struct e1000_eeprom_info *eeprom = &hw->eeprom;
3089	uint32_t eecd, i=0;
3090
3091	eecd = E1000_READ_REG(hw, EECD);
3092
3093	/* Request EEPROM Access */
3094	if(hw->mac_type > e1000_82544) {
3095	eecd \|= E1000_EECD_REQ;
3096	E1000_WRITE_REG(hw, EECD, eecd);
3097	eecd = E1000_READ_REG(hw, EECD);
3098	while((!(eecd & E1000_EECD_GNT)) &&
3099	(i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3100	i++;
3101	udelay(5);
3102	eecd = E1000_READ_REG(hw, EECD);
3103	}
3104	if(!(eecd & E1000_EECD_GNT)) {
3105	eecd &= ~E1000_EECD_REQ;
3106	E1000_WRITE_REG(hw, EECD, eecd);
3107	DEBUGOUT("Could not acquire EEPROM grant\n");
3108	return -E1000_ERR_EEPROM;
3109	}
3110	}
3111
3112	/* Setup EEPROM for Read/Write */
3113
3114	if (eeprom->type == e1000_eeprom_microwire) {
3115	/* Clear SK and DI */
3116	eecd &= ~(E1000_EECD_DI \| E1000_EECD_SK);
3117	E1000_WRITE_REG(hw, EECD, eecd);
3118
3119	/* Set CS */
3120	eecd \|= E1000_EECD_CS;
3121	E1000_WRITE_REG(hw, EECD, eecd);
3122	} else if (eeprom->type == e1000_eeprom_spi) {
3123	/* Clear SK and CS */
3124	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
3125	E1000_WRITE_REG(hw, EECD, eecd);
3126	udelay(1);
3127	}
3128
3129	return E1000_SUCCESS;
3130	}
3131
3132	/******************************************************************************
3133	* Returns EEPROM to a "standby" state
3134	*
3135	* hw - Struct containing variables accessed by shared code
3136	*****************************************************************************/
3137	static void
3138	e1000_standby_eeprom(struct e1000_hw *hw)
3139	{
3140	struct e1000_eeprom_info *eeprom = &hw->eeprom;
3141	uint32_t eecd;
3142
3143	eecd = E1000_READ_REG(hw, EECD);
3144
3145	if(eeprom->type == e1000_eeprom_microwire) {
3146
3147	/* Deselect EEPROM */
3148	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
3149	E1000_WRITE_REG(hw, EECD, eecd);
3150	E1000_WRITE_FLUSH(hw);
3151	udelay(eeprom->delay_usec);
3152
3153	/* Clock high */
3154	eecd \|= E1000_EECD_SK;
3155	E1000_WRITE_REG(hw, EECD, eecd);
3156	E1000_WRITE_FLUSH(hw);
3157	udelay(eeprom->delay_usec);
3158
3159	/* Select EEPROM */
3160	eecd \|= E1000_EECD_CS;
3161	E1000_WRITE_REG(hw, EECD, eecd);
3162	E1000_WRITE_FLUSH(hw);
3163	udelay(eeprom->delay_usec);
3164
3165	/* Clock low */
3166	eecd &= ~E1000_EECD_SK;
3167	E1000_WRITE_REG(hw, EECD, eecd);
3168	E1000_WRITE_FLUSH(hw);
3169	udelay(eeprom->delay_usec);
3170	} else if(eeprom->type == e1000_eeprom_spi) {
3171	/* Toggle CS to flush commands */
3172	eecd \|= E1000_EECD_CS;
3173	E1000_WRITE_REG(hw, EECD, eecd);
3174	E1000_WRITE_FLUSH(hw);
3175	udelay(eeprom->delay_usec);
3176	eecd &= ~E1000_EECD_CS;
3177	E1000_WRITE_REG(hw, EECD, eecd);
3178	E1000_WRITE_FLUSH(hw);
3179	udelay(eeprom->delay_usec);
3180	}
3181	}
3182
3183	/******************************************************************************
3184	* Terminates a command by inverting the EEPROM's chip select pin
3185	*
3186	* hw - Struct containing variables accessed by shared code
3187	*****************************************************************************/
3188	static void
3189	e1000_release_eeprom(struct e1000_hw *hw)
3190	{
3191	uint32_t eecd;
3192
3193	eecd = E1000_READ_REG(hw, EECD);
3194
3195	if (hw->eeprom.type == e1000_eeprom_spi) {
3196	eecd \|= E1000_EECD_CS; /* Pull CS high */
3197	eecd &= ~E1000_EECD_SK; /* Lower SCK */
3198
3199	E1000_WRITE_REG(hw, EECD, eecd);
3200
3201	udelay(hw->eeprom.delay_usec);
3202	} else if(hw->eeprom.type == e1000_eeprom_microwire) {
3203	/* cleanup eeprom */
3204
3205	/* CS on Microwire is active-high */
3206	eecd &= ~(E1000_EECD_CS \| E1000_EECD_DI);
3207
3208	E1000_WRITE_REG(hw, EECD, eecd);
3209
3210	/* Rising edge of clock */
3211	eecd \|= E1000_EECD_SK;
3212	E1000_WRITE_REG(hw, EECD, eecd);
3213	E1000_WRITE_FLUSH(hw);
3214	udelay(hw->eeprom.delay_usec);
3215
3216	/* Falling edge of clock */
3217	eecd &= ~E1000_EECD_SK;
3218	E1000_WRITE_REG(hw, EECD, eecd);
3219	E1000_WRITE_FLUSH(hw);
3220	udelay(hw->eeprom.delay_usec);
3221	}
3222
3223	/* Stop requesting EEPROM access */
3224	if(hw->mac_type > e1000_82544) {
3225	eecd &= ~E1000_EECD_REQ;
3226	E1000_WRITE_REG(hw, EECD, eecd);
3227	}
3228	}
3229
3230	/******************************************************************************
3231	* Reads a 16 bit word from the EEPROM.
3232	*
3233	* hw - Struct containing variables accessed by shared code
3234	*****************************************************************************/
3235	static int32_t
3236	e1000_spi_eeprom_ready(struct e1000_hw *hw)
3237	{
3238	uint16_t retry_count = 0;
3239	uint8_t spi_stat_reg;
3240
3241	/* Read "Status Register" repeatedly until the LSB is cleared. The
3242	* EEPROM will signal that the command has been completed by clearing
3243	* bit 0 of the internal status register. If it's not cleared within
3244	* 5 milliseconds, then error out.
3245	*/
3246	retry_count = 0;
3247	do {
3248	e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3249	hw->eeprom.opcode_bits);
3250	spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3251	if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3252	break;
3253
3254	udelay(5);
3255	retry_count += 5;
3256
3257	} while(retry_count < EEPROM_MAX_RETRY_SPI);
3258
3259	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3260	* only 0-5mSec on 5V devices)
3261	*/
3262	if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3263	DEBUGOUT("SPI EEPROM Status error\n");
3264	return -E1000_ERR_EEPROM;
3265	}
3266
3267	return E1000_SUCCESS;
3268	}
3269
3270	/******************************************************************************
3271	* Reads a 16 bit word from the EEPROM.
3272	*
3273	* hw - Struct containing variables accessed by shared code
3274	* offset - offset of word in the EEPROM to read
3275	* data - word read from the EEPROM
3276	* words - number of words to read
3277	*****************************************************************************/
3278	static int
3279	e1000_read_eeprom(struct e1000_hw *hw,
3280	uint16_t offset,
3281	uint16_t words,
3282	uint16_t *data)
3283	{
3284	struct e1000_eeprom_info *eeprom = &hw->eeprom;
3285	uint32_t i = 0;
3286
3287	DEBUGFUNC("e1000_read_eeprom");
3288
3289	/* A check for invalid values: offset too large, too many words, and not
3290	* enough words.
3291	*/
3292	if((offset > eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
3293	(words == 0)) {
3294	DEBUGOUT("\"words\" parameter out of bounds\n");
3295	return -E1000_ERR_EEPROM;
3296	}
3297
3298	/* Prepare the EEPROM for reading */
3299	if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3300	return -E1000_ERR_EEPROM;
3301
3302	if(eeprom->type == e1000_eeprom_spi) {
3303	uint16_t word_in;
3304	uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3305
3306	if(e1000_spi_eeprom_ready(hw)) {
3307	e1000_release_eeprom(hw);
3308	return -E1000_ERR_EEPROM;
3309	}
3310
3311	e1000_standby_eeprom(hw);
3312
3313	/* Some SPI eeproms use the 8th address bit embedded in the opcode */
3314	if((eeprom->address_bits == 8) && (offset >= 128))
3315	read_opcode \|= EEPROM_A8_OPCODE_SPI;
3316
3317	/* Send the READ command (opcode + addr) */
3318	e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3319	e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3320
3321	/* Read the data. The address of the eeprom internally increments with
3322	* each byte (spi) being read, saving on the overhead of eeprom setup
3323	* and tear-down. The address counter will roll over if reading beyond
3324	* the size of the eeprom, thus allowing the entire memory to be read
3325	* starting from any offset. */
3326	for (i = 0; i < words; i++) {
3327	word_in = e1000_shift_in_ee_bits(hw, 16);
3328	data[i] = (word_in >> 8) \| (word_in << 8);
3329	}
3330	} else if(eeprom->type == e1000_eeprom_microwire) {
3331	for (i = 0; i < words; i++) {
3332	/* Send the READ command (opcode + addr) */
3333	e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3334	eeprom->opcode_bits);
3335	e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3336	eeprom->address_bits);
3337
3338	/* Read the data. For microwire, each word requires the overhead
3339	* of eeprom setup and tear-down. */
3340	data[i] = e1000_shift_in_ee_bits(hw, 16);
3341	e1000_standby_eeprom(hw);
3342	}
3343	}
3344
3345	/* End this read operation */
3346	e1000_release_eeprom(hw);
3347
3348	return E1000_SUCCESS;
3349	}
3350
3351	/******************************************************************************
3352	* Verifies that the EEPROM has a valid checksum
3353	*
3354	* hw - Struct containing variables accessed by shared code
3355	*
3356	* Reads the first 64 16 bit words of the EEPROM and sums the values read.
3357	* If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3358	* valid.
3359	*****************************************************************************/
3360	static int
3361	e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3362	{
3363	uint16_t checksum = 0;
3364	uint16_t i, eeprom_data;
3365
3366	DEBUGFUNC("e1000_validate_eeprom_checksum");
3367
3368	for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3369	if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3370	DEBUGOUT("EEPROM Read Error\n");
3371	return -E1000_ERR_EEPROM;
3372	}
3373	checksum += eeprom_data;
3374	}
3375
3376	if(checksum == (uint16_t) EEPROM_SUM)
3377	return E1000_SUCCESS;
3378	else {
3379	DEBUGOUT("EEPROM Checksum Invalid\n");
3380	return -E1000_ERR_EEPROM;
3381	}
3382	}
3383
3384	/******************************************************************************
3385	* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3386	* second function of dual function devices
3387	*
3388	* hw - Struct containing variables accessed by shared code
3389	*****************************************************************************/
3390	static int
3391	e1000_read_mac_addr(struct e1000_hw *hw)
3392	{
3393	uint16_t offset;
3394	uint16_t eeprom_data;
3395	int i;
3396
3397	DEBUGFUNC("e1000_read_mac_addr");
3398
3399	for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3400	offset = i >> 1;
3401	if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3402	DEBUGOUT("EEPROM Read Error\n");
3403	return -E1000_ERR_EEPROM;
3404	}
3405	hw->mac_addr[i] = eeprom_data & 0xff;
3406	hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
3407	}
3408	if(((hw->mac_type == e1000_82546) \|\| (hw->mac_type == e1000_82546_rev_3)) &&
3409	(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3410	/* Invert the last bit if this is the second device */
3411	hw->mac_addr[5] ^= 1;
3412	return E1000_SUCCESS;
3413	}
3414
3415	/******************************************************************************
3416	* Initializes receive address filters.
3417	*
3418	* hw - Struct containing variables accessed by shared code
3419	*
3420	* Places the MAC address in receive address register 0 and clears the rest
3421	* of the receive addresss registers. Clears the multicast table. Assumes
3422	* the receiver is in reset when the routine is called.
3423	*****************************************************************************/
3424	static void
3425	e1000_init_rx_addrs(struct e1000_hw *hw)
3426	{
3427	uint32_t i;
3428	uint32_t addr_low;
3429	uint32_t addr_high;
3430
3431	DEBUGFUNC("e1000_init_rx_addrs");
3432
3433	/* Setup the receive address. */
3434	DEBUGOUT("Programming MAC Address into RAR[0]\n");
3435	addr_low = (hw->mac_addr[0] \|
3436	(hw->mac_addr[1] << 8) \|
3437	(hw->mac_addr[2] << 16) \| (hw->mac_addr[3] << 24));
3438
3439	addr_high = (hw->mac_addr[4] \|
3440	(hw->mac_addr[5] << 8) \| E1000_RAH_AV);
3441
3442	E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
3443	E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
3444
3445	/* Zero out the other 15 receive addresses. */
3446	DEBUGOUT("Clearing RAR[1-15]\n");
3447	for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3448	E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3449	E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3450	}
3451	}
3452
3453	/******************************************************************************
3454	* Clears the VLAN filer table
3455	*
3456	* hw - Struct containing variables accessed by shared code
3457	*****************************************************************************/
3458	static void
3459	e1000_clear_vfta(struct e1000_hw *hw)
3460	{
3461	uint32_t offset;
3462
3463	for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
3464	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
3465	}
3466
3467	/******************************************************************************
3468	* Writes a value to one of the devices registers using port I/O (as opposed to
3469	* memory mapped I/O). Only 82544 and newer devices support port I/O. *
3470	* hw - Struct containing variables accessed by shared code
3471	* offset - offset to write to * value - value to write
3472	*****************************************************************************/
3473	static void
3474	e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value)
3475	{
3476	uint32_t io_addr = hw->io_base;
3477	uint32_t io_data = hw->io_base + 4;
3478	e1000_io_write(hw, io_addr, offset);
3479	e1000_io_write(hw, io_data, value);
3480	}
3481
3482
3483	/******************************************************************************
3484	* Functions from e1000_main.c of the linux driver
3485	******************************************************************************/
3486
3487	/**
3488	* e1000_reset - Reset the adapter
3489	*/
3490
3491	static int
3492	e1000_reset(struct e1000_hw *hw)
3493	{
3494	uint32_t pba;
3495	/* Repartition Pba for greater than 9k mtu
3496	* To take effect CTRL.RST is required.
3497	*/
3498
3499	if(hw->mac_type < e1000_82547) {
3500	pba = E1000_PBA_48K;
3501	} else if (hw->mac_type == e1000_80003es2lan) {
3502	pba = E1000_PBA_38K;
3503	} else {
3504	pba = E1000_PBA_30K;
3505	}
3506	E1000_WRITE_REG(hw, PBA, pba);
3507
3508	/* flow control settings */
3509	#if 0
3510	hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3511	hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3512	hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3513	hw->fc_send_xon = 1;
3514	hw->fc = hw->original_fc;
3515	#endif
3516
3517	e1000_reset_hw(hw);
3518	if(hw->mac_type >= e1000_82544)
3519	E1000_WRITE_REG(hw, WUC, 0);
3520	return e1000_init_hw(hw);
3521	}
3522
3523	/**
3524	* e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3525	* @adapter: board private structure to initialize
3526	*
3527	* e1000_sw_init initializes the Adapter private data structure.
3528	* Fields are initialized based on PCI device information and
3529	* OS network device settings (MTU size).
3530	**/
3531
3532	static int
3533	e1000_sw_init(struct pci_device pdev, struct e1000_hw hw)
3534	{
3535	int result;
3536
3537	/* PCI config space info */
3538	pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
3539	pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
3540	pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
3541	#if 0
3542	pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
3543	&hw->subsystem_vendor_id);
3544	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
3545	#endif
3546
3547	pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
3548
3549	/* identify the MAC */
3550
3551	result = e1000_set_mac_type(hw);
3552	if (result) {
3553	E1000_ERR("Unknown MAC Type\n");
3554	return result;
3555	}
3556
3557	/* initialize eeprom parameters */
3558
3559	e1000_init_eeprom_params(hw);
3560
3561	#if 0
3562	if((hw->mac_type == e1000_82541) \|\|
3563	(hw->mac_type == e1000_82547) \|\|
3564	(hw->mac_type == e1000_82541_rev_2) \|\|
3565	(hw->mac_type == e1000_82547_rev_2))
3566	hw->phy_init_script = 1;
3567	#endif
3568
3569	e1000_set_media_type(hw);
3570
3571	#if 0
3572	if(hw->mac_type < e1000_82543)
3573	hw->report_tx_early = 0;
3574	else
3575	hw->report_tx_early = 1;
3576
3577	hw->wait_autoneg_complete = FALSE;
3578	#endif
3579	hw->tbi_compatibility_en = TRUE;
3580	#if 0
3581	hw->adaptive_ifs = TRUE;
3582
3583	/* Copper options */
3584
3585	if(hw->media_type == e1000_media_type_copper) {
3586	hw->mdix = AUTO_ALL_MODES;
3587	hw->disable_polarity_correction = FALSE;
3588	hw->master_slave = E1000_MASTER_SLAVE;
3589	}
3590	#endif
3591	return E1000_SUCCESS;
3592	}
3593
3594	#if 0
3595	static uint32_t
3596	e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
3597	{
3598	return inl(port);
3599	}
3600	#endif
3601
3602	static void
3603	e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
3604	{
3605	outl(value, port);
3606	}
3607
3608
3609	/******************************************************************************
3610	* Functions not present in the linux driver
3611	******************************************************************************/
3612
3613	static void fill_rx (void)
3614	{
3615	struct e1000_rx_desc *rd;
3616	rd = rx_base + rx_tail;
3617	memset (rd, 0, 16);
3618	rd->buffer_addr = virt_to_bus(&packets[MAX_PACKET*(rx_tail%RX_BUFS)]);
3619	rx_tail = (rx_tail + 1) % 8;
3620	E1000_WRITE_REG (&hw, RDT, rx_tail);
3621	}
3622
3623	static void init_descriptor (void)
3624	{
3625	unsigned long ptr;
3626	unsigned long tctl;
3627	int i;
3628
3629	ptr = virt_to_phys(tx_pool);
3630	if (ptr & 0xf)
3631	ptr = (ptr + 0x10) & (~0xf);
3632
3633	tx_base = phys_to_virt(ptr);
3634
3635	E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
3636	E1000_WRITE_REG (&hw, TDBAH, 0);
3637	E1000_WRITE_REG (&hw, TDLEN, 128);
3638
3639	/* Setup the HW Tx Head and Tail descriptor pointers */
3640
3641	E1000_WRITE_REG (&hw, TDH, 0);
3642	E1000_WRITE_REG (&hw, TDT, 0);
3643	tx_tail = 0;
3644
3645	/* Program the Transmit Control Register */
3646
3647	#ifdef LINUX_DRIVER_TCTL
3648	tctl = E1000_READ_REG(&hw, TCTL);
3649
3650	tctl &= ~E1000_TCTL_CT;
3651	tctl \|= E1000_TCTL_EN \| E1000_TCTL_PSP \|
3652	(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3653	#else
3654	tctl = E1000_TCTL_PSP \| E1000_TCTL_EN \|
3655	(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) \|
3656	(E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
3657	#endif
3658
3659	E1000_WRITE_REG (&hw, TCTL, tctl);
3660
3661	e1000_config_collision_dist(&hw);
3662
3663
3664	rx_tail = 0;
3665	/* disable receive */
3666	E1000_WRITE_REG (&hw, RCTL, 0);
3667	ptr = virt_to_phys(rx_pool);
3668	if (ptr & 0xf)
3669	ptr = (ptr + 0x10) & (~0xf);
3670	rx_base = phys_to_virt(ptr);
3671
3672	/* Setup the Base and Length of the Rx Descriptor Ring */
3673
3674	E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
3675	E1000_WRITE_REG (&hw, RDBAH, 0);
3676
3677	E1000_WRITE_REG (&hw, RDLEN, 128);
3678
3679	/* Setup the HW Rx Head and Tail Descriptor Pointers */
3680	E1000_WRITE_REG (&hw, RDH, 0);
3681	E1000_WRITE_REG (&hw, RDT, 0);
3682
3683	E1000_WRITE_REG (&hw, RCTL,
3684	E1000_RCTL_EN \|
3685	E1000_RCTL_BAM \|
3686	E1000_RCTL_SZ_2048 \|
3687	E1000_RCTL_MPE);
3688	for (i = 0; i < RX_BUFS; i++)
3689	fill_rx();
3690	}
3691
3692
3693
3694	/**************************************************************************
3695	POLL - Wait for a frame
3696	***************************************************************************/
3697	static int
3698	e1000_poll (struct nic *nic, int retrieve)
3699	{
3700	/* return true if there's an ethernet packet ready to read */
3701	/* nic->packet should contain data on return */
3702	/* nic->packetlen should contain length of data */
3703	struct e1000_rx_desc *rd;
3704	char packet = &packets[MAX_PACKET(rx_last%RX_BUFS)];
3705	uint32_t icr;
3706
3707	rd = rx_base + rx_last;
3708	if (!rd->status & E1000_RXD_STAT_DD)
3709	return 0;
3710
3711	if ( ! retrieve ) return 1;
3712
3713	// printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length);
3714	memcpy (nic->packet, packet, rd->length);
3715	nic->packetlen = rd->length;
3716	rx_last = (rx_last + 1) %8;
3717	fill_rx ();
3718
3719	/* Acknowledge interrupt. */
3720	icr = E1000_READ_REG(&hw, ICR);
3721
3722	return 1;
3723	}
3724
3725	/**************************************************************************
3726	TRANSMIT - Transmit a frame
3727	***************************************************************************/
3728	static void
3729	e1000_transmit (struct nic nic, const char d, /* Destination */
3730	unsigned int type, /* Type */
3731	unsigned int size, /* size */
3732	const char p) / Packet */
3733	{
3734	/* send the packet to destination */
3735	struct eth_hdr {
3736	unsigned char dst_addr[ETH_ALEN];
3737	unsigned char src_addr[ETH_ALEN];
3738	unsigned short type;
3739	} hdr;
3740	struct e1000_tx_desc txhd; / header */
3741	struct e1000_tx_desc txp; / payload */
3742	DEBUGFUNC("send");
3743
3744	memcpy (&hdr.dst_addr, d, ETH_ALEN);
3745	memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
3746
3747	hdr.type = htons (type);
3748	txhd = tx_base + tx_tail;
3749	tx_tail = (tx_tail + 1) % 8;
3750	txp = tx_base + tx_tail;
3751	tx_tail = (tx_tail + 1) % 8;
3752
3753	txhd->buffer_addr = virt_to_bus (&hdr);
3754	txhd->lower.data = sizeof (hdr);
3755	txhd->upper.data = 0;
3756
3757	txp->buffer_addr = virt_to_bus(p);
3758	txp->lower.data = E1000_TXD_CMD_RPS \| E1000_TXD_CMD_EOP \| E1000_TXD_CMD_IFCS \| size;
3759	txp->upper.data = 0;
3760
3761	E1000_WRITE_REG (&hw, TDT, tx_tail);
3762	while (!(txp->upper.data & E1000_TXD_STAT_DD)) {
3763	udelay(10); /* give the nic a chance to write to the register */
3764	poll_interruptions();
3765	}
3766	DEBUGFUNC("send end");
3767	}
3768
3769
3770	/**************************************************************************
3771	DISABLE - Turn off ethernet interface
3772	***************************************************************************/
3773	static void e1000_disable (struct dev *dev __unused)
3774	{
3775	/* Clear the transmit ring */
3776	E1000_WRITE_REG (&hw, TDH, 0);
3777	E1000_WRITE_REG (&hw, TDT, 0);
3778
3779	/* Clear the receive ring */
3780	E1000_WRITE_REG (&hw, RDH, 0);
3781	E1000_WRITE_REG (&hw, RDT, 0);
3782
3783	/* put the card in its initial state */
3784	switch(hw.mac_type) {
3785	case e1000_82544:
3786	case e1000_82540:
3787	case e1000_82545:
3788	case e1000_82546:
3789	case e1000_82541:
3790	case e1000_82541_rev_2:
3791	/* These controllers can't ack the 64-bit write when issuing the
3792	* reset, so use IO-mapping as a workaround to issue the reset */
3793	E1000_WRITE_REG_IO(&hw, CTRL, E1000_CTRL_RST);
3794	break;
3795	case e1000_82545_rev_3:
3796	case e1000_82546_rev_3:
3797	/* Reset is performed on a shadow of the control register */
3798	E1000_WRITE_REG(&hw, CTRL_DUP, E1000_CTRL_RST);
3799	break;
3800	default:
3801	E1000_WRITE_REG(&hw, CTRL, E1000_CTRL_RST);
3802	break;
3803	}
3804
3805	/* Turn off the ethernet interface */
3806	E1000_WRITE_REG (&hw, RCTL, 0);
3807	E1000_WRITE_REG (&hw, TCTL, 0);
3808	mdelay (10);
3809
3810	/* Unmap my window to the device */
3811	iounmap(hw.hw_addr);
3812	}
3813
3814	/**************************************************************************
3815	IRQ - Enable, Disable, or Force interrupts
3816	***************************************************************************/
3817	static void e1000_irq(struct nic *nic __unused, irq_action_t action)
3818	{
3819	switch ( action ) {
3820	case DISABLE :
3821	E1000_WRITE_REG(&hw, IMC, ~0);
3822	E1000_WRITE_FLUSH(&hw);
3823	break;
3824	case ENABLE :
3825	E1000_WRITE_REG(&hw, IMS,
3826	E1000_IMS_RXT0 \| E1000_IMS_RXSEQ);
3827	E1000_WRITE_FLUSH(&hw);
3828	break;
3829	case FORCE :
3830	E1000_WRITE_REG(&hw, ICS, E1000_ICS_RXT0);
3831	break;
3832	}
3833	}
3834
3835	#define IORESOURCE_IO 0x00000100 /* Resource type */
3836	#define BAR_0 0
3837	#define BAR_1 1
3838	#define BAR_5 5
3839
3840	/**************************************************************************
3841	PROBE - Look for an adapter, this routine's visible to the outside
3842	You should omit the last argument struct pci_device * for a non-PCI NIC
3843	***************************************************************************/
3844	static int e1000_probe(struct dev dev, struct pci_device p)
3845	{
3846	struct nic nic = (struct nic )dev;
3847	unsigned long mmio_start, mmio_len;
3848	int ret_val, i;
3849
3850	if (p == 0)
3851	return 0;
3852	/* Initialize hw with default values */
3853	memset(&hw, 0, sizeof(hw));
3854	hw.pdev = p;
3855
3856	#if 1
3857	/* Are these variables needed? */
3858	hw.fc = e1000_fc_none;
3859	#if 0
3860	hw.original_fc = e1000_fc_none;
3861	#endif
3862	hw.autoneg_failed = 0;
3863	#if 0
3864	hw.get_link_status = TRUE;
3865	#endif
3866	#endif
3867
3868	mmio_start = pci_bar_start(p, PCI_BASE_ADDRESS_0);
3869	mmio_len = pci_bar_size(p, PCI_BASE_ADDRESS_0);
3870	hw.hw_addr = ioremap(mmio_start, mmio_len);
3871
3872	for(i = BAR_1; i <= BAR_5; i++) {
3873	if(pci_bar_size(p, i) == 0)
3874	continue;
3875	if(pci_find_capability(p, i) & IORESOURCE_IO) {
3876	hw.io_base = pci_bar_start(p, i);
3877	break;
3878	}
3879	}
3880
3881	adjust_pci_device(p);
3882
3883	nic->ioaddr = p->ioaddr & ~3;
3884	nic->irqno = p->irq;
3885
3886	/* From Matt Hortman <[email protected]> */
3887	/* MAC and Phy settings */
3888
3889	/* setup the private structure */
3890	if (e1000_sw_init(p, &hw) < 0) {
3891	iounmap(hw.hw_addr);
3892	return 0;
3893	}
3894
3895	/* make sure the EEPROM is good */
3896
3897	if (e1000_validate_eeprom_checksum(&hw) < 0) {
3898	printf ("The EEPROM Checksum Is Not Valid\n");
3899	iounmap(hw.hw_addr);
3900	return 0;
3901	}
3902
3903	/* copy the MAC address out of the EEPROM */
3904
3905	e1000_read_mac_addr(&hw);
3906	memcpy (nic->node_addr, hw.mac_addr, ETH_ALEN);
3907
3908	printf("Ethernet addr: %!\n", nic->node_addr);
3909
3910	/* reset the hardware with the new settings */
3911
3912	ret_val = e1000_reset(&hw);
3913	if (ret_val < 0) {
3914	if ((ret_val == -E1000_ERR_NOLINK) \|\|
3915	(ret_val == -E1000_ERR_TIMEOUT)) {
3916	E1000_ERR("Valid Link not detected\n");
3917	} else {
3918	E1000_ERR("Hardware Initialization Failed\n");
3919	}
3920	iounmap(hw.hw_addr);
3921	return 0;
3922	}
3923	init_descriptor();
3924
3925	/* point to NIC specific routines */
3926	dev->disable = e1000_disable;
3927	nic->poll = e1000_poll;
3928	nic->transmit = e1000_transmit;
3929	nic->irq = e1000_irq;
3930
3931	return 1;
3932	}
3933
3934	static struct pci_id e1000_nics[] = {
3935	PCI_ROM(0x8086, 0x1000, "e1000-82542", "Intel EtherExpressPro1000"),
3936	PCI_ROM(0x8086, 0x1001, "e1000-82543gc-fiber", "Intel EtherExpressPro1000 82543GC Fiber"),
3937	PCI_ROM(0x8086, 0x1004, "e1000-82543gc-copper", "Intel EtherExpressPro1000 82543GC Copper"),
3938	PCI_ROM(0x8086, 0x1008, "e1000-82544ei-copper", "Intel EtherExpressPro1000 82544EI Copper"),
3939	PCI_ROM(0x8086, 0x1009, "e1000-82544ei-fiber", "Intel EtherExpressPro1000 82544EI Fiber"),
3940	PCI_ROM(0x8086, 0x100C, "e1000-82544gc-copper", "Intel EtherExpressPro1000 82544GC Copper"),
3941	PCI_ROM(0x8086, 0x100D, "e1000-82544gc-lom", "Intel EtherExpressPro1000 82544GC LOM"),
3942	PCI_ROM(0x8086, 0x100E, "e1000-82540em", "Intel EtherExpressPro1000 82540EM"),
3943	PCI_ROM(0x8086, 0x100F, "e1000-82545em-copper", "Intel EtherExpressPro1000 82545EM Copper"),
3944	PCI_ROM(0x8086, 0x1010, "e1000-82546eb-copper", "Intel EtherExpressPro1000 82546EB Copper"),
3945	PCI_ROM(0x8086, 0x1011, "e1000-82545em-fiber", "Intel EtherExpressPro1000 82545EM Fiber"),
3946	PCI_ROM(0x8086, 0x1012, "e1000-82546eb-fiber", "Intel EtherExpressPro1000 82546EB Copper"),
3947	PCI_ROM(0x8086, 0x1013, "e1000-82541ei", "Intel EtherExpressPro1000 82541EI"),
3948	PCI_ROM(0x8086, 0x1015, "e1000-82540em-lom", "Intel EtherExpressPro1000 82540EM LOM"),
3949	PCI_ROM(0x8086, 0x1016, "e1000-82540ep-lom", "Intel EtherExpressPro1000 82540EP LOM"),
3950	PCI_ROM(0x8086, 0x1017, "e1000-82540ep", "Intel EtherExpressPro1000 82540EP"),
3951	PCI_ROM(0x8086, 0x1018, "e1000-82541ep", "Intel EtherExpressPro1000 82541EP"),
3952	PCI_ROM(0x8086, 0x1019, "e1000-82547ei", "Intel EtherExpressPro1000 82547EI"),
3953	PCI_ROM(0x8086, 0x101d, "e1000-82546eb-quad-copper", "Intel EtherExpressPro1000 82546EB Quad Copper"),
3954	PCI_ROM(0x8086, 0x101e, "e1000-82540ep-lp", "Intel EtherExpressPro1000 82540EP LP"),
3955	PCI_ROM(0x8086, 0x1026, "e1000-82545gm-copper", "Intel EtherExpressPro1000 82545GM Copper"),
3956	PCI_ROM(0x8086, 0x1027, "e1000-82545gm-fiber", "Intel EtherExpressPro1000 82545GM Fiber"),
3957	PCI_ROM(0x8086, 0x1028, "e1000-82545gm-serdes", "Intel EtherExpressPro1000 82545GM SERDES"),
3958	PCI_ROM(0x8086, 0x1075, "e1000-82547gi", "Intel EtherExpressPro1000 82547GI"),
3959	PCI_ROM(0x8086, 0x1076, "e1000-82541gi", "Intel EtherExpressPro1000 82541GI"),
3960	PCI_ROM(0x8086, 0x1077, "e1000-82541gi-mobile", "Intel EtherExpressPro1000 82541GI Mobile"),
3961	PCI_ROM(0x8086, 0x1078, "e1000-82541er", "Intel EtherExpressPro1000 82541ER"),
3962	PCI_ROM(0x8086, 0x1079, "e1000-82546gb-copper", "Intel EtherExpressPro1000 82546GB Copper"),
3963	PCI_ROM(0x8086, 0x107a, "e1000-82546gb-fiber", "Intel EtherExpressPro1000 82546GB Fiber"),
3964	PCI_ROM(0x8086, 0x107b, "e1000-82546gb-serdes", "Intel EtherExpressPro1000 82546GB SERDES"),
3965	PCI_ROM(0x8086, 0x107c, "e1000-82541pi", "Intel EtherExpressPro1000 82541PI"),
3966	PCI_ROM(0x8086, 0x1096, "e1000_80003es2lan", "Intel EtherExpressPro1000 GB COPPER"),
3967	};
3968
3969	static struct pci_driver e1000_driver __pci_driver = {
3970	.type = NIC_DRIVER,
3971	.name = "E1000",
3972	.probe = e1000_probe,
3973	.ids = e1000_nics,
3974	.id_count = sizeof(e1000_nics)/sizeof(e1000_nics[0]),
3975	.class = 0,
3976	};

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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/e1000.c@ 1300

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