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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/e1000_hw.h@ 1300

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1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <[email protected]>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36/* Forward declarations of structures used by the shared code */
37struct e1000_hw;
38struct e1000_hw_stats;
39
40/* Enumerated types specific to the e1000 hardware */
41/* Media Access Controlers */
42typedef enum {
43 e1000_undefined = 0,
44 e1000_82542_rev2_0,
45 e1000_82542_rev2_1,
46 e1000_82543,
47 e1000_82544,
48 e1000_82540,
49 e1000_82545,
50 e1000_82545_rev_3,
51 e1000_82546,
52 e1000_82546_rev_3,
53 e1000_82541,
54 e1000_82541_rev_2,
55 e1000_82547,
56 e1000_82547_rev_2,
57 e1000_80003es2lan,
58 e1000_num_macs
59} e1000_mac_type;
60
61typedef enum {
62 e1000_eeprom_uninitialized = 0,
63 e1000_eeprom_spi,
64 e1000_eeprom_microwire,
65 e1000_num_eeprom_types
66} e1000_eeprom_type;
67
68/* Media Types */
69typedef enum {
70 e1000_media_type_copper = 0,
71 e1000_media_type_fiber = 1,
72 e1000_media_type_internal_serdes = 2,
73 e1000_num_media_types
74} e1000_media_type;
75
76typedef enum {
77 e1000_10_half = 0,
78 e1000_10_full = 1,
79 e1000_100_half = 2,
80 e1000_100_full = 3
81} e1000_speed_duplex_type;
82
83/* Flow Control Settings */
84typedef enum {
85 e1000_fc_none = 0,
86 e1000_fc_rx_pause = 1,
87 e1000_fc_tx_pause = 2,
88 e1000_fc_full = 3,
89 e1000_fc_default = 0xFF
90} e1000_fc_type;
91
92/* PCI bus types */
93typedef enum {
94 e1000_bus_type_unknown = 0,
95 e1000_bus_type_pci,
96 e1000_bus_type_pcix,
97 e1000_bus_type_reserved
98} e1000_bus_type;
99
100/* PCI bus speeds */
101typedef enum {
102 e1000_bus_speed_unknown = 0,
103 e1000_bus_speed_33,
104 e1000_bus_speed_66,
105 e1000_bus_speed_100,
106 e1000_bus_speed_120,
107 e1000_bus_speed_133,
108 e1000_bus_speed_reserved
109} e1000_bus_speed;
110
111/* PCI bus widths */
112typedef enum {
113 e1000_bus_width_unknown = 0,
114 e1000_bus_width_32,
115 e1000_bus_width_64,
116 e1000_bus_width_reserved
117} e1000_bus_width;
118
119/* PHY status info structure and supporting enums */
120typedef enum {
121 e1000_cable_length_50 = 0,
122 e1000_cable_length_50_80,
123 e1000_cable_length_80_110,
124 e1000_cable_length_110_140,
125 e1000_cable_length_140,
126 e1000_cable_length_undefined = 0xFF
127} e1000_cable_length;
128
129typedef enum {
130 e1000_igp_cable_length_10 = 10,
131 e1000_igp_cable_length_20 = 20,
132 e1000_igp_cable_length_30 = 30,
133 e1000_igp_cable_length_40 = 40,
134 e1000_igp_cable_length_50 = 50,
135 e1000_igp_cable_length_60 = 60,
136 e1000_igp_cable_length_70 = 70,
137 e1000_igp_cable_length_80 = 80,
138 e1000_igp_cable_length_90 = 90,
139 e1000_igp_cable_length_100 = 100,
140 e1000_igp_cable_length_110 = 110,
141 e1000_igp_cable_length_120 = 120,
142 e1000_igp_cable_length_130 = 130,
143 e1000_igp_cable_length_140 = 140,
144 e1000_igp_cable_length_150 = 150,
145 e1000_igp_cable_length_160 = 160,
146 e1000_igp_cable_length_170 = 170,
147 e1000_igp_cable_length_180 = 180
148} e1000_igp_cable_length;
149
150typedef enum {
151 e1000_10bt_ext_dist_enable_normal = 0,
152 e1000_10bt_ext_dist_enable_lower,
153 e1000_10bt_ext_dist_enable_undefined = 0xFF
154} e1000_10bt_ext_dist_enable;
155
156typedef enum {
157 e1000_rev_polarity_normal = 0,
158 e1000_rev_polarity_reversed,
159 e1000_rev_polarity_undefined = 0xFF
160} e1000_rev_polarity;
161
162typedef enum {
163 e1000_downshift_normal = 0,
164 e1000_downshift_activated,
165 e1000_downshift_undefined = 0xFF
166} e1000_downshift;
167
168typedef enum {
169 e1000_polarity_reversal_enabled = 0,
170 e1000_polarity_reversal_disabled,
171 e1000_polarity_reversal_undefined = 0xFF
172} e1000_polarity_reversal;
173
174typedef enum {
175 e1000_auto_x_mode_manual_mdi = 0,
176 e1000_auto_x_mode_manual_mdix,
177 e1000_auto_x_mode_auto1,
178 e1000_auto_x_mode_auto2,
179 e1000_auto_x_mode_undefined = 0xFF
180} e1000_auto_x_mode;
181
182typedef enum {
183 e1000_1000t_rx_status_not_ok = 0,
184 e1000_1000t_rx_status_ok,
185 e1000_1000t_rx_status_undefined = 0xFF
186} e1000_1000t_rx_status;
187
188typedef enum {
189 e1000_phy_m88 = 0,
190 e1000_phy_igp,
191 e1000_phy_gg82563,
192 e1000_phy_undefined = 0xFF
193} e1000_phy_type;
194
195typedef enum {
196 e1000_ms_hw_default = 0,
197 e1000_ms_force_master,
198 e1000_ms_force_slave,
199 e1000_ms_auto
200} e1000_ms_type;
201
202typedef enum {
203 e1000_ffe_config_enabled = 0,
204 e1000_ffe_config_active,
205 e1000_ffe_config_blocked
206} e1000_ffe_config;
207
208typedef enum {
209 e1000_dsp_config_disabled = 0,
210 e1000_dsp_config_enabled,
211 e1000_dsp_config_activated,
212 e1000_dsp_config_undefined = 0xFF
213} e1000_dsp_config;
214
215struct e1000_phy_info {
216 e1000_cable_length cable_length;
217 e1000_10bt_ext_dist_enable extended_10bt_distance;
218 e1000_rev_polarity cable_polarity;
219 e1000_downshift downshift;
220 e1000_polarity_reversal polarity_correction;
221 e1000_auto_x_mode mdix_mode;
222 e1000_1000t_rx_status local_rx;
223 e1000_1000t_rx_status remote_rx;
224};
225
226struct e1000_phy_stats {
227 uint32_t idle_errors;
228 uint32_t receive_errors;
229};
230
231struct e1000_eeprom_info {
232 e1000_eeprom_type type;
233 uint16_t word_size;
234 uint16_t opcode_bits;
235 uint16_t address_bits;
236 uint16_t delay_usec;
237 uint16_t page_size;
238};
239
240
241
242/* Error Codes */
243#define E1000_SUCCESS 0
244#define E1000_ERR_EEPROM 1
245#define E1000_ERR_PHY 2
246#define E1000_ERR_CONFIG 3
247#define E1000_ERR_PARAM 4
248#define E1000_ERR_MAC_TYPE 5
249#define E1000_ERR_PHY_TYPE 6
250#define E1000_ERR_NOLINK 7
251#define E1000_ERR_TIMEOUT 8
252#define E1000_ERR_RESET 9
253
254#define E1000_READ_REG_IO(a, reg) \
255 e1000_read_reg_io((a), E1000_##reg)
256#define E1000_WRITE_REG_IO(a, reg, val) \
257 e1000_write_reg_io((a), E1000_##reg, val)
258
259/* PCI Device IDs */
260#define E1000_DEV_ID_82542 0x1000
261#define E1000_DEV_ID_82543GC_FIBER 0x1001
262#define E1000_DEV_ID_82543GC_COPPER 0x1004
263#define E1000_DEV_ID_82544EI_COPPER 0x1008
264#define E1000_DEV_ID_82544EI_FIBER 0x1009
265#define E1000_DEV_ID_82544GC_COPPER 0x100C
266#define E1000_DEV_ID_82544GC_LOM 0x100D
267#define E1000_DEV_ID_82540EM 0x100E
268#define E1000_DEV_ID_82540EM_LOM 0x1015
269#define E1000_DEV_ID_82540EP_LOM 0x1016
270#define E1000_DEV_ID_82540EP 0x1017
271#define E1000_DEV_ID_82540EP_LP 0x101E
272#define E1000_DEV_ID_82545EM_COPPER 0x100F
273#define E1000_DEV_ID_82545EM_FIBER 0x1011
274#define E1000_DEV_ID_82545GM_COPPER 0x1026
275#define E1000_DEV_ID_82545GM_FIBER 0x1027
276#define E1000_DEV_ID_82545GM_SERDES 0x1028
277#define E1000_DEV_ID_82546EB_COPPER 0x1010
278#define E1000_DEV_ID_82546EB_FIBER 0x1012
279#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
280#define E1000_DEV_ID_82541EI 0x1013
281#define E1000_DEV_ID_82541EI_MOBILE 0x1018
282#define E1000_DEV_ID_82541ER 0x1078
283#define E1000_DEV_ID_82547GI 0x1075
284#define E1000_DEV_ID_82541GI 0x1076
285#define E1000_DEV_ID_82541GI_MOBILE 0x1077
286#define E1000_DEV_ID_82546GB_COPPER 0x1079
287#define E1000_DEV_ID_82546GB_FIBER 0x107A
288#define E1000_DEV_ID_82546GB_SERDES 0x107B
289#define E1000_DEV_ID_82547EI 0x1019
290#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
291
292#define NODE_ADDRESS_SIZE 6
293#define ETH_LENGTH_OF_ADDRESS 6
294
295/* MAC decode size is 128K - This is the size of BAR0 */
296#define MAC_DECODE_SIZE (128 * 1024)
297
298#define E1000_82542_2_0_REV_ID 2
299#define E1000_82542_2_1_REV_ID 3
300
301#define SPEED_10 10
302#define SPEED_100 100
303#define SPEED_1000 1000
304#define HALF_DUPLEX 1
305#define FULL_DUPLEX 2
306
307/* The sizes (in bytes) of a ethernet packet */
308#define ENET_HEADER_SIZE 14
309#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
310#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
311#define ETHERNET_FCS_SIZE 4
312#define MAXIMUM_ETHERNET_PACKET_SIZE \
313 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
314#define MINIMUM_ETHERNET_PACKET_SIZE \
315 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
316#define CRC_LENGTH ETHERNET_FCS_SIZE
317#define MAX_JUMBO_FRAME_SIZE 0x3F00
318
319
320/* 802.1q VLAN Packet Sizes */
321#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
322
323/* Ethertype field values */
324#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
325#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
326#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
327
328/* Packet Header defines */
329#define IP_PROTOCOL_TCP 6
330#define IP_PROTOCOL_UDP 0x11
331
332/* This defines the bits that are set in the Interrupt Mask
333 * Set/Read Register. Each bit is documented below:
334 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
335 * o RXSEQ = Receive Sequence Error
336 */
337#define POLL_IMS_ENABLE_MASK ( \
338 E1000_IMS_RXDMT0 | \
339 E1000_IMS_RXSEQ)
340
341/* This defines the bits that are set in the Interrupt Mask
342 * Set/Read Register. Each bit is documented below:
343 * o RXT0 = Receiver Timer Interrupt (ring 0)
344 * o TXDW = Transmit Descriptor Written Back
345 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
346 * o RXSEQ = Receive Sequence Error
347 * o LSC = Link Status Change
348 */
349#define IMS_ENABLE_MASK ( \
350 E1000_IMS_RXT0 | \
351 E1000_IMS_TXDW | \
352 E1000_IMS_RXDMT0 | \
353 E1000_IMS_RXSEQ | \
354 E1000_IMS_LSC)
355
356/* Number of high/low register pairs in the RAR. The RAR (Receive Address
357 * Registers) holds the directed and multicast addresses that we monitor. We
358 * reserve one of these spots for our directed address, allowing us room for
359 * E1000_RAR_ENTRIES - 1 multicast addresses.
360 */
361#define E1000_RAR_ENTRIES 15
362
363#define MIN_NUMBER_OF_DESCRIPTORS 8
364#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
365
366/* Receive Descriptor */
367struct e1000_rx_desc {
368 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
369 uint16_t length; /* Length of data DMAed into data buffer */
370 uint16_t csum; /* Packet checksum */
371 uint8_t status; /* Descriptor status */
372 uint8_t errors; /* Descriptor Errors */
373 uint16_t special;
374};
375
376/* Receive Decriptor bit definitions */
377#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
378#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
379#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
380#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
381#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
382#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
383#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
384#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
385#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
386#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
387#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
388#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
389#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
390#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
391#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
392#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
393#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
394#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
395#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
396
397/* mask to determine if packets should be dropped due to frame errors */
398#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
399 E1000_RXD_ERR_CE | \
400 E1000_RXD_ERR_SE | \
401 E1000_RXD_ERR_SEQ | \
402 E1000_RXD_ERR_CXE | \
403 E1000_RXD_ERR_RXE)
404
405/* Transmit Descriptor */
406struct e1000_tx_desc {
407 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
408 union {
409 uint32_t data;
410 struct {
411 uint16_t length; /* Data buffer length */
412 uint8_t cso; /* Checksum offset */
413 uint8_t cmd; /* Descriptor control */
414 } flags;
415 } lower;
416 union {
417 uint32_t data;
418 struct {
419 uint8_t status; /* Descriptor status */
420 uint8_t css; /* Checksum start */
421 uint16_t special;
422 } fields;
423 } upper;
424};
425
426/* Transmit Descriptor bit definitions */
427#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
428#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
429#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
430#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
431#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
432#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
433#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
434#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
435#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
436#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
437#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
438#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
439#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
440#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
441#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
442#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
443#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
444#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
445#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
446#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
447
448/* Offload Context Descriptor */
449struct e1000_context_desc {
450 union {
451 uint32_t ip_config;
452 struct {
453 uint8_t ipcss; /* IP checksum start */
454 uint8_t ipcso; /* IP checksum offset */
455 uint16_t ipcse; /* IP checksum end */
456 } ip_fields;
457 } lower_setup;
458 union {
459 uint32_t tcp_config;
460 struct {
461 uint8_t tucss; /* TCP checksum start */
462 uint8_t tucso; /* TCP checksum offset */
463 uint16_t tucse; /* TCP checksum end */
464 } tcp_fields;
465 } upper_setup;
466 uint32_t cmd_and_length; /* */
467 union {
468 uint32_t data;
469 struct {
470 uint8_t status; /* Descriptor status */
471 uint8_t hdr_len; /* Header length */
472 uint16_t mss; /* Maximum segment size */
473 } fields;
474 } tcp_seg_setup;
475};
476
477/* Offload data descriptor */
478struct e1000_data_desc {
479 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
480 union {
481 uint32_t data;
482 struct {
483 uint16_t length; /* Data buffer length */
484 uint8_t typ_len_ext; /* */
485 uint8_t cmd; /* */
486 } flags;
487 } lower;
488 union {
489 uint32_t data;
490 struct {
491 uint8_t status; /* Descriptor status */
492 uint8_t popts; /* Packet Options */
493 uint16_t special; /* */
494 } fields;
495 } upper;
496};
497
498/* Filters */
499#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
500#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
501#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
502
503
504/* Receive Address Register */
505struct e1000_rar {
506 volatile uint32_t low; /* receive address low */
507 volatile uint32_t high; /* receive address high */
508};
509
510/* Number of entries in the Multicast Table Array (MTA). */
511#define E1000_NUM_MTA_REGISTERS 128
512
513/* IPv4 Address Table Entry */
514struct e1000_ipv4_at_entry {
515 volatile uint32_t ipv4_addr; /* IP Address (RW) */
516 volatile uint32_t reserved;
517};
518
519/* Four wakeup IP addresses are supported */
520#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
521#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
522#define E1000_IP6AT_SIZE 1
523
524/* IPv6 Address Table Entry */
525struct e1000_ipv6_at_entry {
526 volatile uint8_t ipv6_addr[16];
527};
528
529/* Flexible Filter Length Table Entry */
530struct e1000_fflt_entry {
531 volatile uint32_t length; /* Flexible Filter Length (RW) */
532 volatile uint32_t reserved;
533};
534
535/* Flexible Filter Mask Table Entry */
536struct e1000_ffmt_entry {
537 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
538 volatile uint32_t reserved;
539};
540
541/* Flexible Filter Value Table Entry */
542struct e1000_ffvt_entry {
543 volatile uint32_t value; /* Flexible Filter Value (RW) */
544 volatile uint32_t reserved;
545};
546
547/* Four Flexible Filters are supported */
548#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
549
550/* Each Flexible Filter is at most 128 (0x80) bytes in length */
551#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
552
553#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
554#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
555#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
556
557/* Register Set. (82543, 82544)
558 *
559 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
560 * These registers are physically located on the NIC, but are mapped into the
561 * host memory address space.
562 *
563 * RW - register is both readable and writable
564 * RO - register is read only
565 * WO - register is write only
566 * R/clr - register is read only and is cleared when read
567 * A - register array
568 */
569#define E1000_CTRL 0x00000 /* Device Control - RW */
570#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
571#define E1000_STATUS 0x00008 /* Device Status - RO */
572#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
573#define E1000_EERD 0x00014 /* EEPROM Read - RW */
574#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
575#define E1000_FLA 0x0001C /* Flash Access - RW */
576#define E1000_MDIC 0x00020 /* MDI Control - RW */
577#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
578#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
579#define E1000_FCT 0x00030 /* Flow Control Type - RW */
580#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
581#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
582#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
583#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
584#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
585#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
586#define E1000_RCTL 0x00100 /* RX Control - RW */
587#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
588#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
589#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
590#define E1000_TCTL 0x00400 /* TX Control - RW */
591#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
592#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
593#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
594#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
595#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
596#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
597#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
598#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
599#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
600#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
601#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
602#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
603#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
604#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
605#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
606#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
607#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
608#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
609#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
610#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
611#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
612#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
613#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
614#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
615#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
616#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
617#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
618#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
619#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
620#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
621#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
622#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
623#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
624#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
625#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
626#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
627#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
628#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
629#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
630#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
631#define E1000_COLC 0x04028 /* Collision Count - R/clr */
632#define E1000_DC 0x04030 /* Defer Count - R/clr */
633#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
634#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
635#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
636#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
637#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
638#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
639#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
640#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
641#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
642#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
643#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
644#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
645#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
646#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
647#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
648#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
649#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
650#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
651#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
652#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
653#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
654#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
655#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
656#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
657#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
658#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
659#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
660#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
661#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
662#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
663#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
664#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
665#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
666#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
667#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
668#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
669#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
670#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
671#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
672#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
673#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
674#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
675#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
676#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
677#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
678#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
679#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
680#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
681#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
682#define E1000_RA 0x05400 /* Receive Address - RW Array */
683#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
684#define E1000_WUC 0x05800 /* Wakeup Control - RW */
685#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
686#define E1000_WUS 0x05810 /* Wakeup Status - RO */
687#define E1000_MANC 0x05820 /* Management Control - RW */
688#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
689#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
690#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
691#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
692#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
693#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
694#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
695#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
696#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
697
698/* Register Set (82542)
699 *
700 * Some of the 82542 registers are located at different offsets than they are
701 * in more current versions of the 8254x. Despite the difference in location,
702 * the registers function in the same manner.
703 */
704#define E1000_82542_CTRL E1000_CTRL
705#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
706#define E1000_82542_STATUS E1000_STATUS
707#define E1000_82542_EECD E1000_EECD
708#define E1000_82542_EERD E1000_EERD
709#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
710#define E1000_82542_FLA E1000_FLA
711#define E1000_82542_MDIC E1000_MDIC
712#define E1000_82542_FCAL E1000_FCAL
713#define E1000_82542_FCAH E1000_FCAH
714#define E1000_82542_FCT E1000_FCT
715#define E1000_82542_VET E1000_VET
716#define E1000_82542_RA 0x00040
717#define E1000_82542_ICR E1000_ICR
718#define E1000_82542_ITR E1000_ITR
719#define E1000_82542_ICS E1000_ICS
720#define E1000_82542_IMS E1000_IMS
721#define E1000_82542_IMC E1000_IMC
722#define E1000_82542_RCTL E1000_RCTL
723#define E1000_82542_RDTR 0x00108
724#define E1000_82542_RDBAL 0x00110
725#define E1000_82542_RDBAH 0x00114
726#define E1000_82542_RDLEN 0x00118
727#define E1000_82542_RDH 0x00120
728#define E1000_82542_RDT 0x00128
729#define E1000_82542_FCRTH 0x00160
730#define E1000_82542_FCRTL 0x00168
731#define E1000_82542_FCTTV E1000_FCTTV
732#define E1000_82542_TXCW E1000_TXCW
733#define E1000_82542_RXCW E1000_RXCW
734#define E1000_82542_MTA 0x00200
735#define E1000_82542_TCTL E1000_TCTL
736#define E1000_82542_TIPG E1000_TIPG
737#define E1000_82542_TDBAL 0x00420
738#define E1000_82542_TDBAH 0x00424
739#define E1000_82542_TDLEN 0x00428
740#define E1000_82542_TDH 0x00430
741#define E1000_82542_TDT 0x00438
742#define E1000_82542_TIDV 0x00440
743#define E1000_82542_TBT E1000_TBT
744#define E1000_82542_AIT E1000_AIT
745#define E1000_82542_VFTA 0x00600
746#define E1000_82542_LEDCTL E1000_LEDCTL
747#define E1000_82542_PBA E1000_PBA
748#define E1000_82542_RXDCTL E1000_RXDCTL
749#define E1000_82542_RADV E1000_RADV
750#define E1000_82542_RSRPD E1000_RSRPD
751#define E1000_82542_TXDMAC E1000_TXDMAC
752#define E1000_82542_TDFHS E1000_TDFHS
753#define E1000_82542_TDFTS E1000_TDFTS
754#define E1000_82542_TDFPC E1000_TDFPC
755#define E1000_82542_TXDCTL E1000_TXDCTL
756#define E1000_82542_TADV E1000_TADV
757#define E1000_82542_TSPMT E1000_TSPMT
758#define E1000_82542_CRCERRS E1000_CRCERRS
759#define E1000_82542_ALGNERRC E1000_ALGNERRC
760#define E1000_82542_SYMERRS E1000_SYMERRS
761#define E1000_82542_RXERRC E1000_RXERRC
762#define E1000_82542_MPC E1000_MPC
763#define E1000_82542_SCC E1000_SCC
764#define E1000_82542_ECOL E1000_ECOL
765#define E1000_82542_MCC E1000_MCC
766#define E1000_82542_LATECOL E1000_LATECOL
767#define E1000_82542_COLC E1000_COLC
768#define E1000_82542_DC E1000_DC
769#define E1000_82542_TNCRS E1000_TNCRS
770#define E1000_82542_SEC E1000_SEC
771#define E1000_82542_CEXTERR E1000_CEXTERR
772#define E1000_82542_RLEC E1000_RLEC
773#define E1000_82542_XONRXC E1000_XONRXC
774#define E1000_82542_XONTXC E1000_XONTXC
775#define E1000_82542_XOFFRXC E1000_XOFFRXC
776#define E1000_82542_XOFFTXC E1000_XOFFTXC
777#define E1000_82542_FCRUC E1000_FCRUC
778#define E1000_82542_PRC64 E1000_PRC64
779#define E1000_82542_PRC127 E1000_PRC127
780#define E1000_82542_PRC255 E1000_PRC255
781#define E1000_82542_PRC511 E1000_PRC511
782#define E1000_82542_PRC1023 E1000_PRC1023
783#define E1000_82542_PRC1522 E1000_PRC1522
784#define E1000_82542_GPRC E1000_GPRC
785#define E1000_82542_BPRC E1000_BPRC
786#define E1000_82542_MPRC E1000_MPRC
787#define E1000_82542_GPTC E1000_GPTC
788#define E1000_82542_GORCL E1000_GORCL
789#define E1000_82542_GORCH E1000_GORCH
790#define E1000_82542_GOTCL E1000_GOTCL
791#define E1000_82542_GOTCH E1000_GOTCH
792#define E1000_82542_RNBC E1000_RNBC
793#define E1000_82542_RUC E1000_RUC
794#define E1000_82542_RFC E1000_RFC
795#define E1000_82542_ROC E1000_ROC
796#define E1000_82542_RJC E1000_RJC
797#define E1000_82542_MGTPRC E1000_MGTPRC
798#define E1000_82542_MGTPDC E1000_MGTPDC
799#define E1000_82542_MGTPTC E1000_MGTPTC
800#define E1000_82542_TORL E1000_TORL
801#define E1000_82542_TORH E1000_TORH
802#define E1000_82542_TOTL E1000_TOTL
803#define E1000_82542_TOTH E1000_TOTH
804#define E1000_82542_TPR E1000_TPR
805#define E1000_82542_TPT E1000_TPT
806#define E1000_82542_PTC64 E1000_PTC64
807#define E1000_82542_PTC127 E1000_PTC127
808#define E1000_82542_PTC255 E1000_PTC255
809#define E1000_82542_PTC511 E1000_PTC511
810#define E1000_82542_PTC1023 E1000_PTC1023
811#define E1000_82542_PTC1522 E1000_PTC1522
812#define E1000_82542_MPTC E1000_MPTC
813#define E1000_82542_BPTC E1000_BPTC
814#define E1000_82542_TSCTC E1000_TSCTC
815#define E1000_82542_TSCTFC E1000_TSCTFC
816#define E1000_82542_RXCSUM E1000_RXCSUM
817#define E1000_82542_WUC E1000_WUC
818#define E1000_82542_WUFC E1000_WUFC
819#define E1000_82542_WUS E1000_WUS
820#define E1000_82542_MANC E1000_MANC
821#define E1000_82542_IPAV E1000_IPAV
822#define E1000_82542_IP4AT E1000_IP4AT
823#define E1000_82542_IP6AT E1000_IP6AT
824#define E1000_82542_WUPL E1000_WUPL
825#define E1000_82542_WUPM E1000_WUPM
826#define E1000_82542_FFLT E1000_FFLT
827#define E1000_82542_TDFH 0x08010
828#define E1000_82542_TDFT 0x08018
829#define E1000_82542_FFMT E1000_FFMT
830#define E1000_82542_FFVT E1000_FFVT
831#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
832
833/* Statistics counters collected by the MAC */
834struct e1000_hw_stats {
835 uint64_t crcerrs;
836 uint64_t algnerrc;
837 uint64_t symerrs;
838 uint64_t rxerrc;
839 uint64_t mpc;
840 uint64_t scc;
841 uint64_t ecol;
842 uint64_t mcc;
843 uint64_t latecol;
844 uint64_t colc;
845 uint64_t dc;
846 uint64_t tncrs;
847 uint64_t sec;
848 uint64_t cexterr;
849 uint64_t rlec;
850 uint64_t xonrxc;
851 uint64_t xontxc;
852 uint64_t xoffrxc;
853 uint64_t xofftxc;
854 uint64_t fcruc;
855 uint64_t prc64;
856 uint64_t prc127;
857 uint64_t prc255;
858 uint64_t prc511;
859 uint64_t prc1023;
860 uint64_t prc1522;
861 uint64_t gprc;
862 uint64_t bprc;
863 uint64_t mprc;
864 uint64_t gptc;
865 uint64_t gorcl;
866 uint64_t gorch;
867 uint64_t gotcl;
868 uint64_t gotch;
869 uint64_t rnbc;
870 uint64_t ruc;
871 uint64_t rfc;
872 uint64_t roc;
873 uint64_t rjc;
874 uint64_t mgprc;
875 uint64_t mgpdc;
876 uint64_t mgptc;
877 uint64_t torl;
878 uint64_t torh;
879 uint64_t totl;
880 uint64_t toth;
881 uint64_t tpr;
882 uint64_t tpt;
883 uint64_t ptc64;
884 uint64_t ptc127;
885 uint64_t ptc255;
886 uint64_t ptc511;
887 uint64_t ptc1023;
888 uint64_t ptc1522;
889 uint64_t mptc;
890 uint64_t bptc;
891 uint64_t tsctc;
892 uint64_t tsctfc;
893};
894
895/* Structure containing variables used by the shared code (e1000_hw.c) */
896struct e1000_hw {
897 struct pci_device *pdev;
898 uint8_t *hw_addr;
899 e1000_mac_type mac_type;
900 e1000_phy_type phy_type;
901#if 0
902 uint32_t phy_init_script;
903#endif
904 e1000_media_type media_type;
905 e1000_fc_type fc;
906#if 0
907 e1000_bus_speed bus_speed;
908 e1000_bus_width bus_width;
909 e1000_bus_type bus_type;
910#endif
911 struct e1000_eeprom_info eeprom;
912#if 0
913 e1000_ms_type master_slave;
914 e1000_ms_type original_master_slave;
915 e1000_ffe_config ffe_config_state;
916#endif
917 uint32_t io_base;
918 uint32_t phy_id;
919#ifdef LINUX_DRIVER
920 uint32_t phy_revision;
921#endif
922 uint32_t phy_addr;
923#if 0
924 uint32_t original_fc;
925#endif
926 uint32_t txcw;
927 uint32_t autoneg_failed;
928#if 0
929 uint32_t max_frame_size;
930 uint32_t min_frame_size;
931 uint32_t mc_filter_type;
932 uint32_t num_mc_addrs;
933 uint32_t collision_delta;
934 uint32_t tx_packet_delta;
935 uint32_t ledctl_default;
936 uint32_t ledctl_mode1;
937 uint32_t ledctl_mode2;
938 uint16_t phy_spd_default;
939#endif
940 uint16_t autoneg_advertised;
941 uint16_t pci_cmd_word;
942#if 0
943 uint16_t fc_high_water;
944 uint16_t fc_low_water;
945 uint16_t fc_pause_time;
946 uint16_t current_ifs_val;
947 uint16_t ifs_min_val;
948 uint16_t ifs_max_val;
949 uint16_t ifs_step_size;
950 uint16_t ifs_ratio;
951#endif
952 uint16_t device_id;
953 uint16_t vendor_id;
954#if 0
955 uint16_t subsystem_id;
956 uint16_t subsystem_vendor_id;
957#endif
958 uint8_t revision_id;
959#if 0
960 uint8_t autoneg;
961 uint8_t mdix;
962 uint8_t forced_speed_duplex;
963 uint8_t wait_autoneg_complete;
964 uint8_t dma_fairness;
965#endif
966 uint8_t mac_addr[NODE_ADDRESS_SIZE];
967#if 0
968 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
969 boolean_t disable_polarity_correction;
970 boolean_t speed_downgraded;
971 e1000_dsp_config dsp_config_state;
972 boolean_t get_link_status;
973 boolean_t serdes_link_down;
974#endif
975 boolean_t tbi_compatibility_en;
976 boolean_t tbi_compatibility_on;
977#if 0
978 boolean_t phy_reset_disable;
979 boolean_t fc_send_xon;
980 boolean_t fc_strict_ieee;
981 boolean_t report_tx_early;
982 boolean_t adaptive_ifs;
983 boolean_t ifs_params_forced;
984 boolean_t in_ifs_mode;
985#endif
986};
987
988
989#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
990#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
991
992/* Register Bit Masks */
993/* Device Control */
994#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
995#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
996#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
997#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
998#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
999#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1000#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1001#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1002#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1003#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1004#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1005#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1006#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1007#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1008#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1009#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1010#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1011#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1012#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1013#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1014#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1015#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1016#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1017#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1018#define E1000_CTRL_RST 0x04000000 /* Global reset */
1019#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1020#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1021#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1022#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1023#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1024
1025/* Device Status */
1026#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1027#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1028#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1029#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1030#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1031#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1032#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1033#define E1000_STATUS_SPEED_MASK 0x000000C0
1034#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1035#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1036#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1037#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1038#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1039#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1040#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1041#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1042#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1043
1044/* Constants used to intrepret the masked PCI-X bus speed. */
1045#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1046#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1047#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1048
1049/* EEPROM/Flash Control */
1050#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1051#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1052#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1053#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1054#define E1000_EECD_FWE_MASK 0x00000030
1055#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1056#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1057#define E1000_EECD_FWE_SHIFT 4
1058#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1059#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1060#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1061#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1062#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1063 * (0-small, 1-large) */
1064#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1065#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1066#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1067#endif
1068#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1069
1070/* EEPROM Read */
1071#define E1000_EERD_START 0x00000001 /* Start Read */
1072#define E1000_EERD_DONE 0x00000010 /* Read Done */
1073#define E1000_EERD_ADDR_SHIFT 8
1074#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1075#define E1000_EERD_DATA_SHIFT 16
1076#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1077
1078/* SPI EEPROM Status Register */
1079#define EEPROM_STATUS_RDY_SPI 0x01
1080#define EEPROM_STATUS_WEN_SPI 0x02
1081#define EEPROM_STATUS_BP0_SPI 0x04
1082#define EEPROM_STATUS_BP1_SPI 0x08
1083#define EEPROM_STATUS_WPEN_SPI 0x80
1084
1085/* Extended Device Control */
1086#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1087#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1088#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1089#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1090#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1091#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1092#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1093#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1094#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1095#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1096#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1097#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1098#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1099#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1100#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1101#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1102#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1103#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1104#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1105#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1106#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1107#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1108#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1109#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1110#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1111#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1112
1113/* MDI Control */
1114#define E1000_MDIC_DATA_MASK 0x0000FFFF
1115#define E1000_MDIC_REG_MASK 0x001F0000
1116#define E1000_MDIC_REG_SHIFT 16
1117#define E1000_MDIC_PHY_MASK 0x03E00000
1118#define E1000_MDIC_PHY_SHIFT 21
1119#define E1000_MDIC_OP_WRITE 0x04000000
1120#define E1000_MDIC_OP_READ 0x08000000
1121#define E1000_MDIC_READY 0x10000000
1122#define E1000_MDIC_INT_EN 0x20000000
1123#define E1000_MDIC_ERROR 0x40000000
1124
1125/* LED Control */
1126#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1127#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1128#define E1000_LEDCTL_LED0_IVRT 0x00000040
1129#define E1000_LEDCTL_LED0_BLINK 0x00000080
1130#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1131#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1132#define E1000_LEDCTL_LED1_IVRT 0x00004000
1133#define E1000_LEDCTL_LED1_BLINK 0x00008000
1134#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1135#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1136#define E1000_LEDCTL_LED2_IVRT 0x00400000
1137#define E1000_LEDCTL_LED2_BLINK 0x00800000
1138#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1139#define E1000_LEDCTL_LED3_MODE_SHIFT 24
1140#define E1000_LEDCTL_LED3_IVRT 0x40000000
1141#define E1000_LEDCTL_LED3_BLINK 0x80000000
1142
1143#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1144#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1145#define E1000_LEDCTL_MODE_LINK_UP 0x2
1146#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1147#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1148#define E1000_LEDCTL_MODE_LINK_10 0x5
1149#define E1000_LEDCTL_MODE_LINK_100 0x6
1150#define E1000_LEDCTL_MODE_LINK_1000 0x7
1151#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1152#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1153#define E1000_LEDCTL_MODE_COLLISION 0xA
1154#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1155#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1156#define E1000_LEDCTL_MODE_PAUSED 0xD
1157#define E1000_LEDCTL_MODE_LED_ON 0xE
1158#define E1000_LEDCTL_MODE_LED_OFF 0xF
1159
1160/* Receive Address */
1161#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1162
1163/* Interrupt Cause Read */
1164#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1165#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1166#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1167#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1168#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1169#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1170#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1171#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1172#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1173#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1174#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1175#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1176#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1177#define E1000_ICR_TXD_LOW 0x00008000
1178#define E1000_ICR_SRPD 0x00010000
1179
1180/* Interrupt Cause Set */
1181#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1182#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1183#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1184#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1185#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1186#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1187#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1188#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1189#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1190#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1191#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1192#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1193#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1194#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1195#define E1000_ICS_SRPD E1000_ICR_SRPD
1196
1197/* Interrupt Mask Set */
1198#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1199#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1200#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1201#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1202#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1203#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1204#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1205#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1206#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1207#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1208#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1209#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1210#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1211#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1212#define E1000_IMS_SRPD E1000_ICR_SRPD
1213
1214/* Interrupt Mask Clear */
1215#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1216#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1217#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1218#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1219#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1220#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1221#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1222#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1223#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1224#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1225#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1226#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1227#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1228#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1229#define E1000_IMC_SRPD E1000_ICR_SRPD
1230
1231/* Receive Control */
1232#define E1000_RCTL_RST 0x00000001 /* Software reset */
1233#define E1000_RCTL_EN 0x00000002 /* enable */
1234#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1235#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1236#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1237#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1238#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1239#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1240#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1241#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1242#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1243#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1244#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1245#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1246#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1247#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1248#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1249#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1250#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1251#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1252/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1253#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1254#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1255#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1256#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1257/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1258#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1259#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1260#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1261#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1262#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1263#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1264#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1265#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1266#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1267
1268/* Receive Descriptor */
1269#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1270#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1271#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1272#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1273#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1274
1275/* Flow Control */
1276#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1277#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1278#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1279#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1280
1281/* Receive Descriptor Control */
1282#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1283#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1284#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1285#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1286
1287/* Transmit Descriptor Control */
1288#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1289#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1290#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1291#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1292#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1293#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1294#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.still to be processed. */
1295
1296/* Transmit Configuration Word */
1297#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1298#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1299#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1300#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1301#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1302#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1303#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1304#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1305#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1306#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1307
1308/* Receive Configuration Word */
1309#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1310#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1311#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1312#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1313#define E1000_RXCW_C 0x20000000 /* Receive config */
1314#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1315#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1316
1317/* Transmit Control */
1318#define E1000_TCTL_RST 0x00000001 /* software reset */
1319#define E1000_TCTL_EN 0x00000002 /* enable tx */
1320#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1321#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1322#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1323#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1324#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1325#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1326#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1327#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1328
1329/* Receive Checksum Control */
1330#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1331#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1332#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1333#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1334
1335/* Definitions for power management and wakeup registers */
1336/* Wake Up Control */
1337#define E1000_WUC_APME 0x00000001 /* APM Enable */
1338#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1339#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1340#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1341#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1342
1343/* Wake Up Filter Control */
1344#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1345#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1346#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1347#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1348#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1349#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1350#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1351#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1352#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1353#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1354#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1355#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1356#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1357#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1358#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1359
1360/* Wake Up Status */
1361#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1362#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1363#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1364#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1365#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1366#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1367#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1368#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1369#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1370#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1371#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1372#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1373#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1374
1375/* Management Control */
1376#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1377#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1378#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1379#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1380#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1381#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1382#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1383#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1384#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1385#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1386 * Filtering */
1387#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1388#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1389#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1390#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1391#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1392#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1393#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1394#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1395#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1396
1397#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1398#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1399
1400/* Wake Up Packet Length */
1401#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1402
1403#define E1000_MDALIGN 4096
1404
1405#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1406#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1407#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1408#define E1000_KUMCTRLSTA_REN 0x00200000
1409
1410#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1411#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1412#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1413#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1414#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1415#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1416#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1417#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1418#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1419
1420/* FIFO Control */
1421#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1422#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1423
1424/* In-Band Control */
1425#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1426
1427/* Half-Duplex Control */
1428#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1429#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1430
1431/* EEPROM Commands - Microwire */
1432#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1433#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
1434#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
1435#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
1436#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
1437
1438/* EEPROM Commands - SPI */
1439#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1440#define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */
1441#define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */
1442#define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */
1443#define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */
1444#define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */
1445#define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */
1446#define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */
1447
1448/* EEPROM Size definitions */
1449#define EEPROM_SIZE_16KB 0x1800
1450#define EEPROM_SIZE_8KB 0x1400
1451#define EEPROM_SIZE_4KB 0x1000
1452#define EEPROM_SIZE_2KB 0x0C00
1453#define EEPROM_SIZE_1KB 0x0800
1454#define EEPROM_SIZE_512B 0x0400
1455#define EEPROM_SIZE_128B 0x0000
1456#define EEPROM_SIZE_MASK 0x1C00
1457
1458/* EEPROM Word Offsets */
1459#define EEPROM_COMPAT 0x0003
1460#define EEPROM_ID_LED_SETTINGS 0x0004
1461#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
1462#define EEPROM_INIT_CONTROL1_REG 0x000A
1463#define EEPROM_INIT_CONTROL2_REG 0x000F
1464#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
1465#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
1466#define EEPROM_CFG 0x0012
1467#define EEPROM_FLASH_VERSION 0x0032
1468#define EEPROM_CHECKSUM_REG 0x003F
1469
1470/* Word definitions for ID LED Settings */
1471#define ID_LED_RESERVED_0000 0x0000
1472#define ID_LED_RESERVED_FFFF 0xFFFF
1473#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1474 (ID_LED_OFF1_OFF2 << 8) | \
1475 (ID_LED_DEF1_DEF2 << 4) | \
1476 (ID_LED_DEF1_DEF2))
1477#define ID_LED_DEF1_DEF2 0x1
1478#define ID_LED_DEF1_ON2 0x2
1479#define ID_LED_DEF1_OFF2 0x3
1480#define ID_LED_ON1_DEF2 0x4
1481#define ID_LED_ON1_ON2 0x5
1482#define ID_LED_ON1_OFF2 0x6
1483#define ID_LED_OFF1_DEF2 0x7
1484#define ID_LED_OFF1_ON2 0x8
1485#define ID_LED_OFF1_OFF2 0x9
1486
1487#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1488#define IGP_ACTIVITY_LED_ENABLE 0x0300
1489#define IGP_LED3_MODE 0x07000000
1490
1491
1492/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
1493#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
1494
1495/* Mask bits for fields in Word 0x0a of the EEPROM */
1496#define EEPROM_WORD0A_ILOS 0x0010
1497#define EEPROM_WORD0A_SWDPIO 0x01E0
1498#define EEPROM_WORD0A_LRST 0x0200
1499#define EEPROM_WORD0A_FD 0x0400
1500#define EEPROM_WORD0A_66MHZ 0x0800
1501
1502/* Mask bits for fields in Word 0x0f of the EEPROM */
1503#define EEPROM_WORD0F_PAUSE_MASK 0x3000
1504#define EEPROM_WORD0F_PAUSE 0x1000
1505#define EEPROM_WORD0F_ASM_DIR 0x2000
1506#define EEPROM_WORD0F_ANE 0x0800
1507#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1508
1509/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1510#define EEPROM_SUM 0xBABA
1511
1512/* EEPROM Map defines (WORD OFFSETS)*/
1513#define EEPROM_NODE_ADDRESS_BYTE_0 0
1514#define EEPROM_PBA_BYTE_1 8
1515
1516#define EEPROM_RESERVED_WORD 0xFFFF
1517
1518/* EEPROM Map Sizes (Byte Counts) */
1519#define PBA_SIZE 4
1520
1521/* Collision related configuration parameters */
1522#define E1000_COLLISION_THRESHOLD 16
1523#define E1000_CT_SHIFT 4
1524#define E1000_COLLISION_DISTANCE 64
1525#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1526#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1527#define E1000_COLD_SHIFT 12
1528
1529/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1530#define REQ_TX_DESCRIPTOR_MULTIPLE 8
1531#define REQ_RX_DESCRIPTOR_MULTIPLE 8
1532
1533/* Default values for the transmit IPG register */
1534#define DEFAULT_82542_TIPG_IPGT 10
1535#define DEFAULT_82543_TIPG_IPGT_FIBER 9
1536#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1537
1538#define E1000_TIPG_IPGT_MASK 0x000003FF
1539#define E1000_TIPG_IPGR1_MASK 0x000FFC00
1540#define E1000_TIPG_IPGR2_MASK 0x3FF00000
1541
1542#define DEFAULT_82542_TIPG_IPGR1 2
1543#define DEFAULT_82543_TIPG_IPGR1 8
1544#define E1000_TIPG_IPGR1_SHIFT 10
1545
1546#define DEFAULT_82542_TIPG_IPGR2 10
1547#define DEFAULT_82543_TIPG_IPGR2 6
1548#define E1000_TIPG_IPGR2_SHIFT 20
1549
1550#define E1000_TXDMAC_DPP 0x00000001
1551
1552/* Adaptive IFS defines */
1553#define TX_THRESHOLD_START 8
1554#define TX_THRESHOLD_INCREMENT 10
1555#define TX_THRESHOLD_DECREMENT 1
1556#define TX_THRESHOLD_STOP 190
1557#define TX_THRESHOLD_DISABLE 0
1558#define TX_THRESHOLD_TIMER_MS 10000
1559#define MIN_NUM_XMITS 1000
1560#define IFS_MAX 80
1561#define IFS_STEP 10
1562#define IFS_MIN 40
1563#define IFS_RATIO 4
1564
1565/* PBA constants */
1566#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1567#define E1000_PBA_22K 0x0016
1568#define E1000_PBA_24K 0x0018
1569#define E1000_PBA_30K 0x001E
1570#define E1000_PBA_38K 0x0026
1571#define E1000_PBA_40K 0x0028
1572#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1573
1574/* Flow Control Constants */
1575#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1576#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1577#define FLOW_CONTROL_TYPE 0x8808
1578
1579/* The historical defaults for the flow control values are given below. */
1580#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
1581#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
1582#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
1583
1584/* PCIX Config space */
1585#define PCIX_COMMAND_REGISTER 0xE6
1586#define PCIX_STATUS_REGISTER_LO 0xE8
1587#define PCIX_STATUS_REGISTER_HI 0xEA
1588
1589#define PCIX_COMMAND_MMRBC_MASK 0x000C
1590#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1591#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1592#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1593#define PCIX_STATUS_HI_MMRBC_4K 0x3
1594#define PCIX_STATUS_HI_MMRBC_2K 0x2
1595
1596
1597/* Number of bits required to shift right the "pause" bits from the
1598 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
1599 */
1600#define PAUSE_SHIFT 5
1601
1602/* Number of bits required to shift left the "SWDPIO" bits from the
1603 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
1604 */
1605#define SWDPIO_SHIFT 17
1606
1607/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
1608 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
1609 */
1610#define SWDPIO__EXT_SHIFT 4
1611
1612/* Number of bits required to shift left the "ILOS" bit from the EEPROM
1613 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
1614 */
1615#define ILOS_SHIFT 3
1616
1617
1618#define RECEIVE_BUFFER_ALIGN_SIZE (256)
1619
1620/* Number of milliseconds we wait for auto-negotiation to complete */
1621#define LINK_UP_TIMEOUT 500
1622
1623#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1624
1625/* The carrier extension symbol, as received by the NIC. */
1626#define CARRIER_EXTENSION 0x0F
1627
1628/* TBI_ACCEPT macro definition:
1629 *
1630 * This macro requires:
1631 * adapter = a pointer to struct e1000_hw
1632 * status = the 8 bit status field of the RX descriptor with EOP set
1633 * error = the 8 bit error field of the RX descriptor with EOP set
1634 * length = the sum of all the length fields of the RX descriptors that
1635 * make up the current frame
1636 * last_byte = the last byte of the frame DMAed by the hardware
1637 * max_frame_length = the maximum frame length we want to accept.
1638 * min_frame_length = the minimum frame length we want to accept.
1639 *
1640 * This macro is a conditional that should be used in the interrupt
1641 * handler's Rx processing routine when RxErrors have been detected.
1642 *
1643 * Typical use:
1644 * ...
1645 * if (TBI_ACCEPT) {
1646 * accept_frame = TRUE;
1647 * e1000_tbi_adjust_stats(adapter, MacAddress);
1648 * frame_length--;
1649 * } else {
1650 * accept_frame = FALSE;
1651 * }
1652 * ...
1653 */
1654
1655#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1656 ((adapter)->tbi_compatibility_on && \
1657 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1658 ((last_byte) == CARRIER_EXTENSION) && \
1659 (((status) & E1000_RXD_STAT_VP) ? \
1660 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1661 ((length) <= ((adapter)->max_frame_size + 1))) : \
1662 (((length) > (adapter)->min_frame_size) && \
1663 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1664
1665
1666/* Structures, enums, and macros for the PHY */
1667
1668/* Bit definitions for the Management Data IO (MDIO) and Management Data
1669 * Clock (MDC) pins in the Device Control Register.
1670 */
1671#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1672#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1673#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1674#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1675#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1676#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1677#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1678#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
1679
1680/* PHY 1000 MII Register/Bit Definitions */
1681/* PHY Registers defined by IEEE */
1682#define PHY_CTRL 0x00 /* Control Register */
1683#define PHY_STATUS 0x01 /* Status Regiser */
1684#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1685#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1686#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1687#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1688#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1689#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1690#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1691#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1692#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1693#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1694
1695/* M88E1000 Specific Registers */
1696#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1697#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1698#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1699#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1700#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1701#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1702
1703#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1704#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
1705#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1706#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1707#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1708
1709#define IGP01E1000_IEEE_REGS_PAGE 0x0000
1710#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
1711#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
1712
1713/* IGP01E1000 Specific Registers */
1714#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
1715#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
1716#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
1717#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1718#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
1719#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
1720#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
1721
1722/* IGP01E1000 AGC Registers - stores the cable length values*/
1723#define IGP01E1000_PHY_AGC_A 0x1172
1724#define IGP01E1000_PHY_AGC_B 0x1272
1725#define IGP01E1000_PHY_AGC_C 0x1472
1726#define IGP01E1000_PHY_AGC_D 0x1872
1727
1728/* IGP01E1000 DSP Reset Register */
1729#define IGP01E1000_PHY_DSP_RESET 0x1F33
1730#define IGP01E1000_PHY_DSP_SET 0x1F71
1731#define IGP01E1000_PHY_DSP_FFE 0x1F35
1732
1733#define IGP01E1000_PHY_CHANNEL_NUM 4
1734#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
1735#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
1736#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
1737#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
1738
1739#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
1740#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
1741
1742#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
1743#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
1744#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
1745#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
1746
1747#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
1748/* IGP01E1000 PCS Initialization register - stores the polarity status when
1749 * speed = 1000 Mbps. */
1750#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
1751#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
1752
1753#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
1754
1755#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1756#define MAX_PHY_MULTI_PAGE_REG 0xF /*Registers that are equal on all pages*/
1757/* PHY Control Register */
1758#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1759#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1760#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1761#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1762#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1763#define MII_CR_POWER_DOWN 0x0800 /* Power down */
1764#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1765#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1766#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1767#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1768
1769/* PHY Status Register */
1770#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1771#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1772#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1773#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1774#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1775#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1776#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1777#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1778#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1779#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1780#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1781#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1782#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1783#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1784#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1785
1786/* Autoneg Advertisement Register */
1787#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1788#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1789#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1790#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1791#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1792#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1793#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1794#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1795#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1796#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1797
1798/* Link Partner Ability Register (Base Page) */
1799#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1800#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
1801#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
1802#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
1803#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
1804#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1805#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1806#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
1807#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
1808#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
1809#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1810
1811/* Autoneg Expansion Register */
1812#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1813#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
1814#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
1815#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1816#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
1817
1818/* Next Page TX Register */
1819#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1820#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
1821 * of different NP
1822 */
1823#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1824 * 0 = cannot comply with msg
1825 */
1826#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1827#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1828 * 0 = sending last NP
1829 */
1830
1831/* Link Partner Next Page Register */
1832#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1833#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
1834 * of different NP
1835 */
1836#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1837 * 0 = cannot comply with msg
1838 */
1839#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1840#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
1841#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1842 * 0 = sending last NP
1843 */
1844
1845/* 1000BASE-T Control Register */
1846#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1847#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1848#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1849#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
1850 /* 0=DTE device */
1851#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
1852 /* 0=Configure PHY as Slave */
1853#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
1854 /* 0=Automatic Master/Slave config */
1855#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1856#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1857#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1858#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1859#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1860
1861/* 1000BASE-T Status Register */
1862#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1863#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1864#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1865#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1866#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1867#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1868#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
1869#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1870#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
1871#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
1872#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1873#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
1874#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
1875
1876/* Extended Status Register */
1877#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
1878#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
1879#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
1880#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
1881
1882#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
1883#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
1884
1885#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
1886 /* (0=enable, 1=disable) */
1887
1888/* M88E1000 PHY Specific Control Register */
1889#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1890#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1891#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1892#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
1893 * 0=CLK125 toggling
1894 */
1895#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1896 /* Manual MDI configuration */
1897#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1898#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
1899 * 100BASE-TX/10BASE-T:
1900 * MDI Mode
1901 */
1902#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
1903 * all speeds.
1904 */
1905#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
1906 /* 1=Enable Extended 10BASE-T distance
1907 * (Lower 10BASE-T RX Threshold)
1908 * 0=Normal 10BASE-T RX Threshold */
1909#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1910 /* 1=5-Bit interface in 100BASE-TX
1911 * 0=MII interface in 100BASE-TX */
1912#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1913#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1914#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1915
1916#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
1917#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
1918#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1919
1920/* M88E1000 PHY Specific Status Register */
1921#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1922#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1923#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1924#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1925#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
1926 * 3=110-140M;4=>140M */
1927#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1928#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1929#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1930#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1931#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1932#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1933#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1934#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1935
1936#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
1937#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
1938#define M88E1000_PSSR_MDIX_SHIFT 6
1939#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1940
1941/* M88E1000 Extended PHY Specific Control Register */
1942#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1943#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
1944 * Will assert lost lock and bring
1945 * link down if idle not seen
1946 * within 1ms in 1000BASE-T
1947 */
1948/* Number of times we will attempt to autonegotiate before downshifting if we
1949 * are the master */
1950#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1951#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1952#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1953#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1954#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1955/* Number of times we will attempt to autonegotiate before downshifting if we
1956 * are the slave */
1957#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1958#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1959#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1960#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1961#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1962#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1963#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1964#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1965
1966/* IGP01E1000 Specific Port Config Register - R/W */
1967#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
1968#define IGP01E1000_PSCFR_PRE_EN 0x0020
1969#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
1970#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
1971#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
1972#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
1973
1974/* IGP01E1000 Specific Port Status Register - R/O */
1975#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
1976#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
1977#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
1978#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
1979#define IGP01E1000_PSSR_LINK_UP 0x0400
1980#define IGP01E1000_PSSR_MDIX 0x0800
1981#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
1982#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
1983#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
1984#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
1985#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
1986#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
1987
1988/* IGP01E1000 Specific Port Control Register - R/W */
1989#define IGP01E1000_PSCR_TP_LOOPBACK 0x0001
1990#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
1991#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
1992#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
1993#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
1994#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
1995
1996/* IGP01E1000 Specific Port Link Health Register */
1997#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
1998#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
1999#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2000#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2001#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2002#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2003#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0010
2004#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0008
2005#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0004
2006#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0002
2007#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0001
2008#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0000
2009
2010/* IGP01E1000 Channel Quality Register */
2011#define IGP01E1000_MSE_CHANNEL_D 0x000F
2012#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2013#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2014#define IGP01E1000_MSE_CHANNEL_A 0xF000
2015
2016/* IGP01E1000 DSP reset macros */
2017#define DSP_RESET_ENABLE 0x0
2018#define DSP_RESET_DISABLE 0x2
2019#define E1000_MAX_DSP_RESETS 10
2020
2021/* IGP01E1000 AGC Registers */
2022
2023#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2024
2025/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2026#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2027
2028/* The precision of the length is +/- 10 meters */
2029#define IGP01E1000_AGC_RANGE 10
2030
2031/* IGP01E1000 PCS Initialization register */
2032/* bits 3:6 in the PCS registers stores the channels polarity */
2033#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2034
2035/* IGP01E1000 GMII FIFO Register */
2036#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2037 * on Link-Up */
2038#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2039
2040/* IGP01E1000 Analog Register */
2041#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2042#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2043#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2044#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2045
2046#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2047#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2048#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2049#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2050#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2051
2052#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2053#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2054#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2055#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2056
2057
2058/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
2059#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */
2060#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
2061#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */
2062#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
2063#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */
2064#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */
2065#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */
2066
2067/* PHY Specific Control Register 2 (Page 0, Register 26) */
2068#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */
2069#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
2070#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
2071#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
2072
2073/* MAC Specific Control Register (Page 2, Register 21) */
2074/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
2075#define GG82563_MSCR_TX_CLK_MASK 0x0007
2076#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
2077#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
2078#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
2079#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
2080#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
2081
2082/* Kumeran Mode Control Register (Page 193, Register 16) */
2083#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
2084#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
2085#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
2086
2087/* Power Management Control Register (Page 193, Register 20) */
2088#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */
2089#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
2090
2091/* In-Band Control Register (Page 194, Register 18) */
2092#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
2093
2094/* Bit definitions for valid PHY IDs. */
2095#define M88E1000_E_PHY_ID 0x01410C50
2096#define M88E1000_I_PHY_ID 0x01410C30
2097#define M88E1011_I_PHY_ID 0x01410C20
2098#define IGP01E1000_I_PHY_ID 0x02A80380
2099#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2100#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2101#define M88E1011_I_REV_4 0x04
2102#define GG82563_E_PHY_ID 0x01410CA0
2103
2104/* Miscellaneous PHY bit definitions. */
2105#define PHY_PREAMBLE 0xFFFFFFFF
2106#define PHY_SOF 0x01
2107#define PHY_OP_READ 0x02
2108#define PHY_OP_WRITE 0x01
2109#define PHY_TURNAROUND 0x02
2110#define PHY_PREAMBLE_SIZE 32
2111#define MII_CR_SPEED_1000 0x0040
2112#define MII_CR_SPEED_100 0x2000
2113#define MII_CR_SPEED_10 0x0000
2114#define E1000_PHY_ADDRESS 0x01
2115#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2116#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
2117#define PHY_REVISION_MASK 0xFFFFFFF0
2118#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
2119#define REG4_SPEED_MASK 0x01E0
2120#define REG9_SPEED_MASK 0x0300
2121#define ADVERTISE_10_HALF 0x0001
2122#define ADVERTISE_10_FULL 0x0002
2123#define ADVERTISE_100_HALF 0x0004
2124#define ADVERTISE_100_FULL 0x0008
2125#define ADVERTISE_1000_HALF 0x0010
2126#define ADVERTISE_1000_FULL 0x0020
2127#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2128#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
2129#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
2130
2131#define GG82563_PAGE_SHIFT 5
2132#define GG82563_REG(page, reg) \
2133 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2134#define GG82563_MIN_ALT_REG 30
2135
2136/* GG82563 Specific Registers */
2137#define GG82563_PHY_SPEC_CTRL \
2138 GG82563_REG(0, 16) /* PHY Specific Control */
2139#define GG82563_PHY_SPEC_STATUS_2 \
2140 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2141#define GG82563_PHY_SPEC_CTRL_2 \
2142 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2143#define GG82563_PHY_MAC_SPEC_CTRL \
2144 GG82563_REG(2, 21) /* MAC Specific Control Register */
2145#define GG82563_PHY_MAC_SPEC_CTRL_2 \
2146 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2147
2148/* Page 193 - Port Control Registers */
2149#define GG82563_PHY_KMRN_MODE_CTRL \
2150 GG82563_REG(193, 16) /* Kumeran Mode Control */
2151#define GG82563_PHY_DEVICE_ID \
2152 GG82563_REG(193, 19) /* Device ID */
2153#define GG82563_PHY_PWR_MGMT_CTRL \
2154 GG82563_REG(193, 20) /* Power Management Control */
2155
2156/* Page 194 - KMRN Registers */
2157#define GG82563_PHY_KMRN_CTRL \
2158 GG82563_REG(194, 17) /* Control */
2159#define GG82563_PHY_INBAND_CTRL \
2160 GG82563_REG(194, 18) /* Inband Control */
2161
2162#endif /* _E1000_HW_H_ */
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