eepro.c@ 1300

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1	#ifdef ALLMULTI
2	#error multicast support is not yet implemented
3	#endif
4	/**************************************************************************
5	Etherboot - BOOTP/TFTP Bootstrap Program
6	Intel EEPRO/10 NIC driver for Etherboot
7	Adapted from Linux eepro.c from kernel 2.2.17
8
9	This board accepts a 32 pin EEPROM (29C256), however a test with a
10	27C010 shows that this EPROM also works in the socket, but it's not clear
11	how repeatably. The two top address pins appear to be held low, thus
12	the bottom 32kB of the 27C010 is visible in the CPU's address space.
13	To be sure you could put 4 copies of the code in the 27C010, then
14	it doesn't matter whether the extra lines are held low or high, just
15	hopefully not floating as CMOS chips don't like floating inputs.
16
17	Be careful with seating the EPROM as the socket on my board actually
18	has 34 pins, the top row of 2 are not used.
19	***************************************************************************/
20
21	/*
22
23	timlegge 2005-05-18 remove the relocation changes cards that
24	write directly to the hardware don't need it
25	*/
26
27	/*
28	* This program is free software; you can redistribute it and/or
29	* modify it under the terms of the GNU General Public License as
30	* published by the Free Software Foundation; either version 2, or (at
31	* your option) any later version.
32	*/
33
34	/* to get some global routines like printf */
35	#include "etherboot.h"
36	/* to get the interface to the body of the program */
37	#include "nic.h"
38	#include "isa.h"
39	/* we use timer2 for microsecond waits */
40	#include "timer.h"
41
42	#undef DEBUG /* only after include files */
43
44	/* Different 82595 chips */
45	#define LAN595 0
46	#define LAN595TX 1
47	#define LAN595FX 2
48	#define LAN595FX_10ISA 3
49
50	#define SLOW_DOWN inb(0x80);
51
52	/* The station (ethernet) address prefix, used for IDing the board. */
53	#define SA_ADDR0 0x00 /* Etherexpress Pro/10 */
54	#define SA_ADDR1 0xaa
55	#define SA_ADDR2 0x00
56
57	#define GetBit(x,y) ((x & (1<<y))>>y)
58
59	/* EEPROM Word 0: */
60	#define ee_PnP 0 /* Plug 'n Play enable bit */
61	#define ee_Word1 1 /* Word 1? */
62	#define ee_BusWidth 2 /* 8/16 bit */
63	#define ee_FlashAddr 3 /* Flash Address */
64	#define ee_FlashMask 0x7 /* Mask */
65	#define ee_AutoIO 6 /* */
66	#define ee_reserved0 7 /* =0! */
67	#define ee_Flash 8 /* Flash there? */
68	#define ee_AutoNeg 9 /* Auto Negotiation enabled? */
69	#define ee_IO0 10 /* IO Address LSB */
70	#define ee_IO0Mask 0x /.../
71	#define ee_IO1 15 /* IO MSB */
72
73	/* EEPROM Word 1: */
74	#define ee_IntSel 0 /* Interrupt */
75	#define ee_IntMask 0x7
76	#define ee_LI 3 /* Link Integrity 0= enabled */
77	#define ee_PC 4 /* Polarity Correction 0= enabled */
78	#define ee_TPE_AUI 5 /* PortSelection 1=TPE */
79	#define ee_Jabber 6 /* Jabber prevention 0= enabled */
80	#define ee_AutoPort 7 /* Auto Port Selection 1= Disabled */
81	#define ee_SMOUT 8 /* SMout Pin Control 0= Input */
82	#define ee_PROM 9 /* Flash EPROM / PROM 0=Flash */
83	#define ee_reserved1 10 /* .. 12 =0! */
84	#define ee_AltReady 13 /* Alternate Ready, 0=normal */
85	#define ee_reserved2 14 /* =0! */
86	#define ee_Duplex 15
87
88	/* Word2,3,4: */
89	#define ee_IA5 0 /bit start for individual Addr Byte 5 /
90	#define ee_IA4 8 /bit start for individual Addr Byte 5 /
91	#define ee_IA3 0 /bit start for individual Addr Byte 5 /
92	#define ee_IA2 8 /bit start for individual Addr Byte 5 /
93	#define ee_IA1 0 /bit start for individual Addr Byte 5 /
94	#define ee_IA0 8 /bit start for individual Addr Byte 5 /
95
96	/* Word 5: */
97	#define ee_BNC_TPE 0 /* 0=TPE */
98	#define ee_BootType 1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */
99	#define ee_BootTypeMask 0x3
100	#define ee_NumConn 3 /* Number of Connections 0= One or Two */
101	#define ee_FlashSock 4 /* Presence of Flash Socket 0= Present */
102	#define ee_PortTPE 5
103	#define ee_PortBNC 6
104	#define ee_PortAUI 7
105	#define ee_PowerMgt 10 /* 0= disabled */
106	#define ee_CP 13 /* Concurrent Processing */
107	#define ee_CPMask 0x7
108
109	/* Word 6: */
110	#define ee_Stepping 0 /* Stepping info */
111	#define ee_StepMask 0x0F
112	#define ee_BoardID 4 /* Manucaturer Board ID, reserved */
113	#define ee_BoardMask 0x0FFF
114
115	/* Word 7: */
116	#define ee_INT_TO_IRQ 0 /* int to IRQ Mapping = 0x1EB8 for Pro/10+ */
117	#define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */
118
119	/../
120	#define ee_SIZE 0x40 /* total EEprom Size */
121	#define ee_Checksum 0xBABA /* initial and final value for adding checksum */
122
123
124	/* Card identification via EEprom: */
125	#define ee_addr_vendor 0x10 /* Word offset for EISA Vendor ID */
126	#define ee_addr_id 0x11 /* Word offset for Card ID */
127	#define ee_addr_SN 0x12 /* Serial Number */
128	#define ee_addr_CRC_8 0x14 /* CRC over last thee Bytes */
129
130
131	#define ee_vendor_intel0 0x25 /* Vendor ID Intel */
132	#define ee_vendor_intel1 0xD4
133	#define ee_id_eepro10p0 0x10 /* ID for eepro/10+ */
134	#define ee_id_eepro10p1 0x31
135
136	/* now this section could be used by both boards: the oldies and the ee10:
137	* ee10 uses tx buffer before of rx buffer and the oldies the inverse.
138	* (aris)
139	*/
140	#define RAM_SIZE 0x8000
141
142	#define RCV_HEADER 8
143	#define RCV_DEFAULT_RAM 0x6000
144	#define RCV_RAM rcv_ram
145
146	static unsigned rcv_ram = RCV_DEFAULT_RAM;
147
148	#define XMT_HEADER 8
149	#define XMT_RAM (RAM_SIZE - RCV_RAM)
150
151	#define XMT_START ((rcv_start + RCV_RAM) % RAM_SIZE)
152
153	#define RCV_LOWER_LIMIT (rcv_start >> 8)
154	#define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8)
155	#define XMT_LOWER_LIMIT (XMT_START >> 8)
156	#define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8)
157
158	#define RCV_START_PRO 0x00
159	#define RCV_START_10 XMT_RAM
160	/* by default the old driver */
161	static unsigned rcv_start = RCV_START_PRO;
162
163	#define RCV_DONE 0x0008
164	#define RX_OK 0x2000
165	#define RX_ERROR 0x0d81
166
167	#define TX_DONE_BIT 0x0080
168	#define CHAIN_BIT 0x8000
169	#define XMT_STATUS 0x02
170	#define XMT_CHAIN 0x04
171	#define XMT_COUNT 0x06
172
173	#define BANK0_SELECT 0x00
174	#define BANK1_SELECT 0x40
175	#define BANK2_SELECT 0x80
176
177	/* Bank 0 registers */
178	#define COMMAND_REG 0x00 /* Register 0 */
179	#define MC_SETUP 0x03
180	#define XMT_CMD 0x04
181	#define DIAGNOSE_CMD 0x07
182	#define RCV_ENABLE_CMD 0x08
183	#define RCV_DISABLE_CMD 0x0a
184	#define STOP_RCV_CMD 0x0b
185	#define RESET_CMD 0x0e
186	#define POWER_DOWN_CMD 0x18
187	#define RESUME_XMT_CMD 0x1c
188	#define SEL_RESET_CMD 0x1e
189	#define STATUS_REG 0x01 /* Register 1 */
190	#define RX_INT 0x02
191	#define TX_INT 0x04
192	#define EXEC_STATUS 0x30
193	#define ID_REG 0x02 /* Register 2 */
194	#define R_ROBIN_BITS 0xc0 /* round robin counter */
195	#define ID_REG_MASK 0x2c
196	#define ID_REG_SIG 0x24
197	#define AUTO_ENABLE 0x10
198	#define INT_MASK_REG 0x03 /* Register 3 */
199	#define RX_STOP_MASK 0x01
200	#define RX_MASK 0x02
201	#define TX_MASK 0x04
202	#define EXEC_MASK 0x08
203	#define ALL_MASK 0x0f
204	#define IO_32_BIT 0x10
205	#define RCV_BAR 0x04 /* The following are word (16-bit) registers */
206	#define RCV_STOP 0x06
207
208	#define XMT_BAR_PRO 0x0a
209	#define XMT_BAR_10 0x0b
210	static unsigned xmt_bar = XMT_BAR_PRO;
211
212	#define HOST_ADDRESS_REG 0x0c
213	#define IO_PORT 0x0e
214	#define IO_PORT_32_BIT 0x0c
215
216	/* Bank 1 registers */
217	#define REG1 0x01
218	#define WORD_WIDTH 0x02
219	#define INT_ENABLE 0x80
220	#define INT_NO_REG 0x02
221	#define RCV_LOWER_LIMIT_REG 0x08
222	#define RCV_UPPER_LIMIT_REG 0x09
223
224	#define XMT_LOWER_LIMIT_REG_PRO 0x0a
225	#define XMT_UPPER_LIMIT_REG_PRO 0x0b
226	#define XMT_LOWER_LIMIT_REG_10 0x0b
227	#define XMT_UPPER_LIMIT_REG_10 0x0a
228	static unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO;
229	static unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO;
230
231	/* Bank 2 registers */
232	#define XMT_Chain_Int 0x20 /* Interrupt at the end of the transmit chain */
233	#define XMT_Chain_ErrStop 0x40 /* Interrupt at the end of the chain even if there are errors */
234	#define RCV_Discard_BadFrame 0x80 /* Throw bad frames away, and continue to receive others */
235	#define REG2 0x02
236	#define PRMSC_Mode 0x01
237	#define Multi_IA 0x20
238	#define REG3 0x03
239	#define TPE_BIT 0x04
240	#define BNC_BIT 0x20
241	#define REG13 0x0d
242	#define FDX 0x00
243	#define A_N_ENABLE 0x02
244
245	#define I_ADD_REG0 0x04
246	#define I_ADD_REG1 0x05
247	#define I_ADD_REG2 0x06
248	#define I_ADD_REG3 0x07
249	#define I_ADD_REG4 0x08
250	#define I_ADD_REG5 0x09
251
252	#define EEPROM_REG_PRO 0x0a
253	#define EEPROM_REG_10 0x0b
254	static unsigned eeprom_reg = EEPROM_REG_PRO;
255
256	#define EESK 0x01
257	#define EECS 0x02
258	#define EEDI 0x04
259	#define EEDO 0x08
260
261	/* The horrible routine to read a word from the serial EEPROM. */
262	/* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */
263
264	/* The delay between EEPROM clock transitions. */
265	#define eeprom_delay() { udelay(40); }
266	#define EE_READ_CMD (6 << 6)
267
268	/* do a full reset; data sheet asks for 250us delay */
269	#define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(255);
270
271	/* do a nice reset */
272	#define eepro_sel_reset(ioaddr) { \
273	outb(SEL_RESET_CMD, ioaddr); \
274	SLOW_DOWN; \
275	SLOW_DOWN; \
276	}
277
278	/* clear all interrupts */
279	#define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
280
281	/* enable rx */
282	#define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr)
283
284	/* disable rx */
285	#define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr)
286
287	/* switch bank */
288	#define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
289	#define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
290	#define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
291
292	static unsigned int rx_start, tx_start;
293	static int tx_last;
294	static unsigned int tx_end;
295	static int eepro = 0;
296	static unsigned short ioaddr = 0;
297	static unsigned int mem_start, mem_end = RCV_DEFAULT_RAM / 1024;
298
299	/**************************************************************************
300	RESET - Reset adapter
301	***************************************************************************/
302	static void eepro_reset(struct nic *nic)
303	{
304	int temp_reg, i;
305
306	/* put the card in its initial state */
307	eepro_sw2bank2(ioaddr); /* be careful, bank2 now */
308	temp_reg = inb(ioaddr + eeprom_reg);
309	#ifdef DEBUG
310	printf("Stepping %d\n", temp_reg >> 5);
311	#endif
312	if (temp_reg & 0x10) /* check the TurnOff Enable bit */
313	outb(temp_reg & 0xEF, ioaddr + eeprom_reg);
314	for (i = 0; i < ETH_ALEN; i++) /* fill the MAC address */
315	outb(nic->node_addr[i], ioaddr + I_ADD_REG0 + i);
316	temp_reg = inb(ioaddr + REG1);
317	/* setup Transmit Chaining and discard bad RCV frames */
318	outb(temp_reg \| XMT_Chain_Int \| XMT_Chain_ErrStop
319	\| RCV_Discard_BadFrame, ioaddr + REG1);
320	temp_reg = inb(ioaddr + REG2); /* match broadcast */
321	outb(temp_reg \| 0x14, ioaddr + REG2);
322	temp_reg = inb(ioaddr + REG3);
323	outb(temp_reg & 0x3F, ioaddr + REG3); /* clear test mode */
324	/* set the receiving mode */
325	eepro_sw2bank1(ioaddr); /* be careful, bank1 now */
326	/* initialise the RCV and XMT upper and lower limits */
327	outb(RCV_LOWER_LIMIT, ioaddr + RCV_LOWER_LIMIT_REG);
328	outb(RCV_UPPER_LIMIT, ioaddr + RCV_UPPER_LIMIT_REG);
329	outb(XMT_LOWER_LIMIT, ioaddr + xmt_lower_limit_reg);
330	outb(XMT_UPPER_LIMIT, ioaddr + xmt_upper_limit_reg);
331	eepro_sw2bank0(ioaddr); /* Switch back to bank 0 */
332	eepro_clear_int(ioaddr);
333	/* Initialise RCV */
334	outw(rx_start = (RCV_LOWER_LIMIT << 8), ioaddr + RCV_BAR);
335	outw(((RCV_UPPER_LIMIT << 8) \| 0xFE), ioaddr + RCV_STOP);
336	/* Make sure 1st poll won't find a valid packet header */
337	outw((RCV_LOWER_LIMIT << 8), ioaddr + HOST_ADDRESS_REG);
338	outw(0, ioaddr + IO_PORT);
339	/* Intialise XMT */
340	outw((XMT_LOWER_LIMIT << 8), ioaddr + xmt_bar);
341	eepro_sel_reset(ioaddr);
342	tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
343	tx_last = 0;
344	eepro_en_rx(ioaddr);
345	}
346
347	/* extern void hex_dump(const char data, const unsigned int len); /
348
349	/**************************************************************************
350	POLL - Wait for a frame
351	***************************************************************************/
352	static int eepro_poll(struct nic *nic, int retrieve)
353	{
354	unsigned int rcv_car = rx_start;
355	unsigned int rcv_event, rcv_status, rcv_next_frame, rcv_size;
356
357	/* return true if there's an ethernet packet ready to read */
358	/* nic->packet should contain data on return */
359	/* nic->packetlen should contain length of data */
360	#if 0
361	if ((inb(ioaddr + STATUS_REG) & 0x40) == 0)
362	return (0);
363	outb(0x40, ioaddr + STATUS_REG);
364	#endif
365	outw(rcv_car, ioaddr + HOST_ADDRESS_REG);
366	rcv_event = inw(ioaddr + IO_PORT);
367	if (rcv_event != RCV_DONE)
368	return (0);
369
370	/* FIXME: I'm guessing this might not work with this card, since
371	it looks like once a rcv_event is started it must be completed.
372	maybe there's another way. */
373	if ( ! retrieve ) return 1;
374
375	rcv_status = inw(ioaddr + IO_PORT);
376	rcv_next_frame = inw(ioaddr + IO_PORT);
377	rcv_size = inw(ioaddr + IO_PORT);
378	#if 0
379	printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size,
380	inb(ioaddr + STATUS_REG));
381	#endif
382	if ((rcv_status & (RX_OK\|RX_ERROR)) != RX_OK) {
383	printf("Receive error %hX\n", rcv_status);
384	return (0);
385	}
386	rcv_size &= 0x3FFF;
387	insw(ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1));
388	#if 0
389	{
390	int i;
391	for (i = 0; i < 48; i++) {
392	printf("%hhX", nic->packet[i]);
393	putchar(i % 16 == 15 ? '\n' : ' ');
394	}
395	}
396	#endif
397	nic->packetlen = rcv_size;
398	rcv_car = (rx_start + RCV_HEADER + rcv_size);
399	rx_start = rcv_next_frame;
400	/*
401	hex_dump(rcv_car, nic->packetlen);
402	*/
403
404	if (rcv_car == 0)
405	rcv_car = ((RCV_UPPER_LIMIT << 8) \| 0xff);
406	outw(rcv_car - 1, ioaddr + RCV_STOP);
407	return (1);
408	}
409
410	/**************************************************************************
411	TRANSMIT - Transmit a frame
412	***************************************************************************/
413	static void eepro_transmit(
414	struct nic *nic,
415	const char d, / Destination */
416	unsigned int t, /* Type */
417	unsigned int s, /* size */
418	const char p) / Packet */
419	{
420	unsigned int status, tx_available, last, end, length;
421	unsigned short type;
422	int boguscount = 20;
423
424	length = s + ETH_HLEN;
425	if (tx_end > tx_start)
426	tx_available = XMT_RAM - (tx_end - tx_start);
427	else if (tx_end < tx_start)
428	tx_available = tx_start - tx_end;
429	else
430	tx_available = XMT_RAM;
431	last = tx_end;
432	end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
433	if (end >= (XMT_UPPER_LIMIT << 8)) {
434	last = (XMT_LOWER_LIMIT << 8);
435	end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
436	}
437	outw(last, ioaddr + HOST_ADDRESS_REG);
438	outw(XMT_CMD, ioaddr + IO_PORT);
439	outw(0, ioaddr + IO_PORT);
440	outw(end, ioaddr + IO_PORT);
441	outw(length, ioaddr + IO_PORT);
442	outsw(ioaddr + IO_PORT, d, ETH_ALEN / 2);
443	outsw(ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2);
444	type = htons(t);
445	outsw(ioaddr + IO_PORT, &type, sizeof(type) / 2);
446	outsw(ioaddr + IO_PORT, p, (s + 3) >> 1);
447	/* A dummy read to flush the DRAM write pipeline */
448	status = inw(ioaddr + IO_PORT);
449	outw(last, ioaddr + xmt_bar);
450	outb(XMT_CMD, ioaddr);
451	tx_start = last;
452	tx_last = last;
453	tx_end = end;
454	#if 0
455	printf("%d %d\n", tx_start, tx_end);
456	#endif
457	while (boguscount > 0) {
458	if (((status = inw(ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
459	udelay(40);
460	boguscount--;
461	continue;
462	}
463	#if DEBUG
464	if ((status & 0x2000) == 0)
465	printf("Transmit status %hX\n", status);
466	#endif
467	}
468	}
469
470	/**************************************************************************
471	DISABLE - Turn off ethernet interface
472	***************************************************************************/
473	static void eepro_disable(struct dev *dev __unused)
474	{
475	eepro_sw2bank0(ioaddr); /* Switch to bank 0 */
476	/* Flush the Tx and disable Rx */
477	outb(STOP_RCV_CMD, ioaddr);
478	tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
479	tx_last = 0;
480	/* Reset the 82595 */
481	eepro_full_reset(ioaddr);
482	}
483
484	/**************************************************************************
485	DISABLE - Enable, Disable, or Force interrupts
486	***************************************************************************/
487	static void eepro_irq(struct nic *nic __unused, irq_action_t action __unused)
488	{
489	switch ( action ) {
490	case DISABLE :
491	break;
492	case ENABLE :
493	break;
494	case FORCE :
495	break;
496	}
497	}
498
499	static int read_eeprom(int location)
500	{
501	int i;
502	unsigned short retval = 0;
503	int ee_addr = ioaddr + eeprom_reg;
504	int read_cmd = location \| EE_READ_CMD;
505	int ctrl_val = EECS;
506
507	if (eepro == LAN595FX_10ISA) {
508	eepro_sw2bank1(ioaddr);
509	outb(0x00, ioaddr + STATUS_REG);
510	}
511	eepro_sw2bank2(ioaddr);
512	outb(ctrl_val, ee_addr);
513	/* shift the read command bits out */
514	for (i = 8; i >= 0; i--) {
515	short outval = (read_cmd & (1 << i)) ? ctrl_val \| EEDI : ctrl_val;
516	outb(outval, ee_addr);
517	outb(outval \| EESK, ee_addr); /* EEPROM clock tick */
518	eeprom_delay();
519	outb(outval, ee_addr); /* finish EEPROM clock tick */
520	eeprom_delay();
521	}
522	outb(ctrl_val, ee_addr);
523	for (i = 16; i > 0; i--) {
524	outb(ctrl_val \| EESK, ee_addr);
525	eeprom_delay();
526	retval = (retval << 1) \| ((inb(ee_addr) & EEDO) ? 1 : 0);
527	outb(ctrl_val, ee_addr);
528	eeprom_delay();
529	}
530	/* terminate the EEPROM access */
531	ctrl_val &= ~EECS;
532	outb(ctrl_val \| EESK, ee_addr);
533	eeprom_delay();
534	outb(ctrl_val, ee_addr);
535	eeprom_delay();
536	eepro_sw2bank0(ioaddr);
537	return (retval);
538	}
539
540	static int eepro_probe1(struct nic *nic)
541	{
542	int i, id, counter, l_eepro = 0;
543	union {
544	unsigned char caddr[ETH_ALEN];
545	unsigned short saddr[ETH_ALEN/2];
546	} station_addr;
547	char *name;
548
549	id = inb(ioaddr + ID_REG);
550	if ((id & ID_REG_MASK) != ID_REG_SIG)
551	return (0);
552	counter = id & R_ROBIN_BITS;
553	if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40))
554	return (0);
555	/* yes the 82595 has been found */
556	station_addr.saddr[2] = read_eeprom(2);
557	if (station_addr.saddr[2] == 0x0000 \|\| station_addr.saddr[2] == 0xFFFF) {
558	l_eepro = 3;
559	eepro = LAN595FX_10ISA;
560	eeprom_reg= EEPROM_REG_10;
561	rcv_start = RCV_START_10;
562	xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10;
563	xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10;
564	station_addr.saddr[2] = read_eeprom(2);
565	}
566	station_addr.saddr[1] = read_eeprom(3);
567	station_addr.saddr[0] = read_eeprom(4);
568	if (l_eepro)
569	name = "Intel EtherExpress 10 ISA";
570	else if (read_eeprom(7) == ee_FX_INT2IRQ) {
571	name = "Intel EtherExpress Pro/10+ ISA";
572	l_eepro = 2;
573	} else if (station_addr.saddr[0] == SA_ADDR1) {
574	name = "Intel EtherExpress Pro/10 ISA";
575	l_eepro = 1;
576	} else {
577	l_eepro = 0;
578	name = "Intel 82595-based LAN card";
579	}
580	station_addr.saddr[0] = swap16(station_addr.saddr[0]);
581	station_addr.saddr[1] = swap16(station_addr.saddr[1]);
582	station_addr.saddr[2] = swap16(station_addr.saddr[2]);
583	for (i = 0; i < ETH_ALEN; i++) {
584	nic->node_addr[i] = station_addr.caddr[i];
585	}
586	printf("\n%s ioaddr %#hX, addr %!", name, ioaddr, nic->node_addr);
587	mem_start = RCV_LOWER_LIMIT << 8;
588	if ((mem_end & 0x3F) < 3 \|\| (mem_end & 0x3F) > 29)
589	mem_end = RCV_UPPER_LIMIT << 8;
590	else {
591	mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8);
592	rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8);
593	}
594	printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10,
595	GetBit(read_eeprom(5), ee_BNC_TPE) ? "BNC" : "TP");
596	return (1);
597	}
598
599	/**************************************************************************
600	PROBE - Look for an adapter, this routine's visible to the outside
601	***************************************************************************/
602	static int eepro_probe(struct dev dev, unsigned short probe_addrs)
603	{
604	struct nic nic = (struct nic )dev;
605	unsigned short *p;
606	/* same probe list as the Linux driver */
607	static unsigned short ioaddrs[] = {
608	0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360, 0};
609
610	if (probe_addrs == 0 \|\| probe_addrs[0] == 0)
611	probe_addrs = ioaddrs;
612	for (p = probe_addrs; (ioaddr = *p) != 0; p++) {
613	if (eepro_probe1(nic))
614	break;
615	}
616	if (*p == 0)
617	return (0);
618
619	nic->irqno = 0;
620	nic->ioaddr = *p;
621
622	eepro_reset(nic);
623	/* point to NIC specific routines */
624	dev->disable = eepro_disable;
625	nic->poll = eepro_poll;
626	nic->transmit = eepro_transmit;
627	nic->irq = eepro_irq;
628	/* Based on PnP ISA map */
629	dev->devid.vendor_id = htons(GENERIC_ISAPNP_VENDOR);
630	dev->devid.device_id = htons(0x828a);
631	return 1;
632	}
633
634	static struct isa_driver eepro_driver __isa_driver = {
635	.type = NIC_DRIVER,
636	.name = "EEPRO",
637	.probe = eepro_probe,
638	.ioaddrs = 0,
639	};

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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/eepro.c@ 1300

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