etherfabric.c@ 1300

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1	/**************************************************************************
2	*
3	* Etherboot driver for Level 5 Etherfabric network cards
4	*
5	* Written by Michael Brown <[email protected]>
6	*
7	* Copyright Fen Systems Ltd. 2005
8	* Copyright Level 5 Networks Inc. 2005
9	*
10	* This software may be used and distributed according to the terms of
11	* the GNU General Public License (GPL), incorporated herein by
12	* reference. Drivers based on or derived from this code fall under
13	* the GPL and must retain the authorship, copyright and license
14	* notice.
15	*
16	**************************************************************************
17	*/
18
19	#include "etherboot.h"
20	#include "nic.h"
21	#include "pci.h"
22	#include "timer.h"
23	#define dma_addr_t unsigned long
24	#include "etherfabric.h"
25
26	/**************************************************************************
27	*
28	* Constants and macros
29	*
30	**************************************************************************
31	*/
32
33	#define DBG(...)
34
35	#define EFAB_ASSERT(x) \
36	do { \
37	if ( ! (x) ) { \
38	DBG ( "ASSERT(%s) failed at %s line %d [%s]\n", #x, \
39	__FILE__, __LINE__, __FUNCTION__ ); \
40	} \
41	} while (0)
42
43	#define EFAB_TRACE(...)
44
45	#define EFAB_REGDUMP(...)
46
47	#define FALCON_USE_IO_BAR 1
48
49	/*
50	* EtherFabric constants
51	*
52	*/
53
54	/* PCI Definitions */
55	#define EFAB_VENDID_LEVEL5 0x1924
56	#define FALCON_P_DEVID 0x0703 /* Temporary PCI ID */
57	#define EF1002_DEVID 0xC101
58
59	/**************************************************************************
60	*
61	* Data structures
62	*
63	**************************************************************************
64	*/
65
66	/*
67	* Buffers used for TX, RX and event queue
68	*
69	*/
70	#define EFAB_BUF_ALIGN 4096
71	#define EFAB_DATA_BUF_SIZE 2048
72	#define EFAB_RX_BUFS 16
73	#define EFAB_RXD_SIZE 512
74	#define EFAB_TXD_SIZE 512
75	#define EFAB_EVQ_SIZE 512
76	struct efab_buffers {
77	uint8_t eventq[4096];
78	uint8_t rxd[4096];
79	uint8_t txd[4096];
80	uint8_t tx_buf[EFAB_DATA_BUF_SIZE];
81	uint8_t rx_buf[EFAB_RX_BUFS][EFAB_DATA_BUF_SIZE];
82	uint8_t padding[EFAB_BUF_ALIGN-1];
83	};
84	static struct efab_buffers efab_buffers;
85
86	/** An RX buffer */
87	struct efab_rx_buf {
88	uint8_t *addr;
89	unsigned int len;
90	int id;
91	};
92
93	/** A TX buffer */
94	struct efab_tx_buf {
95	uint8_t *addr;
96	unsigned int len;
97	int id;
98	};
99
100	/** Etherfabric event type */
101	enum efab_event_type {
102	EFAB_EV_NONE = 0,
103	EFAB_EV_TX,
104	EFAB_EV_RX,
105	};
106
107	/** Etherfabric event */
108	struct efab_event {
109	/** Event type */
110	enum efab_event_type type;
111	/** RX buffer ID */
112	int rx_id;
113	/** RX length */
114	unsigned int rx_len;
115	};
116
117	/*
118	* Etherfabric abstraction layer
119	*
120	*/
121	struct efab_nic;
122	struct efab_operations {
123	void ( * get_membase ) ( struct efab_nic *efab );
124	int ( * reset ) ( struct efab_nic *efab );
125	int ( * init_nic ) ( struct efab_nic *efab );
126	int ( * read_eeprom ) ( struct efab_nic *efab );
127	void ( * build_rx_desc ) ( struct efab_nic *efab,
128	struct efab_rx_buf *rx_buf );
129	void ( * notify_rx_desc ) ( struct efab_nic *efab );
130	void ( * build_tx_desc ) ( struct efab_nic *efab,
131	struct efab_tx_buf *tx_buf );
132	void ( * notify_tx_desc ) ( struct efab_nic *efab );
133	int ( * fetch_event ) ( struct efab_nic *efab,
134	struct efab_event *event );
135	void ( * mask_irq ) ( struct efab_nic *efab, int enabled );
136	void ( * generate_irq ) ( struct efab_nic *efab );
137	void ( * mac_writel ) ( struct efab_nic efab, efab_dword_t value,
138	unsigned int mac_reg );
139	void ( * mac_readl ) ( struct efab_nic efab, efab_dword_t value,
140	unsigned int mac_reg );
141	int ( * init_mac ) ( struct efab_nic *efab );
142	void ( * mdio_write ) ( struct efab_nic *efab, int location,
143	int value );
144	int ( * mdio_read ) ( struct efab_nic *efab, int location );
145	};
146
147	/*
148	* Driver private data structure
149	*
150	*/
151	struct efab_nic {
152
153	/** PCI device */
154	struct pci_device *pci;
155
156	/** Operations table */
157	struct efab_operations *op;
158
159	/** Memory base */
160	void *membase;
161
162	/** I/O base */
163	unsigned int iobase;
164
165	/** Buffers */
166	uint8_t eventq; / Falcon only */
167	uint8_t txd; / Falcon only */
168	uint8_t rxd; / Falcon only */
169	struct efab_tx_buf tx_buf;
170	struct efab_rx_buf rx_bufs[EFAB_RX_BUFS];
171
172	/** Buffer pointers */
173	unsigned int eventq_read_ptr; /* Falcon only */
174	unsigned int tx_write_ptr;
175	unsigned int rx_write_ptr;
176	int tx_in_progress;
177
178	/** Port 0/1 on the NIC */
179	int port;
180
181	/** MAC address */
182	uint8_t mac_addr[ETH_ALEN];
183	/** GMII link options */
184	unsigned int link_options;
185	/** Link status */
186	int link_up;
187
188	/** INT_REG_KER for Falcon */
189	efab_oword_t int_ker __attribute__ (( aligned ( 16 ) ));
190	};
191
192	/**************************************************************************
193	*
194	* i2c EEPROM access
195	*
196	**************************************************************************
197	*/
198
199	struct efab_i2c_interface;
200
201	/** i2c bus direct control methods */
202	struct efab_i2c_bit_operations {
203	/** Set state of SDA line */
204	void ( * setsda ) ( struct efab_i2c_interface *i2c );
205	/** Set state of SCL line */
206	void ( * setscl ) ( struct efab_i2c_interface *i2c );
207	/** Get state of SDA line */
208	int ( * getsda ) ( struct efab_i2c_interface *i2c );
209	/** Get state of SCL line */
210	int ( * getscl ) ( struct efab_i2c_interface *i2c );
211	/** Delay between each bit operation */
212	unsigned int udelay;
213	/** Delay between each byte write */
214	unsigned int mdelay;
215	};
216
217	/** An i2c interface */
218	struct efab_i2c_interface {
219	/** Attached Etherfabric NIC */
220	struct efab_nic *efab;
221	/** I2C bus control methods */
222	struct efab_i2c_bit_operations *op;
223	/** Current output state of SDA line */
224	unsigned int sda : 1;
225	/** Current output state of SCL line */
226	unsigned int scl : 1;
227	};
228
229	/*
230	* SDA and SCL line read/writes
231	*
232	*/
233
234	static inline void setsda ( struct efab_i2c_interface *i2c, int state ) {
235	udelay ( i2c->op->udelay );
236	i2c->sda = state;
237	i2c->op->setsda ( i2c );
238	udelay ( i2c->op->udelay );
239	}
240
241	static inline void setscl ( struct efab_i2c_interface *i2c, int state ) {
242	udelay ( i2c->op->udelay );
243	i2c->scl = state;
244	i2c->op->setscl ( i2c );
245	udelay ( i2c->op->udelay );
246	}
247
248	static inline int getsda ( struct efab_i2c_interface *i2c ) {
249	int sda;
250
251	udelay ( i2c->op->udelay );
252	sda = i2c->op->getsda ( i2c );
253	udelay ( i2c->op->udelay );
254	return sda;
255	}
256
257	static inline int getscl ( struct efab_i2c_interface *i2c ) {
258	int scl;
259
260	udelay ( i2c->op->udelay );
261	scl = i2c->op->getscl ( i2c );
262	udelay ( i2c->op->udelay );
263	return scl;
264	}
265
266	/*
267	* i2c low-level protocol operations
268	*
269	*/
270
271	static inline void i2c_release ( struct efab_i2c_interface *i2c ) {
272	EFAB_ASSERT ( i2c->scl );
273	EFAB_ASSERT ( i2c->sda );
274	/* Just in case */
275	setscl ( i2c, 1 );
276	setsda ( i2c, 1 );
277	EFAB_ASSERT ( getsda ( i2c ) == 1 );
278	EFAB_ASSERT ( getscl ( i2c ) == 1 );
279	}
280
281	static inline void i2c_start ( struct efab_i2c_interface *i2c ) {
282	/* We may be restarting immediately after a {send,recv}_bit,
283	* so SCL will not necessarily already be high.
284	*/
285	EFAB_ASSERT ( i2c->sda );
286	setscl ( i2c, 1 );
287	setsda ( i2c, 0 );
288	setscl ( i2c, 0 );
289	setsda ( i2c, 1 );
290	}
291
292	static inline void i2c_send_bit ( struct efab_i2c_interface *i2c, int bit ) {
293	EFAB_ASSERT ( ! i2c->scl );
294	setsda ( i2c, bit );
295	setscl ( i2c, 1 );
296	setscl ( i2c, 0 );
297	setsda ( i2c, 1 );
298	}
299
300	static inline int i2c_recv_bit ( struct efab_i2c_interface *i2c ) {
301	int bit;
302
303	EFAB_ASSERT ( ! i2c->scl );
304	EFAB_ASSERT ( i2c->sda );
305	setscl ( i2c, 1 );
306	bit = getsda ( i2c );
307	setscl ( i2c, 0 );
308	return bit;
309	}
310
311	static inline void i2c_stop ( struct efab_i2c_interface *i2c ) {
312	EFAB_ASSERT ( ! i2c->scl );
313	setsda ( i2c, 0 );
314	setscl ( i2c, 1 );
315	setsda ( i2c, 1 );
316	}
317
318	/*
319	* i2c mid-level protocol operations
320	*
321	*/
322
323	static int i2c_send_byte ( struct efab_i2c_interface *i2c, uint8_t byte ) {
324	int i;
325
326	/* Send byte */
327	for ( i = 0 ; i < 8 ; i++ ) {
328	i2c_send_bit ( i2c, !! ( byte & 0x80 ) );
329	byte <<= 1;
330	}
331
332	/* Check for acknowledgement from slave */
333	return ( i2c_recv_bit ( i2c ) == 0 ? 1 : 0 );
334	}
335
336	static uint8_t i2c_recv_byte ( struct efab_i2c_interface *i2c, int ack ) {
337	uint8_t value = 0;
338	int i;
339
340	/* Receive byte */
341	for ( i = 0 ; i < 8 ; i++ ) {
342	value = ( value << 1 ) \| i2c_recv_bit ( i2c );
343	}
344
345	/* Send ACK/NACK */
346	i2c_send_bit ( i2c, ( ack ? 0 : 1 ) );
347
348	return value;
349	}
350
351	static inline uint8_t i2c_read_cmd ( uint8_t device_id ) {
352	return ( ( device_id << 1 ) \| 1 );
353	}
354
355	static inline uint8_t i2c_write_cmd ( uint8_t device_id ) {
356	return ( ( device_id << 1 ) \| 0 );
357	}
358
359	static int efab_i2c_fast_read ( struct efab_i2c_interface *i2c,
360	uint8_t device_id, uint8_t offset,
361	uint8_t *data, unsigned int len ) {
362	unsigned int i;
363	int rc = 0;
364
365	EFAB_ASSERT ( getsda ( i2c ) == 1 );
366	EFAB_ASSERT ( getscl ( i2c ) == 1 );
367	EFAB_ASSERT ( data != NULL );
368	EFAB_ASSERT ( len >= 1 );
369
370	/* Select device and starting offset */
371	i2c_start ( i2c );
372	if ( ! i2c_send_byte ( i2c, i2c_write_cmd ( device_id ) ) )
373	goto out;
374	if ( ! i2c_send_byte ( i2c, offset ) )
375	goto out;
376
377	/* Read data from device */
378	i2c_start ( i2c );
379	if ( ! i2c_send_byte ( i2c, i2c_read_cmd ( device_id ) ) )
380	goto out;
381	for ( i = 0 ; i < ( len - 1 ); i++ ) {
382	/* Read and acknowledge all but the last byte */
383	data[i] = i2c_recv_byte ( i2c, 1 );
384	}
385	/* Read last byte with no acknowledgement */
386	data[i] = i2c_recv_byte ( i2c, 0 );
387
388	rc = 1;
389	out:
390	i2c_stop ( i2c );
391	i2c_release ( i2c );
392
393	return rc;
394	}
395
396	/**************************************************************************
397	*
398	* GMII routines
399	*
400	**************************************************************************
401	*/
402
403	/* GMII registers */
404	#define MII_BMSR 0x01 /* Basic mode status register */
405	#define MII_ADVERTISE 0x04 /* Advertisement control register */
406	#define MII_LPA 0x05 /* Link partner ability register*/
407	#define GMII_GTCR 0x09 /* 1000BASE-T control register */
408	#define GMII_GTSR 0x0a /* 1000BASE-T status register */
409	#define GMII_PSSR 0x11 /* PHY-specific status register */
410
411	/* Basic mode status register. */
412	#define BMSR_LSTATUS 0x0004 /* Link status */
413
414	/* Link partner ability register. */
415	#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
416	#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
417	#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
418	#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
419	#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
420	#define LPA_PAUSE 0x0400 /* Bit 10 - MAC pause */
421
422	/* Pseudo extensions to the link partner ability register */
423	#define LPA_1000FULL 0x00020000
424	#define LPA_1000HALF 0x00010000
425
426	#define LPA_100 (LPA_100FULL \| LPA_100HALF \| LPA_100BASE4)
427	#define LPA_1000 ( LPA_1000FULL \| LPA_1000HALF )
428	#define LPA_DUPLEX ( LPA_10FULL \| LPA_100FULL \| LPA_1000FULL )
429
430	/* Mask of bits not associated with speed or duplexity. */
431	#define LPA_OTHER ~( LPA_10FULL \| LPA_10HALF \| LPA_100FULL \| \
432	LPA_100HALF \| LPA_1000FULL \| LPA_1000HALF )
433
434	/* PHY-specific status register */
435	#define PSSR_LSTATUS 0x0400 /* Bit 10 - link status */
436
437	/**
438	* Retrieve GMII autonegotiation advertised abilities
439	*
440	*/
441	static unsigned int gmii_autoneg_advertised ( struct efab_nic *efab ) {
442	unsigned int mii_advertise;
443	unsigned int gmii_advertise;
444
445	/* Extended bits are in bits 8 and 9 of GMII_GTCR */
446	mii_advertise = efab->op->mdio_read ( efab, MII_ADVERTISE );
447	gmii_advertise = ( ( efab->op->mdio_read ( efab, GMII_GTCR ) >> 8 )
448	& 0x03 );
449	return ( ( gmii_advertise << 16 ) \| mii_advertise );
450	}
451
452	/**
453	* Retrieve GMII autonegotiation link partner abilities
454	*
455	*/
456	static unsigned int gmii_autoneg_lpa ( struct efab_nic *efab ) {
457	unsigned int mii_lpa;
458	unsigned int gmii_lpa;
459
460	/* Extended bits are in bits 10 and 11 of GMII_GTSR */
461	mii_lpa = efab->op->mdio_read ( efab, MII_LPA );
462	gmii_lpa = ( efab->op->mdio_read ( efab, GMII_GTSR ) >> 10 ) & 0x03;
463	return ( ( gmii_lpa << 16 ) \| mii_lpa );
464	}
465
466	/**
467	* Calculate GMII autonegotiated link technology
468	*
469	*/
470	static unsigned int gmii_nway_result ( unsigned int negotiated ) {
471	unsigned int other_bits;
472
473	/* Mask out the speed and duplexity bits */
474	other_bits = negotiated & LPA_OTHER;
475
476	if ( negotiated & LPA_1000FULL )
477	return ( other_bits \| LPA_1000FULL );
478	else if ( negotiated & LPA_1000HALF )
479	return ( other_bits \| LPA_1000HALF );
480	else if ( negotiated & LPA_100FULL )
481	return ( other_bits \| LPA_100FULL );
482	else if ( negotiated & LPA_100BASE4 )
483	return ( other_bits \| LPA_100BASE4 );
484	else if ( negotiated & LPA_100HALF )
485	return ( other_bits \| LPA_100HALF );
486	else if ( negotiated & LPA_10FULL )
487	return ( other_bits \| LPA_10FULL );
488	else return ( other_bits \| LPA_10HALF );
489	}
490
491	/**
492	* Check GMII PHY link status
493	*
494	*/
495	static int gmii_link_ok ( struct efab_nic *efab ) {
496	int status;
497	int phy_status;
498
499	/* BMSR is latching - it returns "link down" if the link has
500	* been down at any point since the last read. To get a
501	* real-time status, we therefore read the register twice and
502	* use the result of the second read.
503	*/
504	efab->op->mdio_read ( efab, MII_BMSR );
505	status = efab->op->mdio_read ( efab, MII_BMSR );
506
507	/* Read the PHY-specific Status Register. This is
508	* non-latching, so we need do only a single read.
509	*/
510	phy_status = efab->op->mdio_read ( efab, GMII_PSSR );
511
512	return ( ( status & BMSR_LSTATUS ) && ( phy_status & PSSR_LSTATUS ) );
513	}
514
515	/**************************************************************************
516	*
517	* Alaska PHY
518	*
519	**************************************************************************
520	*/
521
522	/**
523	* Initialise Alaska PHY
524	*
525	*/
526	static void alaska_init ( struct efab_nic *efab ) {
527	unsigned int advertised, lpa;
528
529	/* Read link up status */
530	efab->link_up = gmii_link_ok ( efab );
531
532	if ( ! efab->link_up )
533	return;
534
535	/* Determine link options from PHY. */
536	advertised = gmii_autoneg_advertised ( efab );
537	lpa = gmii_autoneg_lpa ( efab );
538	efab->link_options = gmii_nway_result ( advertised & lpa );
539
540	printf ( "%dMbps %s-duplex (%04x,%04x)\n",
541	( efab->link_options & LPA_1000 ? 1000 :
542	( efab->link_options & LPA_100 ? 100 : 10 ) ),
543	( efab->link_options & LPA_DUPLEX ? "full" : "half" ),
544	advertised, lpa );
545	}
546
547	/**************************************************************************
548	*
549	* Mentor MAC
550	*
551	**************************************************************************
552	*/
553
554	/* GMAC configuration register 1 */
555	#define GM_CFG1_REG_MAC 0x00
556	#define GM_SW_RST_LBN 31
557	#define GM_SW_RST_WIDTH 1
558	#define GM_RX_FC_EN_LBN 5
559	#define GM_RX_FC_EN_WIDTH 1
560	#define GM_TX_FC_EN_LBN 4
561	#define GM_TX_FC_EN_WIDTH 1
562	#define GM_RX_EN_LBN 2
563	#define GM_RX_EN_WIDTH 1
564	#define GM_TX_EN_LBN 0
565	#define GM_TX_EN_WIDTH 1
566
567	/* GMAC configuration register 2 */
568	#define GM_CFG2_REG_MAC 0x01
569	#define GM_PAMBL_LEN_LBN 12
570	#define GM_PAMBL_LEN_WIDTH 4
571	#define GM_IF_MODE_LBN 8
572	#define GM_IF_MODE_WIDTH 2
573	#define GM_PAD_CRC_EN_LBN 2
574	#define GM_PAD_CRC_EN_WIDTH 1
575	#define GM_FD_LBN 0
576	#define GM_FD_WIDTH 1
577
578	/* GMAC maximum frame length register */
579	#define GM_MAX_FLEN_REG_MAC 0x04
580	#define GM_MAX_FLEN_LBN 0
581	#define GM_MAX_FLEN_WIDTH 16
582
583	/* GMAC MII management configuration register */
584	#define GM_MII_MGMT_CFG_REG_MAC 0x08
585	#define GM_MGMT_CLK_SEL_LBN 0
586	#define GM_MGMT_CLK_SEL_WIDTH 3
587
588	/* GMAC MII management command register */
589	#define GM_MII_MGMT_CMD_REG_MAC 0x09
590	#define GM_MGMT_SCAN_CYC_LBN 1
591	#define GM_MGMT_SCAN_CYC_WIDTH 1
592	#define GM_MGMT_RD_CYC_LBN 0
593	#define GM_MGMT_RD_CYC_WIDTH 1
594
595	/* GMAC MII management address register */
596	#define GM_MII_MGMT_ADR_REG_MAC 0x0a
597	#define GM_MGMT_PHY_ADDR_LBN 8
598	#define GM_MGMT_PHY_ADDR_WIDTH 5
599	#define GM_MGMT_REG_ADDR_LBN 0
600	#define GM_MGMT_REG_ADDR_WIDTH 5
601
602	/* GMAC MII management control register */
603	#define GM_MII_MGMT_CTL_REG_MAC 0x0b
604	#define GM_MGMT_CTL_LBN 0
605	#define GM_MGMT_CTL_WIDTH 16
606
607	/* GMAC MII management status register */
608	#define GM_MII_MGMT_STAT_REG_MAC 0x0c
609	#define GM_MGMT_STAT_LBN 0
610	#define GM_MGMT_STAT_WIDTH 16
611
612	/* GMAC MII management indicators register */
613	#define GM_MII_MGMT_IND_REG_MAC 0x0d
614	#define GM_MGMT_BUSY_LBN 0
615	#define GM_MGMT_BUSY_WIDTH 1
616
617	/* GMAC station address register 1 */
618	#define GM_ADR1_REG_MAC 0x10
619	#define GM_HWADDR_5_LBN 24
620	#define GM_HWADDR_5_WIDTH 8
621	#define GM_HWADDR_4_LBN 16
622	#define GM_HWADDR_4_WIDTH 8
623	#define GM_HWADDR_3_LBN 8
624	#define GM_HWADDR_3_WIDTH 8
625	#define GM_HWADDR_2_LBN 0
626	#define GM_HWADDR_2_WIDTH 8
627
628	/* GMAC station address register 2 */
629	#define GM_ADR2_REG_MAC 0x11
630	#define GM_HWADDR_1_LBN 24
631	#define GM_HWADDR_1_WIDTH 8
632	#define GM_HWADDR_0_LBN 16
633	#define GM_HWADDR_0_WIDTH 8
634
635	/* GMAC FIFO configuration register 0 */
636	#define GMF_CFG0_REG_MAC 0x12
637	#define GMF_FTFENREQ_LBN 12
638	#define GMF_FTFENREQ_WIDTH 1
639	#define GMF_STFENREQ_LBN 11
640	#define GMF_STFENREQ_WIDTH 1
641	#define GMF_FRFENREQ_LBN 10
642	#define GMF_FRFENREQ_WIDTH 1
643	#define GMF_SRFENREQ_LBN 9
644	#define GMF_SRFENREQ_WIDTH 1
645	#define GMF_WTMENREQ_LBN 8
646	#define GMF_WTMENREQ_WIDTH 1
647
648	/* GMAC FIFO configuration register 1 */
649	#define GMF_CFG1_REG_MAC 0x13
650	#define GMF_CFGFRTH_LBN 16
651	#define GMF_CFGFRTH_WIDTH 5
652	#define GMF_CFGXOFFRTX_LBN 0
653	#define GMF_CFGXOFFRTX_WIDTH 16
654
655	/* GMAC FIFO configuration register 2 */
656	#define GMF_CFG2_REG_MAC 0x14
657	#define GMF_CFGHWM_LBN 16
658	#define GMF_CFGHWM_WIDTH 6
659	#define GMF_CFGLWM_LBN 0
660	#define GMF_CFGLWM_WIDTH 6
661
662	/* GMAC FIFO configuration register 3 */
663	#define GMF_CFG3_REG_MAC 0x15
664	#define GMF_CFGHWMFT_LBN 16
665	#define GMF_CFGHWMFT_WIDTH 6
666	#define GMF_CFGFTTH_LBN 0
667	#define GMF_CFGFTTH_WIDTH 6
668
669	/* GMAC FIFO configuration register 4 */
670	#define GMF_CFG4_REG_MAC 0x16
671	#define GMF_HSTFLTRFRM_PAUSE_LBN 12
672	#define GMF_HSTFLTRFRM_PAUSE_WIDTH 12
673
674	/* GMAC FIFO configuration register 5 */
675	#define GMF_CFG5_REG_MAC 0x17
676	#define GMF_CFGHDPLX_LBN 22
677	#define GMF_CFGHDPLX_WIDTH 1
678	#define GMF_CFGBYTMODE_LBN 19
679	#define GMF_CFGBYTMODE_WIDTH 1
680	#define GMF_HSTDRPLT64_LBN 18
681	#define GMF_HSTDRPLT64_WIDTH 1
682	#define GMF_HSTFLTRFRMDC_PAUSE_LBN 12
683	#define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
684
685	struct efab_mentormac_parameters {
686	int gmf_cfgfrth;
687	int gmf_cfgftth;
688	int gmf_cfghwmft;
689	int gmf_cfghwm;
690	int gmf_cfglwm;
691	};
692
693	/**
694	* Reset Mentor MAC
695	*
696	*/
697	static void mentormac_reset ( struct efab_nic *efab ) {
698	efab_dword_t reg;
699	int save_port;
700
701	/* Take into reset */
702	EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 1 );
703	efab->op->mac_writel ( efab, &reg, GM_CFG1_REG_MAC );
704	udelay ( 1000 );
705
706	/* Take out of reset */
707	EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 0 );
708	efab->op->mac_writel ( efab, &reg, GM_CFG1_REG_MAC );
709	udelay ( 1000 );
710
711	/* Mentor MAC connects both PHYs to MAC 0 */
712	save_port = efab->port;
713	efab->port = 0;
714	/* Configure GMII interface so PHY is accessible. Note that
715	* GMII interface is connected only to port 0, and that on
716	* Falcon this is a no-op.
717	*/
718	EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CLK_SEL, 0x4 );
719	efab->op->mac_writel ( efab, &reg, GM_MII_MGMT_CFG_REG_MAC );
720	udelay ( 10 );
721	efab->port = save_port;
722	}
723
724	/**
725	* Initialise Mentor MAC
726	*
727	*/
728	static void mentormac_init ( struct efab_nic *efab,
729	struct efab_mentormac_parameters *params ) {
730	int pause, if_mode, full_duplex, bytemode, half_duplex;
731	efab_dword_t reg;
732
733	/* Configuration register 1 */
734	pause = ( efab->link_options & LPA_PAUSE ) ? 1 : 0;
735	if ( ! ( efab->link_options & LPA_DUPLEX ) ) {
736	/* Half-duplex operation requires TX flow control */
737	pause = 1;
738	}
739	EFAB_POPULATE_DWORD_4 ( reg,
740	GM_TX_EN, 1,
741	GM_TX_FC_EN, pause,
742	GM_RX_EN, 1,
743	GM_RX_FC_EN, 1 );
744	efab->op->mac_writel ( efab, &reg, GM_CFG1_REG_MAC );
745	udelay ( 10 );
746
747	/* Configuration register 2 */
748	if_mode = ( efab->link_options & LPA_1000 ) ? 2 : 1;
749	full_duplex = ( efab->link_options & LPA_DUPLEX ) ? 1 : 0;
750	EFAB_POPULATE_DWORD_4 ( reg,
751	GM_IF_MODE, if_mode,
752	GM_PAD_CRC_EN, 1,
753	GM_FD, full_duplex,
754	GM_PAMBL_LEN, 0x7 /* ? */ );
755	efab->op->mac_writel ( efab, &reg, GM_CFG2_REG_MAC );
756	udelay ( 10 );
757
758	/* Max frame len register */
759	EFAB_POPULATE_DWORD_1 ( reg, GM_MAX_FLEN, ETH_FRAME_LEN );
760	efab->op->mac_writel ( efab, &reg, GM_MAX_FLEN_REG_MAC );
761	udelay ( 10 );
762
763	/* FIFO configuration register 0 */
764	EFAB_POPULATE_DWORD_5 ( reg,
765	GMF_FTFENREQ, 1,
766	GMF_STFENREQ, 1,
767	GMF_FRFENREQ, 1,
768	GMF_SRFENREQ, 1,
769	GMF_WTMENREQ, 1 );
770	efab->op->mac_writel ( efab, &reg, GMF_CFG0_REG_MAC );
771	udelay ( 10 );
772
773	/* FIFO configuration register 1 */
774	EFAB_POPULATE_DWORD_2 ( reg,
775	GMF_CFGFRTH, params->gmf_cfgfrth,
776	GMF_CFGXOFFRTX, 0xffff );
777	efab->op->mac_writel ( efab, &reg, GMF_CFG1_REG_MAC );
778	udelay ( 10 );
779
780	/* FIFO configuration register 2 */
781	EFAB_POPULATE_DWORD_2 ( reg,
782	GMF_CFGHWM, params->gmf_cfghwm,
783	GMF_CFGLWM, params->gmf_cfglwm );
784	efab->op->mac_writel ( efab, &reg, GMF_CFG2_REG_MAC );
785	udelay ( 10 );
786
787	/* FIFO configuration register 3 */
788	EFAB_POPULATE_DWORD_2 ( reg,
789	GMF_CFGHWMFT, params->gmf_cfghwmft,
790	GMF_CFGFTTH, params->gmf_cfgftth );
791	efab->op->mac_writel ( efab, &reg, GMF_CFG3_REG_MAC );
792	udelay ( 10 );
793
794	/* FIFO configuration register 4 */
795	EFAB_POPULATE_DWORD_1 ( reg, GMF_HSTFLTRFRM_PAUSE, 1 );
796	efab->op->mac_writel ( efab, &reg, GMF_CFG4_REG_MAC );
797	udelay ( 10 );
798
799	/* FIFO configuration register 5 */
800	bytemode = ( efab->link_options & LPA_1000 ) ? 1 : 0;
801	half_duplex = ( efab->link_options & LPA_DUPLEX ) ? 0 : 1;
802	efab->op->mac_readl ( efab, &reg, GMF_CFG5_REG_MAC );
803	EFAB_SET_DWORD_FIELD ( reg, GMF_CFGBYTMODE, bytemode );
804	EFAB_SET_DWORD_FIELD ( reg, GMF_CFGHDPLX, half_duplex );
805	EFAB_SET_DWORD_FIELD ( reg, GMF_HSTDRPLT64, half_duplex );
806	EFAB_SET_DWORD_FIELD ( reg, GMF_HSTFLTRFRMDC_PAUSE, 0 );
807	efab->op->mac_writel ( efab, &reg, GMF_CFG5_REG_MAC );
808	udelay ( 10 );
809
810	/* MAC address */
811	EFAB_POPULATE_DWORD_4 ( reg,
812	GM_HWADDR_5, efab->mac_addr[5],
813	GM_HWADDR_4, efab->mac_addr[4],
814	GM_HWADDR_3, efab->mac_addr[3],
815	GM_HWADDR_2, efab->mac_addr[2] );
816	efab->op->mac_writel ( efab, &reg, GM_ADR1_REG_MAC );
817	udelay ( 10 );
818	EFAB_POPULATE_DWORD_2 ( reg,
819	GM_HWADDR_1, efab->mac_addr[1],
820	GM_HWADDR_0, efab->mac_addr[0] );
821	efab->op->mac_writel ( efab, &reg, GM_ADR2_REG_MAC );
822	udelay ( 10 );
823	}
824
825	/**
826	* Wait for GMII access to complete
827	*
828	*/
829	static int mentormac_gmii_wait ( struct efab_nic *efab ) {
830	int count;
831	efab_dword_t indicator;
832
833	for ( count = 0 ; count < 1000 ; count++ ) {
834	udelay ( 10 );
835	efab->op->mac_readl ( efab, &indicator,
836	GM_MII_MGMT_IND_REG_MAC );
837	if ( EFAB_DWORD_FIELD ( indicator, GM_MGMT_BUSY ) == 0 )
838	return 1;
839	}
840	printf ( "Timed out waiting for GMII\n" );
841	return 0;
842	}
843
844	/**
845	* Write a GMII register
846	*
847	*/
848	static void mentormac_mdio_write ( struct efab_nic *efab, int phy_id,
849	int location, int value ) {
850	efab_dword_t reg;
851	int save_port;
852
853	EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n", phy_id,
854	location, value );
855
856	/* Mentor MAC connects both PHYs to MAC 0 */
857	save_port = efab->port;
858	efab->port = 0;
859
860	/* Check MII not currently being accessed */
861	if ( ! mentormac_gmii_wait ( efab ) )
862	goto out;
863
864	/* Write the address register */
865	EFAB_POPULATE_DWORD_2 ( reg,
866	GM_MGMT_PHY_ADDR, phy_id,
867	GM_MGMT_REG_ADDR, location );
868	efab->op->mac_writel ( efab, &reg, GM_MII_MGMT_ADR_REG_MAC );
869	udelay ( 10 );
870
871	/* Write data */
872	EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CTL, value );
873	efab->op->mac_writel ( efab, &reg, GM_MII_MGMT_CTL_REG_MAC );
874
875	/* Wait for data to be written */
876	mentormac_gmii_wait ( efab );
877
878	out:
879	/* Restore efab->port */
880	efab->port = save_port;
881	}
882
883	/**
884	* Read a GMII register
885	*
886	*/
887	static int mentormac_mdio_read ( struct efab_nic *efab, int phy_id,
888	int location ) {
889	efab_dword_t reg;
890	int value = 0xffff;
891	int save_port;
892
893	/* Mentor MAC connects both PHYs to MAC 0 */
894	save_port = efab->port;
895	efab->port = 0;
896
897	/* Check MII not currently being accessed */
898	if ( ! mentormac_gmii_wait ( efab ) )
899	goto out;
900
901	/* Write the address register */
902	EFAB_POPULATE_DWORD_2 ( reg,
903	GM_MGMT_PHY_ADDR, phy_id,
904	GM_MGMT_REG_ADDR, location );
905	efab->op->mac_writel ( efab, &reg, GM_MII_MGMT_ADR_REG_MAC );
906	udelay ( 10 );
907
908	/* Request data to be read */
909	EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_RD_CYC, 1 );
910	efab->op->mac_writel ( efab, &reg, GM_MII_MGMT_CMD_REG_MAC );
911
912	/* Wait for data to be become available */
913	if ( mentormac_gmii_wait ( efab ) ) {
914	/* Read data */
915	efab->op->mac_readl ( efab, &reg, GM_MII_MGMT_STAT_REG_MAC );
916	value = EFAB_DWORD_FIELD ( reg, GM_MGMT_STAT );
917	EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
918	phy_id, location, value );
919	}
920
921	/* Signal completion */
922	EFAB_ZERO_DWORD ( reg );
923	efab->op->mac_writel ( efab, &reg, GM_MII_MGMT_CMD_REG_MAC );
924	udelay ( 10 );
925
926	out:
927	/* Restore efab->port */
928	efab->port = save_port;
929
930	return value;
931	}
932
933	/**************************************************************************
934	*
935	* EF1002 routines
936	*
937	**************************************************************************
938	*/
939
940	/** Control and General Status */
941	#define EF1_CTR_GEN_STATUS0_REG 0x0
942	#define EF1_MASTER_EVENTS_LBN 12
943	#define EF1_MASTER_EVENTS_WIDTH 1
944	#define EF1_TX_ENGINE_EN_LBN 19
945	#define EF1_TX_ENGINE_EN_WIDTH 1
946	#define EF1_RX_ENGINE_EN_LBN 18
947	#define EF1_RX_ENGINE_EN_WIDTH 1
948	#define EF1_TURBO2_LBN 17
949	#define EF1_TURBO2_WIDTH 1
950	#define EF1_TURBO1_LBN 16
951	#define EF1_TURBO1_WIDTH 1
952	#define EF1_TURBO3_LBN 14
953	#define EF1_TURBO3_WIDTH 1
954	#define EF1_LB_RESET_LBN 3
955	#define EF1_LB_RESET_WIDTH 1
956	#define EF1_MAC_RESET_LBN 2
957	#define EF1_MAC_RESET_WIDTH 1
958	#define EF1_CAM_ENABLE_LBN 1
959	#define EF1_CAM_ENABLE_WIDTH 1
960
961	/** IRQ sources */
962	#define EF1_IRQ_SRC_REG 0x0008
963
964	/** IRQ mask */
965	#define EF1_IRQ_MASK_REG 0x000c
966	#define EF1_IRQ_PHY1_LBN 11
967	#define EF1_IRQ_PHY1_WIDTH 1
968	#define EF1_IRQ_PHY0_LBN 10
969	#define EF1_IRQ_PHY0_WIDTH 1
970	#define EF1_IRQ_SERR_LBN 7
971	#define EF1_IRQ_SERR_WIDTH 1
972	#define EF1_IRQ_EVQ_LBN 3
973	#define EF1_IRQ_EVQ_WIDTH 1
974
975	/** Event generation */
976	#define EF1_EVT3_REG 0x38
977
978	/** EEPROM access */
979	#define EF1_EEPROM_REG 0x40
980	#define EF1_EEPROM_SDA_LBN 31
981	#define EF1_EEPROM_SDA_WIDTH 1
982	#define EF1_EEPROM_SCL_LBN 30
983	#define EF1_EEPROM_SCL_WIDTH 1
984	#define EF1_JTAG_DISCONNECT_LBN 17
985	#define EF1_JTAG_DISCONNECT_WIDTH 1
986
987	/** Control register 2 */
988	#define EF1_CTL2_REG 0x4c
989	#define EF1_PLL_TRAP_LBN 31
990	#define EF1_PLL_TRAP_WIDTH 1
991	#define EF1_MEM_MAP_4MB_LBN 11
992	#define EF1_MEM_MAP_4MB_WIDTH 1
993	#define EF1_EV_INTR_CLR_WRITE_LBN 6
994	#define EF1_EV_INTR_CLR_WRITE_WIDTH 1
995	#define EF1_BURST_MERGE_LBN 5
996	#define EF1_BURST_MERGE_WIDTH 1
997	#define EF1_CLEAR_NULL_PAD_LBN 4
998	#define EF1_CLEAR_NULL_PAD_WIDTH 1
999	#define EF1_SW_RESET_LBN 2
1000	#define EF1_SW_RESET_WIDTH 1
1001	#define EF1_INTR_AFTER_EVENT_LBN 1
1002	#define EF1_INTR_AFTER_EVENT_WIDTH 1
1003
1004	/** Event FIFO */
1005	#define EF1_EVENT_FIFO_REG 0x50
1006
1007	/** Event FIFO count */
1008	#define EF1_EVENT_FIFO_COUNT_REG 0x5c
1009	#define EF1_EV_COUNT_LBN 0
1010	#define EF1_EV_COUNT_WIDTH 16
1011
1012	/** TX DMA control and status */
1013	#define EF1_DMA_TX_CSR_REG 0x80
1014	#define EF1_DMA_TX_CSR_CHAIN_EN_LBN 8
1015	#define EF1_DMA_TX_CSR_CHAIN_EN_WIDTH 1
1016	#define EF1_DMA_TX_CSR_ENABLE_LBN 4
1017	#define EF1_DMA_TX_CSR_ENABLE_WIDTH 1
1018	#define EF1_DMA_TX_CSR_INT_EN_LBN 0
1019	#define EF1_DMA_TX_CSR_INT_EN_WIDTH 1
1020
1021	/** RX DMA control and status */
1022	#define EF1_DMA_RX_CSR_REG 0xa0
1023	#define EF1_DMA_RX_ABOVE_1GB_EN_LBN 6
1024	#define EF1_DMA_RX_ABOVE_1GB_EN_WIDTH 1
1025	#define EF1_DMA_RX_BELOW_1MB_EN_LBN 5
1026	#define EF1_DMA_RX_BELOW_1MB_EN_WIDTH 1
1027	#define EF1_DMA_RX_CSR_ENABLE_LBN 0
1028	#define EF1_DMA_RX_CSR_ENABLE_WIDTH 1
1029
1030	/** Level 5 watermark register (in MAC space) */
1031	#define EF1_GMF_L5WM_REG_MAC 0x20
1032	#define EF1_L5WM_LBN 0
1033	#define EF1_L5WM_WIDTH 32
1034
1035	/** MAC clock */
1036	#define EF1_GM_MAC_CLK_REG 0x112000
1037	#define EF1_GM_PORT0_MAC_CLK_LBN 0
1038	#define EF1_GM_PORT0_MAC_CLK_WIDTH 1
1039	#define EF1_GM_PORT1_MAC_CLK_LBN 1
1040	#define EF1_GM_PORT1_MAC_CLK_WIDTH 1
1041
1042	/** TX descriptor FIFO */
1043	#define EF1_TX_DESC_FIFO 0x141000
1044	#define EF1_TX_KER_EVQ_LBN 80
1045	#define EF1_TX_KER_EVQ_WIDTH 12
1046	#define EF1_TX_KER_IDX_LBN 64
1047	#define EF1_TX_KER_IDX_WIDTH 16
1048	#define EF1_TX_KER_MODE_LBN 63
1049	#define EF1_TX_KER_MODE_WIDTH 1
1050	#define EF1_TX_KER_PORT_LBN 60
1051	#define EF1_TX_KER_PORT_WIDTH 1
1052	#define EF1_TX_KER_CONT_LBN 56
1053	#define EF1_TX_KER_CONT_WIDTH 1
1054	#define EF1_TX_KER_BYTE_CNT_LBN 32
1055	#define EF1_TX_KER_BYTE_CNT_WIDTH 24
1056	#define EF1_TX_KER_BUF_ADR_LBN 0
1057	#define EF1_TX_KER_BUF_ADR_WIDTH 32
1058
1059	/** TX descriptor FIFO flush */
1060	#define EF1_TX_DESC_FIFO_FLUSH 0x141ffc
1061
1062	/** RX descriptor FIFO */
1063	#define EF1_RX_DESC_FIFO 0x145000
1064	#define EF1_RX_KER_EVQ_LBN 48
1065	#define EF1_RX_KER_EVQ_WIDTH 12
1066	#define EF1_RX_KER_IDX_LBN 32
1067	#define EF1_RX_KER_IDX_WIDTH 16
1068	#define EF1_RX_KER_BUF_ADR_LBN 0
1069	#define EF1_RX_KER_BUF_ADR_WIDTH 32
1070
1071	/** RX descriptor FIFO flush */
1072	#define EF1_RX_DESC_FIFO_FLUSH 0x145ffc
1073
1074	/** CAM */
1075	#define EF1_CAM_BASE 0x1c0000
1076	#define EF1_CAM_WTF_DOES_THIS_DO_LBN 0
1077	#define EF1_CAM_WTF_DOES_THIS_DO_WIDTH 32
1078
1079	/** Event queue pointers */
1080	#define EF1_EVQ_PTR_BASE 0x260000
1081	#define EF1_EVQ_SIZE_LBN 29
1082	#define EF1_EVQ_SIZE_WIDTH 2
1083	#define EF1_EVQ_SIZE_4K 3
1084	#define EF1_EVQ_SIZE_2K 2
1085	#define EF1_EVQ_SIZE_1K 1
1086	#define EF1_EVQ_SIZE_512 0
1087	#define EF1_EVQ_BUF_BASE_ID_LBN 0
1088	#define EF1_EVQ_BUF_BASE_ID_WIDTH 29
1089
1090	/* MAC registers */
1091	#define EF1002_MAC_REGBANK 0x110000
1092	#define EF1002_MAC_REGBANK_SIZE 0x1000
1093	#define EF1002_MAC_REG_SIZE 0x08
1094
1095	/** Offset of a MAC register within EF1002 */
1096	#define EF1002_MAC_REG( efab, mac_reg ) \
1097	( EF1002_MAC_REGBANK + \
1098	( (efab)->port * EF1002_MAC_REGBANK_SIZE ) + \
1099	( (mac_reg) * EF1002_MAC_REG_SIZE ) )
1100
1101	/* Event queue entries */
1102	#define EF1_EV_CODE_LBN 20
1103	#define EF1_EV_CODE_WIDTH 8
1104	#define EF1_RX_EV_DECODE 0x01
1105	#define EF1_TX_EV_DECODE 0x02
1106	#define EF1_TIMER_EV_DECODE 0x0b
1107	#define EF1_DRV_GEN_EV_DECODE 0x0f
1108
1109	/* Receive events */
1110	#define EF1_RX_EV_LEN_LBN 48
1111	#define EF1_RX_EV_LEN_WIDTH 16
1112	#define EF1_RX_EV_PORT_LBN 17
1113	#define EF1_RX_EV_PORT_WIDTH 3
1114	#define EF1_RX_EV_OK_LBN 16
1115	#define EF1_RX_EV_OK_WIDTH 1
1116	#define EF1_RX_EV_IDX_LBN 0
1117	#define EF1_RX_EV_IDX_WIDTH 16
1118
1119	/* Transmit events */
1120	#define EF1_TX_EV_PORT_LBN 17
1121	#define EF1_TX_EV_PORT_WIDTH 3
1122	#define EF1_TX_EV_OK_LBN 16
1123	#define EF1_TX_EV_OK_WIDTH 1
1124	#define EF1_TX_EV_IDX_LBN 0
1125	#define EF1_TX_EV_IDX_WIDTH 16
1126
1127	/**
1128	* Write dword to EF1002 register
1129	*
1130	*/
1131	static inline void ef1002_writel ( struct efab_nic efab, efab_dword_t value,
1132	unsigned int reg ) {
1133	EFAB_REGDUMP ( "Writing register %x with " EFAB_DWORD_FMT "\n",
1134	reg, EFAB_DWORD_VAL ( *value ) );
1135	writel ( value->u32[0], efab->membase + reg );
1136	}
1137
1138	/**
1139	* Read dword from an EF1002 register
1140	*
1141	*/
1142	static inline void ef1002_readl ( struct efab_nic efab, efab_dword_t value,
1143	unsigned int reg ) {
1144	value->u32[0] = readl ( efab->membase + reg );
1145	EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n",
1146	reg, EFAB_DWORD_VAL ( *value ) );
1147	}
1148
1149	/**
1150	* Read dword from an EF1002 register, silently
1151	*
1152	*/
1153	static inline void ef1002_readl_silent ( struct efab_nic *efab,
1154	efab_dword_t *value,
1155	unsigned int reg ) {
1156	value->u32[0] = readl ( efab->membase + reg );
1157	}
1158
1159	/**
1160	* Get memory base
1161	*
1162	*/
1163	static void ef1002_get_membase ( struct efab_nic *efab ) {
1164	unsigned long membase_phys;
1165
1166	membase_phys = pci_bar_start ( efab->pci, PCI_BASE_ADDRESS_0 );
1167	efab->membase = ioremap ( membase_phys, 0x800000 );
1168	}
1169
1170	/** PCI registers to backup/restore over a device reset */
1171	static const unsigned int efab_pci_reg_addr[] = {
1172	PCI_COMMAND, 0x0c /* PCI_CACHE_LINE_SIZE */,
1173	PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
1174	PCI_BASE_ADDRESS_3, PCI_ROM_ADDRESS, PCI_INTERRUPT_LINE,
1175	};
1176	/** Number of registers in efab_pci_reg_addr */
1177	#define EFAB_NUM_PCI_REG \
1178	( sizeof ( efab_pci_reg_addr ) / sizeof ( efab_pci_reg_addr[0] ) )
1179	/** PCI configuration space backup */
1180	struct efab_pci_reg {
1181	uint32_t reg[EFAB_NUM_PCI_REG];
1182	};
1183
1184	/**
1185	* Reset device
1186	*
1187	*/
1188	static int ef1002_reset ( struct efab_nic *efab ) {
1189	struct efab_pci_reg pci_reg;
1190	struct pci_device *pci_dev = efab->pci;
1191	efab_dword_t reg;
1192	unsigned int i;
1193	uint32_t tmp;
1194
1195	/* Back up PCI configuration registers */
1196	for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
1197	pci_read_config_dword ( pci_dev, efab_pci_reg_addr[i],
1198	&pci_reg.reg[i] );
1199	}
1200
1201	/* Reset the whole device. */
1202	EFAB_POPULATE_DWORD_1 ( reg, EF1_SW_RESET, 1 );
1203	ef1002_writel ( efab, &reg, EF1_CTL2_REG );
1204	mdelay ( 200 );
1205
1206	/* Restore PCI configuration space */
1207	for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
1208	pci_write_config_dword ( pci_dev, efab_pci_reg_addr[i],
1209	pci_reg.reg[i] );
1210	}
1211
1212	/* Verify PCI configuration space */
1213	for ( i = 0 ; i < EFAB_NUM_PCI_REG ; i++ ) {
1214	pci_read_config_dword ( pci_dev, efab_pci_reg_addr[i], &tmp );
1215	if ( tmp != pci_reg.reg[i] ) {
1216	printf ( "PCI restore failed on register %02x "
1217	"(is %08x, should be %08x); reboot\n",
1218	i, tmp, pci_reg.reg[i] );
1219	return 0;
1220	}
1221	}
1222
1223	/* Verify device reset complete */
1224	ef1002_readl ( efab, &reg, EF1_CTR_GEN_STATUS0_REG );
1225	if ( EFAB_DWORD_IS_ALL_ONES ( reg ) ) {
1226	printf ( "Reset failed\n" );
1227	return 0;
1228	}
1229
1230	return 1;
1231	}
1232
1233	/**
1234	* Initialise NIC
1235	*
1236	*/
1237	static int ef1002_init_nic ( struct efab_nic *efab ) {
1238	efab_dword_t reg;
1239
1240	/* No idea what CAM is, but the 'datasheet' says that we have
1241	* to write these values in at start of day
1242	*/
1243	EFAB_POPULATE_DWORD_1 ( reg, EF1_CAM_WTF_DOES_THIS_DO, 0x6 );
1244	ef1002_writel ( efab, &reg, EF1_CAM_BASE + 0x20018 );
1245	udelay ( 1000 );
1246	EFAB_POPULATE_DWORD_1 ( reg, EF1_CAM_WTF_DOES_THIS_DO, 0x01000000 );
1247	ef1002_writel ( efab, &reg, EF1_CAM_BASE + 0x00018 );
1248	udelay ( 1000 );
1249
1250	/* General control register 0 */
1251	ef1002_readl ( efab, &reg, EF1_CTR_GEN_STATUS0_REG );
1252	EFAB_SET_DWORD_FIELD ( reg, EF1_MASTER_EVENTS, 0 );
1253	EFAB_SET_DWORD_FIELD ( reg, EF1_TX_ENGINE_EN, 0 );
1254	EFAB_SET_DWORD_FIELD ( reg, EF1_RX_ENGINE_EN, 0 );
1255	EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO2, 1 );
1256	EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO1, 1 );
1257	EFAB_SET_DWORD_FIELD ( reg, EF1_TURBO3, 1 );
1258	EFAB_SET_DWORD_FIELD ( reg, EF1_CAM_ENABLE, 1 );
1259	ef1002_writel ( efab, &reg, EF1_CTR_GEN_STATUS0_REG );
1260	udelay ( 1000 );
1261
1262	/* General control register 2 */
1263	ef1002_readl ( efab, &reg, EF1_CTL2_REG );
1264	EFAB_SET_DWORD_FIELD ( reg, EF1_PLL_TRAP, 1 );
1265	EFAB_SET_DWORD_FIELD ( reg, EF1_MEM_MAP_4MB, 0 );
1266	EFAB_SET_DWORD_FIELD ( reg, EF1_EV_INTR_CLR_WRITE, 0 );
1267	EFAB_SET_DWORD_FIELD ( reg, EF1_BURST_MERGE, 0 );
1268	EFAB_SET_DWORD_FIELD ( reg, EF1_CLEAR_NULL_PAD, 1 );
1269	EFAB_SET_DWORD_FIELD ( reg, EF1_INTR_AFTER_EVENT, 1 );
1270	ef1002_writel ( efab, &reg, EF1_CTL2_REG );
1271	udelay ( 1000 );
1272
1273	/* Enable RX DMA */
1274	ef1002_readl ( efab, &reg, EF1_DMA_RX_CSR_REG );
1275	EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_RX_CSR_ENABLE, 1 );
1276	EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_RX_BELOW_1MB_EN, 1 );
1277	EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_RX_ABOVE_1GB_EN, 1 );
1278	ef1002_writel ( efab, &reg, EF1_DMA_RX_CSR_REG );
1279	udelay ( 1000 );
1280
1281	/* Enable TX DMA */
1282	ef1002_readl ( efab, &reg, EF1_DMA_TX_CSR_REG );
1283	EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_TX_CSR_CHAIN_EN, 1 );
1284	EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_TX_CSR_ENABLE, 0 /* ?? */ );
1285	EFAB_SET_DWORD_FIELD ( reg, EF1_DMA_TX_CSR_INT_EN, 0 /* ?? */ );
1286	ef1002_writel ( efab, &reg, EF1_DMA_TX_CSR_REG );
1287	udelay ( 1000 );
1288
1289	/* Disconnect the JTAG chain. Read-modify-write is impossible
1290	* on the I2C control bits, since reading gives the state of
1291	* the line inputs rather than the last written state.
1292	*/
1293	ef1002_readl ( efab, &reg, EF1_EEPROM_REG );
1294	EFAB_SET_DWORD_FIELD ( reg, EF1_EEPROM_SDA, 1 );
1295	EFAB_SET_DWORD_FIELD ( reg, EF1_EEPROM_SCL, 1 );
1296	EFAB_SET_DWORD_FIELD ( reg, EF1_JTAG_DISCONNECT, 1 );
1297	ef1002_writel ( efab, &reg, EF1_EEPROM_REG );
1298	udelay ( 10 );
1299
1300	/* Flush descriptor queues */
1301	EFAB_ZERO_DWORD ( reg );
1302	ef1002_writel ( efab, &reg, EF1_RX_DESC_FIFO_FLUSH );
1303	ef1002_writel ( efab, &reg, EF1_TX_DESC_FIFO_FLUSH );
1304	wmb();
1305	udelay ( 10000 );
1306
1307	/* Reset MAC */
1308	mentormac_reset ( efab );
1309
1310	return 1;
1311	}
1312
1313	/** I2C ID of the EEPROM */
1314	#define EF1002_EEPROM_I2C_ID 0x50
1315
1316	/** Offset of MAC address within EEPROM */
1317	#define EF1002_EEPROM_HWADDR_OFFSET 0x0
1318
1319	/** Set status of i2c outputs */
1320	static void ef1002_setsdascl ( struct efab_i2c_interface *i2c ) {
1321	efab_dword_t eeprom_reg;
1322
1323	EFAB_POPULATE_DWORD_2 ( eeprom_reg,
1324	EF1_EEPROM_SDA, i2c->sda,
1325	EF1_EEPROM_SCL, i2c->scl );
1326	ef1002_writel ( i2c->efab, &eeprom_reg, EF1_EEPROM_REG );
1327	}
1328
1329	/** Get status of i2c SDA line */
1330	static int ef1002_getsda ( struct efab_i2c_interface *i2c ) {
1331	efab_dword_t eeprom_reg;
1332
1333	ef1002_readl ( i2c->efab, &eeprom_reg, EF1_EEPROM_REG );
1334	return EFAB_DWORD_FIELD ( eeprom_reg, EF1_EEPROM_SDA );
1335	}
1336
1337	/** Get status of i2c SCL line */
1338	static int ef1002_getscl ( struct efab_i2c_interface *i2c ) {
1339	efab_dword_t eeprom_reg;
1340
1341	ef1002_readl ( i2c->efab, &eeprom_reg, EF1_EEPROM_REG );
1342	return EFAB_DWORD_FIELD ( eeprom_reg, EF1_EEPROM_SCL );
1343	}
1344
1345	/** i2c bit-bashing data structure template */
1346	static struct efab_i2c_bit_operations ef1002_i2c_bit_operations = {
1347	.setsda = ef1002_setsdascl,
1348	.setscl = ef1002_setsdascl,
1349	.getsda = ef1002_getsda,
1350	.getscl = ef1002_getscl,
1351	.udelay = 20,
1352	.mdelay = 10,
1353	};
1354
1355	/**
1356	* Read MAC address from EEPROM
1357	*
1358	*/
1359	static int ef1002_read_eeprom ( struct efab_nic *efab ) {
1360	struct efab_i2c_interface i2c = {
1361	.efab = efab,
1362	.op = &ef1002_i2c_bit_operations,
1363	.sda = 1,
1364	.scl = 1,
1365	};
1366
1367	if ( ! efab_i2c_fast_read ( &i2c, EF1002_EEPROM_I2C_ID,
1368	EF1002_EEPROM_HWADDR_OFFSET,
1369	efab->mac_addr, ETH_ALEN ) )
1370	return 0;
1371	efab->mac_addr[ETH_ALEN-1] += efab->port;
1372	return 1;
1373	}
1374
1375	/** RX descriptor */
1376	typedef efab_qword_t ef1002_rx_desc_t;
1377
1378	/**
1379	* Build RX descriptor
1380	*
1381	*/
1382	static void ef1002_build_rx_desc ( struct efab_nic *efab,
1383	struct efab_rx_buf *rx_buf ) {
1384	ef1002_rx_desc_t rxd;
1385
1386	EFAB_POPULATE_QWORD_3 ( rxd,
1387	EF1_RX_KER_EVQ, 0,
1388	EF1_RX_KER_IDX, rx_buf->id,
1389	EF1_RX_KER_BUF_ADR,
1390	virt_to_bus ( rx_buf->addr ) );
1391	ef1002_writel ( efab, &rxd.dword[0], EF1_RX_DESC_FIFO + 0 );
1392	wmb();
1393	ef1002_writel ( efab, &rxd.dword[1], EF1_RX_DESC_FIFO + 4 );
1394	udelay ( 10 );
1395	}
1396
1397	/**
1398	* Update RX descriptor write pointer
1399	*
1400	*/
1401	static void ef1002_notify_rx_desc ( struct efab_nic *efab __unused ) {
1402	/* Nothing to do */
1403	}
1404
1405	/** TX descriptor */
1406	typedef efab_oword_t ef1002_tx_desc_t;
1407
1408	/**
1409	* Build TX descriptor
1410	*
1411	*/
1412	static void ef1002_build_tx_desc ( struct efab_nic *efab,
1413	struct efab_tx_buf *tx_buf ) {
1414	ef1002_tx_desc_t txd;
1415
1416	EFAB_POPULATE_OWORD_7 ( txd,
1417	EF1_TX_KER_EVQ, 0,
1418	EF1_TX_KER_IDX, tx_buf->id,
1419	EF1_TX_KER_MODE, 0 /* IP mode */,
1420	EF1_TX_KER_PORT, efab->port,
1421	EF1_TX_KER_CONT, 0,
1422	EF1_TX_KER_BYTE_CNT, tx_buf->len,
1423	EF1_TX_KER_BUF_ADR,
1424	virt_to_bus ( tx_buf->addr ) );
1425
1426	ef1002_writel ( efab, &txd.dword[0], EF1_TX_DESC_FIFO + 0 );
1427	ef1002_writel ( efab, &txd.dword[1], EF1_TX_DESC_FIFO + 4 );
1428	wmb();
1429	ef1002_writel ( efab, &txd.dword[2], EF1_TX_DESC_FIFO + 8 );
1430	udelay ( 10 );
1431	}
1432
1433	/**
1434	* Update TX descriptor write pointer
1435	*
1436	*/
1437	static void ef1002_notify_tx_desc ( struct efab_nic *efab __unused ) {
1438	/* Nothing to do */
1439	}
1440
1441	/** An event */
1442	typedef efab_qword_t ef1002_event_t;
1443
1444	/**
1445	* Retrieve event from event queue
1446	*
1447	*/
1448	static int ef1002_fetch_event ( struct efab_nic *efab,
1449	struct efab_event *event ) {
1450	efab_dword_t reg;
1451	int ev_code;
1452	int words;
1453
1454	/* Check event FIFO depth */
1455	ef1002_readl_silent ( efab, &reg, EF1_EVENT_FIFO_COUNT_REG );
1456	words = EFAB_DWORD_FIELD ( reg, EF1_EV_COUNT );
1457	if ( ! words )
1458	return 0;
1459
1460	/* Read event data */
1461	ef1002_readl ( efab, &reg, EF1_EVENT_FIFO_REG );
1462	DBG ( "Event is " EFAB_DWORD_FMT "\n", EFAB_DWORD_VAL ( reg ) );
1463
1464	/* Decode event */
1465	ev_code = EFAB_DWORD_FIELD ( reg, EF1_EV_CODE );
1466	switch ( ev_code ) {
1467	case EF1_TX_EV_DECODE:
1468	event->type = EFAB_EV_TX;
1469	break;
1470	case EF1_RX_EV_DECODE:
1471	event->type = EFAB_EV_RX;
1472	event->rx_id = EFAB_DWORD_FIELD ( reg, EF1_RX_EV_IDX );
1473	/* RX len not available via event FIFO */
1474	event->rx_len = ETH_FRAME_LEN;
1475	break;
1476	case EF1_TIMER_EV_DECODE:
1477	/* These are safe to ignore. We seem to get some at
1478	* start of day, presumably due to the timers starting
1479	* up with random contents.
1480	*/
1481	event->type = EFAB_EV_NONE;
1482	break;
1483	default:
1484	printf ( "Unknown event type %d\n", ev_code );
1485	event->type = EFAB_EV_NONE;
1486	}
1487
1488	/* Clear any pending interrupts */
1489	ef1002_readl ( efab, &reg, EF1_IRQ_SRC_REG );
1490
1491	return 1;
1492	}
1493
1494	/**
1495	* Enable/disable interrupts
1496	*
1497	*/
1498	static void ef1002_mask_irq ( struct efab_nic *efab, int enabled ) {
1499	efab_dword_t irq_mask;
1500
1501	EFAB_POPULATE_DWORD_2 ( irq_mask,
1502	EF1_IRQ_SERR, enabled,
1503	EF1_IRQ_EVQ, enabled );
1504	ef1002_writel ( efab, &irq_mask, EF1_IRQ_MASK_REG );
1505	}
1506
1507	/**
1508	* Generate interrupt
1509	*
1510	*/
1511	static void ef1002_generate_irq ( struct efab_nic *efab ) {
1512	ef1002_event_t test_event;
1513
1514	EFAB_POPULATE_QWORD_1 ( test_event,
1515	EF1_EV_CODE, EF1_DRV_GEN_EV_DECODE );
1516	ef1002_writel ( efab, &test_event.dword[0], EF1_EVT3_REG );
1517	}
1518
1519	/**
1520	* Write dword to an EF1002 MAC register
1521	*
1522	*/
1523	static void ef1002_mac_writel ( struct efab_nic *efab,
1524	efab_dword_t *value, unsigned int mac_reg ) {
1525	ef1002_writel ( efab, value, EF1002_MAC_REG ( efab, mac_reg ) );
1526	}
1527
1528	/**
1529	* Read dword from an EF1002 MAC register
1530	*
1531	*/
1532	static void ef1002_mac_readl ( struct efab_nic *efab,
1533	efab_dword_t *value, unsigned int mac_reg ) {
1534	ef1002_readl ( efab, value, EF1002_MAC_REG ( efab, mac_reg ) );
1535	}
1536
1537	/**
1538	* Initialise MAC
1539	*
1540	*/
1541	static int ef1002_init_mac ( struct efab_nic *efab ) {
1542	static struct efab_mentormac_parameters ef1002_mentormac_params = {
1543	.gmf_cfgfrth = 0x13,
1544	.gmf_cfgftth = 0x10,
1545	.gmf_cfghwmft = 0x555,
1546	.gmf_cfghwm = 0x2a,
1547	.gmf_cfglwm = 0x15,
1548	};
1549	efab_dword_t reg;
1550	unsigned int mac_clk;
1551
1552	/* Initialise PHY */
1553	alaska_init ( efab );
1554
1555	/* Initialise MAC */
1556	mentormac_init ( efab, &ef1002_mentormac_params );
1557
1558	/* Write Level 5 watermark register */
1559	EFAB_POPULATE_DWORD_1 ( reg, EF1_L5WM, 0x10040000 );
1560	efab->op->mac_writel ( efab, &reg, EF1_GMF_L5WM_REG_MAC );
1561	udelay ( 10 );
1562
1563	/* Set MAC clock speed */
1564	ef1002_readl ( efab, &reg, EF1_GM_MAC_CLK_REG );
1565	mac_clk = ( efab->link_options & LPA_1000 ) ? 0 : 1;
1566	if ( efab->port == 0 ) {
1567	EFAB_SET_DWORD_FIELD ( reg, EF1_GM_PORT0_MAC_CLK, mac_clk );
1568	} else {
1569	EFAB_SET_DWORD_FIELD ( reg, EF1_GM_PORT1_MAC_CLK, mac_clk );
1570	}
1571	ef1002_writel ( efab, &reg, EF1_GM_MAC_CLK_REG );
1572	udelay ( 10 );
1573
1574	return 1;
1575	}
1576
1577	/** MDIO write */
1578	static void ef1002_mdio_write ( struct efab_nic *efab, int location,
1579	int value ) {
1580	mentormac_mdio_write ( efab, efab->port + 2, location, value );
1581	}
1582
1583	/** MDIO read */
1584	static int ef1002_mdio_read ( struct efab_nic *efab, int location ) {
1585	return mentormac_mdio_read ( efab, efab->port + 2, location );
1586	}
1587
1588	static struct efab_operations ef1002_operations = {
1589	.get_membase = ef1002_get_membase,
1590	.reset = ef1002_reset,
1591	.init_nic = ef1002_init_nic,
1592	.read_eeprom = ef1002_read_eeprom,
1593	.build_rx_desc = ef1002_build_rx_desc,
1594	.notify_rx_desc = ef1002_notify_rx_desc,
1595	.build_tx_desc = ef1002_build_tx_desc,
1596	.notify_tx_desc = ef1002_notify_tx_desc,
1597	.fetch_event = ef1002_fetch_event,
1598	.mask_irq = ef1002_mask_irq,
1599	.generate_irq = ef1002_generate_irq,
1600	.mac_writel = ef1002_mac_writel,
1601	.mac_readl = ef1002_mac_readl,
1602	.init_mac = ef1002_init_mac,
1603	.mdio_write = ef1002_mdio_write,
1604	.mdio_read = ef1002_mdio_read,
1605	};
1606
1607	/**************************************************************************
1608	*
1609	* Falcon routines
1610	*
1611	**************************************************************************
1612	*/
1613
1614	/* I/O BAR address register */
1615	#define FCN_IOM_IND_ADR_REG 0x0
1616
1617	/* I/O BAR data register */
1618	#define FCN_IOM_IND_DAT_REG 0x4
1619
1620	/* Interrupt enable register */
1621	#define FCN_INT_EN_REG_KER 0x0010
1622	#define FCN_MEM_PERR_INT_EN_KER_LBN 5
1623	#define FCN_MEM_PERR_INT_EN_KER_WIDTH 1
1624	#define FCN_KER_INT_CHAR_LBN 4
1625	#define FCN_KER_INT_CHAR_WIDTH 1
1626	#define FCN_KER_INT_KER_LBN 3
1627	#define FCN_KER_INT_KER_WIDTH 1
1628	#define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2
1629	#define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1
1630	#define FCN_SRM_PERR_INT_EN_KER_LBN 1
1631	#define FCN_SRM_PERR_INT_EN_KER_WIDTH 1
1632	#define FCN_DRV_INT_EN_KER_LBN 0
1633	#define FCN_DRV_INT_EN_KER_WIDTH 1
1634
1635	/* Interrupt status register */
1636	#define FCN_INT_ADR_REG_KER 0x0030
1637	#define FCN_INT_ADR_KER_LBN 0
1638	#define FCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 )
1639
1640	/* Interrupt acknowledge register */
1641	#define FCN_INT_ACK_KER_REG 0x0050
1642
1643	/* SPI host command register */
1644	#define FCN_EE_SPI_HCMD_REG_KER 0x0100
1645	#define FCN_EE_SPI_HCMD_CMD_EN_LBN 31
1646	#define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1
1647	#define FCN_EE_WR_TIMER_ACTIVE_LBN 28
1648	#define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1
1649	#define FCN_EE_SPI_HCMD_SF_SEL_LBN 24
1650	#define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1
1651	#define FCN_EE_SPI_EEPROM 0
1652	#define FCN_EE_SPI_FLASH 1
1653	#define FCN_EE_SPI_HCMD_DABCNT_LBN 16
1654	#define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5
1655	#define FCN_EE_SPI_HCMD_READ_LBN 15
1656	#define FCN_EE_SPI_HCMD_READ_WIDTH 1
1657	#define FCN_EE_SPI_READ 1
1658	#define FCN_EE_SPI_WRITE 0
1659	#define FCN_EE_SPI_HCMD_DUBCNT_LBN 12
1660	#define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2
1661	#define FCN_EE_SPI_HCMD_ADBCNT_LBN 8
1662	#define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2
1663	#define FCN_EE_SPI_HCMD_ENC_LBN 0
1664	#define FCN_EE_SPI_HCMD_ENC_WIDTH 8
1665
1666	/* SPI host address register */
1667	#define FCN_EE_SPI_HADR_REG_KER 0x0110
1668	#define FCN_EE_SPI_HADR_DUBYTE_LBN 24
1669	#define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8
1670	#define FCN_EE_SPI_HADR_ADR_LBN 0
1671	#define FCN_EE_SPI_HADR_ADR_WIDTH 24
1672
1673	/* SPI host data register */
1674	#define FCN_EE_SPI_HDATA_REG_KER 0x0120
1675	#define FCN_EE_SPI_HDATA3_LBN 96
1676	#define FCN_EE_SPI_HDATA3_WIDTH 32
1677	#define FCN_EE_SPI_HDATA2_LBN 64
1678	#define FCN_EE_SPI_HDATA2_WIDTH 32
1679	#define FCN_EE_SPI_HDATA1_LBN 32
1680	#define FCN_EE_SPI_HDATA1_WIDTH 32
1681	#define FCN_EE_SPI_HDATA0_LBN 0
1682	#define FCN_EE_SPI_HDATA0_WIDTH 32
1683
1684	/* GPIO control register */
1685	#define FCN_GPIO_CTL_REG_KER 0x0210
1686	#define FCN_FLASH_PRESENT_LBN 7
1687	#define FCN_FLASH_PRESENT_WIDTH 1
1688	#define FCN_EEPROM_PRESENT_LBN 6
1689	#define FCN_EEPROM_PRESENT_WIDTH 1
1690
1691	/* Global control register */
1692	#define FCN_GLB_CTL_REG_KER 0x0220
1693	#define FCN_EXT_PHY_RST_CTL_LBN 63
1694	#define FCN_EXT_PHY_RST_CTL_WIDTH 1
1695	#define FCN_PCIE_SD_RST_CTL_LBN 61
1696	#define FCN_PCIE_SD_RST_CTL_WIDTH 1
1697	#define FCN_PCIX_RST_CTL_LBN 60
1698	#define FCN_PCIX_RST_CTL_WIDTH 1
1699	#define FCN_RST_EXT_PHY_LBN 31
1700	#define FCN_RST_EXT_PHY_WIDTH 1
1701	#define FCN_INT_RST_DUR_LBN 4
1702	#define FCN_INT_RST_DUR_WIDTH 3
1703	#define FCN_EXT_PHY_RST_DUR_LBN 1
1704	#define FCN_EXT_PHY_RST_DUR_WIDTH 3
1705	#define FCN_SWRST_LBN 0
1706	#define FCN_SWRST_WIDTH 1
1707	#define FCN_INCLUDE_IN_RESET 0
1708	#define FCN_EXCLUDE_FROM_RESET 1
1709
1710	/* Timer table for kernel access */
1711	#define FCN_TIMER_CMD_REG_KER 0x420
1712	#define FCN_TIMER_MODE_LBN 12
1713	#define FCN_TIMER_MODE_WIDTH 2
1714	#define FCN_TIMER_MODE_DIS 0
1715	#define FCN_TIMER_MODE_INT_HLDOFF 1
1716	#define FCN_TIMER_VAL_LBN 0
1717	#define FCN_TIMER_VAL_WIDTH 12
1718
1719	/* SRAM receive descriptor cache configuration register */
1720	#define FCN_SRM_RX_DC_CFG_REG_KER 0x610
1721	#define FCN_SRM_RX_DC_BASE_ADR_LBN 0
1722	#define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21
1723
1724	/* SRAM transmit descriptor cache configuration register */
1725	#define FCN_SRM_TX_DC_CFG_REG_KER 0x620
1726	#define FCN_SRM_TX_DC_BASE_ADR_LBN 0
1727	#define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21
1728
1729	/* Receive filter control register */
1730	#define FCN_RX_FILTER_CTL_REG_KER 0x810
1731	#define FCN_NUM_KER_LBN 24
1732	#define FCN_NUM_KER_WIDTH 2
1733
1734	/* Receive descriptor update register */
1735	#define FCN_RX_DESC_UPD_REG_KER 0x0830
1736	#define FCN_RX_DESC_WPTR_LBN 96
1737	#define FCN_RX_DESC_WPTR_WIDTH 12
1738	#define FCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 )
1739	#define FCN_RX_DESC_WPTR_DWORD_LBN 0
1740	#define FCN_RX_DESC_WPTR_DWORD_WIDTH 12
1741
1742	/* Receive descriptor cache configuration register */
1743	#define FCN_RX_DC_CFG_REG_KER 0x840
1744	#define FCN_RX_DC_SIZE_LBN 0
1745	#define FCN_RX_DC_SIZE_WIDTH 2
1746
1747	/* Transmit descriptor update register */
1748	#define FCN_TX_DESC_UPD_REG_KER 0x0a10
1749	#define FCN_TX_DESC_WPTR_LBN 96
1750	#define FCN_TX_DESC_WPTR_WIDTH 12
1751	#define FCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 )
1752	#define FCN_TX_DESC_WPTR_DWORD_LBN 0
1753	#define FCN_TX_DESC_WPTR_DWORD_WIDTH 12
1754
1755	/* Transmit descriptor cache configuration register */
1756	#define FCN_TX_DC_CFG_REG_KER 0xa20
1757	#define FCN_TX_DC_SIZE_LBN 0
1758	#define FCN_TX_DC_SIZE_WIDTH 2
1759
1760	/* PHY management transmit data register */
1761	#define FCN_MD_TXD_REG_KER 0xc00
1762	#define FCN_MD_TXD_LBN 0
1763	#define FCN_MD_TXD_WIDTH 16
1764
1765	/* PHY management receive data register */
1766	#define FCN_MD_RXD_REG_KER 0xc10
1767	#define FCN_MD_RXD_LBN 0
1768	#define FCN_MD_RXD_WIDTH 16
1769
1770	/* PHY management configuration & status register */
1771	#define FCN_MD_CS_REG_KER 0xc20
1772	#define FCN_MD_GC_LBN 4
1773	#define FCN_MD_GC_WIDTH 1
1774	#define FCN_MD_RIC_LBN 2
1775	#define FCN_MD_RIC_WIDTH 1
1776	#define FCN_MD_WRC_LBN 0
1777	#define FCN_MD_WRC_WIDTH 1
1778
1779	/* PHY management PHY address register */
1780	#define FCN_MD_PHY_ADR_REG_KER 0xc30
1781	#define FCN_MD_PHY_ADR_LBN 0
1782	#define FCN_MD_PHY_ADR_WIDTH 16
1783
1784	/* PHY management ID register */
1785	#define FCN_MD_ID_REG_KER 0xc40
1786	#define FCN_MD_PRT_ADR_LBN 11
1787	#define FCN_MD_PRT_ADR_WIDTH 5
1788	#define FCN_MD_DEV_ADR_LBN 6
1789	#define FCN_MD_DEV_ADR_WIDTH 5
1790
1791	/* PHY management status & mask register */
1792	#define FCN_MD_STAT_REG_KER 0xc50
1793	#define FCN_MD_BSY_LBN 0
1794	#define FCN_MD_BSY_WIDTH 1
1795
1796	/* Port 0 and 1 MAC control registers */
1797	#define FCN_MAC0_CTRL_REG_KER 0xc80
1798	#define FCN_MAC1_CTRL_REG_KER 0xc90
1799	#define FCN_MAC_XOFF_VAL_LBN 16
1800	#define FCN_MAC_XOFF_VAL_WIDTH 16
1801	#define FCN_MAC_BCAD_ACPT_LBN 4
1802	#define FCN_MAC_BCAD_ACPT_WIDTH 1
1803	#define FCN_MAC_UC_PROM_LBN 3
1804	#define FCN_MAC_UC_PROM_WIDTH 1
1805	#define FCN_MAC_LINK_STATUS_LBN 2
1806	#define FCN_MAC_LINK_STATUS_WIDTH 1
1807	#define FCN_MAC_SPEED_LBN 0
1808	#define FCN_MAC_SPEED_WIDTH 2
1809
1810	/* XGMAC global configuration - port 0*/
1811	#define FCN_XM_GLB_CFG_REG_P0_KER 0x1220
1812	#define FCN_XM_RX_STAT_EN_LBN 11
1813	#define FCN_XM_RX_STAT_EN_WIDTH 1
1814	#define FCN_XM_TX_STAT_EN_LBN 10
1815	#define FCN_XM_TX_STAT_EN_WIDTH 1
1816	#define FCN_XM_CUT_THRU_MODE_LBN 7
1817	#define FCN_XM_CUT_THRU_MODE_WIDTH 1
1818	#define FCN_XM_RX_JUMBO_MODE_LBN 6
1819	#define FCN_XM_RX_JUMBO_MODE_WIDTH 1
1820
1821	/* XGMAC transmit configuration - port 0 */
1822	#define FCN_XM_TX_CFG_REG_P0_KER 0x1230
1823	#define FCN_XM_IPG_LBN 16
1824	#define FCN_XM_IPG_WIDTH 4
1825	#define FCN_XM_WTF_DOES_THIS_DO_LBN 9
1826	#define FCN_XM_WTF_DOES_THIS_DO_WIDTH 1
1827	#define FCN_XM_TXCRC_LBN 8
1828	#define FCN_XM_TXCRC_WIDTH 1
1829	#define FCN_XM_AUTO_PAD_LBN 5
1830	#define FCN_XM_AUTO_PAD_WIDTH 1
1831	#define FCN_XM_TX_PRMBL_LBN 2
1832	#define FCN_XM_TX_PRMBL_WIDTH 1
1833	#define FCN_XM_TXEN_LBN 1
1834	#define FCN_XM_TXEN_WIDTH 1
1835
1836	/* XGMAC receive configuration - port 0 */
1837	#define FCN_XM_RX_CFG_REG_P0_KER 0x1240
1838	#define FCN_XM_PASS_CRC_ERR_LBN 25
1839	#define FCN_XM_PASS_CRC_ERR_WIDTH 1
1840	#define FCN_XM_AUTO_DEPAD_LBN 8
1841	#define FCN_XM_AUTO_DEPAD_WIDTH 1
1842	#define FCN_XM_RXEN_LBN 1
1843	#define FCN_XM_RXEN_WIDTH 1
1844
1845	/* Receive descriptor pointer table */
1846	#define FCN_RX_DESC_PTR_TBL_KER 0x11800
1847	#define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36
1848	#define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20
1849	#define FCN_RX_DESCQ_EVQ_ID_LBN 24
1850	#define FCN_RX_DESCQ_EVQ_ID_WIDTH 12
1851	#define FCN_RX_DESCQ_OWNER_ID_LBN 10
1852	#define FCN_RX_DESCQ_OWNER_ID_WIDTH 14
1853	#define FCN_RX_DESCQ_SIZE_LBN 3
1854	#define FCN_RX_DESCQ_SIZE_WIDTH 2
1855	#define FCN_RX_DESCQ_SIZE_4K 3
1856	#define FCN_RX_DESCQ_SIZE_2K 2
1857	#define FCN_RX_DESCQ_SIZE_1K 1
1858	#define FCN_RX_DESCQ_SIZE_512 0
1859	#define FCN_RX_DESCQ_TYPE_LBN 2
1860	#define FCN_RX_DESCQ_TYPE_WIDTH 1
1861	#define FCN_RX_DESCQ_JUMBO_LBN 1
1862	#define FCN_RX_DESCQ_JUMBO_WIDTH 1
1863	#define FCN_RX_DESCQ_EN_LBN 0
1864	#define FCN_RX_DESCQ_EN_WIDTH 1
1865
1866	/* Transmit descriptor pointer table */
1867	#define FCN_TX_DESC_PTR_TBL_KER 0x11900
1868	#define FCN_TX_DESCQ_EN_LBN 88
1869	#define FCN_TX_DESCQ_EN_WIDTH 1
1870	#define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36
1871	#define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20
1872	#define FCN_TX_DESCQ_EVQ_ID_LBN 24
1873	#define FCN_TX_DESCQ_EVQ_ID_WIDTH 12
1874	#define FCN_TX_DESCQ_OWNER_ID_LBN 10
1875	#define FCN_TX_DESCQ_OWNER_ID_WIDTH 14
1876	#define FCN_TX_DESCQ_SIZE_LBN 3
1877	#define FCN_TX_DESCQ_SIZE_WIDTH 2
1878	#define FCN_TX_DESCQ_SIZE_4K 3
1879	#define FCN_TX_DESCQ_SIZE_2K 2
1880	#define FCN_TX_DESCQ_SIZE_1K 1
1881	#define FCN_TX_DESCQ_SIZE_512 0
1882	#define FCN_TX_DESCQ_TYPE_LBN 1
1883	#define FCN_TX_DESCQ_TYPE_WIDTH 2
1884	#define FCN_TX_DESCQ_FLUSH_LBN 0
1885	#define FCN_TX_DESCQ_FLUSH_WIDTH 1
1886
1887	/* Event queue pointer */
1888	#define FCN_EVQ_PTR_TBL_KER 0x11a00
1889	#define FCN_EVQ_EN_LBN 23
1890	#define FCN_EVQ_EN_WIDTH 1
1891	#define FCN_EVQ_SIZE_LBN 20
1892	#define FCN_EVQ_SIZE_WIDTH 3
1893	#define FCN_EVQ_SIZE_32K 6
1894	#define FCN_EVQ_SIZE_16K 5
1895	#define FCN_EVQ_SIZE_8K 4
1896	#define FCN_EVQ_SIZE_4K 3
1897	#define FCN_EVQ_SIZE_2K 2
1898	#define FCN_EVQ_SIZE_1K 1
1899	#define FCN_EVQ_SIZE_512 0
1900	#define FCN_EVQ_BUF_BASE_ID_LBN 0
1901	#define FCN_EVQ_BUF_BASE_ID_WIDTH 20
1902
1903	/* Event queue read pointer */
1904	#define FCN_EVQ_RPTR_REG_KER 0x11b00
1905	#define FCN_EVQ_RPTR_LBN 0
1906	#define FCN_EVQ_RPTR_WIDTH 14
1907	#define FCN_EVQ_RPTR_REG_KER_DWORD ( FCN_EVQ_RPTR_REG_KER + 0 )
1908	#define FCN_EVQ_RPTR_DWORD_LBN 0
1909	#define FCN_EVQ_RPTR_DWORD_WIDTH 14
1910
1911	/* Special buffer descriptors */
1912	#define FCN_BUF_FULL_TBL_KER 0x18000
1913	#define FCN_IP_DAT_BUF_SIZE_LBN 50
1914	#define FCN_IP_DAT_BUF_SIZE_WIDTH 1
1915	#define FCN_IP_DAT_BUF_SIZE_8K 1
1916	#define FCN_IP_DAT_BUF_SIZE_4K 0
1917	#define FCN_BUF_ADR_FBUF_LBN 14
1918	#define FCN_BUF_ADR_FBUF_WIDTH 34
1919	#define FCN_BUF_OWNER_ID_FBUF_LBN 0
1920	#define FCN_BUF_OWNER_ID_FBUF_WIDTH 14
1921
1922	/* MAC registers */
1923	#define FALCON_MAC_REGBANK 0xe00
1924	#define FALCON_MAC_REGBANK_SIZE 0x200
1925	#define FALCON_MAC_REG_SIZE 0x10
1926
1927	/** Offset of a MAC register within Falcon */
1928	#define FALCON_MAC_REG( efab, mac_reg ) \
1929	( FALCON_MAC_REGBANK + \
1930	( (efab)->port * FALCON_MAC_REGBANK_SIZE ) + \
1931	( (mac_reg) * FALCON_MAC_REG_SIZE ) )
1932	#define FCN_MAC_DATA_LBN 0
1933	#define FCN_MAC_DATA_WIDTH 32
1934
1935	/* Transmit descriptor */
1936	#define FCN_TX_KER_PORT_LBN 63
1937	#define FCN_TX_KER_PORT_WIDTH 1
1938	#define FCN_TX_KER_BYTE_CNT_LBN 48
1939	#define FCN_TX_KER_BYTE_CNT_WIDTH 14
1940	#define FCN_TX_KER_BUF_ADR_LBN 0
1941	#define FCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
1942
1943	/* Receive descriptor */
1944	#define FCN_RX_KER_BUF_SIZE_LBN 48
1945	#define FCN_RX_KER_BUF_SIZE_WIDTH 14
1946	#define FCN_RX_KER_BUF_ADR_LBN 0
1947	#define FCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
1948
1949	/* Event queue entries */
1950	#define FCN_EV_CODE_LBN 60
1951	#define FCN_EV_CODE_WIDTH 4
1952	#define FCN_RX_IP_EV_DECODE 0
1953	#define FCN_TX_IP_EV_DECODE 2
1954	#define FCN_DRIVER_EV_DECODE 5
1955
1956	/* Receive events */
1957	#define FCN_RX_PORT_LBN 30
1958	#define FCN_RX_PORT_WIDTH 1
1959	#define FCN_RX_EV_BYTE_CNT_LBN 16
1960	#define FCN_RX_EV_BYTE_CNT_WIDTH 14
1961	#define FCN_RX_EV_DESC_PTR_LBN 0
1962	#define FCN_RX_EV_DESC_PTR_WIDTH 12
1963
1964	/* Transmit events */
1965	#define FCN_TX_EV_DESC_PTR_LBN 0
1966	#define FCN_TX_EV_DESC_PTR_WIDTH 12
1967
1968	/* Fixed special buffer numbers to use */
1969	#define FALCON_EVQ_ID 0
1970	#define FALCON_TXD_ID 1
1971	#define FALCON_RXD_ID 2
1972
1973	#if FALCON_USE_IO_BAR
1974
1975	/* Write dword via the I/O BAR */
1976	static inline void _falcon_writel ( struct efab_nic *efab, uint32_t value,
1977	unsigned int reg ) {
1978	outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
1979	outl ( value, efab->iobase + FCN_IOM_IND_DAT_REG );
1980	}
1981
1982	/* Read dword via the I/O BAR */
1983	static inline uint32_t _falcon_readl ( struct efab_nic *efab,
1984	unsigned int reg ) {
1985	outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
1986	return inl ( efab->iobase + FCN_IOM_IND_DAT_REG );
1987	}
1988
1989	#else /* FALCON_USE_IO_BAR */
1990
1991	#define _falcon_writel( efab, value, reg ) \
1992	writel ( (value), (efab)->membase + (reg) )
1993	#define _falcon_readl( efab, reg ) readl ( (efab)->membase + (reg) )
1994
1995	#endif /* FALCON_USE_IO_BAR */
1996
1997	/**
1998	* Write to a Falcon register
1999	*
2000	*/
2001	static inline void falcon_write ( struct efab_nic efab, efab_oword_t value,
2002	unsigned int reg ) {
2003
2004	EFAB_REGDUMP ( "Writing register %x with " EFAB_OWORD_FMT "\n",
2005	reg, EFAB_OWORD_VAL ( *value ) );
2006
2007	_falcon_writel ( efab, value->u32[0], reg + 0 );
2008	_falcon_writel ( efab, value->u32[1], reg + 4 );
2009	_falcon_writel ( efab, value->u32[2], reg + 8 );
2010	_falcon_writel ( efab, value->u32[3], reg + 12 );
2011	wmb();
2012	}
2013
2014	/**
2015	* Write to Falcon SRAM
2016	*
2017	*/
2018	static inline void falcon_write_sram ( struct efab_nic *efab,
2019	efab_qword_t *value,
2020	unsigned int index ) {
2021	unsigned int reg = ( FCN_BUF_FULL_TBL_KER +
2022	( index * sizeof ( *value ) ) );
2023
2024	EFAB_REGDUMP ( "Writing SRAM register %x with " EFAB_QWORD_FMT "\n",
2025	reg, EFAB_QWORD_VAL ( *value ) );
2026
2027	_falcon_writel ( efab, value->u32[0], reg + 0 );
2028	_falcon_writel ( efab, value->u32[1], reg + 4 );
2029	wmb();
2030	}
2031
2032	/**
2033	* Write dword to Falcon register that allows partial writes
2034	*
2035	*/
2036	static inline void falcon_writel ( struct efab_nic efab, efab_dword_t value,
2037	unsigned int reg ) {
2038	EFAB_REGDUMP ( "Writing partial register %x with " EFAB_DWORD_FMT "\n",
2039	reg, EFAB_DWORD_VAL ( *value ) );
2040	_falcon_writel ( efab, value->u32[0], reg );
2041	}
2042
2043	/**
2044	* Read from a Falcon register
2045	*
2046	*/
2047	static inline void falcon_read ( struct efab_nic efab, efab_oword_t value,
2048	unsigned int reg ) {
2049	value->u32[0] = _falcon_readl ( efab, reg + 0 );
2050	value->u32[1] = _falcon_readl ( efab, reg + 4 );
2051	value->u32[2] = _falcon_readl ( efab, reg + 8 );
2052	value->u32[3] = _falcon_readl ( efab, reg + 12 );
2053
2054	EFAB_REGDUMP ( "Read from register %x, got " EFAB_OWORD_FMT "\n",
2055	reg, EFAB_OWORD_VAL ( *value ) );
2056	}
2057
2058	/**
2059	* Read from Falcon SRAM
2060	*
2061	*/
2062	static inline void falcon_read_sram ( struct efab_nic *efab,
2063	efab_qword_t *value,
2064	unsigned int index ) {
2065	unsigned int reg = ( FCN_BUF_FULL_TBL_KER +
2066	( index * sizeof ( *value ) ) );
2067
2068	value->u32[0] = _falcon_readl ( efab, reg + 0 );
2069	value->u32[1] = _falcon_readl ( efab, reg + 4 );
2070	EFAB_REGDUMP ( "Read from SRAM register %x, got " EFAB_QWORD_FMT "\n",
2071	reg, EFAB_QWORD_VAL ( *value ) );
2072	}
2073
2074	/**
2075	* Read dword from a portion of a Falcon register
2076	*
2077	*/
2078	static inline void falcon_readl ( struct efab_nic efab, efab_dword_t value,
2079	unsigned int reg ) {
2080	value->u32[0] = _falcon_readl ( efab, reg );
2081	EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n",
2082	reg, EFAB_DWORD_VAL ( *value ) );
2083	}
2084
2085	/**
2086	* Verified write to Falcon SRAM
2087	*
2088	*/
2089	static inline void falcon_write_sram_verify ( struct efab_nic *efab,
2090	efab_qword_t *value,
2091	unsigned int index ) {
2092	efab_qword_t verify;
2093
2094	falcon_write_sram ( efab, value, index );
2095	udelay ( 1000 );
2096	falcon_read_sram ( efab, &verify, index );
2097	if ( memcmp ( &verify, value, sizeof ( verify ) ) != 0 ) {
2098	printf ( "SRAM index %x failure: wrote " EFAB_QWORD_FMT
2099	" got " EFAB_QWORD_FMT "\n", index,
2100	EFAB_QWORD_VAL ( *value ),
2101	EFAB_QWORD_VAL ( verify ) );
2102	}
2103	}
2104
2105	/**
2106	* Get memory base
2107	*
2108	*/
2109	static void falcon_get_membase ( struct efab_nic *efab ) {
2110	unsigned long membase_phys;
2111
2112	membase_phys = pci_bar_start ( efab->pci, PCI_BASE_ADDRESS_2 );
2113	efab->membase = ioremap ( membase_phys, 0x20000 );
2114	}
2115
2116	#define FCN_DUMP_REG( efab, _reg ) do { \
2117	efab_oword_t reg; \
2118	falcon_read ( efab, &reg, _reg ); \
2119	printf ( #_reg " = " EFAB_OWORD_FMT "\n", \
2120	EFAB_OWORD_VAL ( reg ) ); \
2121	} while ( 0 );
2122
2123	#define FCN_DUMP_MAC_REG( efab, _mac_reg ) do { \
2124	efab_dword_t reg; \
2125	efab->op->mac_readl ( efab, &reg, _mac_reg ); \
2126	printf ( #_mac_reg " = " EFAB_DWORD_FMT "\n", \
2127	EFAB_DWORD_VAL ( reg ) ); \
2128	} while ( 0 );
2129
2130	/**
2131	* Dump register contents (for debugging)
2132	*
2133	* Marked as static inline so that it will not be compiled in if not
2134	* used.
2135	*/
2136	static inline void falcon_dump_regs ( struct efab_nic *efab ) {
2137	FCN_DUMP_REG ( efab, FCN_INT_EN_REG_KER );
2138	FCN_DUMP_REG ( efab, FCN_INT_ADR_REG_KER );
2139	FCN_DUMP_REG ( efab, FCN_GLB_CTL_REG_KER );
2140	FCN_DUMP_REG ( efab, FCN_TIMER_CMD_REG_KER );
2141	FCN_DUMP_REG ( efab, FCN_SRM_RX_DC_CFG_REG_KER );
2142	FCN_DUMP_REG ( efab, FCN_SRM_TX_DC_CFG_REG_KER );
2143	FCN_DUMP_REG ( efab, FCN_RX_FILTER_CTL_REG_KER );
2144	FCN_DUMP_REG ( efab, FCN_RX_DC_CFG_REG_KER );
2145	FCN_DUMP_REG ( efab, FCN_TX_DC_CFG_REG_KER );
2146	FCN_DUMP_REG ( efab, FCN_MAC0_CTRL_REG_KER );
2147	FCN_DUMP_REG ( efab, FCN_MAC1_CTRL_REG_KER );
2148	FCN_DUMP_REG ( efab, FCN_XM_GLB_CFG_REG_P0_KER );
2149	FCN_DUMP_REG ( efab, FCN_XM_TX_CFG_REG_P0_KER );
2150	FCN_DUMP_REG ( efab, FCN_XM_RX_CFG_REG_P0_KER );
2151	FCN_DUMP_REG ( efab, FCN_RX_DESC_PTR_TBL_KER );
2152	FCN_DUMP_REG ( efab, FCN_TX_DESC_PTR_TBL_KER );
2153	FCN_DUMP_REG ( efab, FCN_EVQ_PTR_TBL_KER );
2154	FCN_DUMP_MAC_REG ( efab, GM_CFG1_REG_MAC );
2155	FCN_DUMP_MAC_REG ( efab, GM_CFG2_REG_MAC );
2156	FCN_DUMP_MAC_REG ( efab, GM_MAX_FLEN_REG_MAC );
2157	FCN_DUMP_MAC_REG ( efab, GM_MII_MGMT_CFG_REG_MAC );
2158	FCN_DUMP_MAC_REG ( efab, GM_ADR1_REG_MAC );
2159	FCN_DUMP_MAC_REG ( efab, GM_ADR2_REG_MAC );
2160	FCN_DUMP_MAC_REG ( efab, GMF_CFG0_REG_MAC );
2161	FCN_DUMP_MAC_REG ( efab, GMF_CFG1_REG_MAC );
2162	FCN_DUMP_MAC_REG ( efab, GMF_CFG2_REG_MAC );
2163	FCN_DUMP_MAC_REG ( efab, GMF_CFG3_REG_MAC );
2164	FCN_DUMP_MAC_REG ( efab, GMF_CFG4_REG_MAC );
2165	FCN_DUMP_MAC_REG ( efab, GMF_CFG5_REG_MAC );
2166	}
2167
2168	/**
2169	* Create special buffer
2170	*
2171	*/
2172	static void falcon_create_special_buffer ( struct efab_nic *efab,
2173	void *addr, unsigned int index ) {
2174	efab_qword_t buf_desc;
2175	unsigned long dma_addr;
2176
2177	memset ( addr, 0, 4096 );
2178	dma_addr = virt_to_bus ( addr );
2179	EFAB_ASSERT ( ( dma_addr & ( EFAB_BUF_ALIGN - 1 ) ) == 0 );
2180	EFAB_POPULATE_QWORD_3 ( buf_desc,
2181	FCN_IP_DAT_BUF_SIZE, FCN_IP_DAT_BUF_SIZE_4K,
2182	FCN_BUF_ADR_FBUF, ( dma_addr >> 12 ),
2183	FCN_BUF_OWNER_ID_FBUF, 0 );
2184	falcon_write_sram_verify ( efab, &buf_desc, index );
2185	}
2186
2187	/**
2188	* Update event queue read pointer
2189	*
2190	*/
2191	static void falcon_eventq_read_ack ( struct efab_nic *efab ) {
2192	efab_dword_t reg;
2193
2194	EFAB_ASSERT ( efab->eventq_read_ptr < EFAB_EVQ_SIZE );
2195
2196	EFAB_POPULATE_DWORD_1 ( reg, FCN_EVQ_RPTR_DWORD,
2197	efab->eventq_read_ptr );
2198	falcon_writel ( efab, &reg, FCN_EVQ_RPTR_REG_KER_DWORD );
2199	}
2200
2201	/**
2202	* Reset device
2203	*
2204	*/
2205	static int falcon_reset ( struct efab_nic *efab ) {
2206	efab_oword_t glb_ctl_reg_ker;
2207
2208	/* Initiate software reset */
2209	EFAB_POPULATE_OWORD_5 ( glb_ctl_reg_ker,
2210	FCN_EXT_PHY_RST_CTL, FCN_EXCLUDE_FROM_RESET,
2211	FCN_PCIE_SD_RST_CTL, FCN_EXCLUDE_FROM_RESET,
2212	FCN_PCIX_RST_CTL, FCN_EXCLUDE_FROM_RESET,
2213	FCN_INT_RST_DUR, 0x7 /* datasheet */,
2214	FCN_SWRST, 1 );
2215	falcon_write ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
2216
2217	/* Allow 20ms for reset */
2218	mdelay ( 20 );
2219
2220	/* Check for device reset complete */
2221	falcon_read ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
2222	if ( EFAB_OWORD_FIELD ( glb_ctl_reg_ker, FCN_SWRST ) != 0 ) {
2223	printf ( "Reset failed\n" );
2224	return 0;
2225	}
2226
2227	return 1;
2228	}
2229
2230	/**
2231	* Initialise NIC
2232	*
2233	*/
2234	static int falcon_init_nic ( struct efab_nic *efab ) {
2235	efab_oword_t reg;
2236	efab_dword_t timer_cmd;
2237
2238	/* Set up TX and RX descriptor caches in SRAM */
2239	EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR,
2240	0x130000 /* recommended in datasheet */ );
2241	falcon_write ( efab, &reg, FCN_SRM_TX_DC_CFG_REG_KER );
2242	EFAB_POPULATE_OWORD_1 ( reg, FCN_TX_DC_SIZE, 2 /* 32 descriptors */ );
2243	falcon_write ( efab, &reg, FCN_TX_DC_CFG_REG_KER );
2244	EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_RX_DC_BASE_ADR,
2245	0x100000 /* recommended in datasheet */ );
2246	falcon_write ( efab, &reg, FCN_SRM_RX_DC_CFG_REG_KER );
2247	EFAB_POPULATE_OWORD_1 ( reg, FCN_RX_DC_SIZE, 2 /* 32 descriptors */ );
2248	falcon_write ( efab, &reg, FCN_RX_DC_CFG_REG_KER );
2249
2250	/* Set number of RSS CPUs */
2251	EFAB_POPULATE_OWORD_1 ( reg, FCN_NUM_KER, 0 );
2252	falcon_write ( efab, &reg, FCN_RX_FILTER_CTL_REG_KER );
2253	udelay ( 1000 );
2254
2255	/* Reset the MAC */
2256	mentormac_reset ( efab );
2257
2258	/* Set up event queue */
2259	falcon_create_special_buffer ( efab, efab->eventq, FALCON_EVQ_ID );
2260	EFAB_POPULATE_OWORD_3 ( reg,
2261	FCN_EVQ_EN, 1,
2262	FCN_EVQ_SIZE, FCN_EVQ_SIZE_512,
2263	FCN_EVQ_BUF_BASE_ID, FALCON_EVQ_ID );
2264	falcon_write ( efab, &reg, FCN_EVQ_PTR_TBL_KER );
2265	udelay ( 1000 );
2266
2267	/* Set timer register */
2268	EFAB_POPULATE_DWORD_2 ( timer_cmd,
2269	FCN_TIMER_MODE, FCN_TIMER_MODE_DIS,
2270	FCN_TIMER_VAL, 0 );
2271	falcon_writel ( efab, &timer_cmd, FCN_TIMER_CMD_REG_KER );
2272	udelay ( 1000 );
2273
2274	/* Initialise event queue read pointer */
2275	falcon_eventq_read_ack ( efab );
2276
2277	/* Set up TX descriptor ring */
2278	falcon_create_special_buffer ( efab, efab->txd, FALCON_TXD_ID );
2279	EFAB_POPULATE_OWORD_5 ( reg,
2280	FCN_TX_DESCQ_EN, 1,
2281	FCN_TX_DESCQ_BUF_BASE_ID, FALCON_TXD_ID,
2282	FCN_TX_DESCQ_EVQ_ID, 0,
2283	FCN_TX_DESCQ_SIZE, FCN_TX_DESCQ_SIZE_512,
2284	FCN_TX_DESCQ_TYPE, 0 /* kernel queue */ );
2285	falcon_write ( efab, &reg, FCN_TX_DESC_PTR_TBL_KER );
2286
2287	/* Set up RX descriptor ring */
2288	falcon_create_special_buffer ( efab, efab->rxd, FALCON_RXD_ID );
2289	EFAB_POPULATE_OWORD_6 ( reg,
2290	FCN_RX_DESCQ_BUF_BASE_ID, FALCON_RXD_ID,
2291	FCN_RX_DESCQ_EVQ_ID, 0,
2292	FCN_RX_DESCQ_SIZE, FCN_RX_DESCQ_SIZE_512,
2293	FCN_RX_DESCQ_TYPE, 0 /* kernel queue */,
2294	FCN_RX_DESCQ_JUMBO, 1,
2295	FCN_RX_DESCQ_EN, 1 );
2296	falcon_write ( efab, &reg, FCN_RX_DESC_PTR_TBL_KER );
2297
2298	/* Program INT_ADR_REG_KER */
2299	EFAB_POPULATE_OWORD_1 ( reg,
2300	FCN_INT_ADR_KER,
2301	virt_to_bus ( &efab->int_ker ) );
2302	falcon_write ( efab, &reg, FCN_INT_ADR_REG_KER );
2303	udelay ( 1000 );
2304
2305	return 1;
2306	}
2307
2308	/** SPI device */
2309	struct efab_spi_device {
2310	/** Device ID */
2311	unsigned int device_id;
2312	/** Address length (in bytes) */
2313	unsigned int addr_len;
2314	/** Read command */
2315	unsigned int read_command;
2316	};
2317
2318	/**
2319	* Wait for SPI command completion
2320	*
2321	*/
2322	static int falcon_spi_wait ( struct efab_nic *efab ) {
2323	efab_oword_t reg;
2324	int count;
2325
2326	count = 0;
2327	do {
2328	udelay ( 100 );
2329	falcon_read ( efab, &reg, FCN_EE_SPI_HCMD_REG_KER );
2330	if ( EFAB_OWORD_FIELD ( reg, FCN_EE_SPI_HCMD_CMD_EN ) == 0 )
2331	return 1;
2332	} while ( ++count < 1000 );
2333	printf ( "Timed out waiting for SPI\n" );
2334	return 0;
2335	}
2336
2337	/**
2338	* Perform SPI read
2339	*
2340	*/
2341	static int falcon_spi_read ( struct efab_nic *efab,
2342	struct efab_spi_device *spi,
2343	int address, void *data, unsigned int len ) {
2344	efab_oword_t reg;
2345
2346	/* Program address register */
2347	EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address );
2348	falcon_write ( efab, &reg, FCN_EE_SPI_HADR_REG_KER );
2349
2350	/* Issue read command */
2351	EFAB_POPULATE_OWORD_7 ( reg,
2352	FCN_EE_SPI_HCMD_CMD_EN, 1,
2353	FCN_EE_SPI_HCMD_SF_SEL, spi->device_id,
2354	FCN_EE_SPI_HCMD_DABCNT, len,
2355	FCN_EE_SPI_HCMD_READ, FCN_EE_SPI_READ,
2356	FCN_EE_SPI_HCMD_DUBCNT, 0,
2357	FCN_EE_SPI_HCMD_ADBCNT, spi->addr_len,
2358	FCN_EE_SPI_HCMD_ENC, spi->read_command );
2359	falcon_write ( efab, &reg, FCN_EE_SPI_HCMD_REG_KER );
2360
2361	/* Wait for read to complete */
2362	if ( ! falcon_spi_wait ( efab ) )
2363	return 0;
2364
2365	/* Read data */
2366	falcon_read ( efab, &reg, FCN_EE_SPI_HDATA_REG_KER );
2367	memcpy ( data, &reg, len );
2368
2369	return 1;
2370	}
2371
2372	#define SPI_READ_CMD 0x03
2373	#define AT25F1024_ADDR_LEN 3
2374	#define AT25F1024_READ_CMD SPI_READ_CMD
2375	#define MC25XX640_ADDR_LEN 2
2376	#define MC25XX640_READ_CMD SPI_READ_CMD
2377
2378	/** Falcon Flash SPI device */
2379	static struct efab_spi_device falcon_spi_flash = {
2380	.device_id = FCN_EE_SPI_FLASH,
2381	.addr_len = AT25F1024_ADDR_LEN,
2382	.read_command = AT25F1024_READ_CMD,
2383	};
2384
2385	/** Falcon EEPROM SPI device */
2386	static struct efab_spi_device falcon_spi_large_eeprom = {
2387	.device_id = FCN_EE_SPI_EEPROM,
2388	.addr_len = MC25XX640_ADDR_LEN,
2389	.read_command = MC25XX640_READ_CMD,
2390	};
2391
2392	/** Offset of MAC address within EEPROM or Flash */
2393	#define FALCON_MAC_ADDRESS_OFFSET(port) ( 0x310 + 0x08 * (port) )
2394
2395	/**
2396	* Read MAC address from EEPROM
2397	*
2398	*/
2399	static int falcon_read_eeprom ( struct efab_nic *efab ) {
2400	efab_oword_t reg;
2401	int has_flash;
2402	struct efab_spi_device *spi;
2403
2404	/* Determine the SPI device containing the MAC address */
2405	falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
2406	has_flash = EFAB_OWORD_FIELD ( reg, FCN_FLASH_PRESENT );
2407	spi = has_flash ? &falcon_spi_flash : &falcon_spi_large_eeprom;
2408
2409	return falcon_spi_read ( efab, spi,
2410	FALCON_MAC_ADDRESS_OFFSET ( efab->port ),
2411	efab->mac_addr, sizeof ( efab->mac_addr ) );
2412	}
2413
2414	/** RX descriptor */
2415	typedef efab_qword_t falcon_rx_desc_t;
2416
2417	/**
2418	* Build RX descriptor
2419	*
2420	*/
2421	static void falcon_build_rx_desc ( struct efab_nic *efab,
2422	struct efab_rx_buf *rx_buf ) {
2423	falcon_rx_desc_t *rxd;
2424
2425	rxd = ( ( falcon_rx_desc_t * ) efab->rxd ) + rx_buf->id;
2426	EFAB_POPULATE_QWORD_2 ( *rxd,
2427	FCN_RX_KER_BUF_SIZE, EFAB_DATA_BUF_SIZE,
2428	FCN_RX_KER_BUF_ADR,
2429	virt_to_bus ( rx_buf->addr ) );
2430	}
2431
2432	/**
2433	* Update RX descriptor write pointer
2434	*
2435	*/
2436	static void falcon_notify_rx_desc ( struct efab_nic *efab ) {
2437	efab_dword_t reg;
2438
2439	EFAB_POPULATE_DWORD_1 ( reg, FCN_RX_DESC_WPTR_DWORD,
2440	efab->rx_write_ptr );
2441	falcon_writel ( efab, &reg, FCN_RX_DESC_UPD_REG_KER_DWORD );
2442	}
2443
2444	/** TX descriptor */
2445	typedef efab_qword_t falcon_tx_desc_t;
2446
2447	/**
2448	* Build TX descriptor
2449	*
2450	*/
2451	static void falcon_build_tx_desc ( struct efab_nic *efab,
2452	struct efab_tx_buf *tx_buf ) {
2453	falcon_rx_desc_t *txd;
2454
2455	txd = ( ( falcon_rx_desc_t * ) efab->txd ) + tx_buf->id;
2456	EFAB_POPULATE_QWORD_3 ( *txd,
2457	FCN_TX_KER_PORT, efab->port,
2458	FCN_TX_KER_BYTE_CNT, tx_buf->len,
2459	FCN_TX_KER_BUF_ADR,
2460	virt_to_bus ( tx_buf->addr ) );
2461	}
2462
2463	/**
2464	* Update TX descriptor write pointer
2465	*
2466	*/
2467	static void falcon_notify_tx_desc ( struct efab_nic *efab ) {
2468	efab_dword_t reg;
2469
2470	EFAB_POPULATE_DWORD_1 ( reg, FCN_TX_DESC_WPTR_DWORD,
2471	efab->tx_write_ptr );
2472	falcon_writel ( efab, &reg, FCN_TX_DESC_UPD_REG_KER_DWORD );
2473	}
2474
2475	/** An event */
2476	typedef efab_qword_t falcon_event_t;
2477
2478	/**
2479	* Retrieve event from event queue
2480	*
2481	*/
2482	static int falcon_fetch_event ( struct efab_nic *efab,
2483	struct efab_event *event ) {
2484	falcon_event_t *evt;
2485	int ev_code;
2486	int rx_port;
2487
2488	/* Check for event */
2489	evt = ( ( falcon_event_t * ) efab->eventq ) + efab->eventq_read_ptr;
2490	if ( EFAB_QWORD_IS_ZERO ( *evt ) ) {
2491	/* No event */
2492	return 0;
2493	}
2494
2495	DBG ( "Event is " EFAB_QWORD_FMT "\n", EFAB_QWORD_VAL ( *evt ) );
2496
2497	/* Decode event */
2498	ev_code = EFAB_QWORD_FIELD ( *evt, FCN_EV_CODE );
2499	switch ( ev_code ) {
2500	case FCN_TX_IP_EV_DECODE:
2501	event->type = EFAB_EV_TX;
2502	break;
2503	case FCN_RX_IP_EV_DECODE:
2504	event->type = EFAB_EV_RX;
2505	event->rx_id = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_DESC_PTR );
2506	event->rx_len = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_BYTE_CNT );
2507	rx_port = EFAB_QWORD_FIELD ( *evt, FCN_RX_PORT );
2508	if ( rx_port != efab->port ) {
2509	/* Ignore packets on the wrong port. We can't
2510	* just set event->type = EFAB_EV_NONE,
2511	* because then the descriptor ring won't get
2512	* refilled.
2513	*/
2514	event->rx_len = 0;
2515	}
2516	break;
2517	case FCN_DRIVER_EV_DECODE:
2518	/* Ignore start-of-day events */
2519	event->type = EFAB_EV_NONE;
2520	break;
2521	default:
2522	printf ( "Unknown event type %d\n", ev_code );
2523	event->type = EFAB_EV_NONE;
2524	}
2525
2526	/* Clear event and any pending interrupts */
2527	EFAB_ZERO_QWORD ( *evt );
2528	falcon_writel ( efab, 0, FCN_INT_ACK_KER_REG );
2529	udelay ( 10 );
2530
2531	/* Increment and update event queue read pointer */
2532	efab->eventq_read_ptr = ( ( efab->eventq_read_ptr + 1 )
2533	% EFAB_EVQ_SIZE );
2534	falcon_eventq_read_ack ( efab );
2535
2536	return 1;
2537	}
2538
2539	/**
2540	* Enable/disable/generate interrupt
2541	*
2542	*/
2543	static inline void falcon_interrupts ( struct efab_nic *efab, int enabled,
2544	int force ) {
2545	efab_oword_t int_en_reg_ker;
2546
2547	EFAB_POPULATE_OWORD_2 ( int_en_reg_ker,
2548	FCN_KER_INT_KER, force,
2549	FCN_DRV_INT_EN_KER, enabled );
2550	falcon_write ( efab, &int_en_reg_ker, FCN_INT_EN_REG_KER );
2551	}
2552
2553	/**
2554	* Enable/disable interrupts
2555	*
2556	*/
2557	static void falcon_mask_irq ( struct efab_nic *efab, int enabled ) {
2558	falcon_interrupts ( efab, enabled, 0 );
2559	if ( enabled ) {
2560	/* Events won't trigger interrupts until we do this */
2561	falcon_eventq_read_ack ( efab );
2562	}
2563	}
2564
2565	/**
2566	* Generate interrupt
2567	*
2568	*/
2569	static void falcon_generate_irq ( struct efab_nic *efab ) {
2570	falcon_interrupts ( efab, 1, 1 );
2571	}
2572
2573	/**
2574	* Write dword to a Falcon MAC register
2575	*
2576	*/
2577	static void falcon_mac_writel ( struct efab_nic *efab,
2578	efab_dword_t *value, unsigned int mac_reg ) {
2579	efab_oword_t temp;
2580
2581	EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
2582	EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
2583	falcon_write ( efab, &temp, FALCON_MAC_REG ( efab, mac_reg ) );
2584	}
2585
2586	/**
2587	* Read dword from a Falcon MAC register
2588	*
2589	*/
2590	static void falcon_mac_readl ( struct efab_nic efab, efab_dword_t value,
2591	unsigned int mac_reg ) {
2592	efab_oword_t temp;
2593
2594	falcon_read ( efab, &temp, FALCON_MAC_REG ( efab, mac_reg ) );
2595	EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
2596	EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
2597	}
2598
2599	/**
2600	* Initialise MAC
2601	*
2602	*/
2603	static int falcon_init_mac ( struct efab_nic *efab ) {
2604	static struct efab_mentormac_parameters falcon_mentormac_params = {
2605	.gmf_cfgfrth = 0x12,
2606	.gmf_cfgftth = 0x08,
2607	.gmf_cfghwmft = 0x1c,
2608	.gmf_cfghwm = 0x3f,
2609	.gmf_cfglwm = 0xa,
2610	};
2611	efab_oword_t reg;
2612	int link_speed;
2613
2614	/* Initialise PHY */
2615	alaska_init ( efab );
2616
2617	/* Initialise MAC */
2618	mentormac_init ( efab, &falcon_mentormac_params );
2619
2620	/* Configure the Falcon MAC wrapper */
2621	EFAB_POPULATE_OWORD_4 ( reg,
2622	FCN_XM_RX_JUMBO_MODE, 0,
2623	FCN_XM_CUT_THRU_MODE, 0,
2624	FCN_XM_TX_STAT_EN, 1,
2625	FCN_XM_RX_STAT_EN, 1);
2626	falcon_write ( efab, &reg, FCN_XM_GLB_CFG_REG_P0_KER );
2627
2628	EFAB_POPULATE_OWORD_6 ( reg,
2629	FCN_XM_TXEN, 1,
2630	FCN_XM_TX_PRMBL, 1,
2631	FCN_XM_AUTO_PAD, 1,
2632	FCN_XM_TXCRC, 1,
2633	FCN_XM_WTF_DOES_THIS_DO, 1,
2634	FCN_XM_IPG, 0x3 );
2635	falcon_write ( efab, &reg, FCN_XM_TX_CFG_REG_P0_KER );
2636
2637	EFAB_POPULATE_OWORD_3 ( reg,
2638	FCN_XM_RXEN, 1,
2639	FCN_XM_AUTO_DEPAD, 1,
2640	FCN_XM_PASS_CRC_ERR, 1 );
2641	falcon_write ( efab, &reg, FCN_XM_RX_CFG_REG_P0_KER );
2642
2643	#warning "10G support not yet present"
2644	#define LPA_10000 0
2645	if ( efab->link_options & LPA_10000 ) {
2646	link_speed = 0x3;
2647	} else if ( efab->link_options & LPA_1000 ) {
2648	link_speed = 0x2;
2649	} else if ( efab->link_options & LPA_100 ) {
2650	link_speed = 0x1;
2651	} else {
2652	link_speed = 0x0;
2653	}
2654	EFAB_POPULATE_OWORD_5 ( reg,
2655	FCN_MAC_XOFF_VAL, 0xffff /* datasheet */,
2656	FCN_MAC_BCAD_ACPT, 1,
2657	FCN_MAC_UC_PROM, 0,
2658	FCN_MAC_LINK_STATUS, 1,
2659	FCN_MAC_SPEED, link_speed );
2660	falcon_write ( efab, &reg, ( efab->port == 0 ?
2661	FCN_MAC0_CTRL_REG_KER : FCN_MAC1_CTRL_REG_KER ) );
2662
2663	return 1;
2664	}
2665
2666	/**
2667	* Wait for GMII access to complete
2668	*
2669	*/
2670	static int falcon_gmii_wait ( struct efab_nic *efab ) {
2671	efab_oword_t md_stat;
2672	int count;
2673
2674	for ( count = 0 ; count < 1000 ; count++ ) {
2675	udelay ( 10 );
2676	falcon_read ( efab, &md_stat, FCN_MD_STAT_REG_KER );
2677	if ( EFAB_OWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 )
2678	return 1;
2679	}
2680	printf ( "Timed out waiting for GMII\n" );
2681	return 0;
2682	}
2683
2684	/** MDIO write */
2685	static void falcon_mdio_write ( struct efab_nic *efab, int location,
2686	int value ) {
2687	int phy_id = efab->port + 2;
2688	efab_oword_t reg;
2689
2690	#warning "10G PHY access not yet in place"
2691
2692	EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n",
2693	phy_id, location, value );
2694
2695	/* Check MII not currently being accessed */
2696	if ( ! falcon_gmii_wait ( efab ) )
2697	return;
2698
2699	/* Write the address registers */
2700	EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, 0 /* phy_id ? */ );
2701	falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
2702	udelay ( 10 );
2703	EFAB_POPULATE_OWORD_2 ( reg,
2704	FCN_MD_PRT_ADR, phy_id,
2705	FCN_MD_DEV_ADR, location );
2706	falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
2707	udelay ( 10 );
2708
2709	/* Write data */
2710	EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_TXD, value );
2711	falcon_write ( efab, &reg, FCN_MD_TXD_REG_KER );
2712	udelay ( 10 );
2713	EFAB_POPULATE_OWORD_2 ( reg,
2714	FCN_MD_WRC, 1,
2715	FCN_MD_GC, 1 );
2716	falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
2717	udelay ( 10 );
2718
2719	/* Wait for data to be written */
2720	falcon_gmii_wait ( efab );
2721	}
2722
2723	/** MDIO read */
2724	static int falcon_mdio_read ( struct efab_nic *efab, int location ) {
2725	int phy_id = efab->port + 2;
2726	efab_oword_t reg;
2727	int value;
2728
2729	/* Check MII not currently being accessed */
2730	if ( ! falcon_gmii_wait ( efab ) )
2731	return 0xffff;
2732
2733	/* Write the address registers */
2734	EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, 0 /* phy_id ? */ );
2735	falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
2736	udelay ( 10 );
2737	EFAB_POPULATE_OWORD_2 ( reg,
2738	FCN_MD_PRT_ADR, phy_id,
2739	FCN_MD_DEV_ADR, location );
2740	falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
2741	udelay ( 10 );
2742
2743	/* Request data to be read */
2744	EFAB_POPULATE_OWORD_2 ( reg,
2745	FCN_MD_RIC, 1,
2746	FCN_MD_GC, 1 );
2747	falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
2748	udelay ( 10 );
2749
2750	/* Wait for data to become available */
2751	falcon_gmii_wait ( efab );
2752
2753	/* Read the data */
2754	falcon_read ( efab, &reg, FCN_MD_RXD_REG_KER );
2755	value = EFAB_OWORD_FIELD ( reg, FCN_MD_RXD );
2756
2757	EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
2758	phy_id, location, value );
2759
2760	return value;
2761	}
2762
2763	static struct efab_operations falcon_operations = {
2764	.get_membase = falcon_get_membase,
2765	.reset = falcon_reset,
2766	.init_nic = falcon_init_nic,
2767	.read_eeprom = falcon_read_eeprom,
2768	.build_rx_desc = falcon_build_rx_desc,
2769	.notify_rx_desc = falcon_notify_rx_desc,
2770	.build_tx_desc = falcon_build_tx_desc,
2771	.notify_tx_desc = falcon_notify_tx_desc,
2772	.fetch_event = falcon_fetch_event,
2773	.mask_irq = falcon_mask_irq,
2774	.generate_irq = falcon_generate_irq,
2775	.mac_writel = falcon_mac_writel,
2776	.mac_readl = falcon_mac_readl,
2777	.init_mac = falcon_init_mac,
2778	.mdio_write = falcon_mdio_write,
2779	.mdio_read = falcon_mdio_read,
2780	};
2781
2782	/**************************************************************************
2783	*
2784	* Etherfabric abstraction layer
2785	*
2786	**************************************************************************
2787	*/
2788
2789	/**
2790	* Push RX buffer to RXD ring
2791	*
2792	*/
2793	static inline void efab_push_rx_buffer ( struct efab_nic *efab,
2794	struct efab_rx_buf *rx_buf ) {
2795	/* Create RX descriptor */
2796	rx_buf->id = efab->rx_write_ptr;
2797	efab->op->build_rx_desc ( efab, rx_buf );
2798
2799	/* Update RX write pointer */
2800	efab->rx_write_ptr = ( efab->rx_write_ptr + 1 ) % EFAB_RXD_SIZE;
2801	efab->op->notify_rx_desc ( efab );
2802
2803	DBG ( "Added RX id %x\n", rx_buf->id );
2804	}
2805
2806	/**
2807	* Push TX buffer to TXD ring
2808	*
2809	*/
2810	static inline void efab_push_tx_buffer ( struct efab_nic *efab,
2811	struct efab_tx_buf *tx_buf ) {
2812	/* Create TX descriptor */
2813	tx_buf->id = efab->tx_write_ptr;
2814	efab->op->build_tx_desc ( efab, tx_buf );
2815
2816	/* Update TX write pointer */
2817	efab->tx_write_ptr = ( efab->tx_write_ptr + 1 ) % EFAB_TXD_SIZE;
2818	efab->op->notify_tx_desc ( efab );
2819
2820	DBG ( "Added TX id %x\n", tx_buf->id );
2821	}
2822
2823	/**
2824	* Initialise MAC and wait for link up
2825	*
2826	*/
2827	static int efab_init_mac ( struct efab_nic *efab ) {
2828	int count;
2829
2830	/* This can take several seconds */
2831	printf ( "Waiting for link.." );
2832	count = 0;
2833	do {
2834	putchar ( '.' );
2835	if ( ! efab->op->init_mac ( efab ) ) {
2836	printf ( "failed\n" );
2837	return 0;
2838	}
2839	if ( efab->link_up ) {
2840	/* PHY init printed the message for us */
2841	return 1;
2842	}
2843	sleep ( 1 );
2844	} while ( ++count < 5 );
2845	printf ( "timed out\n" );
2846
2847	return 0;
2848	}
2849
2850	/**
2851	* Initialise NIC
2852	*
2853	*/
2854	static int efab_init_nic ( struct efab_nic *efab ) {
2855	int i;
2856
2857	/* Initialise NIC */
2858	if ( ! efab->op->init_nic ( efab ) )
2859	return 0;
2860
2861	/* Push RX descriptors */
2862	for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
2863	efab_push_rx_buffer ( efab, &efab->rx_bufs[i] );
2864	}
2865
2866	/* Read MAC address from EEPROM */
2867	if ( ! efab->op->read_eeprom ( efab ) )
2868	return 0;
2869
2870	/* Initialise MAC and wait for link up */
2871	if ( ! efab_init_mac ( efab ) )
2872	return 0;
2873
2874	return 1;
2875	}
2876
2877	/**************************************************************************
2878	*
2879	* Etherboot interface
2880	*
2881	**************************************************************************
2882	*/
2883
2884	/**************************************************************************
2885	POLL - Wait for a frame
2886	***************************************************************************/
2887	static int etherfabric_poll ( struct nic *nic, int retrieve ) {
2888	struct efab_nic *efab = nic->priv_data;
2889	struct efab_event event;
2890	static struct efab_rx_buf *rx_buf = NULL;
2891	int i;
2892
2893	/* Process the event queue until we hit either a packet
2894	* received event or an empty event slot.
2895	*/
2896	while ( ( rx_buf == NULL ) &&
2897	efab->op->fetch_event ( efab, &event ) ) {
2898	if ( event.type == EFAB_EV_TX ) {
2899	/* TX completed - mark as done */
2900	DBG ( "TX id %x complete\n",
2901	efab->tx_buf.id );
2902	efab->tx_in_progress = 0;
2903	} else if ( event.type == EFAB_EV_RX ) {
2904	/* RX - find corresponding buffer */
2905	for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
2906	if ( efab->rx_bufs[i].id == event.rx_id ) {
2907	rx_buf = &efab->rx_bufs[i];
2908	rx_buf->len = event.rx_len;
2909	DBG ( "RX id %x (len %x) received\n",
2910	rx_buf->id, rx_buf->len );
2911	break;
2912	}
2913	}
2914	if ( ! rx_buf ) {
2915	printf ( "Invalid RX ID %x\n", event.rx_id );
2916	}
2917	} else if ( event.type == EFAB_EV_NONE ) {
2918	DBG ( "Ignorable event\n" );
2919	} else {
2920	DBG ( "Unknown event\n" );
2921	}
2922	}
2923
2924	/* If there is no packet, return 0 */
2925	if ( ! rx_buf )
2926	return 0;
2927
2928	/* If we don't want to retrieve it just yet, return 1 */
2929	if ( ! retrieve )
2930	return 1;
2931
2932	/* There seems to be a hardware race. The event can show up
2933	* on the event FIFO before the DMA has completed, so we
2934	* insert a tiny delay. If this proves unreliable, we should
2935	* switch to using event DMA rather than the event FIFO, since
2936	* event DMA ordering is guaranteed.
2937	*/
2938	udelay ( 1 );
2939
2940	/* Copy packet contents */
2941	nic->packetlen = rx_buf->len;
2942	memcpy ( nic->packet, rx_buf->addr, nic->packetlen );
2943
2944	/* Give this buffer back to the NIC */
2945	efab_push_rx_buffer ( efab, rx_buf );
2946
2947	/* Prepare to receive next packet */
2948	rx_buf = NULL;
2949
2950	return 1;
2951	}
2952
2953	/**************************************************************************
2954	TRANSMIT - Transmit a frame
2955	***************************************************************************/
2956	static void etherfabric_transmit ( struct nic nic, const char dest,
2957	unsigned int type, unsigned int size,
2958	const char *data ) {
2959	struct efab_nic *efab = nic->priv_data;
2960	unsigned int nstype = htons ( type );
2961
2962	/* We can only transmit one packet at a time; a TX completion
2963	* event must be received before we can transmit the next
2964	* packet. Since there is only one static TX buffer, we don't
2965	* worry unduly about overflow, but we report it anyway.
2966	*/
2967	if ( efab->tx_in_progress ) {
2968	printf ( "TX overflow!\n" );
2969	}
2970
2971	/* Fill TX buffer, pad to ETH_ZLEN */
2972	memcpy ( efab->tx_buf.addr, dest, ETH_ALEN );
2973	memcpy ( efab->tx_buf.addr + ETH_ALEN, nic->node_addr, ETH_ALEN );
2974	memcpy ( efab->tx_buf.addr + 2 * ETH_ALEN, &nstype, 2 );
2975	memcpy ( efab->tx_buf.addr + ETH_HLEN, data, size );
2976	size += ETH_HLEN;
2977	while ( size < ETH_ZLEN ) {
2978	efab->tx_buf.addr[size++] = '\0';
2979	}
2980	efab->tx_buf.len = size;
2981
2982	/* Push TX descriptor */
2983	efab_push_tx_buffer ( efab, &efab->tx_buf );
2984
2985	/* There is no way to wait for TX complete (i.e. TX buffer
2986	* available to re-use for the next transmit) without reading
2987	* from the event queue. We therefore simply leave the TX
2988	* buffer marked as "in use" until a TX completion event
2989	* happens to be picked up by a call to etherfabric_poll().
2990	*/
2991	efab->tx_in_progress = 1;
2992
2993	return;
2994	}
2995
2996	/**************************************************************************
2997	DISABLE - Turn off ethernet interface
2998	***************************************************************************/
2999	static void etherfabric_disable ( struct dev *dev ) {
3000	struct nic nic = ( struct nic ) dev;
3001	struct efab_nic *efab = nic->priv_data;
3002
3003	efab->op->reset ( efab );
3004	if ( efab->membase )
3005	iounmap ( efab->membase );
3006	}
3007
3008	/**************************************************************************
3009	IRQ - handle interrupts
3010	***************************************************************************/
3011	static void etherfabric_irq ( struct nic *nic, irq_action_t action ) {
3012	struct efab_nic *efab = nic->priv_data;
3013
3014	switch ( action ) {
3015	case DISABLE :
3016	efab->op->mask_irq ( efab, 1 );
3017	break;
3018	case ENABLE :
3019	efab->op->mask_irq ( efab, 0 );
3020	break;
3021	case FORCE :
3022	/* Force NIC to generate a receive interrupt */
3023	efab->op->generate_irq ( efab );
3024	break;
3025	}
3026
3027	return;
3028	}
3029
3030	/**************************************************************************
3031	PROBE - Look for an adapter, this routine's visible to the outside
3032	***************************************************************************/
3033	static int etherfabric_probe ( struct dev dev, struct pci_device pci ) {
3034	struct nic nic = ( struct nic ) dev;
3035	static struct efab_nic efab;
3036	static int nic_port = 1;
3037	struct efab_buffers *buffers;
3038	int i;
3039
3040	/* Set up our private data structure */
3041	nic->priv_data = &efab;
3042	memset ( &efab, 0, sizeof ( efab ) );
3043	memset ( &efab_buffers, 0, sizeof ( efab_buffers ) );
3044
3045	/* Hook in appropriate operations table. Do this early. */
3046	if ( pci->dev_id == EF1002_DEVID ) {
3047	efab.op = &ef1002_operations;
3048	} else {
3049	efab.op = &falcon_operations;
3050	}
3051
3052	/* Initialise efab data structure */
3053	efab.pci = pci;
3054	buffers = ( ( struct efab_buffers * )
3055	( ( ( void * ) &efab_buffers ) +
3056	( - virt_to_bus ( &efab_buffers ) ) % EFAB_BUF_ALIGN ) );
3057	efab.eventq = buffers->eventq;
3058	efab.txd = buffers->txd;
3059	efab.rxd = buffers->rxd;
3060	efab.tx_buf.addr = buffers->tx_buf;
3061	for ( i = 0 ; i < EFAB_RX_BUFS ; i++ ) {
3062	efab.rx_bufs[i].addr = buffers->rx_buf[i];
3063	}
3064
3065	/* Enable the PCI device */
3066	adjust_pci_device ( pci );
3067	nic->ioaddr = pci->ioaddr & ~3;
3068	nic->irqno = pci->irq;
3069
3070	/* Get iobase/membase */
3071	efab.iobase = nic->ioaddr;
3072	efab.op->get_membase ( &efab );
3073
3074	/* Switch NIC ports (i.e. try different ports on each probe) */
3075	nic_port = 1 - nic_port;
3076	efab.port = nic_port;
3077
3078	/* Initialise hardware */
3079	if ( ! efab_init_nic ( &efab ) )
3080	return 0;
3081	memcpy ( nic->node_addr, efab.mac_addr, ETH_ALEN );
3082
3083	/* hello world */
3084	printf ( "Found EtherFabric %s NIC %!\n", pci->name, nic->node_addr );
3085
3086	/* point to NIC specific routines */
3087	dev->disable = etherfabric_disable;
3088	nic->poll = etherfabric_poll;
3089	nic->transmit = etherfabric_transmit;
3090	nic->irq = etherfabric_irq;
3091
3092	return 1;
3093	}
3094
3095	static struct pci_id etherfabric_nics[] = {
3096	PCI_ROM(0x1924, 0xC101, "ef1002", "EtherFabric EF1002"),
3097	PCI_ROM(0x1924, 0x0703, "falcon", "EtherFabric Falcon"),
3098	};
3099
3100	static struct pci_driver etherfabric_driver __pci_driver = {
3101	.type = NIC_DRIVER,
3102	.name = "EFAB",
3103	.probe = etherfabric_probe,
3104	.ids = etherfabric_nics,
3105	.id_count = sizeof(etherfabric_nics)/sizeof(etherfabric_nics[0]),
3106	.class = 0,
3107	};
3108
3109	/*
3110	* Local variables:
3111	* c-basic-offset: 8
3112	* c-indent-level: 8
3113	* tab-width: 8
3114	* End:
3115	*/

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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/etherfabric.c@ 1300

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