pcnet32.c@ 34708

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1	/**************************************************************************
2	*
3	* pcnet32.c -- Etherboot device driver for the AMD PCnet32
4	* Written 2003-2003 by Timothy Legge <[email protected]>
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19	*
20	* Portions of this code based on:
21	* pcnet32.c: An AMD PCnet32 ethernet driver for linux:
22	*
23	* (C) 1996-1999 Thomas Bogendoerfer
24	* See Linux Driver for full information
25	*
26	* The transmit and poll functions were written with reference to:
27	* lance.c - LANCE NIC driver for Etherboot written by Ken Yap
28	*
29	* Linux Driver Version 1.27a, 10.02.2002
30	*
31	*
32	* REVISION HISTORY:
33	* ================
34	* v1.0 08-06-2003 timlegge Initial port of Linux driver
35	* v1.1 08-23-2003 timlegge Add multicast support
36	* v1.2 01-17-2004 timlegge Initial driver output cleanup
37	* v1.3 03-29-2004 timlegge More driver cleanup
38	*
39	* Indent Options: indent -kr -i8
40	***************************************************************************/
41
42	/*
43	* Oracle GPL Disclaimer: For the avoidance of doubt, except that if any license choice
44	* other than GPL or LGPL is available it will apply instead, Oracle elects to use only
45	* the General Public License version 2 (GPLv2) at this time for any software where
46	* a choice of GPL license versions is made available with the language indicating
47	* that GPLv2 or any later version may be used, or where a choice of which version
48	* of the GPL is applied is otherwise unspecified.
49	*/
50
51	/* to get some global routines like printf */
52	#include "etherboot.h"
53	/* to get the interface to the body of the program */
54	#include "nic.h"
55	/* to get the PCI support functions, if this is a PCI NIC */
56	#include "pci.h"
57	/* Include the time functions */
58	#include "timer.h"
59	#include "mii.h"
60	/* void hex_dump(const char data, const unsigned int len); /
61
62	/* Etherboot Specific definations */
63	#define drv_version "v1.3"
64	#define drv_date "03-29-2004"
65
66	static u32 ioaddr; /* Globally used for the card's io address */
67
68	#ifdef EDEBUG
69	#define dprintf(x) printf x
70	#else
71	#define dprintf(x)
72	#endif
73
74	/* Condensed operations for readability. */
75	#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
76	#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
77
78	/* End Etherboot Specific */
79
80	int cards_found /* __initdata */ ;
81
82	#ifdef REMOVE
83	/* FIXME: Remove these they are probably pointless */
84
85	/*
86	* VLB I/O addresses
87	*/
88	static unsigned int pcnet32_portlist[] /__initdata / =
89	{ 0x300, 0x320, 0x340, 0x360, 0 };
90
91	static int pcnet32_debug = 1;
92	static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
93	static int pcnet32vlb; /* check for VLB cards ? */
94
95	static struct net_device *pcnet32_dev;
96
97	static int max_interrupt_work = 80;
98	static int rx_copybreak = 200;
99	#endif
100	#define PCNET32_PORT_AUI 0x00
101	#define PCNET32_PORT_10BT 0x01
102	#define PCNET32_PORT_GPSI 0x02
103	#define PCNET32_PORT_MII 0x03
104
105	#define PCNET32_PORT_PORTSEL 0x03
106	#define PCNET32_PORT_ASEL 0x04
107	#define PCNET32_PORT_100 0x40
108	#define PCNET32_PORT_FD 0x80
109
110	#define PCNET32_DMA_MASK 0xffffffff
111
112	/*
113	* table to translate option values from tulip
114	* to internal options
115	*/
116	static unsigned char options_mapping[] = {
117	PCNET32_PORT_ASEL, /* 0 Auto-select */
118	PCNET32_PORT_AUI, /* 1 BNC/AUI */
119	PCNET32_PORT_AUI, /* 2 AUI/BNC */
120	PCNET32_PORT_ASEL, /* 3 not supported */
121	PCNET32_PORT_10BT \| PCNET32_PORT_FD, /* 4 10baseT-FD */
122	PCNET32_PORT_ASEL, /* 5 not supported */
123	PCNET32_PORT_ASEL, /* 6 not supported */
124	PCNET32_PORT_ASEL, /* 7 not supported */
125	PCNET32_PORT_ASEL, /* 8 not supported */
126	PCNET32_PORT_MII, /* 9 MII 10baseT */
127	PCNET32_PORT_MII \| PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128	PCNET32_PORT_MII, /* 11 MII (autosel) */
129	PCNET32_PORT_10BT, /* 12 10BaseT */
130	PCNET32_PORT_MII \| PCNET32_PORT_100, /* 13 MII 100BaseTx */
131	PCNET32_PORT_MII \| PCNET32_PORT_100 \| PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
132	PCNET32_PORT_ASEL /* 15 not supported */
133	};
134
135	#define MAX_UNITS 8 /* More are supported, limit only on options */
136	static int options[MAX_UNITS];
137	static int full_duplex[MAX_UNITS];
138
139	/*
140	* Theory of Operation
141	*
142	* This driver uses the same software structure as the normal lance
143	* driver. So look for a verbose description in lance.c. The differences
144	* to the normal lance driver is the use of the 32bit mode of PCnet32
145	* and PCnetPCI chips. Because these chips are 32bit chips, there is no
146	* 16MB limitation and we don't need bounce buffers.
147	*/
148
149
150
151	/*
152	* Set the number of Tx and Rx buffers, using Log_2(# buffers).
153	* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
154	* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
155	*/
156	#ifndef PCNET32_LOG_TX_BUFFERS
157	#define PCNET32_LOG_TX_BUFFERS 1
158	#define PCNET32_LOG_RX_BUFFERS 2
159	#endif
160
161	#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
162	#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
163	/* FIXME: Fix this to allow multiple tx_ring descriptors */
164	#define TX_RING_LEN_BITS 0x0000 /PCNET32_LOG_TX_BUFFERS) << 12) /
165
166	#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
167	#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
168	#define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
169
170	#define PKT_BUF_SZ 1544
171
172	/* Offsets from base I/O address. */
173	#define PCNET32_WIO_RDP 0x10
174	#define PCNET32_WIO_RAP 0x12
175	#define PCNET32_WIO_RESET 0x14
176	#define PCNET32_WIO_BDP 0x16
177
178	#define PCNET32_DWIO_RDP 0x10
179	#define PCNET32_DWIO_RAP 0x14
180	#define PCNET32_DWIO_RESET 0x18
181	#define PCNET32_DWIO_BDP 0x1C
182
183	#define PCNET32_TOTAL_SIZE 0x20
184
185	/* Buffers for the tx and Rx */
186
187	/* Create a static buffer of size PKT_BUF_SZ for each
188	TX Descriptor. All descriptors point to a
189	part of this buffer */
190	static unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE];
191	// __attribute__ ((aligned(16)));
192
193	/* Create a static buffer of size PKT_BUF_SZ for each
194	RX Descriptor All descriptors point to a
195	part of this buffer */
196	static unsigned char rxb[RX_RING_SIZE * PKT_BUF_SZ];
197	// __attribute__ ((aligned(16)));
198
199	/* The PCNET32 Rx and Tx ring descriptors. */
200	struct pcnet32_rx_head {
201	u32 base;
202	s16 buf_length;
203	s16 status;
204	u32 msg_length;
205	u32 reserved;
206	};
207
208	struct pcnet32_tx_head {
209	u32 base;
210	s16 length;
211	s16 status;
212	u32 misc;
213	u32 reserved;
214	};
215
216	/* The PCNET32 32-Bit initialization block, described in databook. */
217	struct pcnet32_init_block {
218	u16 mode;
219	u16 tlen_rlen;
220	u8 phys_addr[6];
221	u16 reserved;
222	u32 filter[2];
223	/* Receive and transmit ring base, along with extra bits. */
224	u32 rx_ring;
225	u32 tx_ring;
226	};
227	/* PCnet32 access functions */
228	struct pcnet32_access {
229	u16(*read_csr) (unsigned long, int);
230	void (*write_csr) (unsigned long, int, u16);
231	u16(*read_bcr) (unsigned long, int);
232	void (*write_bcr) (unsigned long, int, u16);
233	u16(*read_rap) (unsigned long);
234	void (*write_rap) (unsigned long, u16);
235	void (*reset) (unsigned long);
236	};
237
238	/* Define the TX Descriptor */
239	static struct pcnet32_tx_head tx_ring[TX_RING_SIZE]
240	__attribute__ ((aligned(16)));
241
242
243	/* Define the RX Descriptor */
244	static struct pcnet32_rx_head rx_ring[RX_RING_SIZE]
245	__attribute__ ((aligned(16)));
246
247	/* May need to be moved to mii.h */
248	struct mii_if_info {
249	int phy_id;
250	int advertising;
251	unsigned int full_duplex:1; /* is full duplex? */
252	};
253
254	/*
255	* The first three fields of pcnet32_private are read by the ethernet device
256	* so we allocate the structure should be allocated by pci_alloc_consistent().
257	*/
258	#define MII_CNT 4
259	struct pcnet32_private {
260	struct pcnet32_init_block init_block;
261	struct pci_dev pci_dev; / Pointer to the associated pci device structure */
262	const char *name;
263	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
264	struct sk_buff *tx_skbuff[TX_RING_SIZE];
265	struct sk_buff *rx_skbuff[RX_RING_SIZE];
266	struct pcnet32_access a;
267	unsigned int cur_rx, cur_tx; /* The next free ring entry */
268	char tx_full;
269	int options;
270	int shared_irq:1, /* shared irq possible */
271	ltint:1, /* enable TxDone-intr inhibitor */
272	dxsuflo:1, /* disable transmit stop on uflo */
273	mii:1; /* mii port available */
274	struct mii_if_info mii_if;
275	unsigned char phys[MII_CNT];
276	struct net_device *next;
277	int full_duplex:1;
278	} lpx;
279
280	static struct pcnet32_private *lp;
281
282	static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num);
283	#if 0
284	static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
285	int val);
286	#endif
287	enum pci_flags_bit {
288	PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4,
289	PCI_ADDR0 = 0x10 << 0, PCI_ADDR1 = 0x10 << 1, PCI_ADDR2 =
290	0x10 << 2, PCI_ADDR3 = 0x10 << 3,
291	};
292
293
294	static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
295	{
296	outw(index, addr + PCNET32_WIO_RAP);
297	return inw(addr + PCNET32_WIO_RDP);
298	}
299
300	static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
301	{
302	outw(index, addr + PCNET32_WIO_RAP);
303	outw(val, addr + PCNET32_WIO_RDP);
304	}
305
306	static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
307	{
308	outw(index, addr + PCNET32_WIO_RAP);
309	return inw(addr + PCNET32_WIO_BDP);
310	}
311
312	static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
313	{
314	outw(index, addr + PCNET32_WIO_RAP);
315	outw(val, addr + PCNET32_WIO_BDP);
316	}
317
318	static u16 pcnet32_wio_read_rap(unsigned long addr)
319	{
320	return inw(addr + PCNET32_WIO_RAP);
321	}
322
323	static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
324	{
325	outw(val, addr + PCNET32_WIO_RAP);
326	}
327
328	static void pcnet32_wio_reset(unsigned long addr)
329	{
330	inw(addr + PCNET32_WIO_RESET);
331	}
332
333	static int pcnet32_wio_check(unsigned long addr)
334	{
335	outw(88, addr + PCNET32_WIO_RAP);
336	return (inw(addr + PCNET32_WIO_RAP) == 88);
337	}
338
339	static struct pcnet32_access pcnet32_wio = {
340	read_csr:pcnet32_wio_read_csr,
341	write_csr:pcnet32_wio_write_csr,
342	read_bcr:pcnet32_wio_read_bcr,
343	write_bcr:pcnet32_wio_write_bcr,
344	read_rap:pcnet32_wio_read_rap,
345	write_rap:pcnet32_wio_write_rap,
346	reset:pcnet32_wio_reset
347	};
348
349	static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
350	{
351	outl(index, addr + PCNET32_DWIO_RAP);
352	return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
353	}
354
355	static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
356	{
357	outl(index, addr + PCNET32_DWIO_RAP);
358	outl(val, addr + PCNET32_DWIO_RDP);
359	}
360
361	static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
362	{
363	outl(index, addr + PCNET32_DWIO_RAP);
364	return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
365	}
366
367	static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
368	{
369	outl(index, addr + PCNET32_DWIO_RAP);
370	outl(val, addr + PCNET32_DWIO_BDP);
371	}
372
373	static u16 pcnet32_dwio_read_rap(unsigned long addr)
374	{
375	return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
376	}
377
378	static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
379	{
380	outl(val, addr + PCNET32_DWIO_RAP);
381	}
382
383	static void pcnet32_dwio_reset(unsigned long addr)
384	{
385	inl(addr + PCNET32_DWIO_RESET);
386	}
387
388	static int pcnet32_dwio_check(unsigned long addr)
389	{
390	outl(88, addr + PCNET32_DWIO_RAP);
391	return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
392	}
393
394	static struct pcnet32_access pcnet32_dwio = {
395	read_csr:pcnet32_dwio_read_csr,
396	write_csr:pcnet32_dwio_write_csr,
397	read_bcr:pcnet32_dwio_read_bcr,
398	write_bcr:pcnet32_dwio_write_bcr,
399	read_rap:pcnet32_dwio_read_rap,
400	write_rap:pcnet32_dwio_write_rap,
401	reset:pcnet32_dwio_reset
402	};
403
404
405	/* Initialize the PCNET32 Rx and Tx rings. */
406	static int pcnet32_init_ring(struct nic *nic)
407	{
408	int i;
409
410	lp->tx_full = 0;
411	lp->cur_rx = lp->cur_tx = 0;
412
413	for (i = 0; i < RX_RING_SIZE; i++) {
414	rx_ring[i].base = (u32) virt_to_le32desc(&rxb[i * PKT_BUF_SZ]);
415	rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
416	rx_ring[i].status = le16_to_cpu(0x8000);
417	}
418
419	/* The Tx buffer address is filled in as needed, but we do need to clear
420	the upper ownership bit. */
421	for (i = 0; i < TX_RING_SIZE; i++) {
422	tx_ring[i].base = 0;
423	tx_ring[i].status = 0;
424	}
425
426
427	lp->init_block.tlen_rlen =
428	le16_to_cpu(TX_RING_LEN_BITS \| RX_RING_LEN_BITS);
429	for (i = 0; i < 6; i++)
430	lp->init_block.phys_addr[i] = nic->node_addr[i];
431	lp->init_block.rx_ring = (u32) virt_to_le32desc(&rx_ring[0]);
432	lp->init_block.tx_ring = (u32) virt_to_le32desc(&tx_ring[0]);
433	return 0;
434	}
435
436	/**************************************************************************
437	RESET - Reset adapter
438	***************************************************************************/
439	static void pcnet32_reset(struct nic *nic)
440	{
441	/* put the card in its initial state */
442	u16 val;
443	int i;
444
445	/* Reset the PCNET32 */
446	lp->a.reset(ioaddr);
447
448	/* switch pcnet32 to 32bit mode */
449	lp->a.write_bcr(ioaddr, 20, 2);
450
451	/* set/reset autoselect bit */
452	val = lp->a.read_bcr(ioaddr, 2) & ~2;
453	if (lp->options & PCNET32_PORT_ASEL)
454	val \|= 2;
455	lp->a.write_bcr(ioaddr, 2, val);
456
457	/* handle full duplex setting */
458	if (lp->full_duplex) {
459	val = lp->a.read_bcr(ioaddr, 9) & ~3;
460	if (lp->options & PCNET32_PORT_FD) {
461	val \|= 1;
462	if (lp->options ==
463	(PCNET32_PORT_FD \| PCNET32_PORT_AUI))
464	val \|= 2;
465	} else if (lp->options & PCNET32_PORT_ASEL) {
466	/* workaround of xSeries250, turn on for 79C975 only */
467	i = ((lp->a.
468	read_csr(ioaddr,
469	88) \| (lp->a.read_csr(ioaddr,
470	89) << 16)) >>
471	12) & 0xffff;
472	if (i == 0x2627)
473	val \|= 3;
474	}
475	lp->a.write_bcr(ioaddr, 9, val);
476	}
477
478	/* set/reset GPSI bit in test register */
479	val = lp->a.read_csr(ioaddr, 124) & ~0x10;
480	if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
481	val \|= 0x10;
482	lp->a.write_csr(ioaddr, 124, val);
483
484	if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
485	val = lp->a.read_bcr(ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
486	if (lp->options & PCNET32_PORT_FD)
487	val \|= 0x10;
488	if (lp->options & PCNET32_PORT_100)
489	val \|= 0x08;
490	lp->a.write_bcr(ioaddr, 32, val);
491	} else {
492	if (lp->options & PCNET32_PORT_ASEL) { /* enable auto negotiate, setup, disable fd */
493	val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
494	val \|= 0x20;
495	lp->a.write_bcr(ioaddr, 32, val);
496	}
497	}
498
499	#ifdef DO_DXSUFLO
500	if (lp->dxsuflo) { /* Disable transmit stop on underflow */
501	val = lp->a.read_csr(ioaddr, 3);
502	val \|= 0x40;
503	lp->a.write_csr(ioaddr, 3, val);
504	}
505	#endif
506	if (1)
507	{
508	//disable interrupts
509	val = lp->a.read_csr(ioaddr, 3);
510	val = val
511	\| (1 << 14) //BABLM intr disabled
512	\| (1 << 12) //MISSM missed frame mask intr disabled
513	\| (1 << 10) //RINTM receive intr disabled
514	\| (1 << 9) //TINTM transmit intr disabled
515	\| (1 << 8) //IDONM init done intr disabled
516	;
517	lp->a.write_csr(ioaddr, 3, val);
518	}
519
520	if (lp->ltint) { /* Enable TxDone-intr inhibitor */
521	val = lp->a.read_csr(ioaddr, 5);
522	val \|= (1 << 14);
523	lp->a.write_csr(ioaddr, 5, val);
524	}
525	lp->init_block.mode =
526	le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
527	lp->init_block.filter[0] = 0xffffffff;
528	lp->init_block.filter[1] = 0xffffffff;
529
530	pcnet32_init_ring(nic);
531
532
533	/* Re-initialize the PCNET32, and start it when done. */
534	lp->a.write_csr(ioaddr, 1,
535	(virt_to_bus(&lp->init_block)) & 0xffff);
536	lp->a.write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
537	lp->a.write_csr(ioaddr, 4, 0x0915);
538	lp->a.write_csr(ioaddr, 0, 0x0001);
539
540
541	i = 0;
542	while (i++ < 100)
543	if (lp->a.read_csr(ioaddr, 0) & 0x0100)
544	break;
545	/*
546	* We used to clear the InitDone bit, 0x0100, here but Mark Stockton
547	* reports that doing so triggers a bug in the '974.
548	*/
549	lp->a.write_csr(ioaddr, 0, 0x0042);
550
551	dprintf(("pcnet32 open, csr0 %hX.\n", lp->a.read_csr(ioaddr, 0)));
552
553	}
554
555	/**************************************************************************
556	POLL - Wait for a frame
557	***************************************************************************/
558	static int pcnet32_poll(struct nic *nic __unused, int retrieve)
559	{
560	/* return true if there's an ethernet packet ready to read */
561	/* nic->packet should contain data on return */
562	/* nic->packetlen should contain length of data */
563
564	int status;
565	int entry;
566
567	#ifdef VBOX
568	/* Check if there is any interrupt pending. */
569	status = lp->a.read_csr(ioaddr, 0) & (1 << 7);
570	/** @todo the following line is a workaround for the pcnet device implementation in VBox, it unsets the INTR bit in CSR0 way too early for UINT. Remove when the pcnet device is fixed*/
571	status \|= lp->a.read_csr(ioaddr, 4) & (1 << 6);
572	/* Acknowledge all extended2 interrupts. */
573	lp->a.write_csr(ioaddr, 7, lp->a.read_csr(ioaddr, 7));
574	/* Acknowledge all extended interrupts. */
575	lp->a.write_csr(ioaddr, 5, lp->a.read_csr(ioaddr, 5));
576	/* Acknowledge all test and feature control interrupts (we use UINT). */
577	lp->a.write_csr(ioaddr, 4, lp->a.read_csr(ioaddr, 4));
578	/* Acknowledge all normal interrupts. */
579	lp->a.write_csr(ioaddr, 0, lp->a.read_csr(ioaddr, 0));
580	if (status && !retrieve)
581	return 1;
582	#endif /* VBOX */
583
584	entry = lp->cur_rx & RX_RING_MOD_MASK;
585	status = ((short) le16_to_cpu(rx_ring[entry].status) >> 8);
586
587	#ifdef VBOX
588	if (status != 0x03)
589	#else /* !VBOX */
590	if (status < 0)
591	#endif /* !VBOX */
592	return 0;
593
594	if ( ! retrieve ) return 1;
595
596	if (status == 0x03) {
597	nic->packetlen =
598	(le32_to_cpu(rx_ring[entry].msg_length) & 0xfff) - 4;
599	memcpy(nic->packet, &rxb[entry * PKT_BUF_SZ], nic->packetlen);
600
601	/* Andrew Boyd of QNX reports that some revs of the 79C765
602	* clear the buffer length */
603	rx_ring[entry].buf_length = le16_to_cpu(-PKT_BUF_SZ);
604	rx_ring[entry].status \|= le16_to_cpu(0x8000); /* prime for next receive */
605	/* Switch to the next Rx ring buffer */
606	lp->cur_rx++;
607
608	} else {
609	return 0;
610	}
611
612	return 1;
613	}
614
615	/**************************************************************************
616	TRANSMIT - Transmit a frame
617	***************************************************************************/
618	static void pcnet32_transmit(struct nic nic __unused, const char d, /* Destination */
619	unsigned int t, /* Type */
620	unsigned int s, /* size */
621	const char *p)
622	{ /* Packet */
623	/* send the packet to destination */
624	unsigned long time;
625	u8 *ptxb;
626	u16 nstype;
627	u16 status;
628	int entry = 0; /lp->cur_tx & TX_RING_MOD_MASK; /
629
630	status = 0x8300;
631	/* point to the current txb incase multiple tx_rings are used */
632	ptxb = txb + (lp->cur_tx * PKT_BUF_SZ);
633
634	/* copy the packet to ring buffer */
635	memcpy(ptxb, d, ETH_ALEN); /* dst */
636	memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
637	nstype = htons((u16) t); /* type */
638	memcpy(ptxb + 2 * ETH_ALEN, (u8 ) & nstype, 2); / type */
639	memcpy(ptxb + ETH_HLEN, p, s);
640
641	s += ETH_HLEN;
642	while (s < ETH_ZLEN) /* pad to min length */
643	ptxb[s++] = '\0';
644
645	tx_ring[entry].length = le16_to_cpu(-s);
646	tx_ring[entry].misc = 0x00000000;
647	tx_ring[entry].base = (u32) virt_to_le32desc(ptxb);
648
649	/* we set the top byte as the very last thing */
650	tx_ring[entry].status = le16_to_cpu(status);
651
652
653	/* Trigger an immediate send poll */
654	lp->a.write_csr(ioaddr, 0, 0x0048);
655
656	/* wait for transmit complete */
657	lp->cur_tx = 0; /* (lp->cur_tx + 1); */
658	time = currticks() + TICKS_PER_SEC; /* wait one second */
659	while (currticks() < time &&
660	((short) le16_to_cpu(tx_ring[entry].status) < 0));
661
662	if ((short) le16_to_cpu(tx_ring[entry].status) < 0)
663	printf("PCNET32 timed out on transmit\n");
664
665	/* Stop pointing at the current txb
666	* otherwise the card continues to send the packet */
667	tx_ring[entry].base = 0;
668
669	}
670
671	/**************************************************************************
672	DISABLE - Turn off ethernet interface
673	***************************************************************************/
674	static void pcnet32_disable(struct dev *dev __unused)
675	{
676	/* Stop the PCNET32 here -- it ocassionally polls memory if we don't */
677	lp->a.write_csr(ioaddr, 0, 0x0004);
678
679	/*
680	* Switch back to 16-bit mode to avoid problems with dumb
681	* DOS packet driver after a warm reboot
682	*/
683	lp->a.write_bcr(ioaddr, 20, 0);
684	}
685
686	/**************************************************************************
687	IRQ - Enable, Disable, or Force interrupts
688	***************************************************************************/
689	#ifdef VBOX
690	static void pcnet32_irq(struct nic *nic __unused, irq_action_t action)
691	{
692	u16 val;
693	switch ( action ) {
694	case DISABLE :
695	val = lp->a.read_csr(ioaddr, 3);
696	val = val
697	\| (1 << 14) //BABLM intr disabled
698	\| (1 << 12) //MISSM missed frame mask intr disabled
699	\| (1 << 10) //RINTM receive intr disabled
700	\| (1 << 9) //TINTM transmit intr disabled
701	\| (1 << 8) //IDONM init done intr disabled
702	;
703	lp->a.write_csr(ioaddr, 3, val);
704	lp->a.write_csr(ioaddr, 0, lp->a.read_csr(ioaddr, 0) & ~0x0040);
705	break;
706	case ENABLE :
707	val = lp->a.read_csr(ioaddr, 3);
708	val = val & ~(1 << 10); //RINTM receive intr enabled
709	lp->a.write_csr(ioaddr, 3, val);
710	lp->a.write_csr(ioaddr, 0, lp->a.read_csr(ioaddr, 0) \| 0x0040);
711	break;
712	case FORCE :
713	lp->a.write_csr(ioaddr, 0, lp->a.read_csr(ioaddr, 0) \| 0x0040);
714	lp->a.write_csr(ioaddr, 4, 1 << 7); /* Trigger a "UINT" = user interrupt */
715	break;
716	}
717	}
718	#else /* !VBOX */
719	static void pcnet32_irq(struct nic *nic __unused, irq_action_t action __unused)
720	{
721	switch ( action ) {
722	case DISABLE :
723	break;
724	case ENABLE :
725	break;
726	case FORCE :
727	break;
728	}
729	}
730	#endif /* VBOX */
731
732	/**************************************************************************
733	PROBE - Look for an adapter, this routine's visible to the outside
734	You should omit the last argument struct pci_device * for a non-PCI NIC
735	***************************************************************************/
736	static int pcnet32_probe(struct dev dev, struct pci_device pci)
737	{
738	struct nic nic = (struct nic ) dev;
739	int i, media;
740	int fdx, mii, fset, dxsuflo, ltint;
741	int chip_version;
742	char *chipname;
743	struct pcnet32_access *a = NULL;
744	u8 promaddr[6];
745
746	int shared = 1;
747	if (pci->ioaddr == 0)
748	return 0;
749
750	/* BASE is used throughout to address the card */
751	ioaddr = pci->ioaddr;
752	#ifndef VBOX
753	printf("pcnet32.c: Found %s, Vendor=0x%hX Device=0x%hX\n",
754	pci->name, pci->vendor, pci->dev_id);
755	#endif /* !VBOX */
756
757	#ifdef VBOX
758	nic->irqno = pci->irq;
759	#else /* !VBOX */
760	nic->irqno = 0;
761	#endif /* !VBOX */
762	nic->ioaddr = pci->ioaddr & ~3;
763
764	/* reset the chip */
765	pcnet32_wio_reset(ioaddr);
766
767	/* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
768	if (pcnet32_wio_read_csr(ioaddr, 0) == 4
769	&& pcnet32_wio_check(ioaddr)) {
770	a = &pcnet32_wio;
771	} else {
772	pcnet32_dwio_reset(ioaddr);
773	if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
774	&& pcnet32_dwio_check(ioaddr)) {
775	a = &pcnet32_dwio;
776	} else
777	return 0;
778	}
779
780	chip_version =
781	a->read_csr(ioaddr, 88) \| (a->read_csr(ioaddr, 89) << 16);
782
783	dprintf(("PCnet chip version is 0x%X\n", chip_version));
784	if ((chip_version & 0xfff) != 0x003)
785	return 0;
786
787	/* initialize variables */
788	fdx = mii = fset = dxsuflo = ltint = 0;
789	chip_version = (chip_version >> 12) & 0xffff;
790
791	switch (chip_version) {
792	case 0x2420:
793	chipname = "PCnet/PCI 79C970"; /* PCI */
794	break;
795	case 0x2430:
796	if (shared)
797	chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
798	else
799	chipname = "PCnet/32 79C965"; /* 486/VL bus */
800	break;
801	case 0x2621:
802	chipname = "PCnet/PCI II 79C970A"; /* PCI */
803	fdx = 1;
804	break;
805	case 0x2623:
806	chipname = "PCnet/FAST 79C971"; /* PCI */
807	fdx = 1;
808	mii = 1;
809	fset = 1;
810	ltint = 1;
811	break;
812	case 0x2624:
813	chipname = "PCnet/FAST+ 79C972"; /* PCI */
814	fdx = 1;
815	mii = 1;
816	fset = 1;
817	break;
818	case 0x2625:
819	chipname = "PCnet/FAST III 79C973"; /* PCI */
820	fdx = 1;
821	mii = 1;
822	break;
823	case 0x2626:
824	chipname = "PCnet/Home 79C978"; /* PCI */
825	fdx = 1;
826	/*
827	* This is based on specs published at www.amd.com. This section
828	* assumes that a card with a 79C978 wants to go into 1Mb HomePNA
829	* mode. The 79C978 can also go into standard ethernet, and there
830	* probably should be some sort of module option to select the
831	* mode by which the card should operate
832	*/
833	/* switch to home wiring mode */
834	media = a->read_bcr(ioaddr, 49);
835
836	printf("media reset to %#x.\n", media);
837	a->write_bcr(ioaddr, 49, media);
838	break;
839	case 0x2627:
840	chipname = "PCnet/FAST III 79C975"; /* PCI */
841	fdx = 1;
842	mii = 1;
843	break;
844	default:
845	chipname = "UNKNOWN";
846	printf("PCnet version %#x, no PCnet32 chip.\n",
847	chip_version);
848	return 0;
849	}
850
851	/*
852	* On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
853	* starting until the packet is loaded. Strike one for reliability, lose
854	* one for latency - although on PCI this isnt a big loss. Older chips
855	* have FIFO's smaller than a packet, so you can't do this.
856	*/
857
858	if (fset) {
859	a->write_bcr(ioaddr, 18,
860	(a->read_bcr(ioaddr, 18) \| 0x0800));
861	a->write_csr(ioaddr, 80,
862	(a->read_csr(ioaddr, 80) & 0x0C00) \| 0x0c00);
863	dxsuflo = 1;
864	ltint = 1;
865	}
866
867	dprintf(("%s at %hX,", chipname, ioaddr));
868
869	/* read PROM address */
870	for (i = 0; i < 6; i++)
871	promaddr[i] = inb(ioaddr + i);
872
873	/* Update the nic structure with the MAC Address */
874	for (i = 0; i < ETH_ALEN; i++) {
875	nic->node_addr[i] = promaddr[i];
876	}
877	#ifndef VBOX
878	/* Print out some hardware info */
879	printf("%s: %! at ioaddr 0x%hX, ", chipname, nic->node_addr,
880	ioaddr);
881	#endif /* VBOX */
882
883	/* Set to pci bus master */
884	adjust_pci_device(pci);
885
886	/* point to private storage */
887	lp = &lpx;
888
889	#if EBDEBUG
890	if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */
891	i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
892	dprintf((" tx_start_pt(0x%hX):", i));
893	switch (i >> 10) {
894	case 0:
895	dprintf((" 20 bytes,"));
896	break;
897	case 1:
898	dprintf((" 64 bytes,"));
899	break;
900	case 2:
901	dprintf((" 128 bytes,"));
902	break;
903	case 3:
904	dprintf(("~220 bytes,"));
905	break;
906	}
907	i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
908	dprintf((" BCR18(%hX):", i & 0xffff));
909	if (i & (1 << 5))
910	dprintf(("BurstWrEn "));
911	if (i & (1 << 6))
912	dprintf(("BurstRdEn "));
913	if (i & (1 << 7))
914	dprintf(("DWordIO "));
915	if (i & (1 << 11))
916	dprintf(("NoUFlow "));
917	i = a->read_bcr(ioaddr, 25);
918	dprintf((" SRAMSIZE=0x%hX,", i << 8));
919	i = a->read_bcr(ioaddr, 26);
920	dprintf((" SRAM_BND=0x%hX,", i << 8));
921	i = a->read_bcr(ioaddr, 27);
922	if (i & (1 << 14))
923	dprintf(("LowLatRx"));
924	}
925	#endif
926	lp->name = chipname;
927	lp->shared_irq = shared;
928	lp->full_duplex = fdx;
929	lp->dxsuflo = dxsuflo;
930	lp->ltint = ltint;
931	lp->mii = mii;
932	/* FIXME: Fix Options for only one card */
933	if ((cards_found >= MAX_UNITS)
934	\|\| ((unsigned int) options[cards_found] > sizeof(options_mapping)))
935	lp->options = PCNET32_PORT_ASEL;
936	else
937	lp->options = options_mapping[options[cards_found]];
938
939	if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
940	((cards_found >= MAX_UNITS) \|\| full_duplex[cards_found]))
941	lp->options \|= PCNET32_PORT_FD;
942
943	if (!a) {
944	printf("No access methods\n");
945	return 0;
946	}
947	lp->a = *a;
948
949	/* detect special T1/E1 WAN card by checking for MAC address */
950	if (nic->node_addr[0] == 0x00 && nic->node_addr[1] == 0xe0
951	&& nic->node_addr[2] == 0x75)
952	lp->options = PCNET32_PORT_FD \| PCNET32_PORT_GPSI;
953
954	lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
955	lp->init_block.tlen_rlen =
956	le16_to_cpu(TX_RING_LEN_BITS \| RX_RING_LEN_BITS);
957	for (i = 0; i < 6; i++)
958	lp->init_block.phys_addr[i] = nic->node_addr[i];
959	lp->init_block.filter[0] = 0xffffffff;
960	lp->init_block.filter[1] = 0xffffffff;
961	lp->init_block.rx_ring = virt_to_bus(&rx_ring);
962	lp->init_block.tx_ring = virt_to_bus(&tx_ring);
963
964	/* switch pcnet32 to 32bit mode */
965	a->write_bcr(ioaddr, 20, 2);
966
967	a->write_csr(ioaddr, 1, (virt_to_bus(&lp->init_block)) & 0xffff);
968	a->write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
969
970	/*
971	* To auto-IRQ we enable the initialization-done and DMA error
972	* interrupts. For ISA boards we get a DMA error, but VLB and PCI
973	* boards will work.
974	*/
975	/* Trigger an initialization just for the interrupt. */
976
977
978	// a->write_csr(ioaddr, 0, 0x41);
979	// mdelay(1);
980
981	cards_found++;
982
983	/* point to NIC specific routines */
984	pcnet32_reset(nic);
985	if (mii) {
986	int tmp;
987	int phy, phy_idx = 0;
988	u16 mii_lpa;
989	lp->phys[0] = 1; /* Default Setting */
990	#ifdef VBOX
991	for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
992	#else /* !VBOX */
993	for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
994	#endif /* !VBOX */
995	int mii_status = mdio_read(nic, phy, MII_BMSR);
996	if (mii_status != 0xffff && mii_status != 0x0000) {
997	lp->phys[phy_idx++] = phy;
998	lp->mii_if.advertising =
999	mdio_read(nic, phy, MII_ADVERTISE);
1000	if ((mii_status & 0x0040) == 0) {
1001	tmp = phy;
1002	dprintf (("MII PHY found at address %d, status "
1003	"%hX advertising %hX\n", phy, mii_status,
1004	lp->mii_if.advertising));
1005	}
1006	}
1007	}
1008	if (phy_idx == 0)
1009	printf("No MII transceiver found!\n");
1010	lp->mii_if.phy_id = lp->phys[0];
1011
1012	lp->mii_if.advertising =
1013	mdio_read(nic, lp->phys[0], MII_ADVERTISE);
1014
1015	mii_lpa = mdio_read(nic, lp->phys[0], MII_LPA);
1016	lp->mii_if.advertising &= mii_lpa;
1017	#ifndef VBOX
1018	if (lp->mii_if.advertising & ADVERTISE_100FULL)
1019	printf("100Mbps Full-Duplex\n");
1020	else if (lp->mii_if.advertising & ADVERTISE_100HALF)
1021	printf("100Mbps Half-Duplex\n");
1022	else if (lp->mii_if.advertising & ADVERTISE_10FULL)
1023	printf("10Mbps Full-Duplex\n");
1024	else if (lp->mii_if.advertising & ADVERTISE_10HALF)
1025	printf("10Mbps Half-Duplex\n");
1026	else
1027	printf("No Link?\n");
1028	#endif /* !VBOX */
1029	} else {
1030	/* The older chips are fixed 10Mbps, and some support full duplex,
1031	* although not via autonegotiation, but only via configuration. */
1032	#ifndef VBOX
1033	if (fdx)
1034	printf("10Mbps Full-Duplex\n");
1035	else
1036	printf("10Mbps Half-Duplex\n");
1037	#endif /* !VBOX */
1038	}
1039
1040	nic->poll = pcnet32_poll;
1041	nic->transmit = pcnet32_transmit;
1042	dev->disable = pcnet32_disable;
1043	nic->irq = pcnet32_irq;
1044
1045	return 1;
1046	}
1047	static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num)
1048	{
1049	u16 val_out;
1050	int phyaddr;
1051
1052	if (!lp->mii)
1053	return 0;
1054
1055	phyaddr = lp->a.read_bcr(ioaddr, 33);
1056
1057	lp->a.write_bcr(ioaddr, 33,
1058	((phy_id & 0x1f) << 5) \| (reg_num & 0x1f));
1059	val_out = lp->a.read_bcr(ioaddr, 34);
1060	lp->a.write_bcr(ioaddr, 33, phyaddr);
1061
1062	return val_out;
1063	}
1064
1065	#if 0
1066	static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
1067	int val)
1068	{
1069	int phyaddr;
1070
1071	if (!lp->mii)
1072	return;
1073
1074	phyaddr = lp->a.read_bcr(ioaddr, 33);
1075
1076	lp->a.write_bcr(ioaddr, 33,
1077	((phy_id & 0x1f) << 5) \| (reg_num & 0x1f));
1078	lp->a.write_bcr(ioaddr, 34, val);
1079	lp->a.write_bcr(ioaddr, 33, phyaddr);
1080	}
1081	#endif
1082
1083	static struct pci_id pcnet32_nics[] = {
1084	PCI_ROM(0x1022, 0x2000, "pcnet32", "AMD PCnet/PCI"),
1085	PCI_ROM(0x1022, 0x2625, "pcnetfastiii", "AMD PCNet FAST III"),
1086	PCI_ROM(0x1022, 0x2001, "amdhomepna", "AMD PCnet/HomePNA"),
1087	};
1088
1089	static struct pci_driver pcnet32_driver __pci_driver = {
1090	.type = NIC_DRIVER,
1091	.name = "PCNET32/PCI",
1092	.probe = pcnet32_probe,
1093	.ids = pcnet32_nics,
1094	.id_count = sizeof(pcnet32_nics) / sizeof(pcnet32_nics[0]),
1095	.class = 0,
1096	};

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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/pcnet32.c@ 34708

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