tlan.c@ 1

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1	/**************************************************************************
2	*
3	* tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
4	* Written 2003-2003 by Timothy Legge <[email protected]>
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19	*
20	* Portions of this code based on:
21	* lan.c: Linux ThunderLan Driver:
22	*
23	* by James Banks
24	*
25	* (C) 1997-1998 Caldera, Inc.
26	* (C) 1998 James Banks
27	* (C) 1999-2001 Torben Mathiasen
28	* (C) 2002 Samuel Chessman
29	*
30	* REVISION HISTORY:
31	* ================
32	* v1.0 07-08-2003 timlegge Initial not quite working version
33	* v1.1 07-27-2003 timlegge Sync 5.0 and 5.1 versions
34	* v1.2 08-19-2003 timlegge Implement Multicast Support
35	* v1.3 08-23-2003 timlegge Fix the transmit Function
36	* v1.4 01-17-2004 timlegge Initial driver output cleanup
37	*
38	* Indent Options: indent -kr -i8
39	***************************************************************************/
40
41	/* to get some global routines like printf */
42	#include "etherboot.h"
43	/* to get the interface to the body of the program */
44	#include "nic.h"
45	/* to get the PCI support functions, if this is a PCI NIC */
46	#include "pci.h"
47	#include "timer.h"
48	#include "tlan.h"
49
50	#define drv_version "v1.4"
51	#define drv_date "01-17-2004"
52
53	/* NIC specific static variables go here */
54	#define HZ 100
55	#define TX_TIME_OUT (6*HZ)
56
57	/* Condensed operations for readability. */
58	#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
59	#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
60
61	//#define EDEBUG
62	#ifdef EDEBUG
63	#define dprintf(x) printf x
64	#else
65	#define dprintf(x)
66	#endif
67
68	static void TLan_ResetLists(struct nic *nic __unused);
69	static void TLan_ResetAdapter(struct nic *nic __unused);
70	static void TLan_FinishReset(struct nic *nic __unused);
71
72	static void TLan_EeSendStart(u16);
73	static int TLan_EeSendByte(u16, u8, int);
74	static void TLan_EeReceiveByte(u16, u8 *, int);
75	static int TLan_EeReadByte(u16 io_base, u8, u8 *);
76
77	static void TLan_PhyDetect(struct nic *nic);
78	static void TLan_PhyPowerDown(struct nic *nic);
79	static void TLan_PhyPowerUp(struct nic *nic);
80
81
82	static void TLan_SetMac(struct nic nic __unused, int areg, char mac);
83
84	static void TLan_PhyReset(struct nic *nic);
85	static void TLan_PhyStartLink(struct nic *nic);
86	static void TLan_PhyFinishAutoNeg(struct nic *nic);
87
88	#ifdef MONITOR
89	static void TLan_PhyMonitor(struct nic *nic);
90	#endif
91
92
93	static void refill_rx(struct nic *nic __unused);
94
95	static int TLan_MiiReadReg(struct nic nic __unused, u16, u16, u16 );
96	static void TLan_MiiSendData(u16, u32, unsigned);
97	static void TLan_MiiSync(u16);
98	static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16);
99
100
101	const char *media[] = {
102	"10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
103	"100baseTx-FD", "100baseT4", 0
104	};
105
106	/* This much match tlan_pci_tbl[]! */
107	enum tlan_nics {
108	NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
109	4, NETEL100PI = 5,
110	NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
111	10, NETELLIGENT_10_100_WS_5100 = 11,
112	NETELLIGENT_10_T2 = 12
113	};
114
115	struct pci_id_info {
116	const char *name;
117	int nic_id;
118	struct match_info {
119	u32 pci, pci_mask, subsystem, subsystem_mask;
120	u32 revision, revision_mask; /* Only 8 bits. */
121	} id;
122	u32 flags;
123	u16 addrOfs; /* Address Offset */
124	};
125
126	static struct pci_id_info tlan_pci_tbl[] = {
127	{"Compaq Netelligent 10 T PCI UTP", NETEL10,
128	{0xae340e11, 0xffffffff, 0, 0, 0, 0},
129	TLAN_ADAPTER_ACTIVITY_LED, 0x83},
130	{"Compaq Netelligent 10/100 TX PCI UTP", NETEL100,
131	{0xae320e11, 0xffffffff, 0, 0, 0, 0},
132	TLAN_ADAPTER_ACTIVITY_LED, 0x83},
133	{"Compaq Integrated NetFlex-3/P", NETFLEX3I,
134	{0xae350e11, 0xffffffff, 0, 0, 0, 0},
135	TLAN_ADAPTER_NONE, 0x83},
136	{"Compaq NetFlex-3/P", THUNDER,
137	{0xf1300e11, 0xffffffff, 0, 0, 0, 0},
138	TLAN_ADAPTER_UNMANAGED_PHY \| TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
139	{"Compaq NetFlex-3/P", NETFLEX3B,
140	{0xf1500e11, 0xffffffff, 0, 0, 0, 0},
141	TLAN_ADAPTER_NONE, 0x83},
142	{"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI,
143	{0xae430e11, 0xffffffff, 0, 0, 0, 0},
144	TLAN_ADAPTER_ACTIVITY_LED, 0x83},
145	{"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D,
146	{0xae400e11, 0xffffffff, 0, 0, 0, 0},
147	TLAN_ADAPTER_NONE, 0x83},
148	{"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I,
149	{0xb0110e11, 0xffffffff, 0, 0, 0, 0},
150	TLAN_ADAPTER_NONE, 0x83},
151	{"Olicom OC-2183/2185", OC2183,
152	{0x0013108d, 0xffffffff, 0, 0, 0, 0},
153	TLAN_ADAPTER_USE_INTERN_10, 0x83},
154	{"Olicom OC-2325", OC2325,
155	{0x0012108d, 0xffffffff, 0, 0, 0, 0},
156	TLAN_ADAPTER_UNMANAGED_PHY, 0xF8},
157	{"Olicom OC-2326", OC2326,
158	{0x0014108d, 0xffffffff, 0, 0, 0, 0},
159	TLAN_ADAPTER_USE_INTERN_10, 0xF8},
160	{"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100,
161	{0xb0300e11, 0xffffffff, 0, 0, 0, 0},
162	TLAN_ADAPTER_ACTIVITY_LED, 0x83},
163	{"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2,
164	{0xb0120e11, 0xffffffff, 0, 0, 0, 0},
165	TLAN_ADAPTER_NONE, 0x83},
166	{"Compaq NetFlex-3/E", 0, /* EISA card */
167	{0, 0, 0, 0, 0, 0},
168	TLAN_ADAPTER_ACTIVITY_LED \| TLAN_ADAPTER_UNMANAGED_PHY \|
169	TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
170	{"Compaq NetFlex-3/E", 0, /* EISA card */
171	{0, 0, 0, 0, 0, 0},
172	TLAN_ADAPTER_ACTIVITY_LED, 0x83},
173	{0, 0,
174	{0, 0, 0, 0, 0, 0},
175	0, 0},
176	};
177
178	struct TLanList {
179	u32 forward;
180	u16 cStat;
181	u16 frameSize;
182	struct {
183	u32 count;
184	u32 address;
185	} buffer[TLAN_BUFFERS_PER_LIST];
186	};
187
188	struct TLanList tx_ring[TLAN_NUM_TX_LISTS];
189	static unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS];
190
191	struct TLanList rx_ring[TLAN_NUM_RX_LISTS];
192	static unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS];
193
194	typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
195
196	int chip_idx;
197
198	/*****************************************************************
199	* TLAN Private Information Structure
200	*
201	****************************************************************/
202	struct tlan_private {
203	unsigned short vendor_id; /* PCI Vendor code */
204	unsigned short dev_id; /* PCI Device code */
205	const char *nic_name;
206	unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indicies */
207	unsigned rx_buf_sz; /* Based on mtu + Slack */
208	struct TLanList *txList;
209	u32 txHead;
210	u32 txInProgress;
211	u32 txTail;
212	int eoc;
213	u32 phyOnline;
214	u32 aui;
215	u32 duplex;
216	u32 phy[2];
217	u32 phyNum;
218	u32 speed;
219	u8 tlanRev;
220	u8 tlanFullDuplex;
221	u8 link;
222	u8 neg_be_verbose;
223	} TLanPrivateInfo;
224
225	static struct tlan_private *priv;
226
227	u32 BASE;
228
229	/***************************************************************
230	* TLan_ResetLists
231	*
232	* Returns:
233	* Nothing
234	* Parms:
235	* dev The device structure with the list
236	* stuctures to be reset.
237	*
238	* This routine sets the variables associated with managing
239	* the TLAN lists to their initial values.
240	*
241	**************************************************************/
242
243	void TLan_ResetLists(struct nic *nic __unused)
244	{
245
246	int i;
247	struct TLanList *list;
248	priv->txHead = 0;
249	priv->txTail = 0;
250
251	for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
252	list = &tx_ring[i];
253	list->cStat = TLAN_CSTAT_UNUSED;
254	list->buffer[0].address = virt_to_bus(txb +
255	(i * TLAN_MAX_FRAME_SIZE));
256	list->buffer[2].count = 0;
257	list->buffer[2].address = 0;
258	list->buffer[9].address = 0;
259	}
260
261	priv->cur_rx = 0;
262	priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
263	// priv->rx_head_desc = &rx_ring[0];
264
265	/* Initialize all the Rx descriptors */
266	for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
267	rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
268	rx_ring[i].cStat = TLAN_CSTAT_READY;
269	rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
270	rx_ring[i].buffer[0].count =
271	TLAN_MAX_FRAME_SIZE \| TLAN_LAST_BUFFER;
272	rx_ring[i].buffer[0].address =
273	virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
274	rx_ring[i].buffer[1].count = 0;
275	rx_ring[i].buffer[1].address = 0;
276	}
277
278	/* Mark the last entry as wrapping the ring */
279	rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
280	priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
281
282	} /* TLan_ResetLists */
283
284	/***************************************************************
285	* TLan_Reset
286	*
287	* Returns:
288	* 0
289	* Parms:
290	* dev Pointer to device structure of adapter
291	* to be reset.
292	*
293	* This function resets the adapter and it's physical
294	* device. See Chap. 3, pp. 9-10 of the "ThunderLAN
295	* Programmer's Guide" for details. The routine tries to
296	* implement what is detailed there, though adjustments
297	* have been made.
298	*
299	**************************************************************/
300
301	void TLan_ResetAdapter(struct nic *nic __unused)
302	{
303	int i;
304	u32 addr;
305	u32 data;
306	u8 data8;
307
308	priv->tlanFullDuplex = FALSE;
309	priv->phyOnline = 0;
310	/* 1. Assert reset bit. */
311
312	data = inl(BASE + TLAN_HOST_CMD);
313	data \|= TLAN_HC_AD_RST;
314	outl(data, BASE + TLAN_HOST_CMD);
315
316	udelay(1000);
317
318	/* 2. Turn off interrupts. ( Probably isn't necessary ) */
319
320	data = inl(BASE + TLAN_HOST_CMD);
321	data \|= TLAN_HC_INT_OFF;
322	outl(data, BASE + TLAN_HOST_CMD);
323	/* 3. Clear AREGs and HASHs. */
324
325	for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
326	TLan_DioWrite32(BASE, (u16) i, 0);
327	}
328
329	/* 4. Setup NetConfig register. */
330
331	data =
332	TLAN_NET_CFG_1FRAG \| TLAN_NET_CFG_1CHAN \| TLAN_NET_CFG_PHY_EN;
333	TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
334
335	/* 5. Load Ld_Tmr and Ld_Thr in HOST_CMD. */
336
337	outl(TLAN_HC_LD_TMR \| 0x3f, BASE + TLAN_HOST_CMD);
338	outl(TLAN_HC_LD_THR \| 0x0, BASE + TLAN_HOST_CMD);
339
340	/* 6. Unreset the MII by setting NMRST (in NetSio) to 1. */
341
342	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
343	addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
344	TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
345
346	/* 7. Setup the remaining registers. */
347
348	if (priv->tlanRev >= 0x30) {
349	data8 = TLAN_ID_TX_EOC \| TLAN_ID_RX_EOC;
350	TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
351	}
352	TLan_PhyDetect(nic);
353	data = TLAN_NET_CFG_1FRAG \| TLAN_NET_CFG_1CHAN;
354
355	if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
356	data \|= TLAN_NET_CFG_BIT;
357	if (priv->aui == 1) {
358	TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
359	} else if (priv->duplex == TLAN_DUPLEX_FULL) {
360	TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
361	priv->tlanFullDuplex = TRUE;
362	} else {
363	TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
364	}
365	}
366
367	if (priv->phyNum == 0) {
368	data \|= TLAN_NET_CFG_PHY_EN;
369	}
370	TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
371
372	if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
373	TLan_FinishReset(nic);
374	} else {
375	TLan_PhyPowerDown(nic);
376	}
377
378	} /* TLan_ResetAdapter */
379
380	void TLan_FinishReset(struct nic *nic)
381	{
382
383	u8 data;
384	u32 phy;
385	u8 sio;
386	u16 status;
387	u16 partner;
388	u16 tlphy_ctl;
389	u16 tlphy_par;
390	u16 tlphy_id1, tlphy_id2;
391	int i;
392
393	phy = priv->phy[priv->phyNum];
394
395	data = TLAN_NET_CMD_NRESET \| TLAN_NET_CMD_NWRAP;
396	if (priv->tlanFullDuplex) {
397	data \|= TLAN_NET_CMD_DUPLEX;
398	}
399	TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
400	data = TLAN_NET_MASK_MASK4 \| TLAN_NET_MASK_MASK5;
401	if (priv->phyNum == 0) {
402	data \|= TLAN_NET_MASK_MASK7;
403	}
404	TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
405	TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
406	TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &tlphy_id1);
407	TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &tlphy_id2);
408
409	if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
410	\|\| (priv->aui)) {
411	status = MII_GS_LINK;
412	dprintf(("TLAN: %s: Link forced.\n", priv->nic_name));
413	} else {
414	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
415	udelay(1000);
416	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
417	if ((status & MII_GS_LINK) && /* We only support link info on Nat.Sem. PHY's */
418	(tlphy_id1 == NAT_SEM_ID1)
419	&& (tlphy_id2 == NAT_SEM_ID2)) {
420	TLan_MiiReadReg(nic, phy, MII_AN_LPA, &partner);
421	TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
422	&tlphy_par);
423
424	dprintf(("TLAN: %s: Link active with ",
425	priv->nic_name));
426	if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
427	dprintf(("forced 10%sMbps %s-Duplex\n",
428	tlphy_par & TLAN_PHY_SPEED_100 ? ""
429	: "0",
430	tlphy_par & TLAN_PHY_DUPLEX_FULL ?
431	"Full" : "Half"));
432	} else {
433	dprintf
434	(("AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
435	tlphy_par & TLAN_PHY_SPEED_100 ? "" :
436	"0",
437	tlphy_par & TLAN_PHY_DUPLEX_FULL ?
438	"Full" : "Half"));
439	dprintf(("TLAN: Partner capability: "));
440	for (i = 5; i <= 10; i++)
441	if (partner & (1 << i))
442	dprintf(("%s", media[i - 5]));
443	dprintf(("\n"));
444	}
445
446	TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
447	#ifdef MONITOR
448	/* We have link beat..for now anyway */
449	priv->link = 1;
450	/Enabling link beat monitoring /
451	/* TLan_SetTimer( nic, (10HZ), TLAN_TIMER_LINK_BEAT ); /
452	mdelay(10000);
453	TLan_PhyMonitor(nic);
454	#endif
455	} else if (status & MII_GS_LINK) {
456	dprintf(("TLAN: %s: Link active\n", priv->nic_name));
457	TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
458	}
459	}
460
461	if (priv->phyNum == 0) {
462	TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
463	tlphy_ctl \|= TLAN_TC_INTEN;
464	TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
465	sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
466	sio \|= TLAN_NET_SIO_MINTEN;
467	TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
468	}
469
470	if (status & MII_GS_LINK) {
471	TLan_SetMac(nic, 0, nic->node_addr);
472	priv->phyOnline = 1;
473	outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
474	outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
475	outl(TLAN_HC_GO \| TLAN_HC_RT, BASE + TLAN_HOST_CMD);
476	} else {
477	dprintf
478	(("TLAN: %s: Link inactive, will retry in 10 secs...\n",
479	priv->nic_name));
480	/* TLan_SetTimer( nic, (10HZ), TLAN_TIMER_FINISH_RESET ); /
481	mdelay(10000);
482	TLan_FinishReset(nic);
483	return;
484
485	}
486
487	} /* TLan_FinishReset */
488
489	/**************************************************************************
490	POLL - Wait for a frame
491	***************************************************************************/
492	static int tlan_poll(struct nic *nic, int retrieve)
493	{
494	/* return true if there's an ethernet packet ready to read */
495	/* nic->packet should contain data on return */
496	/* nic->packetlen should contain length of data */
497	u32 framesize;
498	u32 host_cmd = 0;
499	u32 ack = 1;
500	int eoc = 0;
501	int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
502	u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
503	u16 host_int = inw(BASE + TLAN_HOST_INT);
504
505	if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
506	return 1;
507
508	outw(host_int, BASE + TLAN_HOST_INT);
509
510	if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
511	return 0;
512
513	/* printf("PI-1: 0x%hX\n", host_int); */
514	if (tmpCStat & TLAN_CSTAT_EOC)
515	eoc = 1;
516
517	framesize = rx_ring[entry].frameSize;
518
519	nic->packetlen = framesize;
520
521	dprintf((".%d.", framesize));
522
523	memcpy(nic->packet, rxb +
524	(priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
525
526	rx_ring[entry].cStat = 0;
527
528	dprintf(("%d", entry));
529
530	entry = (entry + 1) % TLAN_NUM_RX_LISTS;
531	priv->cur_rx = entry;
532	if (eoc) {
533	if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
534	TLAN_CSTAT_READY) {
535	ack \|= TLAN_HC_GO \| TLAN_HC_RT;
536	host_cmd = TLAN_HC_ACK \| ack \| 0x001C0000;
537	outl(host_cmd, BASE + TLAN_HOST_CMD);
538	}
539	} else {
540	host_cmd = TLAN_HC_ACK \| ack \| (0x000C0000);
541	outl(host_cmd, BASE + TLAN_HOST_CMD);
542
543	dprintf(("AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM)));
544	dprintf(("PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT)));
545	}
546	refill_rx(nic);
547	return (1); /* initially as this is called to flush the input */
548	}
549
550	static void refill_rx(struct nic *nic __unused)
551	{
552	int entry = 0;
553
554	for (;
555	(priv->cur_rx - priv->dirty_rx +
556	TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
557	priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
558	entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
559	rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
560	rx_ring[entry].cStat = TLAN_CSTAT_READY;
561	}
562
563	}
564
565	/**************************************************************************
566	TRANSMIT - Transmit a frame
567	***************************************************************************/
568	static void tlan_transmit(struct nic nic, const char d, /* Destination */
569	unsigned int t, /* Type */
570	unsigned int s, /* size */
571	const char *p)
572	{ /* Packet */
573	u16 nstype;
574	u32 to;
575	struct TLanList *tail_list;
576	struct TLanList *head_list;
577	u8 *tail_buffer;
578	u32 ack = 0;
579	u32 host_cmd;
580	int eoc = 0;
581	u16 tmpCStat;
582	#ifdef EBDEBUG
583	u16 host_int = inw(BASE + TLAN_HOST_INT);
584	#endif
585	int entry = 0;
586
587	dprintf(("INT0-0x%hX\n", host_int));
588
589	if (!priv->phyOnline) {
590	printf("TRANSMIT: %s PHY is not ready\n", priv->nic_name);
591	return;
592	}
593
594	tail_list = priv->txList + priv->txTail;
595
596	if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
597	printf("TRANSMIT: %s is busy (Head=%d Tail=%d)\n",
598	priv->nic_name, priv->txList, priv->txTail);
599	tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
600	// priv->txBusyCount++;
601	return;
602	}
603
604	tail_list->forward = 0;
605
606	tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
607
608	/* send the packet to destination */
609	memcpy(tail_buffer, d, ETH_ALEN);
610	memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
611	nstype = htons((u16) t);
612	memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
613	memcpy(tail_buffer + ETH_HLEN, p, s);
614
615	s += ETH_HLEN;
616	s &= 0x0FFF;
617	while (s < ETH_ZLEN)
618	tail_buffer[s++] = '\0';
619
620	/=====================================================/
621	/* Receive
622	* 0000 0000 0001 1100
623	* 0000 0000 0000 1100
624	* 0000 0000 0000 0011 = 0x0003
625	*
626	* 0000 0000 0000 0000 0000 0000 0000 0011
627	* 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
628	*
629	* Transmit
630	* 0000 0000 0001 1100
631	* 0000 0000 0000 0100
632	* 0000 0000 0000 0001 = 0x0001
633	*
634	* 0000 0000 0000 0000 0000 0000 0000 0001
635	* 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
636	* */
637
638	/* Setup the transmit descriptor */
639	tail_list->frameSize = (u16) s;
640	tail_list->buffer[0].count = TLAN_LAST_BUFFER \| (u32) s;
641	tail_list->buffer[1].count = 0;
642	tail_list->buffer[1].address = 0;
643
644	tail_list->cStat = TLAN_CSTAT_READY;
645
646	dprintf(("INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT)));
647
648	if (!priv->txInProgress) {
649	priv->txInProgress = 1;
650	outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
651	outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
652	} else {
653	if (priv->txTail == 0) {
654	dprintf(("Out buffer\n"));
655	(priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
656	virt_to_le32desc(tail_list);
657	} else {
658	dprintf(("Fix this \n"));
659	(priv->txList + (priv->txTail - 1))->forward =
660	virt_to_le32desc(tail_list);
661	}
662	}
663
664	CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
665
666	dprintf(("INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT)));
667
668	to = currticks() + TX_TIME_OUT;
669	while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
670
671	head_list = priv->txList + priv->txHead;
672	while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP)
673	&& (ack < 255)) {
674	ack++;
675	if(tmpCStat & TLAN_CSTAT_EOC)
676	eoc =1;
677	head_list->cStat = TLAN_CSTAT_UNUSED;
678	CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
679	head_list = priv->txList + priv->txHead;
680
681	}
682	if(!ack)
683	printf("Incomplete TX Frame\n");
684
685	if(eoc) {
686	head_list = priv->txList + priv->txHead;
687	if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
688	outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
689	ack \|= TLAN_HC_GO;
690	} else {
691	priv->txInProgress = 0;
692	}
693	}
694	if(ack) {
695	host_cmd = TLAN_HC_ACK \| ack;
696	outl(host_cmd, BASE + TLAN_HOST_CMD);
697	}
698
699	if(priv->tlanRev < 0x30 ) {
700	ack = 1;
701	head_list = priv->txList + priv->txHead;
702	if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
703	outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
704	ack \|= TLAN_HC_GO;
705	} else {
706	priv->txInProgress = 0;
707	}
708	host_cmd = TLAN_HC_ACK \| ack \| 0x00140000;
709	outl(host_cmd, BASE + TLAN_HOST_CMD);
710
711	}
712
713	if (currticks() >= to) {
714	printf("TX Time Out");
715	}
716	}
717
718	/**************************************************************************
719	DISABLE - Turn off ethernet interface
720	***************************************************************************/
721	static void tlan_disable(struct dev *dev __unused)
722	{
723	/* put the card in its initial state */
724	/* This function serves 3 purposes.
725	* This disables DMA and interrupts so we don't receive
726	* unexpected packets or interrupts from the card after
727	* etherboot has finished.
728	* This frees resources so etherboot may use
729	* this driver on another interface
730	* This allows etherboot to reinitialize the interface
731	* if something is something goes wrong.
732	*
733	*/
734	outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
735	}
736
737	/**************************************************************************
738	IRQ - Enable, Disable, or Force interrupts
739	***************************************************************************/
740	static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused)
741	{
742	switch ( action ) {
743	case DISABLE :
744	break;
745	case ENABLE :
746	break;
747	case FORCE :
748	break;
749	}
750	}
751
752	static void TLan_SetMulticastList(struct nic *nic) {
753	int i;
754	u8 tmp;
755
756	/* !IFF_PROMISC */
757	tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
758	TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
759
760	/* IFF_ALLMULTI */
761	for(i = 0; i< 3; i++)
762	TLan_SetMac(nic, i + 1, NULL);
763	TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
764	TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
765
766
767	}
768	/**************************************************************************
769	PROBE - Look for an adapter, this routine's visible to the outside
770	***************************************************************************/
771
772	#define board_found 1
773	#define valid_link 0
774	static int tlan_probe(struct dev dev, struct pci_device pci)
775	{
776	struct nic nic = (struct nic ) dev;
777	u16 data = 0;
778	int err;
779	int i;
780
781	if (pci->ioaddr == 0)
782	return 0;
783
784	nic->irqno = 0;
785	nic->ioaddr = pci->ioaddr & ~3;
786
787	BASE = pci->ioaddr;
788
789	printf("tlan.c: Found %s, Vendor 0x%hX, Device 0x%hX\n",
790	pci->name, pci->vendor, pci->dev_id);
791
792	/* Set nic as PCI bus master */
793	adjust_pci_device(pci);
794
795	/* Point to private storage */
796	priv = &TLanPrivateInfo;
797
798	/* Figure out which chip we're dealing with */
799	i = 0;
800	chip_idx = -1;
801	while (tlan_pci_tbl[i].name) {
802	if ((((u32) pci->dev_id << 16) \| pci->vendor) ==
803	(tlan_pci_tbl[i].id.pci & 0xffffffff)) {
804	chip_idx = i;
805	break;
806	}
807	i++;
808	}
809
810	priv->vendor_id = pci->vendor;
811	priv->dev_id = pci->dev_id;
812	priv->nic_name = pci->name;
813	priv->eoc = 0;
814
815	err = 0;
816	for (i = 0; i < 6; i++)
817	err \|= TLan_EeReadByte(BASE,
818	(u8) tlan_pci_tbl[chip_idx].
819	addrOfs + i,
820	(u8 *) & nic->node_addr[i]);
821	if (err) {
822	printf("TLAN: %s: Error reading MAC from eeprom: %d\n",
823	pci->name, err);
824	} else
825	/* Print out some hardware info */
826	printf("%s: %! at ioaddr %hX, ",
827	pci->name, nic->node_addr, pci->ioaddr);
828
829	priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
830	printf("revision: 0x%hX\n", priv->tlanRev);
831
832	TLan_ResetLists(nic);
833	TLan_ResetAdapter(nic);
834
835	data = inl(BASE + TLAN_HOST_CMD);
836	data \|= TLAN_HC_INT_OFF;
837	outw(data, BASE + TLAN_HOST_CMD);
838
839	TLan_SetMulticastList(nic);
840	udelay(100);
841	priv->txList = tx_ring;
842
843	/* if (board_found && valid_link)
844	{*/
845	/* point to NIC specific routines */
846
847	dev->disable = tlan_disable;
848	nic->poll = tlan_poll;
849	nic->transmit = tlan_transmit;
850	nic->irq = tlan_irq;
851	return 1;
852	}
853
854
855	/*****************************************************************************
856	******************************************************************************
857
858	ThunderLAN Driver Eeprom routines
859
860	The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A
861	EEPROM. These functions are based on information in Microchip's
862	data sheet. I don't know how well this functions will work with
863	other EEPROMs.
864
865	******************************************************************************
866	*****************************************************************************/
867
868
869	/***************************************************************
870	* TLan_EeSendStart
871	*
872	* Returns:
873	* Nothing
874	* Parms:
875	* io_base The IO port base address for the
876	* TLAN device with the EEPROM to
877	* use.
878	*
879	* This function sends a start cycle to an EEPROM attached
880	* to a TLAN chip.
881	*
882	**************************************************************/
883
884	void TLan_EeSendStart(u16 io_base)
885	{
886	u16 sio;
887
888	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
889	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
890
891	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
892	TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
893	TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
894	TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
895	TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
896
897	} /* TLan_EeSendStart */
898
899	/***************************************************************
900	* TLan_EeSendByte
901	*
902	* Returns:
903	* If the correct ack was received, 0, otherwise 1
904	* Parms: io_base The IO port base address for the
905	* TLAN device with the EEPROM to
906	* use.
907	* data The 8 bits of information to
908	* send to the EEPROM.
909	* stop If TLAN_EEPROM_STOP is passed, a
910	* stop cycle is sent after the
911	* byte is sent after the ack is
912	* read.
913	*
914	* This function sends a byte on the serial EEPROM line,
915	* driving the clock to send each bit. The function then
916	* reverses transmission direction and reads an acknowledge
917	* bit.
918	*
919	**************************************************************/
920
921	int TLan_EeSendByte(u16 io_base, u8 data, int stop)
922	{
923	int err;
924	u8 place;
925	u16 sio;
926
927	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
928	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
929
930	/* Assume clock is low, tx is enabled; */
931	for (place = 0x80; place != 0; place >>= 1) {
932	if (place & data)
933	TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
934	else
935	TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
936	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
937	TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
938	}
939	TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
940	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
941	err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
942	TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
943	TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
944
945	if ((!err) && stop) {
946	TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
947	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
948	TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
949	}
950
951	return (err);
952
953	} /* TLan_EeSendByte */
954
955	/***************************************************************
956	* TLan_EeReceiveByte
957	*
958	* Returns:
959	* Nothing
960	* Parms:
961	* io_base The IO port base address for the
962	* TLAN device with the EEPROM to
963	* use.
964	* data An address to a char to hold the
965	* data sent from the EEPROM.
966	* stop If TLAN_EEPROM_STOP is passed, a
967	* stop cycle is sent after the
968	* byte is received, and no ack is
969	* sent.
970	*
971	* This function receives 8 bits of data from the EEPROM
972	* over the serial link. It then sends and ack bit, or no
973	* ack and a stop bit. This function is used to retrieve
974	* data after the address of a byte in the EEPROM has been
975	* sent.
976	*
977	**************************************************************/
978
979	void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop)
980	{
981	u8 place;
982	u16 sio;
983
984	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
985	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
986	*data = 0;
987
988	/* Assume clock is low, tx is enabled; */
989	TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
990	for (place = 0x80; place; place >>= 1) {
991	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
992	if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
993	*data \|= place;
994	TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
995	}
996
997	TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
998	if (!stop) {
999	TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */
1000	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1001	TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1002	} else {
1003	TLan_SetBit(TLAN_NET_SIO_EDATA, sio); /* No ack = 1 (?) */
1004	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1005	TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1006	TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
1007	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1008	TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1009	}
1010
1011	} /* TLan_EeReceiveByte */
1012
1013	/***************************************************************
1014	* TLan_EeReadByte
1015	*
1016	* Returns:
1017	* No error = 0, else, the stage at which the error
1018	* occurred.
1019	* Parms:
1020	* io_base The IO port base address for the
1021	* TLAN device with the EEPROM to
1022	* use.
1023	* ee_addr The address of the byte in the
1024	* EEPROM whose contents are to be
1025	* retrieved.
1026	* data An address to a char to hold the
1027	* data obtained from the EEPROM.
1028	*
1029	* This function reads a byte of information from an byte
1030	* cell in the EEPROM.
1031	*
1032	**************************************************************/
1033
1034	int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data)
1035	{
1036	int err;
1037	int ret = 0;
1038
1039
1040	TLan_EeSendStart(io_base);
1041	err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
1042	if (err) {
1043	ret = 1;
1044	goto fail;
1045	}
1046	err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
1047	if (err) {
1048	ret = 2;
1049	goto fail;
1050	}
1051	TLan_EeSendStart(io_base);
1052	err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
1053	if (err) {
1054	ret = 3;
1055	goto fail;
1056	}
1057	TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
1058	fail:
1059
1060	return ret;
1061
1062	} /* TLan_EeReadByte */
1063
1064
1065	/*****************************************************************************
1066	******************************************************************************
1067
1068	ThunderLAN Driver MII Routines
1069
1070	These routines are based on the information in Chap. 2 of the
1071	"ThunderLAN Programmer's Guide", pp. 15-24.
1072
1073	******************************************************************************
1074	*****************************************************************************/
1075
1076
1077	/***************************************************************
1078	* TLan_MiiReadReg
1079	*
1080	* Returns:
1081	* 0 if ack received ok
1082	* 1 otherwise.
1083	*
1084	* Parms:
1085	* dev The device structure containing
1086	* The io address and interrupt count
1087	* for this device.
1088	* phy The address of the PHY to be queried.
1089	* reg The register whose contents are to be
1090	* retreived.
1091	* val A pointer to a variable to store the
1092	* retrieved value.
1093	*
1094	* This function uses the TLAN's MII bus to retreive the contents
1095	* of a given register on a PHY. It sends the appropriate info
1096	* and then reads the 16-bit register value from the MII bus via
1097	* the TLAN SIO register.
1098	*
1099	**************************************************************/
1100
1101	int TLan_MiiReadReg(struct nic nic __unused, u16 phy, u16 reg, u16 val)
1102	{
1103	u8 nack;
1104	u16 sio, tmp;
1105	u32 i;
1106	int err;
1107	int minten;
1108
1109	err = FALSE;
1110	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1111	sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1112
1113	TLan_MiiSync(BASE);
1114
1115	minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1116	if (minten)
1117	TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1118
1119	TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1120	TLan_MiiSendData(BASE, 0x2, 2); /* Read ( 10b ) */
1121	TLan_MiiSendData(BASE, phy, 5); /* Device # */
1122	TLan_MiiSendData(BASE, reg, 5); /* Register # */
1123
1124
1125	TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */
1126
1127	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Clock Idle bit */
1128	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1129	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Wait 300ns */
1130
1131	nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio); /* Check for ACK */
1132	TLan_SetBit(TLAN_NET_SIO_MCLK, sio); /* Finish ACK */
1133	if (nack) { /* No ACK, so fake it */
1134	for (i = 0; i < 16; i++) {
1135	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1136	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1137	}
1138	tmp = 0xffff;
1139	err = TRUE;
1140	} else { /* ACK, so read data */
1141	for (tmp = 0, i = 0x8000; i; i >>= 1) {
1142	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1143	if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
1144	tmp \|= i;
1145	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1146	}
1147	}
1148
1149
1150	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Idle cycle */
1151	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1152
1153	if (minten)
1154	TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1155
1156	*val = tmp;
1157
1158	return err;
1159
1160	} /* TLan_MiiReadReg */
1161
1162	/***************************************************************
1163	* TLan_MiiSendData
1164	*
1165	* Returns:
1166	* Nothing
1167	* Parms:
1168	* base_port The base IO port of the adapter in
1169	* question.
1170	* dev The address of the PHY to be queried.
1171	* data The value to be placed on the MII bus.
1172	* num_bits The number of bits in data that are to
1173	* be placed on the MII bus.
1174	*
1175	* This function sends on sequence of bits on the MII
1176	* configuration bus.
1177	*
1178	**************************************************************/
1179
1180	void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits)
1181	{
1182	u16 sio;
1183	u32 i;
1184
1185	if (num_bits == 0)
1186	return;
1187
1188	outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1189	sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1190	TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
1191
1192	for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
1193	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1194	(void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1195	if (data & i)
1196	TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
1197	else
1198	TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
1199	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1200	(void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1201	}
1202
1203	} /* TLan_MiiSendData */
1204
1205	/***************************************************************
1206	* TLan_MiiSync
1207	*
1208	* Returns:
1209	* Nothing
1210	* Parms:
1211	* base_port The base IO port of the adapter in
1212	* question.
1213	*
1214	* This functions syncs all PHYs in terms of the MII configuration
1215	* bus.
1216	*
1217	**************************************************************/
1218
1219	void TLan_MiiSync(u16 base_port)
1220	{
1221	int i;
1222	u16 sio;
1223
1224	outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1225	sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1226
1227	TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
1228	for (i = 0; i < 32; i++) {
1229	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1230	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1231	}
1232
1233	} /* TLan_MiiSync */
1234
1235	/***************************************************************
1236	* TLan_MiiWriteReg
1237	*
1238	* Returns:
1239	* Nothing
1240	* Parms:
1241	* dev The device structure for the device
1242	* to write to.
1243	* phy The address of the PHY to be written to.
1244	* reg The register whose contents are to be
1245	* written.
1246	* val The value to be written to the register.
1247	*
1248	* This function uses the TLAN's MII bus to write the contents of a
1249	* given register on a PHY. It sends the appropriate info and then
1250	* writes the 16-bit register value from the MII configuration bus
1251	* via the TLAN SIO register.
1252	*
1253	**************************************************************/
1254
1255	void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
1256	{
1257	u16 sio;
1258	int minten;
1259
1260	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1261	sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1262
1263	TLan_MiiSync(BASE);
1264
1265	minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1266	if (minten)
1267	TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1268
1269	TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1270	TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
1271	TLan_MiiSendData(BASE, phy, 5); /* Device # */
1272	TLan_MiiSendData(BASE, reg, 5); /* Register # */
1273
1274	TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
1275	TLan_MiiSendData(BASE, val, 16); /* Send Data */
1276
1277	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio); /* Idle cycle */
1278	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1279
1280	if (minten)
1281	TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1282
1283
1284	} /* TLan_MiiWriteReg */
1285
1286	/***************************************************************
1287	* TLan_SetMac
1288	*
1289	* Returns:
1290	* Nothing
1291	* Parms:
1292	* dev Pointer to device structure of adapter
1293	* on which to change the AREG.
1294	* areg The AREG to set the address in (0 - 3).
1295	* mac A pointer to an array of chars. Each
1296	* element stores one byte of the address.
1297	* IE, it isn't in ascii.
1298	*
1299	* This function transfers a MAC address to one of the
1300	* TLAN AREGs (address registers). The TLAN chip locks
1301	* the register on writing to offset 0 and unlocks the
1302	* register after writing to offset 5. If NULL is passed
1303	* in mac, then the AREG is filled with 0's.
1304	*
1305	**************************************************************/
1306
1307	void TLan_SetMac(struct nic nic __unused, int areg, char mac)
1308	{
1309	int i;
1310
1311	areg *= 6;
1312
1313	if (mac != NULL) {
1314	for (i = 0; i < 6; i++)
1315	TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1316	mac[i]);
1317	} else {
1318	for (i = 0; i < 6; i++)
1319	TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1320	}
1321
1322	} /* TLan_SetMac */
1323
1324	/*********************************************************************
1325	* TLan_PhyDetect
1326	*
1327	* Returns:
1328	* Nothing
1329	* Parms:
1330	* dev A pointer to the device structure of the adapter
1331	* for which the PHY needs determined.
1332	*
1333	* So far I've found that adapters which have external PHYs
1334	* may also use the internal PHY for part of the functionality.
1335	* (eg, AUI/Thinnet). This function finds out if this TLAN
1336	* chip has an internal PHY, and then finds the first external
1337	* PHY (starting from address 0) if it exists).
1338	*
1339	********************************************************************/
1340
1341	void TLan_PhyDetect(struct nic *nic)
1342	{
1343	u16 control;
1344	u16 hi;
1345	u16 lo;
1346	u32 phy;
1347
1348	if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
1349	priv->phyNum = 0xFFFF;
1350	return;
1351	}
1352
1353	TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_GEN_ID_HI, &hi);
1354
1355	if (hi != 0xFFFF) {
1356	priv->phy[0] = TLAN_PHY_MAX_ADDR;
1357	} else {
1358	priv->phy[0] = TLAN_PHY_NONE;
1359	}
1360
1361	priv->phy[1] = TLAN_PHY_NONE;
1362	for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
1363	TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &control);
1364	TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &hi);
1365	TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &lo);
1366	if ((control != 0xFFFF) \|\| (hi != 0xFFFF)
1367	\|\| (lo != 0xFFFF)) {
1368	printf("PHY found at %hX %hX %hX %hX\n", phy,
1369	control, hi, lo);
1370	if ((priv->phy[1] == TLAN_PHY_NONE)
1371	&& (phy != TLAN_PHY_MAX_ADDR)) {
1372	priv->phy[1] = phy;
1373	}
1374	}
1375	}
1376
1377	if (priv->phy[1] != TLAN_PHY_NONE) {
1378	priv->phyNum = 1;
1379	} else if (priv->phy[0] != TLAN_PHY_NONE) {
1380	priv->phyNum = 0;
1381	} else {
1382	printf
1383	("TLAN: Cannot initialize device, no PHY was found!\n");
1384	}
1385
1386	} /* TLan_PhyDetect */
1387
1388	void TLan_PhyPowerDown(struct nic *nic)
1389	{
1390
1391	u16 value;
1392	dprintf(("%s: Powering down PHY(s).\n", priv->nic_name));
1393	value = MII_GC_PDOWN \| MII_GC_LOOPBK \| MII_GC_ISOLATE;
1394	TLan_MiiSync(BASE);
1395	TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1396	if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
1397	&&
1398	(!(tlan_pci_tbl[chip_idx].
1399	flags & TLAN_ADAPTER_USE_INTERN_10))) {
1400	TLan_MiiSync(BASE);
1401	TLan_MiiWriteReg(nic, priv->phy[1], MII_GEN_CTL, value);
1402	}
1403
1404	/* Wait for 50 ms and powerup
1405	* This is abitrary. It is intended to make sure the
1406	* tranceiver settles.
1407	*/
1408	/* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
1409	mdelay(50);
1410	TLan_PhyPowerUp(nic);
1411
1412	} /* TLan_PhyPowerDown */
1413
1414
1415	void TLan_PhyPowerUp(struct nic *nic)
1416	{
1417	u16 value;
1418
1419	dprintf(("%s: Powering up PHY.\n", priv->nic_name));
1420	TLan_MiiSync(BASE);
1421	value = MII_GC_LOOPBK;
1422	TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1423	TLan_MiiSync(BASE);
1424	/* Wait for 500 ms and reset the
1425	* tranceiver. The TLAN docs say both 50 ms and
1426	* 500 ms, so do the longer, just in case.
1427	*/
1428	mdelay(500);
1429	TLan_PhyReset(nic);
1430	/* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
1431
1432	} /* TLan_PhyPowerUp */
1433
1434	void TLan_PhyReset(struct nic *nic)
1435	{
1436	u16 phy;
1437	u16 value;
1438
1439	phy = priv->phy[priv->phyNum];
1440
1441	dprintf(("%s: Reseting PHY.\n", priv->nic_name));
1442	TLan_MiiSync(BASE);
1443	value = MII_GC_LOOPBK \| MII_GC_RESET;
1444	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, value);
1445	TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1446	while (value & MII_GC_RESET) {
1447	TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1448	}
1449
1450	/* Wait for 500 ms and initialize.
1451	* I don't remember why I wait this long.
1452	* I've changed this to 50ms, as it seems long enough.
1453	*/
1454	/* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
1455	mdelay(50);
1456	TLan_PhyStartLink(nic);
1457
1458	} /* TLan_PhyReset */
1459
1460
1461	void TLan_PhyStartLink(struct nic *nic)
1462	{
1463
1464	u16 ability;
1465	u16 control;
1466	u16 data;
1467	u16 phy;
1468	u16 status;
1469	u16 tctl;
1470
1471	phy = priv->phy[priv->phyNum];
1472	dprintf(("%s: Trying to activate link.\n", priv->nic_name));
1473	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1474	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &ability);
1475
1476	if ((status & MII_GS_AUTONEG) && (!priv->aui)) {
1477	ability = status >> 11;
1478	if (priv->speed == TLAN_SPEED_10 &&
1479	priv->duplex == TLAN_DUPLEX_HALF) {
1480	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0000);
1481	} else if (priv->speed == TLAN_SPEED_10 &&
1482	priv->duplex == TLAN_DUPLEX_FULL) {
1483	priv->tlanFullDuplex = TRUE;
1484	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0100);
1485	} else if (priv->speed == TLAN_SPEED_100 &&
1486	priv->duplex == TLAN_DUPLEX_HALF) {
1487	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2000);
1488	} else if (priv->speed == TLAN_SPEED_100 &&
1489	priv->duplex == TLAN_DUPLEX_FULL) {
1490	priv->tlanFullDuplex = TRUE;
1491	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2100);
1492	} else {
1493
1494	/* Set Auto-Neg advertisement */
1495	TLan_MiiWriteReg(nic, phy, MII_AN_ADV,
1496	(ability << 5) \| 1);
1497	/* Enablee Auto-Neg */
1498	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1000);
1499	/* Restart Auto-Neg */
1500	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1200);
1501	/* Wait for 4 sec for autonegotiation
1502	* to complete. The max spec time is less than this
1503	* but the card need additional time to start AN.
1504	* .5 sec should be plenty extra.
1505	*/
1506	dprintf(("TLAN: %s: Starting autonegotiation.\n",
1507	priv->nic_name));
1508	mdelay(4000);
1509	TLan_PhyFinishAutoNeg(nic);
1510	/* TLan_SetTimer( dev, (2HZ), TLAN_TIMER_PHY_FINISH_AN ); /
1511	return;
1512	}
1513
1514	}
1515
1516	if ((priv->aui) && (priv->phyNum != 0)) {
1517	priv->phyNum = 0;
1518	data =
1519	TLAN_NET_CFG_1FRAG \| TLAN_NET_CFG_1CHAN \|
1520	TLAN_NET_CFG_PHY_EN;
1521	TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1522	mdelay(50);
1523	/* TLan_SetTimer( dev, (40HZ/1000), TLAN_TIMER_PHY_PDOWN ); /
1524	TLan_PhyPowerDown(nic);
1525	return;
1526	} else if (priv->phyNum == 0) {
1527	control = 0;
1528	TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
1529	if (priv->aui) {
1530	tctl \|= TLAN_TC_AUISEL;
1531	} else {
1532	tctl &= ~TLAN_TC_AUISEL;
1533	if (priv->duplex == TLAN_DUPLEX_FULL) {
1534	control \|= MII_GC_DUPLEX;
1535	priv->tlanFullDuplex = TRUE;
1536	}
1537	if (priv->speed == TLAN_SPEED_100) {
1538	control \|= MII_GC_SPEEDSEL;
1539	}
1540	}
1541	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, control);
1542	TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
1543	}
1544
1545	/* Wait for 2 sec to give the tranceiver time
1546	* to establish link.
1547	*/
1548	/* TLan_SetTimer( dev, (4HZ), TLAN_TIMER_FINISH_RESET ); /
1549	mdelay(2000);
1550	TLan_FinishReset(nic);
1551
1552	} /* TLan_PhyStartLink */
1553
1554	void TLan_PhyFinishAutoNeg(struct nic *nic)
1555	{
1556
1557	u16 an_adv;
1558	u16 an_lpa;
1559	u16 data;
1560	u16 mode;
1561	u16 phy;
1562	u16 status;
1563
1564	phy = priv->phy[priv->phyNum];
1565
1566	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1567	udelay(1000);
1568	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1569
1570	if (!(status & MII_GS_AUTOCMPLT)) {
1571	/* Wait for 8 sec to give the process
1572	* more time. Perhaps we should fail after a while.
1573	*/
1574	if (!priv->neg_be_verbose++) {
1575	printf
1576	("TLAN: Giving autonegotiation more time.\n");
1577	printf
1578	("TLAN: Please check that your adapter has\n");
1579	printf
1580	("TLAN: been properly connected to a HUB or Switch.\n");
1581	printf
1582	("TLAN: Trying to establish link in the background...\n");
1583	}
1584	mdelay(8000);
1585	TLan_PhyFinishAutoNeg(nic);
1586	/* TLan_SetTimer( dev, (8HZ), TLAN_TIMER_PHY_FINISH_AN ); /
1587	return;
1588	}
1589
1590	dprintf(("TLAN: %s: Autonegotiation complete.\n", priv->nic_name));
1591	TLan_MiiReadReg(nic, phy, MII_AN_ADV, &an_adv);
1592	TLan_MiiReadReg(nic, phy, MII_AN_LPA, &an_lpa);
1593	mode = an_adv & an_lpa & 0x03E0;
1594	if (mode & 0x0100) {
1595	printf("Full Duplex\n");
1596	priv->tlanFullDuplex = TRUE;
1597	} else if (!(mode & 0x0080) && (mode & 0x0040)) {
1598	priv->tlanFullDuplex = TRUE;
1599	printf("Full Duplex\n");
1600	}
1601
1602	if ((!(mode & 0x0180))
1603	&& (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
1604	&& (priv->phyNum != 0)) {
1605	priv->phyNum = 0;
1606	data =
1607	TLAN_NET_CFG_1FRAG \| TLAN_NET_CFG_1CHAN \|
1608	TLAN_NET_CFG_PHY_EN;
1609	TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1610	/* TLan_SetTimer( nic, (400HZ/1000), TLAN_TIMER_PHY_PDOWN ); /
1611	mdelay(400);
1612	TLan_PhyPowerDown(nic);
1613	return;
1614	}
1615
1616	if (priv->phyNum == 0) {
1617	if ((priv->duplex == TLAN_DUPLEX_FULL)
1618	\|\| (an_adv & an_lpa & 0x0040)) {
1619	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1620	MII_GC_AUTOENB \| MII_GC_DUPLEX);
1621	dprintf
1622	(("TLAN: Starting internal PHY with FULL-DUPLEX\n"));
1623	} else {
1624	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1625	MII_GC_AUTOENB);
1626	dprintf
1627	(("TLAN: Starting internal PHY with HALF-DUPLEX\n"));
1628	}
1629	}
1630
1631	/* Wait for 100 ms. No reason in partiticular.
1632	*/
1633	/* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
1634	mdelay(100);
1635	TLan_FinishReset(nic);
1636
1637	} /* TLan_PhyFinishAutoNeg */
1638
1639	#ifdef MONITOR
1640
1641	/*********************************************************************
1642	*
1643	* TLan_phyMonitor
1644	*
1645	* Returns:
1646	* None
1647	*
1648	* Params:
1649	* dev The device structure of this device.
1650	*
1651	*
1652	* This function monitors PHY condition by reading the status
1653	* register via the MII bus. This can be used to give info
1654	* about link changes (up/down), and possible switch to alternate
1655	* media.
1656	*
1657	********************************************************************/
1658
1659	void TLan_PhyMonitor(struct net_device *dev)
1660	{
1661	TLanPrivateInfo *priv = dev->priv;
1662	u16 phy;
1663	u16 phy_status;
1664
1665	phy = priv->phy[priv->phyNum];
1666
1667	/* Get PHY status register */
1668	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &phy_status);
1669
1670	/* Check if link has been lost */
1671	if (!(phy_status & MII_GS_LINK)) {
1672	if (priv->link) {
1673	priv->link = 0;
1674	printf("TLAN: %s has lost link\n", priv->nic_name);
1675	priv->flags &= ~IFF_RUNNING;
1676	mdelay(2000);
1677	TLan_PhyMonitor(nic);
1678	/* TLan_SetTimer( dev, (2HZ), TLAN_TIMER_LINK_BEAT ); /
1679	return;
1680	}
1681	}
1682
1683	/* Link restablished? */
1684	if ((phy_status & MII_GS_LINK) && !priv->link) {
1685	priv->link = 1;
1686	printf("TLAN: %s has reestablished link\n",
1687	priv->nic_name);
1688	priv->flags \|= IFF_RUNNING;
1689	}
1690
1691	/* Setup a new monitor */
1692	/* TLan_SetTimer( dev, (2HZ), TLAN_TIMER_LINK_BEAT ); /
1693	mdelay(2000);
1694	TLan_PhyMonitor(nic);
1695	}
1696
1697	#endif /* MONITOR */
1698
1699	static struct pci_id tlan_nics[] = {
1700	PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP"),
1701	PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP"),
1702	PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P"),
1703	PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P"),
1704	PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P"),
1705	PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP"),
1706	PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP"),
1707	PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP"),
1708	PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185"),
1709	PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325"),
1710	PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326"),
1711	PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP"),
1712	PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax"),
1713	};
1714
1715	static struct pci_driver tlan_driver __pci_driver = {
1716	.type = NIC_DRIVER,
1717	.name = "TLAN/PCI",
1718	.probe = tlan_probe,
1719	.ids = tlan_nics,
1720	.id_count = sizeof(tlan_nics) / sizeof(tlan_nics[0]),
1721	.class = 0,
1722	};

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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/tlan.c@ 1

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