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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/tlan.h@ 1300

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1/**************************************************************************
2*
3* tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
4* Written 2003-2003 by Timothy Legge <[email protected]>
5*
6* This program is free software; you can redistribute it and/or modify
7* it under the terms of the GNU General Public License as published by
8* the Free Software Foundation; either version 2 of the License, or
9* (at your option) any later version.
10*
11* This program is distributed in the hope that it will be useful,
12* but WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14* GNU General Public License for more details.
15*
16* You should have received a copy of the GNU General Public License
17* along with this program; if not, write to the Free Software
18* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*
20* Portions of this code (almost all) based on:
21* tlan.c: Linux ThunderLan Driver:
22*
23* by James Banks
24*
25* (C) 1997-1998 Caldera, Inc.
26* (C) 1998 James Banks
27* (C) 1999-2001 Torben Mathiasen
28* (C) 2002 Samuel Chessman
29*
30* REVISION HISTORY:
31* ================
32* v1.0 07-08-2003 timlegge Initial not quite working version
33*
34* Indent Style: indent -kr -i8
35***************************************************************************/
36
37/*****************************************************************
38* TLan Definitions
39*
40****************************************************************/
41
42#define FALSE 0
43#define TRUE 1
44
45#define TLAN_MIN_FRAME_SIZE 64
46#define TLAN_MAX_FRAME_SIZE 1600
47
48#define TLAN_NUM_RX_LISTS 4
49#define TLAN_NUM_TX_LISTS 2
50
51#define TLAN_IGNORE 0
52#define TLAN_RECORD 1
53/*
54#define TLAN_DBG(lvl, format, args...) if (debug&lvl) printf("TLAN: " format, ##args );
55*/
56#define TLAN_DEBUG_GNRL 0x0001
57#define TLAN_DEBUG_TX 0x0002
58#define TLAN_DEBUG_RX 0x0004
59#define TLAN_DEBUG_LIST 0x0008
60#define TLAN_DEBUG_PROBE 0x0010
61
62#define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */
63#define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */
64
65
66 /*****************************************************************
67 * Device Identification Definitions
68 *
69 ****************************************************************/
70
71#define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
72#define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
73#ifndef PCI_DEVICE_ID_OLICOM_OC2183
74#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
75#endif
76#ifndef PCI_DEVICE_ID_OLICOM_OC2325
77#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
78#endif
79#ifndef PCI_DEVICE_ID_OLICOM_OC2326
80#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
81#endif
82
83typedef struct tlan_adapter_entry {
84 u16 vendorId;
85 u16 deviceId;
86 char *deviceLabel;
87 u32 flags;
88 u16 addrOfs;
89} TLanAdapterEntry;
90
91#define TLAN_ADAPTER_NONE 0x00000000
92#define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001
93#define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002
94#define TLAN_ADAPTER_USE_INTERN_10 0x00000004
95#define TLAN_ADAPTER_ACTIVITY_LED 0x00000008
96
97#define TLAN_SPEED_DEFAULT 0
98#define TLAN_SPEED_10 10
99#define TLAN_SPEED_100 100
100
101#define TLAN_DUPLEX_DEFAULT 0
102#define TLAN_DUPLEX_HALF 1
103#define TLAN_DUPLEX_FULL 2
104
105
106
107 /*****************************************************************
108 * EISA Definitions
109 *
110 ****************************************************************/
111
112#define EISA_ID 0xc80 /* EISA ID Registers */
113#define EISA_ID0 0xc80 /* EISA ID Register 0 */
114#define EISA_ID1 0xc81 /* EISA ID Register 1 */
115#define EISA_ID2 0xc82 /* EISA ID Register 2 */
116#define EISA_ID3 0xc83 /* EISA ID Register 3 */
117#define EISA_CR 0xc84 /* EISA Control Register */
118#define EISA_REG0 0xc88 /* EISA Configuration Register 0 */
119#define EISA_REG1 0xc89 /* EISA Configuration Register 1 */
120#define EISA_REG2 0xc8a /* EISA Configuration Register 2 */
121#define EISA_REG3 0xc8f /* EISA Configuration Register 3 */
122#define EISA_APROM 0xc90 /* Ethernet Address PROM */
123
124
125
126 /*****************************************************************
127 * Rx/Tx List Definitions
128 *
129 ****************************************************************/
130
131#define TLAN_BUFFERS_PER_LIST 10
132#define TLAN_LAST_BUFFER 0x80000000
133#define TLAN_CSTAT_UNUSED 0x8000
134#define TLAN_CSTAT_FRM_CMP 0x4000
135#define TLAN_CSTAT_READY 0x3000
136#define TLAN_CSTAT_EOC 0x0800
137#define TLAN_CSTAT_RX_ERROR 0x0400
138#define TLAN_CSTAT_PASS_CRC 0x0200
139#define TLAN_CSTAT_DP_PR 0x0100
140
141
142
143
144
145
146 /*****************************************************************
147 * PHY definitions
148 *
149 ****************************************************************/
150
151#define TLAN_PHY_MAX_ADDR 0x1F
152#define TLAN_PHY_NONE 0x20
153
154
155
156 /*****************************************************************
157 * TLan Driver Timer Definitions
158 *
159 ****************************************************************/
160
161#define TLAN_TIMER_LINK_BEAT 1
162#define TLAN_TIMER_ACTIVITY 2
163#define TLAN_TIMER_PHY_PDOWN 3
164#define TLAN_TIMER_PHY_PUP 4
165#define TLAN_TIMER_PHY_RESET 5
166#define TLAN_TIMER_PHY_START_LINK 6
167#define TLAN_TIMER_PHY_FINISH_AN 7
168#define TLAN_TIMER_FINISH_RESET 8
169
170#define TLAN_TIMER_ACT_DELAY (HZ/10)
171
172
173
174
175 /*****************************************************************
176 * TLan Driver Eeprom Definitions
177 *
178 ****************************************************************/
179
180#define TLAN_EEPROM_ACK 0
181#define TLAN_EEPROM_STOP 1
182
183
184
185
186 /*****************************************************************
187 * Host Register Offsets and Contents
188 *
189 ****************************************************************/
190
191#define TLAN_HOST_CMD 0x00
192#define TLAN_HC_GO 0x80000000
193#define TLAN_HC_STOP 0x40000000
194#define TLAN_HC_ACK 0x20000000
195#define TLAN_HC_CS_MASK 0x1FE00000
196#define TLAN_HC_EOC 0x00100000
197#define TLAN_HC_RT 0x00080000
198#define TLAN_HC_NES 0x00040000
199#define TLAN_HC_AD_RST 0x00008000
200#define TLAN_HC_LD_TMR 0x00004000
201#define TLAN_HC_LD_THR 0x00002000
202#define TLAN_HC_REQ_INT 0x00001000
203#define TLAN_HC_INT_OFF 0x00000800
204#define TLAN_HC_INT_ON 0x00000400
205#define TLAN_HC_AC_MASK 0x000000FF
206#define TLAN_CH_PARM 0x04
207#define TLAN_DIO_ADR 0x08
208#define TLAN_DA_ADR_INC 0x8000
209#define TLAN_DA_RAM_ADR 0x4000
210#define TLAN_HOST_INT 0x0A
211#define TLAN_HI_IV_MASK 0x1FE0
212#define TLAN_HI_IT_MASK 0x001C
213#define TLAN_DIO_DATA 0x0C
214
215
216/* ThunderLAN Internal Register DIO Offsets */
217
218#define TLAN_NET_CMD 0x00
219#define TLAN_NET_CMD_NRESET 0x80
220#define TLAN_NET_CMD_NWRAP 0x40
221#define TLAN_NET_CMD_CSF 0x20
222#define TLAN_NET_CMD_CAF 0x10
223#define TLAN_NET_CMD_NOBRX 0x08
224#define TLAN_NET_CMD_DUPLEX 0x04
225#define TLAN_NET_CMD_TRFRAM 0x02
226#define TLAN_NET_CMD_TXPACE 0x01
227#define TLAN_NET_SIO 0x01
228#define TLAN_NET_SIO_MINTEN 0x80
229#define TLAN_NET_SIO_ECLOK 0x40
230#define TLAN_NET_SIO_ETXEN 0x20
231#define TLAN_NET_SIO_EDATA 0x10
232#define TLAN_NET_SIO_NMRST 0x08
233#define TLAN_NET_SIO_MCLK 0x04
234#define TLAN_NET_SIO_MTXEN 0x02
235#define TLAN_NET_SIO_MDATA 0x01
236#define TLAN_NET_STS 0x02
237#define TLAN_NET_STS_MIRQ 0x80
238#define TLAN_NET_STS_HBEAT 0x40
239#define TLAN_NET_STS_TXSTOP 0x20
240#define TLAN_NET_STS_RXSTOP 0x10
241#define TLAN_NET_STS_RSRVD 0x0F
242#define TLAN_NET_MASK 0x03
243#define TLAN_NET_MASK_MASK7 0x80
244#define TLAN_NET_MASK_MASK6 0x40
245#define TLAN_NET_MASK_MASK5 0x20
246#define TLAN_NET_MASK_MASK4 0x10
247#define TLAN_NET_MASK_RSRVD 0x0F
248#define TLAN_NET_CONFIG 0x04
249#define TLAN_NET_CFG_RCLK 0x8000
250#define TLAN_NET_CFG_TCLK 0x4000
251#define TLAN_NET_CFG_BIT 0x2000
252#define TLAN_NET_CFG_RXCRC 0x1000
253#define TLAN_NET_CFG_PEF 0x0800
254#define TLAN_NET_CFG_1FRAG 0x0400
255#define TLAN_NET_CFG_1CHAN 0x0200
256#define TLAN_NET_CFG_MTEST 0x0100
257#define TLAN_NET_CFG_PHY_EN 0x0080
258#define TLAN_NET_CFG_MSMASK 0x007F
259#define TLAN_MAN_TEST 0x06
260#define TLAN_DEF_VENDOR_ID 0x08
261#define TLAN_DEF_DEVICE_ID 0x0A
262#define TLAN_DEF_REVISION 0x0C
263#define TLAN_DEF_SUBCLASS 0x0D
264#define TLAN_DEF_MIN_LAT 0x0E
265#define TLAN_DEF_MAX_LAT 0x0F
266#define TLAN_AREG_0 0x10
267#define TLAN_AREG_1 0x16
268#define TLAN_AREG_2 0x1C
269#define TLAN_AREG_3 0x22
270#define TLAN_HASH_1 0x28
271#define TLAN_HASH_2 0x2C
272#define TLAN_GOOD_TX_FRMS 0x30
273#define TLAN_TX_UNDERUNS 0x33
274#define TLAN_GOOD_RX_FRMS 0x34
275#define TLAN_RX_OVERRUNS 0x37
276#define TLAN_DEFERRED_TX 0x38
277#define TLAN_CRC_ERRORS 0x3A
278#define TLAN_CODE_ERRORS 0x3B
279#define TLAN_MULTICOL_FRMS 0x3C
280#define TLAN_SINGLECOL_FRMS 0x3E
281#define TLAN_EXCESSCOL_FRMS 0x40
282#define TLAN_LATE_COLS 0x41
283#define TLAN_CARRIER_LOSS 0x42
284#define TLAN_ACOMMIT 0x43
285#define TLAN_LED_REG 0x44
286#define TLAN_LED_ACT 0x10
287#define TLAN_LED_LINK 0x01
288#define TLAN_BSIZE_REG 0x45
289#define TLAN_MAX_RX 0x46
290#define TLAN_INT_DIS 0x48
291#define TLAN_ID_TX_EOC 0x04
292#define TLAN_ID_RX_EOF 0x02
293#define TLAN_ID_RX_EOC 0x01
294
295
296
297/* ThunderLAN Interrupt Codes */
298
299#define TLAN_INT_NUMBER_OF_INTS 8
300
301#define TLAN_INT_NONE 0x0000
302#define TLAN_INT_TX_EOF 0x0001
303#define TLAN_INT_STAT_OVERFLOW 0x0002
304#define TLAN_INT_RX_EOF 0x0003
305#define TLAN_INT_DUMMY 0x0004
306#define TLAN_INT_TX_EOC 0x0005
307#define TLAN_INT_STATUS_CHECK 0x0006
308#define TLAN_INT_RX_EOC 0x0007
309
310
311
312/* ThunderLAN MII Registers */
313
314/* Generic MII/PHY Registers */
315
316#define MII_GEN_CTL 0x00
317#define MII_GC_RESET 0x8000
318#define MII_GC_LOOPBK 0x4000
319#define MII_GC_SPEEDSEL 0x2000
320#define MII_GC_AUTOENB 0x1000
321#define MII_GC_PDOWN 0x0800
322#define MII_GC_ISOLATE 0x0400
323#define MII_GC_AUTORSRT 0x0200
324#define MII_GC_DUPLEX 0x0100
325#define MII_GC_COLTEST 0x0080
326#define MII_GC_RESERVED 0x007F
327#define MII_GEN_STS 0x01
328#define MII_GS_100BT4 0x8000
329#define MII_GS_100BTXFD 0x4000
330#define MII_GS_100BTXHD 0x2000
331#define MII_GS_10BTFD 0x1000
332#define MII_GS_10BTHD 0x0800
333#define MII_GS_RESERVED 0x07C0
334#define MII_GS_AUTOCMPLT 0x0020
335#define MII_GS_RFLT 0x0010
336#define MII_GS_AUTONEG 0x0008
337#define MII_GS_LINK 0x0004
338#define MII_GS_JABBER 0x0002
339#define MII_GS_EXTCAP 0x0001
340#define MII_GEN_ID_HI 0x02
341#define MII_GEN_ID_LO 0x03
342#define MII_GIL_OUI 0xFC00
343#define MII_GIL_MODEL 0x03F0
344#define MII_GIL_REVISION 0x000F
345#define MII_AN_ADV 0x04
346#define MII_AN_LPA 0x05
347#define MII_AN_EXP 0x06
348
349/* ThunderLAN Specific MII/PHY Registers */
350
351#define TLAN_TLPHY_ID 0x10
352#define TLAN_TLPHY_CTL 0x11
353#define TLAN_TC_IGLINK 0x8000
354#define TLAN_TC_SWAPOL 0x4000
355#define TLAN_TC_AUISEL 0x2000
356#define TLAN_TC_SQEEN 0x1000
357#define TLAN_TC_MTEST 0x0800
358#define TLAN_TC_RESERVED 0x07F8
359#define TLAN_TC_NFEW 0x0004
360#define TLAN_TC_INTEN 0x0002
361#define TLAN_TC_TINT 0x0001
362#define TLAN_TLPHY_STS 0x12
363#define TLAN_TS_MINT 0x8000
364#define TLAN_TS_PHOK 0x4000
365#define TLAN_TS_POLOK 0x2000
366#define TLAN_TS_TPENERGY 0x1000
367#define TLAN_TS_RESERVED 0x0FFF
368#define TLAN_TLPHY_PAR 0x19
369#define TLAN_PHY_CIM_STAT 0x0020
370#define TLAN_PHY_SPEED_100 0x0040
371#define TLAN_PHY_DUPLEX_FULL 0x0080
372#define TLAN_PHY_AN_EN_STAT 0x0400
373
374/* National Sem. & Level1 PHY id's */
375#define NAT_SEM_ID1 0x2000
376#define NAT_SEM_ID2 0x5C01
377#define LEVEL1_ID1 0x7810
378#define LEVEL1_ID2 0x0000
379
380#define CIRC_INC( a, b ) if ( ++a >= b ) a = 0
381
382/* Routines to access internal registers. */
383
384inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
385{
386 outw(internal_addr, base_addr + TLAN_DIO_ADR);
387 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
388
389} /* TLan_DioRead8 */
390
391
392
393
394inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
395{
396 outw(internal_addr, base_addr + TLAN_DIO_ADR);
397 return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
398
399} /* TLan_DioRead16 */
400
401
402
403
404inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
405{
406 outw(internal_addr, base_addr + TLAN_DIO_ADR);
407 return (inl(base_addr + TLAN_DIO_DATA));
408
409} /* TLan_DioRead32 */
410
411
412
413
414inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
415{
416 outw(internal_addr, base_addr + TLAN_DIO_ADR);
417 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
418
419}
420
421
422
423
424inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
425{
426 outw(internal_addr, base_addr + TLAN_DIO_ADR);
427 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
428
429}
430
431
432
433
434inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
435{
436 outw(internal_addr, base_addr + TLAN_DIO_ADR);
437 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
438
439}
440
441
442
443#if 0
444inline void TLan_ClearBit(u8 bit, u16 port)
445{
446 outb_p(inb_p(port) & ~bit, port);
447}
448
449
450
451
452inline int TLan_GetBit(u8 bit, u16 port)
453{
454 return ((int) (inb_p(port) & bit));
455}
456
457
458
459
460inline void TLan_SetBit(u8 bit, u16 port)
461{
462 outb_p(inb_p(port) | bit, port);
463}
464#endif
465
466#define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port)
467#define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit))
468#define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port)
469
470#ifdef I_LIKE_A_FAST_HASH_FUNCTION
471/* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those */
472/* the code below is about seven times as fast as the original code */
473inline u32 TLan_HashFunc(u8 * a)
474{
475 u8 hash;
476
477 hash = (a[0] ^ a[3]); /* & 077 */
478 hash ^= ((a[0] ^ a[3]) >> 6); /* & 003 */
479 hash ^= ((a[1] ^ a[4]) << 2); /* & 074 */
480 hash ^= ((a[1] ^ a[4]) >> 4); /* & 017 */
481 hash ^= ((a[2] ^ a[5]) << 4); /* & 060 */
482 hash ^= ((a[2] ^ a[5]) >> 2); /* & 077 */
483
484 return (hash & 077);
485}
486
487#else /* original code */
488
489inline u32 xor(u32 a, u32 b)
490{
491 return ((a && !b) || (!a && b));
492}
493
494#define XOR8( a, b, c, d, e, f, g, h ) xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
495#define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
496
497inline u32 TLan_HashFunc(u8 * a)
498{
499 u32 hash;
500
501 hash =
502 XOR8(DA(a, 0), DA(a, 6), DA(a, 12), DA(a, 18), DA(a, 24),
503 DA(a, 30), DA(a, 36), DA(a, 42));
504 hash |=
505 XOR8(DA(a, 1), DA(a, 7), DA(a, 13), DA(a, 19), DA(a, 25),
506 DA(a, 31), DA(a, 37), DA(a, 43)) << 1;
507 hash |=
508 XOR8(DA(a, 2), DA(a, 8), DA(a, 14), DA(a, 20), DA(a, 26),
509 DA(a, 32), DA(a, 38), DA(a, 44)) << 2;
510 hash |=
511 XOR8(DA(a, 3), DA(a, 9), DA(a, 15), DA(a, 21), DA(a, 27),
512 DA(a, 33), DA(a, 39), DA(a, 45)) << 3;
513 hash |=
514 XOR8(DA(a, 4), DA(a, 10), DA(a, 16), DA(a, 22), DA(a, 28),
515 DA(a, 34), DA(a, 40), DA(a, 46)) << 4;
516 hash |=
517 XOR8(DA(a, 5), DA(a, 11), DA(a, 17), DA(a, 23), DA(a, 29),
518 DA(a, 35), DA(a, 41), DA(a, 47)) << 5;
519
520 return hash;
521
522}
523
524#endif /* I_LIKE_A_FAST_HASH_FUNCTION */
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