| 1 | /* rhine.c:Fast Ethernet driver for Linux. */
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| 2 | /*
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| 3 | Adapted 09-jan-2000 by Paolo Marini ([email protected])
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| 4 |
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| 5 | originally written by Donald Becker.
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| 6 |
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| 7 | This software may be used and distributed according to the terms
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| 8 | of the GNU Public License (GPL), incorporated herein by reference.
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| 9 | Drivers derived from this code also fall under the GPL and must retain
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| 10 | this authorship and copyright notice.
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| 11 |
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| 12 | Under no circumstances are the authors responsible for
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| 13 | the proper functioning of this software, nor do the authors assume any
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| 14 | responsibility for damages incurred with its use.
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| 15 |
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| 16 | This driver is designed for the VIA VT86C100A Rhine-II PCI Fast Ethernet
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| 17 | controller.
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| 18 |
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| 19 | */
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| 20 |
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| 21 | static const char *version = "rhine.c v1.0.2 2004-10-29\n";
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| 22 |
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| 23 | /* A few user-configurable values. */
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| 24 |
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| 25 | // max time out delay time
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| 26 | #define W_MAX_TIMEOUT 0x0FFFU
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| 27 |
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| 28 | /* Size of the in-memory receive ring. */
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| 29 | #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K */
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| 30 | #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
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| 31 |
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| 32 | /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
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| 33 | #define TX_BUF_SIZE 1536
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| 34 | #define RX_BUF_SIZE 1536
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| 35 |
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| 36 | /* PCI Tuning Parameters
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| 37 | Threshold is bytes transferred to chip before transmission starts. */
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| 38 | #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
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| 39 |
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| 40 | /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024. */
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| 41 | #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
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| 42 | #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
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| 43 | #define TX_DMA_BURST 4
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| 44 |
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| 45 | /* Operational parameters that usually are not changed. */
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| 46 | /* Time in jiffies before concluding the transmitter is hung. */
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| 47 | #define TX_TIMEOUT ((2000*HZ)/1000)
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| 48 |
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| 49 | #include "etherboot.h"
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| 50 | #include "nic.h"
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| 51 | #include "pci.h"
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| 52 | #include "timer.h"
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| 53 |
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| 54 | /* define all ioaddr */
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| 55 |
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| 56 | #define byPAR0 ioaddr
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| 57 | #define byRCR ioaddr + 6
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| 58 | #define byTCR ioaddr + 7
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| 59 | #define byCR0 ioaddr + 8
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| 60 | #define byCR1 ioaddr + 9
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| 61 | #define byISR0 ioaddr + 0x0c
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| 62 | #define byISR1 ioaddr + 0x0d
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| 63 | #define byIMR0 ioaddr + 0x0e
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| 64 | #define byIMR1 ioaddr + 0x0f
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| 65 | #define byMAR0 ioaddr + 0x10
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| 66 | #define byMAR1 ioaddr + 0x11
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| 67 | #define byMAR2 ioaddr + 0x12
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| 68 | #define byMAR3 ioaddr + 0x13
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| 69 | #define byMAR4 ioaddr + 0x14
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| 70 | #define byMAR5 ioaddr + 0x15
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| 71 | #define byMAR6 ioaddr + 0x16
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| 72 | #define byMAR7 ioaddr + 0x17
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| 73 | #define dwCurrentRxDescAddr ioaddr + 0x18
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| 74 | #define dwCurrentTxDescAddr ioaddr + 0x1c
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| 75 | #define dwCurrentRDSE0 ioaddr + 0x20
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| 76 | #define dwCurrentRDSE1 ioaddr + 0x24
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| 77 | #define dwCurrentRDSE2 ioaddr + 0x28
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| 78 | #define dwCurrentRDSE3 ioaddr + 0x2c
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| 79 | #define dwNextRDSE0 ioaddr + 0x30
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| 80 | #define dwNextRDSE1 ioaddr + 0x34
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| 81 | #define dwNextRDSE2 ioaddr + 0x38
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| 82 | #define dwNextRDSE3 ioaddr + 0x3c
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| 83 | #define dwCurrentTDSE0 ioaddr + 0x40
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| 84 | #define dwCurrentTDSE1 ioaddr + 0x44
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| 85 | #define dwCurrentTDSE2 ioaddr + 0x48
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| 86 | #define dwCurrentTDSE3 ioaddr + 0x4c
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| 87 | #define dwNextTDSE0 ioaddr + 0x50
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| 88 | #define dwNextTDSE1 ioaddr + 0x54
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| 89 | #define dwNextTDSE2 ioaddr + 0x58
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| 90 | #define dwNextTDSE3 ioaddr + 0x5c
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| 91 | #define dwCurrRxDMAPtr ioaddr + 0x60
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| 92 | #define dwCurrTxDMAPtr ioaddr + 0x64
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| 93 | #define byMPHY ioaddr + 0x6c
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| 94 | #define byMIISR ioaddr + 0x6d
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| 95 | #define byBCR0 ioaddr + 0x6e
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| 96 | #define byBCR1 ioaddr + 0x6f
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| 97 | #define byMIICR ioaddr + 0x70
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| 98 | #define byMIIAD ioaddr + 0x71
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| 99 | #define wMIIDATA ioaddr + 0x72
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| 100 | #define byEECSR ioaddr + 0x74
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| 101 | #define byTEST ioaddr + 0x75
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| 102 | #define byGPIO ioaddr + 0x76
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| 103 | #define byCFGA ioaddr + 0x78
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| 104 | #define byCFGB ioaddr + 0x79
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| 105 | #define byCFGC ioaddr + 0x7a
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| 106 | #define byCFGD ioaddr + 0x7b
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| 107 | #define wTallyCntMPA ioaddr + 0x7c
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| 108 | #define wTallyCntCRC ioaddr + 0x7d
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| 109 | #define bySTICKHW ioaddr + 0x83
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| 110 | #define byWOLcrClr ioaddr + 0xA4
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| 111 | #define byWOLcgClr ioaddr + 0xA7
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| 112 | #define byPwrcsrClr ioaddr + 0xAC
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| 113 |
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| 114 | /*--------------------- Exioaddr Definitions -------------------------*/
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| 115 |
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| 116 | /*
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| 117 | * Bits in the RCR register
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| 118 | */
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| 119 |
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| 120 | #define RCR_RRFT2 0x80
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| 121 | #define RCR_RRFT1 0x40
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| 122 | #define RCR_RRFT0 0x20
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| 123 | #define RCR_PROM 0x10
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| 124 | #define RCR_AB 0x08
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| 125 | #define RCR_AM 0x04
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| 126 | #define RCR_AR 0x02
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| 127 | #define RCR_SEP 0x01
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| 128 |
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| 129 | /*
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| 130 | * Bits in the TCR register
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| 131 | */
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| 132 |
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| 133 | #define TCR_RTSF 0x80
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| 134 | #define TCR_RTFT1 0x40
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| 135 | #define TCR_RTFT0 0x20
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| 136 | #define TCR_OFSET 0x08
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| 137 | #define TCR_LB1 0x04 /* loopback[1] */
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| 138 | #define TCR_LB0 0x02 /* loopback[0] */
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| 139 |
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| 140 | /*
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| 141 | * Bits in the CR0 register
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| 142 | */
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| 143 |
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| 144 | #define CR0_RDMD 0x40 /* rx descriptor polling demand */
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| 145 | #define CR0_TDMD 0x20 /* tx descriptor polling demand */
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| 146 | #define CR0_TXON 0x10
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| 147 | #define CR0_RXON 0x08
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| 148 | #define CR0_STOP 0x04 /* stop NIC, default = 1 */
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| 149 | #define CR0_STRT 0x02 /* start NIC */
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| 150 | #define CR0_INIT 0x01 /* start init process */
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| 151 |
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| 152 |
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| 153 | /*
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| 154 | * Bits in the CR1 register
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| 155 | */
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| 156 |
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| 157 | #define CR1_SFRST 0x80 /* software reset */
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| 158 | #define CR1_RDMD1 0x40 /* RDMD1 */
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| 159 | #define CR1_TDMD1 0x20 /* TDMD1 */
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| 160 | #define CR1_KEYPAG 0x10 /* turn on par/key */
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| 161 | #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
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| 162 | #define CR1_FDX 0x04 /* full duplex mode */
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| 163 | #define CR1_ETEN 0x02 /* early tx mode */
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| 164 | #define CR1_EREN 0x01 /* early rx mode */
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| 165 |
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| 166 | /*
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| 167 | * Bits in the CR register
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| 168 | */
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| 169 |
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| 170 | #define CR_RDMD 0x0040 /* rx descriptor polling demand */
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| 171 | #define CR_TDMD 0x0020 /* tx descriptor polling demand */
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| 172 | #define CR_TXON 0x0010
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| 173 | #define CR_RXON 0x0008
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| 174 | #define CR_STOP 0x0004 /* stop NIC, default = 1 */
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| 175 | #define CR_STRT 0x0002 /* start NIC */
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| 176 | #define CR_INIT 0x0001 /* start init process */
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| 177 | #define CR_SFRST 0x8000 /* software reset */
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| 178 | #define CR_RDMD1 0x4000 /* RDMD1 */
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| 179 | #define CR_TDMD1 0x2000 /* TDMD1 */
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| 180 | #define CR_KEYPAG 0x1000 /* turn on par/key */
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| 181 | #define CR_DPOLL 0x0800 /* disable rx/tx auto polling */
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| 182 | #define CR_FDX 0x0400 /* full duplex mode */
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| 183 | #define CR_ETEN 0x0200 /* early tx mode */
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| 184 | #define CR_EREN 0x0100 /* early rx mode */
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| 185 |
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| 186 | /*
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| 187 | * Bits in the IMR0 register
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| 188 | */
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| 189 |
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| 190 | #define IMR0_CNTM 0x80
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| 191 | #define IMR0_BEM 0x40
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| 192 | #define IMR0_RUM 0x20
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| 193 | #define IMR0_TUM 0x10
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| 194 | #define IMR0_TXEM 0x08
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| 195 | #define IMR0_RXEM 0x04
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| 196 | #define IMR0_PTXM 0x02
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| 197 | #define IMR0_PRXM 0x01
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| 198 |
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| 199 | /* define imrshadow */
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| 200 |
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| 201 | #define IMRShadow 0x5AFF
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| 202 |
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| 203 | /*
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| 204 | * Bits in the IMR1 register
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| 205 | */
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| 206 |
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| 207 | #define IMR1_INITM 0x80
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| 208 | #define IMR1_SRCM 0x40
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| 209 | #define IMR1_NBFM 0x10
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| 210 | #define IMR1_PRAIM 0x08
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| 211 | #define IMR1_RES0M 0x04
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| 212 | #define IMR1_ETM 0x02
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| 213 | #define IMR1_ERM 0x01
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| 214 |
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| 215 | /*
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| 216 | * Bits in the ISR register
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| 217 | */
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| 218 |
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| 219 | #define ISR_INITI 0x8000
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| 220 | #define ISR_SRCI 0x4000
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| 221 | #define ISR_ABTI 0x2000
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| 222 | #define ISR_NORBF 0x1000
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| 223 | #define ISR_PKTRA 0x0800
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| 224 | #define ISR_RES0 0x0400
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| 225 | #define ISR_ETI 0x0200
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| 226 | #define ISR_ERI 0x0100
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| 227 | #define ISR_CNT 0x0080
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| 228 | #define ISR_BE 0x0040
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| 229 | #define ISR_RU 0x0020
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| 230 | #define ISR_TU 0x0010
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| 231 | #define ISR_TXE 0x0008
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| 232 | #define ISR_RXE 0x0004
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| 233 | #define ISR_PTX 0x0002
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| 234 | #define ISR_PRX 0x0001
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| 235 |
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| 236 | /*
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| 237 | * Bits in the ISR0 register
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| 238 | */
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| 239 |
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| 240 | #define ISR0_CNT 0x80
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| 241 | #define ISR0_BE 0x40
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| 242 | #define ISR0_RU 0x20
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| 243 | #define ISR0_TU 0x10
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| 244 | #define ISR0_TXE 0x08
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| 245 | #define ISR0_RXE 0x04
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| 246 | #define ISR0_PTX 0x02
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| 247 | #define ISR0_PRX 0x01
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| 248 |
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| 249 | /*
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| 250 | * Bits in the ISR1 register
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| 251 | */
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| 252 |
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| 253 | #define ISR1_INITI 0x80
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| 254 | #define ISR1_SRCI 0x40
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| 255 | #define ISR1_NORBF 0x10
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| 256 | #define ISR1_PKTRA 0x08
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| 257 | #define ISR1_ETI 0x02
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| 258 | #define ISR1_ERI 0x01
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| 259 |
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| 260 | /* ISR ABNORMAL CONDITION */
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| 261 |
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| 262 | #define ISR_ABNORMAL ISR_BE+ISR_RU+ISR_TU+ISR_CNT+ISR_NORBF+ISR_PKTRA
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| 263 |
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| 264 | /*
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| 265 | * Bits in the MIISR register
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| 266 | */
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| 267 |
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| 268 | #define MIISR_MIIERR 0x08
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| 269 | #define MIISR_MRERR 0x04
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| 270 | #define MIISR_LNKFL 0x02
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| 271 | #define MIISR_SPEED 0x01
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| 272 |
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| 273 | /*
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| 274 | * Bits in the MIICR register
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| 275 | */
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| 276 |
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| 277 | #define MIICR_MAUTO 0x80
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| 278 | #define MIICR_RCMD 0x40
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| 279 | #define MIICR_WCMD 0x20
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| 280 | #define MIICR_MDPM 0x10
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| 281 | #define MIICR_MOUT 0x08
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| 282 | #define MIICR_MDO 0x04
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| 283 | #define MIICR_MDI 0x02
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| 284 | #define MIICR_MDC 0x01
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| 285 |
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| 286 | /*
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| 287 | * Bits in the EECSR register
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| 288 | */
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| 289 |
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| 290 | #define EECSR_EEPR 0x80 /* eeprom programed status, 73h means programed */
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| 291 | #define EECSR_EMBP 0x40 /* eeprom embeded programming */
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| 292 | #define EECSR_AUTOLD 0x20 /* eeprom content reload */
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| 293 | #define EECSR_DPM 0x10 /* eeprom direct programming */
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| 294 | #define EECSR_CS 0x08 /* eeprom CS pin */
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| 295 | #define EECSR_SK 0x04 /* eeprom SK pin */
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| 296 | #define EECSR_DI 0x02 /* eeprom DI pin */
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| 297 | #define EECSR_DO 0x01 /* eeprom DO pin */
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| 298 |
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| 299 | /*
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| 300 | * Bits in the BCR0 register
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| 301 | */
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| 302 |
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| 303 | #define BCR0_CRFT2 0x20
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| 304 | #define BCR0_CRFT1 0x10
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| 305 | #define BCR0_CRFT0 0x08
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| 306 | #define BCR0_DMAL2 0x04
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| 307 | #define BCR0_DMAL1 0x02
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| 308 | #define BCR0_DMAL0 0x01
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| 309 |
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| 310 | /*
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| 311 | * Bits in the BCR1 register
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| 312 | */
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| 313 |
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| 314 | #define BCR1_CTSF 0x20
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| 315 | #define BCR1_CTFT1 0x10
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| 316 | #define BCR1_CTFT0 0x08
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| 317 | #define BCR1_POT2 0x04
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| 318 | #define BCR1_POT1 0x02
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| 319 | #define BCR1_POT0 0x01
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| 320 |
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| 321 | /*
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| 322 | * Bits in the CFGA register
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| 323 | */
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| 324 |
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| 325 | #define CFGA_EELOAD 0x80 /* enable eeprom embeded and direct programming */
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| 326 | #define CFGA_JUMPER 0x40
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| 327 | #define CFGA_MTGPIO 0x08
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| 328 | #define CFGA_T10EN 0x02
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| 329 | #define CFGA_AUTO 0x01
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| 330 |
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| 331 | /*
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| 332 | * Bits in the CFGB register
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| 333 | */
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| 334 |
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| 335 | #define CFGB_PD 0x80
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| 336 | #define CFGB_POLEN 0x02
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| 337 | #define CFGB_LNKEN 0x01
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| 338 |
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| 339 | /*
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| 340 | * Bits in the CFGC register
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| 341 | */
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| 342 |
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| 343 | #define CFGC_M10TIO 0x80
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| 344 | #define CFGC_M10POL 0x40
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| 345 | #define CFGC_PHY1 0x20
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| 346 | #define CFGC_PHY0 0x10
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| 347 | #define CFGC_BTSEL 0x08
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| 348 | #define CFGC_BPS2 0x04 /* bootrom select[2] */
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| 349 | #define CFGC_BPS1 0x02 /* bootrom select[1] */
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| 350 | #define CFGC_BPS0 0x01 /* bootrom select[0] */
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| 351 |
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| 352 | /*
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| 353 | * Bits in the CFGD register
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| 354 | */
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| 355 |
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| 356 | #define CFGD_GPIOEN 0x80
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| 357 | #define CFGD_DIAG 0x40
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| 358 | #define CFGD_MAGIC 0x10
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| 359 | #define CFGD_RANDOM 0x08
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| 360 | #define CFGD_CFDX 0x04
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| 361 | #define CFGD_CEREN 0x02
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| 362 | #define CFGD_CETEN 0x01
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| 363 |
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| 364 | /* Bits in RSR */
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| 365 | #define RSR_RERR 0x00000001
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| 366 | #define RSR_CRC 0x00000002
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| 367 | #define RSR_FAE 0x00000004
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| 368 | #define RSR_FOV 0x00000008
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| 369 | #define RSR_LONG 0x00000010
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| 370 | #define RSR_RUNT 0x00000020
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| 371 | #define RSR_SERR 0x00000040
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| 372 | #define RSR_BUFF 0x00000080
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| 373 | #define RSR_EDP 0x00000100
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| 374 | #define RSR_STP 0x00000200
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| 375 | #define RSR_CHN 0x00000400
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| 376 | #define RSR_PHY 0x00000800
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| 377 | #define RSR_BAR 0x00001000
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| 378 | #define RSR_MAR 0x00002000
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| 379 | #define RSR_RXOK 0x00008000
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| 380 | #define RSR_ABNORMAL RSR_RERR+RSR_LONG+RSR_RUNT
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| 381 |
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| 382 | /* Bits in TSR */
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| 383 | #define TSR_NCR0 0x00000001
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| 384 | #define TSR_NCR1 0x00000002
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| 385 | #define TSR_NCR2 0x00000004
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| 386 | #define TSR_NCR3 0x00000008
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| 387 | #define TSR_COLS 0x00000010
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| 388 | #define TSR_CDH 0x00000080
|
|---|
| 389 | #define TSR_ABT 0x00000100
|
|---|
| 390 | #define TSR_OWC 0x00000200
|
|---|
| 391 | #define TSR_CRS 0x00000400
|
|---|
| 392 | #define TSR_UDF 0x00000800
|
|---|
| 393 | #define TSR_TBUFF 0x00001000
|
|---|
| 394 | #define TSR_SERR 0x00002000
|
|---|
| 395 | #define TSR_JAB 0x00004000
|
|---|
| 396 | #define TSR_TERR 0x00008000
|
|---|
| 397 | #define TSR_ABNORMAL TSR_TERR+TSR_OWC+TSR_ABT+TSR_JAB+TSR_CRS
|
|---|
| 398 | #define TSR_OWN_BIT 0x80000000
|
|---|
| 399 |
|
|---|
| 400 | #define CB_DELAY_LOOP_WAIT 10 /* 10ms */
|
|---|
| 401 | /* enabled mask value of irq */
|
|---|
| 402 |
|
|---|
| 403 | #define W_IMR_MASK_VALUE 0x1BFF /* initial value of IMR */
|
|---|
| 404 |
|
|---|
| 405 | /* Ethernet address filter type */
|
|---|
| 406 | #define PKT_TYPE_DIRECTED 0x0001 /* obsolete, directed address is always accepted */
|
|---|
| 407 | #define PKT_TYPE_MULTICAST 0x0002
|
|---|
| 408 | #define PKT_TYPE_ALL_MULTICAST 0x0004
|
|---|
| 409 | #define PKT_TYPE_BROADCAST 0x0008
|
|---|
| 410 | #define PKT_TYPE_PROMISCUOUS 0x0020
|
|---|
| 411 | #define PKT_TYPE_LONG 0x2000
|
|---|
| 412 | #define PKT_TYPE_RUNT 0x4000
|
|---|
| 413 | #define PKT_TYPE_ERROR 0x8000 /* accept error packets, e.g. CRC error */
|
|---|
| 414 |
|
|---|
| 415 | /* Loopback mode */
|
|---|
| 416 |
|
|---|
| 417 | #define NIC_LB_NONE 0x00
|
|---|
| 418 | #define NIC_LB_INTERNAL 0x01
|
|---|
| 419 | #define NIC_LB_PHY 0x02 /* MII or Internal-10BaseT loopback */
|
|---|
| 420 |
|
|---|
| 421 | #define TX_RING_SIZE 2
|
|---|
| 422 | #define RX_RING_SIZE 2
|
|---|
| 423 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
|
|---|
| 424 |
|
|---|
| 425 | #define PCI_REG_MODE3 0x53
|
|---|
| 426 | #define MODE3_MIION 0x04 /* in PCI_REG_MOD3 OF PCI space */
|
|---|
| 427 |
|
|---|
| 428 | enum rhine_revs {
|
|---|
| 429 | VT86C100A = 0x00,
|
|---|
| 430 | VTunknown0 = 0x20,
|
|---|
| 431 | VT6102 = 0x40,
|
|---|
| 432 | VT8231 = 0x50, /* Integrated MAC */
|
|---|
| 433 | VT8233 = 0x60, /* Integrated MAC */
|
|---|
| 434 | VT8235 = 0x74, /* Integrated MAC */
|
|---|
| 435 | VT8237 = 0x78, /* Integrated MAC */
|
|---|
| 436 | VTunknown1 = 0x7C,
|
|---|
| 437 | VT6105 = 0x80,
|
|---|
| 438 | VT6105_B0 = 0x83,
|
|---|
| 439 | VT6105L = 0x8A,
|
|---|
| 440 | VT6107 = 0x8C,
|
|---|
| 441 | VTunknown2 = 0x8E,
|
|---|
| 442 | VT6105M = 0x90,
|
|---|
| 443 | };
|
|---|
| 444 |
|
|---|
| 445 | /* Transmit and receive descriptors definition */
|
|---|
| 446 |
|
|---|
| 447 | struct rhine_tx_desc
|
|---|
| 448 | {
|
|---|
| 449 | union VTC_tx_status_tag
|
|---|
| 450 | {
|
|---|
| 451 | struct
|
|---|
| 452 | {
|
|---|
| 453 | unsigned long ncro:1;
|
|---|
| 454 | unsigned long ncr1:1;
|
|---|
| 455 | unsigned long ncr2:1;
|
|---|
| 456 | unsigned long ncr3:1;
|
|---|
| 457 | unsigned long cols:1;
|
|---|
| 458 | unsigned long reserve_1:2;
|
|---|
| 459 | unsigned long cdh:1;
|
|---|
| 460 | unsigned long abt:1;
|
|---|
| 461 | unsigned long owc:1;
|
|---|
| 462 | unsigned long crs:1;
|
|---|
| 463 | unsigned long udf:1;
|
|---|
| 464 | unsigned long tbuff:1;
|
|---|
| 465 | unsigned long serr:1;
|
|---|
| 466 | unsigned long jab:1;
|
|---|
| 467 | unsigned long terr:1;
|
|---|
| 468 | unsigned long reserve_2:15;
|
|---|
| 469 | unsigned long own_bit:1;
|
|---|
| 470 | }
|
|---|
| 471 | bits;
|
|---|
| 472 | unsigned long lw;
|
|---|
| 473 | }
|
|---|
| 474 | tx_status;
|
|---|
| 475 |
|
|---|
| 476 | union VTC_tx_ctrl_tag
|
|---|
| 477 | {
|
|---|
| 478 | struct
|
|---|
| 479 | {
|
|---|
| 480 | unsigned long tx_buf_size:11;
|
|---|
| 481 | unsigned long extend_tx_buf_size:4;
|
|---|
| 482 | unsigned long chn:1;
|
|---|
| 483 | unsigned long crc:1;
|
|---|
| 484 | unsigned long reserve_1:4;
|
|---|
| 485 | unsigned long stp:1;
|
|---|
| 486 | unsigned long edp:1;
|
|---|
| 487 | unsigned long ic:1;
|
|---|
| 488 | unsigned long reserve_2:8;
|
|---|
| 489 | }
|
|---|
| 490 | bits;
|
|---|
| 491 | unsigned long lw;
|
|---|
| 492 | }
|
|---|
| 493 | tx_ctrl;
|
|---|
| 494 |
|
|---|
| 495 | unsigned long buf_addr_1:32;
|
|---|
| 496 | unsigned long buf_addr_2:32;
|
|---|
| 497 |
|
|---|
| 498 | };
|
|---|
| 499 |
|
|---|
| 500 | struct rhine_rx_desc
|
|---|
| 501 | {
|
|---|
| 502 | union VTC_rx_status_tag
|
|---|
| 503 | {
|
|---|
| 504 | struct
|
|---|
| 505 | {
|
|---|
| 506 | unsigned long rerr:1;
|
|---|
| 507 | unsigned long crc_error:1;
|
|---|
| 508 | unsigned long fae:1;
|
|---|
| 509 | unsigned long fov:1;
|
|---|
| 510 | unsigned long toolong:1;
|
|---|
| 511 | unsigned long runt:1;
|
|---|
| 512 | unsigned long serr:1;
|
|---|
| 513 | unsigned long buff:1;
|
|---|
| 514 | unsigned long edp:1;
|
|---|
| 515 | unsigned long stp:1;
|
|---|
| 516 | unsigned long chn:1;
|
|---|
| 517 | unsigned long phy:1;
|
|---|
| 518 | unsigned long bar:1;
|
|---|
| 519 | unsigned long mar:1;
|
|---|
| 520 | unsigned long reserve_1:1;
|
|---|
| 521 | unsigned long rxok:1;
|
|---|
| 522 | unsigned long frame_length:11;
|
|---|
| 523 | unsigned long reverve_2:4;
|
|---|
| 524 | unsigned long own_bit:1;
|
|---|
| 525 | }
|
|---|
| 526 | bits;
|
|---|
| 527 | unsigned long lw;
|
|---|
| 528 | }
|
|---|
| 529 | rx_status;
|
|---|
| 530 |
|
|---|
| 531 | union VTC_rx_ctrl_tag
|
|---|
| 532 | {
|
|---|
| 533 | struct
|
|---|
| 534 | {
|
|---|
| 535 | unsigned long rx_buf_size:11;
|
|---|
| 536 | unsigned long extend_rx_buf_size:4;
|
|---|
| 537 | unsigned long reserved_1:17;
|
|---|
| 538 | }
|
|---|
| 539 | bits;
|
|---|
| 540 | unsigned long lw;
|
|---|
| 541 | }
|
|---|
| 542 | rx_ctrl;
|
|---|
| 543 |
|
|---|
| 544 | unsigned long buf_addr_1:32;
|
|---|
| 545 | unsigned long buf_addr_2:32;
|
|---|
| 546 |
|
|---|
| 547 | };
|
|---|
| 548 |
|
|---|
| 549 |
|
|---|
| 550 | /* The I/O extent. */
|
|---|
| 551 | #define rhine_TOTAL_SIZE 0x80
|
|---|
| 552 |
|
|---|
| 553 | #ifdef HAVE_DEVLIST
|
|---|
| 554 | struct netdev_entry rhine_drv =
|
|---|
| 555 | { "rhine", rhine_probe, rhine_TOTAL_SIZE, NULL };
|
|---|
| 556 | #endif
|
|---|
| 557 |
|
|---|
| 558 | static int rhine_debug = 1;
|
|---|
| 559 |
|
|---|
| 560 | /*
|
|---|
| 561 | Theory of Operation
|
|---|
| 562 |
|
|---|
| 563 | I. Board Compatibility
|
|---|
| 564 |
|
|---|
| 565 | This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
|
|---|
| 566 | controller.
|
|---|
| 567 |
|
|---|
| 568 | II. Board-specific settings
|
|---|
| 569 |
|
|---|
| 570 | Boards with this chip are functional only in a bus-master PCI slot.
|
|---|
| 571 |
|
|---|
| 572 | Many operational settings are loaded from the EEPROM to the Config word at
|
|---|
| 573 | offset 0x78. This driver assumes that they are correct.
|
|---|
| 574 | If this driver is compiled to use PCI memory space operations the EEPROM
|
|---|
| 575 | must be configured to enable memory ops.
|
|---|
| 576 |
|
|---|
| 577 | III. Driver operation
|
|---|
| 578 |
|
|---|
| 579 | IIIa. Ring buffers
|
|---|
| 580 |
|
|---|
| 581 | This driver uses two statically allocated fixed-size descriptor lists
|
|---|
| 582 | formed into rings by a branch from the final descriptor to the beginning of
|
|---|
| 583 | the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
|
|---|
| 584 |
|
|---|
| 585 | IIIb/c. Transmit/Receive Structure
|
|---|
| 586 |
|
|---|
| 587 | This driver attempts to use a zero-copy receive and transmit scheme.
|
|---|
| 588 |
|
|---|
| 589 | Alas, all data buffers are required to start on a 32 bit boundary, so
|
|---|
| 590 | the driver must often copy transmit packets into bounce buffers.
|
|---|
| 591 |
|
|---|
| 592 | The driver allocates full frame size skbuffs for the Rx ring buffers at
|
|---|
| 593 | open() time and passes the skb->data field to the chip as receive data
|
|---|
| 594 | buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
|
|---|
| 595 | a fresh skbuff is allocated and the frame is copied to the new skbuff.
|
|---|
| 596 | When the incoming frame is larger, the skbuff is passed directly up the
|
|---|
| 597 | protocol stack. Buffers consumed this way are replaced by newly allocated
|
|---|
| 598 | skbuffs in the last phase of netdev_rx().
|
|---|
| 599 |
|
|---|
| 600 | The RX_COPYBREAK value is chosen to trade-off the memory wasted by
|
|---|
| 601 | using a full-sized skbuff for small frames vs. the copying costs of larger
|
|---|
| 602 | frames. New boards are typically used in generously configured machines
|
|---|
| 603 | and the underfilled buffers have negligible impact compared to the benefit of
|
|---|
| 604 | a single allocation size, so the default value of zero results in never
|
|---|
| 605 | copying packets. When copying is done, the cost is usually mitigated by using
|
|---|
| 606 | a combined copy/checksum routine. Copying also preloads the cache, which is
|
|---|
| 607 | most useful with small frames.
|
|---|
| 608 |
|
|---|
| 609 | Since the VIA chips are only able to transfer data to buffers on 32 bit
|
|---|
| 610 | boundaries, the the IP header at offset 14 in an ethernet frame isn't
|
|---|
| 611 | longword aligned for further processing. Copying these unaligned buffers
|
|---|
| 612 | has the beneficial effect of 16-byte aligning the IP header.
|
|---|
| 613 |
|
|---|
| 614 | IIId. Synchronization
|
|---|
| 615 |
|
|---|
| 616 | The driver runs as two independent, single-threaded flows of control. One
|
|---|
| 617 | is the send-packet routine, which enforces single-threaded use by the
|
|---|
| 618 | dev->tbusy flag. The other thread is the interrupt handler, which is single
|
|---|
| 619 | threaded by the hardware and interrupt handling software.
|
|---|
| 620 |
|
|---|
| 621 | The send packet thread has partial control over the Tx ring and 'dev->tbusy'
|
|---|
| 622 | flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
|
|---|
| 623 | queue slot is empty, it clears the tbusy flag when finished otherwise it sets
|
|---|
| 624 | the 'lp->tx_full' flag.
|
|---|
| 625 |
|
|---|
| 626 | The interrupt handler has exclusive control over the Rx ring and records stats
|
|---|
| 627 | from the Tx ring. After reaping the stats, it marks the Tx queue entry as
|
|---|
| 628 | empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
|
|---|
| 629 | clears both the tx_full and tbusy flags.
|
|---|
| 630 |
|
|---|
| 631 | IV. Notes
|
|---|
| 632 |
|
|---|
| 633 | IVb. References
|
|---|
| 634 |
|
|---|
| 635 | Preliminary VT86C100A manual from http://www.via.com.tw/
|
|---|
| 636 | http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
|
|---|
| 637 | http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
|
|---|
| 638 |
|
|---|
| 639 | IVc. Errata
|
|---|
| 640 |
|
|---|
| 641 | The VT86C100A manual is not reliable information.
|
|---|
| 642 | The chip does not handle unaligned transmit or receive buffers, resulting
|
|---|
| 643 | in significant performance degradation for bounce buffer copies on transmit
|
|---|
| 644 | and unaligned IP headers on receive.
|
|---|
| 645 | The chip does not pad to minimum transmit length.
|
|---|
| 646 |
|
|---|
| 647 | */
|
|---|
| 648 |
|
|---|
| 649 | /* The rest of these values should never change. */
|
|---|
| 650 | #define NUM_TX_DESC 2 /* Number of Tx descriptor registers. */
|
|---|
| 651 |
|
|---|
| 652 | static struct rhine_private
|
|---|
| 653 | {
|
|---|
| 654 | char devname[8]; /* Used only for kernel debugging. */
|
|---|
| 655 | const char *product_name;
|
|---|
| 656 | struct rhine_rx_desc *rx_ring;
|
|---|
| 657 | struct rhine_tx_desc *tx_ring;
|
|---|
| 658 | char *rx_buffs[RX_RING_SIZE];
|
|---|
| 659 | char *tx_buffs[TX_RING_SIZE];
|
|---|
| 660 |
|
|---|
| 661 | /* temporary Rx buffers. */
|
|---|
| 662 |
|
|---|
| 663 | int chip_id;
|
|---|
| 664 | int chip_revision;
|
|---|
| 665 | unsigned short ioaddr;
|
|---|
| 666 | unsigned int cur_rx, cur_tx; /* The next free and used entries */
|
|---|
| 667 | unsigned int dirty_rx, dirty_tx;
|
|---|
| 668 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */
|
|---|
| 669 | struct sk_buff *tx_skbuff[TX_RING_SIZE];
|
|---|
| 670 | unsigned char mc_filter[8]; /* Current multicast filter. */
|
|---|
| 671 | char phys[4]; /* MII device addresses. */
|
|---|
| 672 | unsigned int tx_full:1; /* The Tx queue is full. */
|
|---|
| 673 | unsigned int full_duplex:1; /* Full-duplex operation requested. */
|
|---|
| 674 | unsigned int default_port:4; /* Last dev->if_port value. */
|
|---|
| 675 | unsigned int media2:4; /* Secondary monitored media port. */
|
|---|
| 676 | unsigned int medialock:1; /* Don't sense media type. */
|
|---|
| 677 | unsigned int mediasense:1; /* Media sensing in progress. */
|
|---|
| 678 | }
|
|---|
| 679 | rhine;
|
|---|
| 680 |
|
|---|
| 681 | static void rhine_probe1 (struct nic *nic, struct pci_device *pci, int ioaddr,
|
|---|
| 682 | int chip_id, int options);
|
|---|
| 683 | static int QueryAuto (int);
|
|---|
| 684 | static int ReadMII (int byMIIIndex, int);
|
|---|
| 685 | static void WriteMII (char, char, char, int);
|
|---|
| 686 | static void MIIDelay (void);
|
|---|
| 687 | static void rhine_init_ring (struct nic *dev);
|
|---|
| 688 | static void rhine_disable (struct dev *dev);
|
|---|
| 689 | static void rhine_reset (struct nic *nic);
|
|---|
| 690 | static int rhine_poll (struct nic *nic, int retreive);
|
|---|
| 691 | static void rhine_transmit (struct nic *nic, const char *d, unsigned int t,
|
|---|
| 692 | unsigned int s, const char *p);
|
|---|
| 693 | static void reload_eeprom(int ioaddr);
|
|---|
| 694 |
|
|---|
| 695 |
|
|---|
| 696 | static void reload_eeprom(int ioaddr)
|
|---|
| 697 | {
|
|---|
| 698 | int i;
|
|---|
| 699 | outb(0x20, byEECSR);
|
|---|
| 700 | /* Typically 2 cycles to reload. */
|
|---|
| 701 | for (i = 0; i < 150; i++)
|
|---|
| 702 | if (! (inb(byEECSR) & 0x20))
|
|---|
| 703 | break;
|
|---|
| 704 | }
|
|---|
| 705 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
|
|---|
| 706 | static void
|
|---|
| 707 | rhine_init_ring (struct nic *nic)
|
|---|
| 708 | {
|
|---|
| 709 | struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
|
|---|
| 710 | int i;
|
|---|
| 711 |
|
|---|
| 712 | tp->tx_full = 0;
|
|---|
| 713 | tp->cur_rx = tp->cur_tx = 0;
|
|---|
| 714 | tp->dirty_rx = tp->dirty_tx = 0;
|
|---|
| 715 |
|
|---|
| 716 | for (i = 0; i < RX_RING_SIZE; i++)
|
|---|
| 717 | {
|
|---|
| 718 |
|
|---|
| 719 | tp->rx_ring[i].rx_status.bits.own_bit = 1;
|
|---|
| 720 | tp->rx_ring[i].rx_ctrl.bits.rx_buf_size = 1536;
|
|---|
| 721 |
|
|---|
| 722 | tp->rx_ring[i].buf_addr_1 = virt_to_bus (tp->rx_buffs[i]);
|
|---|
| 723 | tp->rx_ring[i].buf_addr_2 = virt_to_bus (&tp->rx_ring[i + 1]);
|
|---|
| 724 | /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->rx_ring[i].buf_addr_1,tp->rx_ring[i].buf_addr_2); */
|
|---|
| 725 | }
|
|---|
| 726 | /* Mark the last entry as wrapping the ring. */
|
|---|
| 727 | /* tp->rx_ring[i-1].rx_ctrl.bits.rx_buf_size =1518; */
|
|---|
| 728 | tp->rx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->rx_ring[0]);
|
|---|
| 729 | /*printf("[%d]buf1=%hX,buf2=%hX",i-1,tp->rx_ring[i-1].buf_addr_1,tp->rx_ring[i-1].buf_addr_2); */
|
|---|
| 730 |
|
|---|
| 731 | /* The Tx buffer descriptor is filled in as needed, but we
|
|---|
| 732 | do need to clear the ownership bit. */
|
|---|
| 733 |
|
|---|
| 734 | for (i = 0; i < TX_RING_SIZE; i++)
|
|---|
| 735 | {
|
|---|
| 736 |
|
|---|
| 737 | tp->tx_ring[i].tx_status.lw = 0;
|
|---|
| 738 | tp->tx_ring[i].tx_ctrl.lw = 0x00e08000;
|
|---|
| 739 | tp->tx_ring[i].buf_addr_1 = virt_to_bus (tp->tx_buffs[i]);
|
|---|
| 740 | tp->tx_ring[i].buf_addr_2 = virt_to_bus (&tp->tx_ring[i + 1]);
|
|---|
| 741 | /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i].buf_addr_1,tp->tx_ring[i].buf_addr_2); */
|
|---|
| 742 | }
|
|---|
| 743 |
|
|---|
| 744 | tp->tx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->tx_ring[0]);
|
|---|
| 745 | /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i-1].buf_addr_1,tp->tx_ring[i-1].buf_addr_2); */
|
|---|
| 746 | }
|
|---|
| 747 |
|
|---|
| 748 | int
|
|---|
| 749 | QueryAuto (int ioaddr)
|
|---|
| 750 | {
|
|---|
| 751 | int byMIIIndex;
|
|---|
| 752 | int MIIReturn;
|
|---|
| 753 |
|
|---|
| 754 | int advertising,mii_reg5;
|
|---|
| 755 | int negociated;
|
|---|
| 756 |
|
|---|
| 757 | byMIIIndex = 0x04;
|
|---|
| 758 | MIIReturn = ReadMII (byMIIIndex, ioaddr);
|
|---|
| 759 | advertising=MIIReturn;
|
|---|
| 760 |
|
|---|
| 761 | byMIIIndex = 0x05;
|
|---|
| 762 | MIIReturn = ReadMII (byMIIIndex, ioaddr);
|
|---|
| 763 | mii_reg5=MIIReturn;
|
|---|
| 764 |
|
|---|
| 765 | negociated=mii_reg5 & advertising;
|
|---|
| 766 |
|
|---|
| 767 | if ( (negociated & 0x100) || (negociated & 0x1C0) == 0x40 )
|
|---|
| 768 | return 1;
|
|---|
| 769 | else
|
|---|
| 770 | return 0;
|
|---|
| 771 |
|
|---|
| 772 | }
|
|---|
| 773 |
|
|---|
| 774 | int
|
|---|
| 775 | ReadMII (int byMIIIndex, int ioaddr)
|
|---|
| 776 | {
|
|---|
| 777 | int ReturnMII;
|
|---|
| 778 | char byMIIAdrbak;
|
|---|
| 779 | char byMIICRbak;
|
|---|
| 780 | char byMIItemp;
|
|---|
| 781 |
|
|---|
| 782 | byMIIAdrbak = inb (byMIIAD);
|
|---|
| 783 | byMIICRbak = inb (byMIICR);
|
|---|
| 784 | outb (byMIICRbak & 0x7f, byMIICR);
|
|---|
| 785 | MIIDelay ();
|
|---|
| 786 |
|
|---|
| 787 | outb (byMIIIndex, byMIIAD);
|
|---|
| 788 | MIIDelay ();
|
|---|
| 789 |
|
|---|
| 790 | outb (inb (byMIICR) | 0x40, byMIICR);
|
|---|
| 791 |
|
|---|
| 792 | byMIItemp = inb (byMIICR);
|
|---|
| 793 | byMIItemp = byMIItemp & 0x40;
|
|---|
| 794 |
|
|---|
| 795 | load_timer2(2*TICKS_PER_MS);
|
|---|
| 796 | while (byMIItemp != 0 && timer2_running())
|
|---|
| 797 | {
|
|---|
| 798 | byMIItemp = inb (byMIICR);
|
|---|
| 799 | byMIItemp = byMIItemp & 0x40;
|
|---|
| 800 | }
|
|---|
| 801 | MIIDelay ();
|
|---|
| 802 |
|
|---|
| 803 | ReturnMII = inw (wMIIDATA);
|
|---|
| 804 |
|
|---|
| 805 | outb (byMIIAdrbak, byMIIAD);
|
|---|
| 806 | outb (byMIICRbak, byMIICR);
|
|---|
| 807 | MIIDelay ();
|
|---|
| 808 |
|
|---|
| 809 | return (ReturnMII);
|
|---|
| 810 |
|
|---|
| 811 | }
|
|---|
| 812 |
|
|---|
| 813 | void
|
|---|
| 814 | WriteMII (char byMIISetByte, char byMIISetBit, char byMIIOP, int ioaddr)
|
|---|
| 815 | {
|
|---|
| 816 | int ReadMIItmp;
|
|---|
| 817 | int MIIMask;
|
|---|
| 818 | char byMIIAdrbak;
|
|---|
| 819 | char byMIICRbak;
|
|---|
| 820 | char byMIItemp;
|
|---|
| 821 |
|
|---|
| 822 |
|
|---|
| 823 | byMIIAdrbak = inb (byMIIAD);
|
|---|
| 824 |
|
|---|
| 825 | byMIICRbak = inb (byMIICR);
|
|---|
| 826 | outb (byMIICRbak & 0x7f, byMIICR);
|
|---|
| 827 | MIIDelay ();
|
|---|
| 828 | outb (byMIISetByte, byMIIAD);
|
|---|
| 829 | MIIDelay ();
|
|---|
| 830 |
|
|---|
| 831 | outb (inb (byMIICR) | 0x40, byMIICR);
|
|---|
| 832 |
|
|---|
| 833 | byMIItemp = inb (byMIICR);
|
|---|
| 834 | byMIItemp = byMIItemp & 0x40;
|
|---|
| 835 |
|
|---|
| 836 | load_timer2(2*TICKS_PER_MS);
|
|---|
| 837 | while (byMIItemp != 0 && timer2_running())
|
|---|
| 838 | {
|
|---|
| 839 | byMIItemp = inb (byMIICR);
|
|---|
| 840 | byMIItemp = byMIItemp & 0x40;
|
|---|
| 841 | }
|
|---|
| 842 | MIIDelay ();
|
|---|
| 843 |
|
|---|
| 844 | ReadMIItmp = inw (wMIIDATA);
|
|---|
| 845 | MIIMask = 0x0001;
|
|---|
| 846 | MIIMask = MIIMask << byMIISetBit;
|
|---|
| 847 |
|
|---|
| 848 |
|
|---|
| 849 | if (byMIIOP == 0)
|
|---|
| 850 | {
|
|---|
| 851 | MIIMask = ~MIIMask;
|
|---|
| 852 | ReadMIItmp = ReadMIItmp & MIIMask;
|
|---|
| 853 | }
|
|---|
| 854 | else
|
|---|
| 855 | {
|
|---|
| 856 | ReadMIItmp = ReadMIItmp | MIIMask;
|
|---|
| 857 |
|
|---|
| 858 | }
|
|---|
| 859 | outw (ReadMIItmp, wMIIDATA);
|
|---|
| 860 | MIIDelay ();
|
|---|
| 861 |
|
|---|
| 862 | outb (inb (byMIICR) | 0x20, byMIICR);
|
|---|
| 863 | byMIItemp = inb (byMIICR);
|
|---|
| 864 | byMIItemp = byMIItemp & 0x20;
|
|---|
| 865 |
|
|---|
| 866 | load_timer2(2*TICKS_PER_MS);
|
|---|
| 867 | while (byMIItemp != 0 && timer2_running())
|
|---|
| 868 | {
|
|---|
| 869 | byMIItemp = inb (byMIICR);
|
|---|
| 870 | byMIItemp = byMIItemp & 0x20;
|
|---|
| 871 | }
|
|---|
| 872 | MIIDelay ();
|
|---|
| 873 |
|
|---|
| 874 | outb (byMIIAdrbak & 0x7f, byMIIAD);
|
|---|
| 875 | outb (byMIICRbak, byMIICR);
|
|---|
| 876 | MIIDelay ();
|
|---|
| 877 |
|
|---|
| 878 | }
|
|---|
| 879 |
|
|---|
| 880 | void
|
|---|
| 881 | MIIDelay (void)
|
|---|
| 882 | {
|
|---|
| 883 | int i;
|
|---|
| 884 | for (i = 0; i < 0x7fff; i++)
|
|---|
| 885 | {
|
|---|
| 886 | inb (0x61);
|
|---|
| 887 | inb (0x61);
|
|---|
| 888 | inb (0x61);
|
|---|
| 889 | inb (0x61);
|
|---|
| 890 | }
|
|---|
| 891 | }
|
|---|
| 892 |
|
|---|
| 893 | /* Offsets to the device registers. */
|
|---|
| 894 | enum register_offsets {
|
|---|
| 895 | StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
|
|---|
| 896 | IntrStatus=0x0C, IntrEnable=0x0E,
|
|---|
| 897 | MulticastFilter0=0x10, MulticastFilter1=0x14,
|
|---|
| 898 | RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
|
|---|
| 899 | MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
|
|---|
| 900 | MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
|
|---|
| 901 | ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
|
|---|
| 902 | RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
|
|---|
| 903 | StickyHW=0x83, IntrStatus2=0x84, WOLcrClr=0xA4, WOLcgClr=0xA7,
|
|---|
| 904 | PwrcsrClr=0xAC,
|
|---|
| 905 | };
|
|---|
| 906 |
|
|---|
| 907 | /* Bits in the interrupt status/mask registers. */
|
|---|
| 908 | enum intr_status_bits {
|
|---|
| 909 | IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
|
|---|
| 910 | IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
|
|---|
| 911 | IntrPCIErr=0x0040,
|
|---|
| 912 | IntrStatsMax=0x0080, IntrRxEarly=0x0100,
|
|---|
| 913 | IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
|
|---|
| 914 | IntrTxAborted=0x2000, IntrLinkChange=0x4000,
|
|---|
| 915 | IntrRxWakeUp=0x8000,
|
|---|
| 916 | IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
|
|---|
| 917 | IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
|
|---|
| 918 | IntrTxErrSummary=0x082218,
|
|---|
| 919 | };
|
|---|
| 920 | #define DEFAULT_INTR (IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | \
|
|---|
| 921 | IntrRxDropped | IntrRxNoBuf)
|
|---|
| 922 |
|
|---|
| 923 | /***************************************************************************
|
|---|
| 924 | IRQ - PXE IRQ Handler
|
|---|
| 925 | ***************************************************************************/
|
|---|
| 926 | void rhine_irq ( struct nic *nic, irq_action_t action ) {
|
|---|
| 927 | struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
|
|---|
| 928 | /* Enable interrupts by setting the interrupt mask. */
|
|---|
| 929 | unsigned int intr_status;
|
|---|
| 930 |
|
|---|
| 931 | switch ( action ) {
|
|---|
| 932 | case DISABLE :
|
|---|
| 933 | case ENABLE :
|
|---|
| 934 | intr_status = inw(nic->ioaddr + IntrStatus);
|
|---|
| 935 | /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
|
|---|
| 936 |
|
|---|
| 937 | /* added comment by guard */
|
|---|
| 938 | /* For supporting VT6107, please use revision id to recognize different chips in driver */
|
|---|
| 939 | // if (tp->chip_id == 0x3065)
|
|---|
| 940 | if( tp->chip_revision < 0x80 && tp->chip_revision >=0x40 )
|
|---|
| 941 | intr_status |= inb(nic->ioaddr + IntrStatus2) << 16;
|
|---|
| 942 | intr_status = (intr_status & ~DEFAULT_INTR);
|
|---|
| 943 | if ( action == ENABLE )
|
|---|
| 944 | intr_status = intr_status | DEFAULT_INTR;
|
|---|
| 945 | outw(intr_status, nic->ioaddr + IntrEnable);
|
|---|
| 946 | break;
|
|---|
| 947 | case FORCE :
|
|---|
| 948 | outw(0x0010, nic->ioaddr + 0x84);
|
|---|
| 949 | break;
|
|---|
| 950 | }
|
|---|
| 951 | }
|
|---|
| 952 |
|
|---|
| 953 | static int
|
|---|
| 954 | rhine_probe (struct dev *dev, struct pci_device *pci)
|
|---|
| 955 | {
|
|---|
| 956 | struct nic *nic = (struct nic *)dev;
|
|---|
| 957 | struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
|
|---|
| 958 | if (!pci->ioaddr)
|
|---|
| 959 | return 0;
|
|---|
| 960 | rhine_probe1 (nic, pci, pci->ioaddr, pci->dev_id, -1);
|
|---|
| 961 |
|
|---|
| 962 | adjust_pci_device(pci);
|
|---|
| 963 | rhine_reset (nic);
|
|---|
| 964 |
|
|---|
| 965 | dev->disable = rhine_disable;
|
|---|
| 966 | nic->poll = rhine_poll;
|
|---|
| 967 | nic->transmit = rhine_transmit;
|
|---|
| 968 | nic->irqno = pci->irq;
|
|---|
| 969 | nic->irq = rhine_irq;
|
|---|
| 970 | nic->ioaddr = tp->ioaddr;
|
|---|
| 971 |
|
|---|
| 972 |
|
|---|
| 973 | return 1;
|
|---|
| 974 | }
|
|---|
| 975 |
|
|---|
| 976 | static void set_rx_mode(struct nic *nic __unused) {
|
|---|
| 977 | struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
|
|---|
| 978 | unsigned char rx_mode;
|
|---|
| 979 | int ioaddr = tp->ioaddr;
|
|---|
| 980 |
|
|---|
| 981 | /* ! IFF_PROMISC */
|
|---|
| 982 | outl(0xffffffff, byMAR0);
|
|---|
| 983 | outl(0xffffffff, byMAR4);
|
|---|
| 984 | rx_mode = 0x0C;
|
|---|
| 985 |
|
|---|
| 986 | outb(0x60 /* thresh */ | rx_mode, byRCR );
|
|---|
| 987 | }
|
|---|
| 988 |
|
|---|
| 989 | static void
|
|---|
| 990 | rhine_probe1 (struct nic *nic, struct pci_device *pci, int ioaddr, int chip_id, int options)
|
|---|
| 991 | {
|
|---|
| 992 | struct rhine_private *tp;
|
|---|
| 993 | static int did_version = 0; /* Already printed version info. */
|
|---|
| 994 | int i, ww;
|
|---|
| 995 | unsigned int timeout;
|
|---|
| 996 | int FDXFlag;
|
|---|
| 997 | int byMIIvalue, LineSpeed, MIICRbak;
|
|---|
| 998 | uint8_t revision_id;
|
|---|
| 999 | unsigned char mode3_reg;
|
|---|
| 1000 |
|
|---|
| 1001 | if (rhine_debug > 0 && did_version++ == 0)
|
|---|
| 1002 | printf (version);
|
|---|
| 1003 |
|
|---|
| 1004 | // get revision id.
|
|---|
| 1005 | pci_read_config_byte(pci, PCI_REVISION, &revision_id);
|
|---|
| 1006 |
|
|---|
| 1007 | /* D-Link provided reset code (with comment additions) */
|
|---|
| 1008 | if (revision_id >= 0x40) {
|
|---|
| 1009 | unsigned char byOrgValue;
|
|---|
| 1010 |
|
|---|
| 1011 | if(rhine_debug > 0)
|
|---|
| 1012 | printf("Enabling Sticky Bit Workaround for Chip_id: 0x%hX\n"
|
|---|
| 1013 | , chip_id);
|
|---|
| 1014 | /* clear sticky bit before reset & read ethernet address */
|
|---|
| 1015 | byOrgValue = inb(bySTICKHW);
|
|---|
| 1016 | byOrgValue = byOrgValue & 0xFC;
|
|---|
| 1017 | outb(byOrgValue, bySTICKHW);
|
|---|
| 1018 |
|
|---|
| 1019 | /* (bits written are cleared?) */
|
|---|
| 1020 | /* disable force PME-enable */
|
|---|
| 1021 | outb(0x80, byWOLcgClr);
|
|---|
| 1022 | /* disable power-event config bit */
|
|---|
| 1023 | outb(0xFF, byWOLcrClr);
|
|---|
| 1024 | /* clear power status (undocumented in vt6102 docs?) */
|
|---|
| 1025 | outb(0xFF, byPwrcsrClr);
|
|---|
| 1026 |
|
|---|
| 1027 | }
|
|---|
| 1028 |
|
|---|
| 1029 | /* Reset the chip to erase previous misconfiguration. */
|
|---|
| 1030 | outw(CR_SFRST, byCR0);
|
|---|
| 1031 | // if vt3043 delay after reset
|
|---|
| 1032 | if (revision_id <0x40) {
|
|---|
| 1033 | udelay(10000);
|
|---|
| 1034 | }
|
|---|
| 1035 | // polling till software reset complete
|
|---|
| 1036 | // W_MAX_TIMEOUT is the timeout period
|
|---|
| 1037 | for(ww = 0; ww < W_MAX_TIMEOUT; ww++) {
|
|---|
| 1038 | if ((inw(byCR0) & CR_SFRST) == 0)
|
|---|
| 1039 | break;
|
|---|
| 1040 | }
|
|---|
| 1041 |
|
|---|
| 1042 | // issue AUTOLoad in EECSR to reload eeprom
|
|---|
| 1043 | outb(0x20, byEECSR );
|
|---|
| 1044 |
|
|---|
| 1045 | // if vt3065 delay after reset
|
|---|
| 1046 | if (revision_id >=0x40) {
|
|---|
| 1047 | // delay 8ms to let MAC stable
|
|---|
| 1048 | mdelay(8);
|
|---|
| 1049 | /*
|
|---|
| 1050 | * for 3065D, EEPROM reloaded will cause bit 0 in MAC_REG_CFGA
|
|---|
| 1051 | * turned on. it makes MAC receive magic packet
|
|---|
| 1052 | * automatically. So, we turn it off. (D-Link)
|
|---|
| 1053 | */
|
|---|
| 1054 | outb(inb(byCFGA) & 0xFE, byCFGA);
|
|---|
| 1055 | }
|
|---|
| 1056 |
|
|---|
| 1057 | /* turn on bit2 in PCI configuration register 0x53 , only for 3065*/
|
|---|
| 1058 | if (revision_id >= 0x40) {
|
|---|
| 1059 | pci_read_config_byte(pci, PCI_REG_MODE3, &mode3_reg);
|
|---|
| 1060 | pci_write_config_byte(pci, PCI_REG_MODE3, mode3_reg|MODE3_MIION);
|
|---|
| 1061 | }
|
|---|
| 1062 |
|
|---|
| 1063 |
|
|---|
| 1064 | /* back off algorithm ,disable the right-most 4-bit off CFGD*/
|
|---|
| 1065 | outb(inb(byCFGD) & (~(CFGD_RANDOM | CFGD_CFDX | CFGD_CEREN | CFGD_CETEN)), byCFGD);
|
|---|
| 1066 |
|
|---|
| 1067 | /* reload eeprom */
|
|---|
| 1068 | reload_eeprom(ioaddr);
|
|---|
| 1069 |
|
|---|
| 1070 | /* Perhaps this should be read from the EEPROM? */
|
|---|
| 1071 | for (i = 0; i < ETH_ALEN; i++)
|
|---|
| 1072 | nic->node_addr[i] = inb (byPAR0 + i);
|
|---|
| 1073 | printf ("IO address %hX Ethernet Address: %!\n", ioaddr, nic->node_addr);
|
|---|
| 1074 |
|
|---|
| 1075 | /* restart MII auto-negotiation */
|
|---|
| 1076 | WriteMII (0, 9, 1, ioaddr);
|
|---|
| 1077 | printf ("Analyzing Media type,this will take several seconds........");
|
|---|
| 1078 | for (i = 0; i < 5; i++)
|
|---|
| 1079 | {
|
|---|
| 1080 | /* need to wait 1 millisecond - we will round it up to 50-100ms */
|
|---|
| 1081 | timeout = currticks() + 2;
|
|---|
| 1082 | for (timeout = currticks() + 2; currticks() < timeout;)
|
|---|
| 1083 | /* nothing */;
|
|---|
| 1084 | if (ReadMII (1, ioaddr) & 0x0020)
|
|---|
| 1085 | break;
|
|---|
| 1086 | }
|
|---|
| 1087 | printf ("OK\n");
|
|---|
| 1088 |
|
|---|
| 1089 | #if 0
|
|---|
| 1090 | /* JJM : for Debug */
|
|---|
| 1091 | printf("MII : Address %hhX ",inb(ioaddr+0x6c));
|
|---|
| 1092 | {
|
|---|
| 1093 | unsigned char st1,st2,adv1,adv2,l1,l2;
|
|---|
| 1094 |
|
|---|
| 1095 | st1=ReadMII(1,ioaddr)>>8;
|
|---|
| 1096 | st2=ReadMII(1,ioaddr)&0xFF;
|
|---|
| 1097 | adv1=ReadMII(4,ioaddr)>>8;
|
|---|
| 1098 | adv2=ReadMII(4,ioaddr)&0xFF;
|
|---|
| 1099 | l1=ReadMII(5,ioaddr)>>8;
|
|---|
| 1100 | l2=ReadMII(5,ioaddr)&0xFF;
|
|---|
| 1101 | printf(" status 0x%hhX%hhX, advertising 0x%hhX%hhX, link 0x%hhX%hhX\n", st1,st2,adv1,adv2,l1,l2);
|
|---|
| 1102 | }
|
|---|
| 1103 | #endif
|
|---|
| 1104 |
|
|---|
| 1105 |
|
|---|
| 1106 | /* query MII to know LineSpeed,duplex mode */
|
|---|
| 1107 | byMIIvalue = inb (ioaddr + 0x6d);
|
|---|
| 1108 | LineSpeed = byMIIvalue & MIISR_SPEED;
|
|---|
| 1109 | if (LineSpeed != 0) //JJM
|
|---|
| 1110 | {
|
|---|
| 1111 | printf ("Linespeed=10Mbs");
|
|---|
| 1112 | }
|
|---|
| 1113 | else
|
|---|
| 1114 | {
|
|---|
| 1115 | printf ("Linespeed=100Mbs");
|
|---|
| 1116 | }
|
|---|
| 1117 |
|
|---|
| 1118 | FDXFlag = QueryAuto (ioaddr);
|
|---|
| 1119 | if (FDXFlag == 1)
|
|---|
| 1120 | {
|
|---|
| 1121 | printf (" Fullduplex\n");
|
|---|
| 1122 | outw (CR_FDX, byCR0);
|
|---|
| 1123 | }
|
|---|
| 1124 | else
|
|---|
| 1125 | {
|
|---|
| 1126 | printf (" Halfduplex\n");
|
|---|
| 1127 | }
|
|---|
| 1128 |
|
|---|
| 1129 |
|
|---|
| 1130 | /* set MII 10 FULL ON, only apply in vt3043 */
|
|---|
| 1131 | if(chip_id == 0x3043)
|
|---|
| 1132 | WriteMII (0x17, 1, 1, ioaddr);
|
|---|
| 1133 |
|
|---|
| 1134 | /* turn on MII link change */
|
|---|
| 1135 | MIICRbak = inb (byMIICR);
|
|---|
| 1136 | outb (MIICRbak & 0x7F, byMIICR);
|
|---|
| 1137 | MIIDelay ();
|
|---|
| 1138 | outb (0x41, byMIIAD);
|
|---|
| 1139 | MIIDelay ();
|
|---|
| 1140 |
|
|---|
| 1141 | /* while((inb(byMIIAD)&0x20)==0) ; */
|
|---|
| 1142 | outb (MIICRbak | 0x80, byMIICR);
|
|---|
| 1143 |
|
|---|
| 1144 | nic->priv_data = &rhine;
|
|---|
| 1145 | tp = &rhine;
|
|---|
| 1146 | tp->chip_id = chip_id;
|
|---|
| 1147 | tp->ioaddr = ioaddr;
|
|---|
| 1148 | tp->phys[0] = -1;
|
|---|
| 1149 | tp->chip_revision = revision_id;
|
|---|
| 1150 |
|
|---|
| 1151 | /* The lower four bits are the media type. */
|
|---|
| 1152 | if (options > 0)
|
|---|
| 1153 | {
|
|---|
| 1154 | tp->full_duplex = (options & 16) ? 1 : 0;
|
|---|
| 1155 | tp->default_port = options & 15;
|
|---|
| 1156 | if (tp->default_port)
|
|---|
| 1157 | tp->medialock = 1;
|
|---|
| 1158 | }
|
|---|
| 1159 | return;
|
|---|
| 1160 | }
|
|---|
| 1161 |
|
|---|
| 1162 | static void
|
|---|
| 1163 | rhine_disable (struct dev *dev)
|
|---|
| 1164 | {
|
|---|
| 1165 | struct nic *nic = (struct nic *)dev;
|
|---|
| 1166 | struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
|
|---|
| 1167 | int ioaddr = tp->ioaddr;
|
|---|
| 1168 |
|
|---|
| 1169 | /* merge reset and disable */
|
|---|
| 1170 | rhine_reset(nic);
|
|---|
| 1171 |
|
|---|
| 1172 | printf ("rhine disable\n");
|
|---|
| 1173 | /* Switch to loopback mode to avoid hardware races. */
|
|---|
| 1174 | writeb(0x60 | 0x01, byTCR);
|
|---|
| 1175 | /* Stop the chip's Tx and Rx processes. */
|
|---|
| 1176 | writew(CR_STOP, byCR0);
|
|---|
| 1177 | }
|
|---|
| 1178 |
|
|---|
| 1179 | /**************************************************************************
|
|---|
| 1180 | ETH_RESET - Reset adapter
|
|---|
| 1181 | ***************************************************************************/
|
|---|
| 1182 | static void
|
|---|
| 1183 | rhine_reset (struct nic *nic)
|
|---|
| 1184 | {
|
|---|
| 1185 | struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
|
|---|
| 1186 | int ioaddr = tp->ioaddr;
|
|---|
| 1187 | int i, j;
|
|---|
| 1188 | int FDXFlag, CRbak;
|
|---|
| 1189 | int rx_ring_tmp, rx_ring_tmp1;
|
|---|
| 1190 | int tx_ring_tmp, tx_ring_tmp1;
|
|---|
| 1191 | int rx_bufs_tmp, rx_bufs_tmp1;
|
|---|
| 1192 | int tx_bufs_tmp, tx_bufs_tmp1;
|
|---|
| 1193 |
|
|---|
| 1194 | static char buf1[TX_RING_SIZE * PKT_BUF_SZ + 32];
|
|---|
| 1195 | static char buf2[RX_RING_SIZE * PKT_BUF_SZ + 32];
|
|---|
| 1196 | static char desc1[TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32];
|
|---|
| 1197 | static char desc2[RX_RING_SIZE * sizeof (struct rhine_rx_desc) + 32];
|
|---|
| 1198 |
|
|---|
| 1199 | /* printf ("rhine_reset\n"); */
|
|---|
| 1200 | /* Soft reset the chip. */
|
|---|
| 1201 | /*outb(CmdReset, ioaddr + ChipCmd); */
|
|---|
| 1202 |
|
|---|
| 1203 | tx_bufs_tmp = (int) buf1;
|
|---|
| 1204 | tx_ring_tmp = (int) desc1;
|
|---|
| 1205 | rx_bufs_tmp = (int) buf2;
|
|---|
| 1206 | rx_ring_tmp = (int) desc2;
|
|---|
| 1207 |
|
|---|
| 1208 | /* tune RD TD 32 byte alignment */
|
|---|
| 1209 | rx_ring_tmp1 = (int) virt_to_bus ((char *) rx_ring_tmp);
|
|---|
| 1210 | j = (rx_ring_tmp1 + 32) & (~0x1f);
|
|---|
| 1211 | /* printf ("txring[%d]", j); */
|
|---|
| 1212 | tp->rx_ring = (struct rhine_rx_desc *) bus_to_virt (j);
|
|---|
| 1213 |
|
|---|
| 1214 | tx_ring_tmp1 = (int) virt_to_bus ((char *) tx_ring_tmp);
|
|---|
| 1215 | j = (tx_ring_tmp1 + 32) & (~0x1f);
|
|---|
| 1216 | tp->tx_ring = (struct rhine_tx_desc *) bus_to_virt (j);
|
|---|
| 1217 | /* printf ("rxring[%X]", j); */
|
|---|
| 1218 |
|
|---|
| 1219 |
|
|---|
| 1220 | tx_bufs_tmp1 = (int) virt_to_bus ((char *) tx_bufs_tmp);
|
|---|
| 1221 | j = (int) (tx_bufs_tmp1 + 32) & (~0x1f);
|
|---|
| 1222 | tx_bufs_tmp = (int) bus_to_virt (j);
|
|---|
| 1223 | /* printf ("txb[%X]", j); */
|
|---|
| 1224 |
|
|---|
| 1225 | rx_bufs_tmp1 = (int) virt_to_bus ((char *) rx_bufs_tmp);
|
|---|
| 1226 | j = (int) (rx_bufs_tmp1 + 32) & (~0x1f);
|
|---|
| 1227 | rx_bufs_tmp = (int) bus_to_virt (j);
|
|---|
| 1228 | /* printf ("rxb[%X][%X]", rx_bufs_tmp1, j); */
|
|---|
| 1229 |
|
|---|
| 1230 | for (i = 0; i < RX_RING_SIZE; i++)
|
|---|
| 1231 | {
|
|---|
| 1232 | tp->rx_buffs[i] = (char *) rx_bufs_tmp;
|
|---|
| 1233 | /* printf("r[%X]",tp->rx_buffs[i]); */
|
|---|
| 1234 | rx_bufs_tmp += 1536;
|
|---|
| 1235 | }
|
|---|
| 1236 |
|
|---|
| 1237 | for (i = 0; i < TX_RING_SIZE; i++)
|
|---|
| 1238 | {
|
|---|
| 1239 | tp->tx_buffs[i] = (char *) tx_bufs_tmp;
|
|---|
| 1240 | /* printf("t[%X]",tp->tx_buffs[i]); */
|
|---|
| 1241 | tx_bufs_tmp += 1536;
|
|---|
| 1242 | }
|
|---|
| 1243 |
|
|---|
| 1244 | /* software reset */
|
|---|
| 1245 | outb (CR1_SFRST, byCR1);
|
|---|
| 1246 | MIIDelay ();
|
|---|
| 1247 |
|
|---|
| 1248 | /* printf ("init ring"); */
|
|---|
| 1249 | rhine_init_ring (nic);
|
|---|
| 1250 | /*write TD RD Descriptor to MAC */
|
|---|
| 1251 | outl (virt_to_bus (tp->rx_ring), dwCurrentRxDescAddr);
|
|---|
| 1252 | outl (virt_to_bus (tp->tx_ring), dwCurrentTxDescAddr);
|
|---|
| 1253 |
|
|---|
| 1254 | /* Setup Multicast */
|
|---|
| 1255 | set_rx_mode(nic);
|
|---|
| 1256 |
|
|---|
| 1257 | /* set TCR RCR threshold to store and forward*/
|
|---|
| 1258 | outb (0x3e, byBCR0);
|
|---|
| 1259 | outb (0x38, byBCR1);
|
|---|
| 1260 | outb (0x2c, byRCR);
|
|---|
| 1261 | outb (0x60, byTCR);
|
|---|
| 1262 | /* Set Fulldupex */
|
|---|
| 1263 | FDXFlag = QueryAuto (ioaddr);
|
|---|
| 1264 | if (FDXFlag == 1)
|
|---|
| 1265 | {
|
|---|
| 1266 | outb (CFGD_CFDX, byCFGD);
|
|---|
| 1267 | outw (CR_FDX, byCR0);
|
|---|
| 1268 | }
|
|---|
| 1269 |
|
|---|
| 1270 | /* KICK NIC to WORK */
|
|---|
| 1271 | CRbak = inw (byCR0);
|
|---|
| 1272 | CRbak = CRbak & 0xFFFB; /* not CR_STOP */
|
|---|
| 1273 | outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0);
|
|---|
| 1274 |
|
|---|
| 1275 | /* disable all known interrupt */
|
|---|
| 1276 | outw (0, byIMR0);
|
|---|
| 1277 | }
|
|---|
| 1278 | /* Beware of PCI posted writes */
|
|---|
| 1279 | #define IOSYNC do { readb(nic->ioaddr + StationAddr); } while (0)
|
|---|
| 1280 |
|
|---|
| 1281 | static int
|
|---|
| 1282 | rhine_poll (struct nic *nic, int retreive)
|
|---|
| 1283 | {
|
|---|
| 1284 | struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
|
|---|
| 1285 | int rxstatus, good = 0;;
|
|---|
| 1286 |
|
|---|
| 1287 | if (tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit == 0)
|
|---|
| 1288 | {
|
|---|
| 1289 | unsigned int intr_status;
|
|---|
| 1290 | /* There is a packet ready */
|
|---|
| 1291 | if(!retreive)
|
|---|
| 1292 | return 1;
|
|---|
| 1293 |
|
|---|
| 1294 | intr_status = inw(nic->ioaddr + IntrStatus);
|
|---|
| 1295 | /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
|
|---|
| 1296 | #if 0
|
|---|
| 1297 | if (tp->chip_id == 0x3065)
|
|---|
| 1298 | intr_status |= inb(nic->ioaddr + IntrStatus2) << 16;
|
|---|
| 1299 | #endif
|
|---|
| 1300 | /* Acknowledge all of the current interrupt sources ASAP. */
|
|---|
| 1301 | if (intr_status & IntrTxDescRace)
|
|---|
| 1302 | outb(0x08, nic->ioaddr + IntrStatus2);
|
|---|
| 1303 | outw(intr_status & 0xffff, nic->ioaddr + IntrStatus);
|
|---|
| 1304 | IOSYNC;
|
|---|
| 1305 |
|
|---|
| 1306 | rxstatus = tp->rx_ring[tp->cur_rx].rx_status.lw;
|
|---|
| 1307 | if ((rxstatus & 0x0300) != 0x0300)
|
|---|
| 1308 | {
|
|---|
| 1309 | printf("rhine_poll: bad status\n");
|
|---|
| 1310 | }
|
|---|
| 1311 | else if (rxstatus & (RSR_ABNORMAL))
|
|---|
| 1312 | {
|
|---|
| 1313 | printf ("rxerr[%X]\n", rxstatus);
|
|---|
| 1314 | }
|
|---|
| 1315 | else
|
|---|
| 1316 | good = 1;
|
|---|
| 1317 |
|
|---|
| 1318 | if (good)
|
|---|
| 1319 | {
|
|---|
| 1320 | nic->packetlen = tp->rx_ring[tp->cur_rx].rx_status.bits.frame_length;
|
|---|
| 1321 | memcpy (nic->packet, tp->rx_buffs[tp->cur_rx], nic->packetlen);
|
|---|
| 1322 | /* printf ("Packet RXed\n"); */
|
|---|
| 1323 | }
|
|---|
| 1324 | tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit = 1;
|
|---|
| 1325 | tp->cur_rx++;
|
|---|
| 1326 | tp->cur_rx = tp->cur_rx % RX_RING_SIZE;
|
|---|
| 1327 | }
|
|---|
| 1328 | /* Acknowledge all of the current interrupt sources ASAP. */
|
|---|
| 1329 | outw(DEFAULT_INTR & ~IntrRxDone, nic->ioaddr + IntrStatus);
|
|---|
| 1330 |
|
|---|
| 1331 | IOSYNC;
|
|---|
| 1332 |
|
|---|
| 1333 | return good;
|
|---|
| 1334 | }
|
|---|
| 1335 |
|
|---|
| 1336 | static void
|
|---|
| 1337 | rhine_transmit (struct nic *nic,
|
|---|
| 1338 | const char *d, unsigned int t, unsigned int s, const char *p)
|
|---|
| 1339 | {
|
|---|
| 1340 | struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
|
|---|
| 1341 | int ioaddr = tp->ioaddr;
|
|---|
| 1342 | int entry;
|
|---|
| 1343 | unsigned char CR1bak;
|
|---|
| 1344 | unsigned char CR0bak;
|
|---|
| 1345 | unsigned int nstype;
|
|---|
| 1346 |
|
|---|
| 1347 |
|
|---|
| 1348 | /*printf ("rhine_transmit\n"); */
|
|---|
| 1349 | /* setup ethernet header */
|
|---|
| 1350 |
|
|---|
| 1351 |
|
|---|
| 1352 | /* Calculate the next Tx descriptor entry. */
|
|---|
| 1353 | entry = tp->cur_tx % TX_RING_SIZE;
|
|---|
| 1354 |
|
|---|
| 1355 | memcpy (tp->tx_buffs[entry], d, ETH_ALEN); /* dst */
|
|---|
| 1356 | memcpy (tp->tx_buffs[entry] + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
|
|---|
| 1357 |
|
|---|
| 1358 | nstype=htons(t);
|
|---|
| 1359 | memcpy(tp->tx_buffs[entry] + 2 * ETH_ALEN, (char*)&nstype, 2);
|
|---|
| 1360 |
|
|---|
| 1361 | memcpy (tp->tx_buffs[entry] + ETH_HLEN, p, s);
|
|---|
| 1362 | s += ETH_HLEN;
|
|---|
| 1363 | while (s < ETH_ZLEN)
|
|---|
| 1364 | *((char *) tp->tx_buffs[entry] + (s++)) = 0;
|
|---|
| 1365 |
|
|---|
| 1366 | tp->tx_ring[entry].tx_ctrl.bits.tx_buf_size = s;
|
|---|
| 1367 |
|
|---|
| 1368 | tp->tx_ring[entry].tx_status.bits.own_bit = 1;
|
|---|
| 1369 |
|
|---|
| 1370 |
|
|---|
| 1371 | CR1bak = inb (byCR1);
|
|---|
| 1372 |
|
|---|
| 1373 | CR1bak = CR1bak | CR1_TDMD1;
|
|---|
| 1374 | /*printf("tdsw=[%X]",tp->tx_ring[entry].tx_status.lw); */
|
|---|
| 1375 | /*printf("tdcw=[%X]",tp->tx_ring[entry].tx_ctrl.lw); */
|
|---|
| 1376 | /*printf("tdbuf1=[%X]",tp->tx_ring[entry].buf_addr_1); */
|
|---|
| 1377 | /*printf("tdbuf2=[%X]",tp->tx_ring[entry].buf_addr_2); */
|
|---|
| 1378 | /*printf("td1=[%X]",inl(dwCurrentTDSE0)); */
|
|---|
| 1379 | /*printf("td2=[%X]",inl(dwCurrentTDSE1)); */
|
|---|
| 1380 | /*printf("td3=[%X]",inl(dwCurrentTDSE2)); */
|
|---|
| 1381 | /*printf("td4=[%X]",inl(dwCurrentTDSE3)); */
|
|---|
| 1382 |
|
|---|
| 1383 | outb (CR1bak, byCR1);
|
|---|
| 1384 | do
|
|---|
| 1385 | {
|
|---|
| 1386 | load_timer2(10*TICKS_PER_MS);
|
|---|
| 1387 | /* Wait until transmit is finished or timeout*/
|
|---|
| 1388 | while((tp->tx_ring[entry].tx_status.bits.own_bit !=0) && timer2_running())
|
|---|
| 1389 | ;
|
|---|
| 1390 |
|
|---|
| 1391 | if(tp->tx_ring[entry].tx_status.bits.terr == 0)
|
|---|
| 1392 | break;
|
|---|
| 1393 |
|
|---|
| 1394 | if(tp->tx_ring[entry].tx_status.bits.abt == 1)
|
|---|
| 1395 | {
|
|---|
| 1396 | // turn on TX
|
|---|
| 1397 | CR0bak = inb(byCR0);
|
|---|
| 1398 | CR0bak = CR0bak|CR_TXON;
|
|---|
| 1399 | outb(CR0bak,byCR0);
|
|---|
| 1400 | }
|
|---|
| 1401 | }while(0);
|
|---|
| 1402 | tp->cur_tx++;
|
|---|
| 1403 |
|
|---|
| 1404 | /*outw(IMRShadow,byIMR0); */
|
|---|
| 1405 | /*dev_kfree_skb(tp->tx_skbuff[entry], FREE_WRITE); */
|
|---|
| 1406 | /*tp->tx_skbuff[entry] = 0; */
|
|---|
| 1407 | }
|
|---|
| 1408 |
|
|---|
| 1409 | static struct pci_id rhine_nics[] = {
|
|---|
| 1410 | PCI_ROM(0x1106, 0x3065, "dlink-530tx", "VIA 6102"),
|
|---|
| 1411 | PCI_ROM(0x1106, 0x3106, "via-rhine-6105", "VIA 6105"),
|
|---|
| 1412 | PCI_ROM(0x1106, 0x3043, "dlink-530tx-old", "VIA 3043"), /* Rhine-I 86c100a */
|
|---|
| 1413 | PCI_ROM(0x1106, 0x3053, "via6105m", "VIA 6105M"),
|
|---|
| 1414 | PCI_ROM(0x1106, 0x6100, "via-rhine-old", "VIA 86C100A"), /* Rhine-II */
|
|---|
| 1415 | };
|
|---|
| 1416 |
|
|---|
| 1417 | static struct pci_driver rhine_driver __pci_driver = {
|
|---|
| 1418 | .type = NIC_DRIVER,
|
|---|
| 1419 | .name = "VIA 86C100",
|
|---|
| 1420 | .probe = rhine_probe,
|
|---|
| 1421 | .ids = rhine_nics,
|
|---|
| 1422 | .id_count = sizeof(rhine_nics)/sizeof(rhine_nics[0]),
|
|---|
| 1423 | .class = 0,
|
|---|
| 1424 | };
|
|---|
| 1425 |
|
|---|
| 1426 | /* EOF via-rhine.c */
|
|---|
