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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/via-velocity.h@ 1300

Last change on this file since 1300 was 1300, checked in by vboxsync, 18 years ago

Fix eol style properties for header files
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1#define EB54 1
2/*
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
4 * All rights reserved.
5 *
6 * This software may be redistributed and/or modified under
7 * the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * File: via-velocity.h
17 *
18 * Purpose: Header file to define driver's private structures.
19 *
20 * Author: Chuang Liang-Shing, AJ Jiang
21 *
22 * Date: Jan 24, 2003
23 *
24 * Changes for Etherboot Port:
25 * Copyright (c) 2006 by Timothy Legge <[email protected]>
26 */
27
28#include "timer.h"
29
30#ifndef EB54
31typedef unsigned char u8;
32typedef signed char s8;
33typedef unsigned short u16;
34typedef signed short s16;
35typedef unsigned int u32;
36typedef signed int s32;
37#endif
38#ifndef VELOCITY_H
39#define VELOCITY_H
40
41#define VELOCITY_TX_CSUM_SUPPORT
42
43#define VELOCITY_NAME "via-velocity"
44#define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
45#define VELOCITY_VERSION "1.13"
46
47#define PKT_BUF_SZ 1564
48
49#define MAX_UNITS 1
50#define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
51
52#define REV_ID_VT6110 (0)
53
54#define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
55#define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
56#define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
57
58#define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
59#define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
60#define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
61
62#define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
63#define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
64#define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
65
66#define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
67#define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
68#define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
69
70#define VAR_USED(p) do {(p)=(p);} while (0)
71
72/*
73 * Purpose: Structures for MAX RX/TX descriptors.
74 */
75
76
77#define B_OWNED_BY_CHIP 1
78#define B_OWNED_BY_HOST 0
79
80/*
81 * Bits in the RSR0 register
82 */
83
84#define RSR_DETAG 0x0080
85#define RSR_SNTAG 0x0040
86#define RSR_RXER 0x0020
87#define RSR_RL 0x0010
88#define RSR_CE 0x0008
89#define RSR_FAE 0x0004
90#define RSR_CRC 0x0002
91#define RSR_VIDM 0x0001
92
93/*
94 * Bits in the RSR1 register
95 */
96
97#define RSR_RXOK 0x8000 // rx OK
98#define RSR_PFT 0x4000 // Perfect filtering address match
99#define RSR_MAR 0x2000 // MAC accept multicast address packet
100#define RSR_BAR 0x1000 // MAC accept broadcast address packet
101#define RSR_PHY 0x0800 // MAC accept physical address packet
102#define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator
103#define RSR_STP 0x0200 // start of packet
104#define RSR_EDP 0x0100 // end of packet
105
106/*
107 * Bits in the RSR1 register
108 */
109
110#define RSR1_RXOK 0x80 // rx OK
111#define RSR1_PFT 0x40 // Perfect filtering address match
112#define RSR1_MAR 0x20 // MAC accept multicast address packet
113#define RSR1_BAR 0x10 // MAC accept broadcast address packet
114#define RSR1_PHY 0x08 // MAC accept physical address packet
115#define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator
116#define RSR1_STP 0x02 // start of packet
117#define RSR1_EDP 0x01 // end of packet
118
119/*
120 * Bits in the CSM register
121 */
122
123#define CSM_IPOK 0x40 //IP Checkusm validatiaon ok
124#define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok
125#define CSM_FRAG 0x10 //Fragment IP datagram
126#define CSM_IPKT 0x04 //Received an IP packet
127#define CSM_TCPKT 0x02 //Received a TCP packet
128#define CSM_UDPKT 0x01 //Received a UDP packet
129
130/*
131 * Bits in the TSR0 register
132 */
133
134#define TSR0_ABT 0x0080 // Tx abort because of excessive collision
135#define TSR0_OWT 0x0040 // Jumbo frame Tx abort
136#define TSR0_OWC 0x0020 // Out of window collision
137#define TSR0_COLS 0x0010 // experience collision in this transmit event
138#define TSR0_NCR3 0x0008 // collision retry counter[3]
139#define TSR0_NCR2 0x0004 // collision retry counter[2]
140#define TSR0_NCR1 0x0002 // collision retry counter[1]
141#define TSR0_NCR0 0x0001 // collision retry counter[0]
142#define TSR0_TERR 0x8000 //
143#define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode
144#define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode
145#define TSR0_LNKFL 0x1000 // packet serviced during link down
146#define TSR0_SHDN 0x0400 // shutdown case
147#define TSR0_CRS 0x0200 // carrier sense lost
148#define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat)
149
150/*
151 * Bits in the TSR1 register
152 */
153
154#define TSR1_TERR 0x80 //
155#define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode
156#define TSR1_GMII 0x20 // current transaction is serviced by GMII mode
157#define TSR1_LNKFL 0x10 // packet serviced during link down
158#define TSR1_SHDN 0x04 // shutdown case
159#define TSR1_CRS 0x02 // carrier sense lost
160#define TSR1_CDH 0x01 // AQE test fail (CD heartbeat)
161
162//
163// Bits in the TCR0 register
164//
165#define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
166#define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
167#define TCR0_VETAG 0x20 // enable VLAN tag
168#define TCR0_IPCK 0x10 // request IP checksum calculation.
169#define TCR0_UDPCK 0x08 // request UDP checksum calculation.
170#define TCR0_TCPCK 0x04 // request TCP checksum calculation.
171#define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
172#define TCR0_CRC 0x01 // disable CRC generation
173
174#define TCPLS_NORMAL 3
175#define TCPLS_START 2
176#define TCPLS_END 1
177#define TCPLS_MED 0
178
179
180// max transmit or receive buffer size
181#define CB_RX_BUF_SIZE 2048UL // max buffer size
182 // NOTE: must be multiple of 4
183
184#define CB_MAX_RD_NUM 512 // MAX # of RD
185#define CB_MAX_TD_NUM 256 // MAX # of TD
186
187#define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
188#define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
189
190#define CB_INIT_RD_NUM 128 // init # of RD, for setup default
191#define CB_INIT_TD_NUM 64 // init # of TD, for setup default
192
193// for 3119
194#define CB_TD_RING_NUM 4 // # of TD rings.
195#define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
196
197
198/*
199 * If collisions excess 15 times , tx will abort, and
200 * if tx fifo underflow, tx will fail
201 * we should try to resend it
202 */
203
204#define CB_MAX_TX_ABORT_RETRY 3
205
206/*
207 * Receive descriptor
208 */
209
210struct rdesc0 {
211 u16 RSR; /* Receive status */
212 u16 len:14; /* Received packet length */
213 u16 reserved:1;
214 u16 owner:1; /* Who owns this buffer ? */
215};
216
217struct rdesc1 {
218 u16 PQTAG;
219 u8 CSM;
220 u8 IPKT;
221};
222
223struct rx_desc {
224 struct rdesc0 rdesc0;
225 struct rdesc1 rdesc1;
226 u32 pa_low; /* Low 32 bit PCI address */
227 u16 pa_high; /* Next 16 bit PCI address (48 total) */
228 u16 len:15; /* Frame size */
229 u16 inten:1; /* Enable interrupt */
230} __attribute__ ((__packed__));
231
232/*
233 * Transmit descriptor
234 */
235
236struct tdesc0 {
237 u16 TSR; /* Transmit status register */
238 u16 pktsize:14; /* Size of frame */
239 u16 reserved:1;
240 u16 owner:1; /* Who owns the buffer */
241};
242
243struct pqinf { /* Priority queue info */
244 u16 VID:12;
245 u16 CFI:1;
246 u16 priority:3;
247} __attribute__ ((__packed__));
248
249struct tdesc1 {
250 struct pqinf pqinf;
251 u8 TCR;
252 u8 TCPLS:2;
253 u8 reserved:2;
254 u8 CMDZ:4;
255} __attribute__ ((__packed__));
256
257struct td_buf {
258 u32 pa_low;
259 u16 pa_high;
260 u16 bufsize:14;
261 u16 reserved:1;
262 u16 queue:1;
263} __attribute__ ((__packed__));
264
265struct tx_desc {
266 struct tdesc0 tdesc0;
267 struct tdesc1 tdesc1;
268 struct td_buf td_buf[7];
269};
270
271#ifdef LINUX
272struct velocity_rd_info {
273 struct sk_buff *skb;
274 dma_addr_t skb_dma;
275};
276
277
278/**
279 * alloc_rd_info - allocate an rd info block
280 *
281 * Alocate and initialize a receive info structure used for keeping
282 * track of kernel side information related to each receive
283 * descriptor we are using
284 */
285
286static inline struct velocity_rd_info *alloc_rd_info(void)
287{
288 struct velocity_rd_info *ptr;
289 if ((ptr =
290 kmalloc(sizeof(struct velocity_rd_info), GFP_ATOMIC)) == NULL)
291 return NULL;
292 else {
293 memset(ptr, 0, sizeof(struct velocity_rd_info));
294 return ptr;
295 }
296}
297
298/*
299 * Used to track transmit side buffers.
300 */
301
302struct velocity_td_info {
303 struct sk_buff *skb;
304 u8 *buf;
305 int nskb_dma;
306 dma_addr_t skb_dma[7];
307 dma_addr_t buf_dma;
308};
309
310#endif
311enum {
312 OWNED_BY_HOST = 0,
313 OWNED_BY_NIC = 1
314} velocity_owner;
315
316
317/*
318 * MAC registers and macros.
319 */
320
321
322#define MCAM_SIZE 64
323#define VCAM_SIZE 64
324#define TX_QUEUE_NO 4
325
326#define MAX_HW_MIB_COUNTER 32
327#define VELOCITY_MIN_MTU (1514-14)
328#define VELOCITY_MAX_MTU (9000)
329
330/*
331 * Registers in the MAC
332 */
333
334#define MAC_REG_PAR 0x00 // physical address
335#define MAC_REG_RCR 0x06
336#define MAC_REG_TCR 0x07
337#define MAC_REG_CR0_SET 0x08
338#define MAC_REG_CR1_SET 0x09
339#define MAC_REG_CR2_SET 0x0A
340#define MAC_REG_CR3_SET 0x0B
341#define MAC_REG_CR0_CLR 0x0C
342#define MAC_REG_CR1_CLR 0x0D
343#define MAC_REG_CR2_CLR 0x0E
344#define MAC_REG_CR3_CLR 0x0F
345#define MAC_REG_MAR 0x10
346#define MAC_REG_CAM 0x10
347#define MAC_REG_DEC_BASE_HI 0x18
348#define MAC_REG_DBF_BASE_HI 0x1C
349#define MAC_REG_ISR_CTL 0x20
350#define MAC_REG_ISR_HOTMR 0x20
351#define MAC_REG_ISR_TSUPTHR 0x20
352#define MAC_REG_ISR_RSUPTHR 0x20
353#define MAC_REG_ISR_CTL1 0x21
354#define MAC_REG_TXE_SR 0x22
355#define MAC_REG_RXE_SR 0x23
356#define MAC_REG_ISR 0x24
357#define MAC_REG_ISR0 0x24
358#define MAC_REG_ISR1 0x25
359#define MAC_REG_ISR2 0x26
360#define MAC_REG_ISR3 0x27
361#define MAC_REG_IMR 0x28
362#define MAC_REG_IMR0 0x28
363#define MAC_REG_IMR1 0x29
364#define MAC_REG_IMR2 0x2A
365#define MAC_REG_IMR3 0x2B
366#define MAC_REG_TDCSR_SET 0x30
367#define MAC_REG_RDCSR_SET 0x32
368#define MAC_REG_TDCSR_CLR 0x34
369#define MAC_REG_RDCSR_CLR 0x36
370#define MAC_REG_RDBASE_LO 0x38
371#define MAC_REG_RDINDX 0x3C
372#define MAC_REG_TDBASE_LO 0x40
373#define MAC_REG_RDCSIZE 0x50
374#define MAC_REG_TDCSIZE 0x52
375#define MAC_REG_TDINDX 0x54
376#define MAC_REG_TDIDX0 0x54
377#define MAC_REG_TDIDX1 0x56
378#define MAC_REG_TDIDX2 0x58
379#define MAC_REG_TDIDX3 0x5A
380#define MAC_REG_PAUSE_TIMER 0x5C
381#define MAC_REG_RBRDU 0x5E
382#define MAC_REG_FIFO_TEST0 0x60
383#define MAC_REG_FIFO_TEST1 0x64
384#define MAC_REG_CAMADDR 0x68
385#define MAC_REG_CAMCR 0x69
386#define MAC_REG_GFTEST 0x6A
387#define MAC_REG_FTSTCMD 0x6B
388#define MAC_REG_MIICFG 0x6C
389#define MAC_REG_MIISR 0x6D
390#define MAC_REG_PHYSR0 0x6E
391#define MAC_REG_PHYSR1 0x6F
392#define MAC_REG_MIICR 0x70
393#define MAC_REG_MIIADR 0x71
394#define MAC_REG_MIIDATA 0x72
395#define MAC_REG_SOFT_TIMER0 0x74
396#define MAC_REG_SOFT_TIMER1 0x76
397#define MAC_REG_CFGA 0x78
398#define MAC_REG_CFGB 0x79
399#define MAC_REG_CFGC 0x7A
400#define MAC_REG_CFGD 0x7B
401#define MAC_REG_DCFG0 0x7C
402#define MAC_REG_DCFG1 0x7D
403#define MAC_REG_MCFG0 0x7E
404#define MAC_REG_MCFG1 0x7F
405
406#define MAC_REG_TBIST 0x80
407#define MAC_REG_RBIST 0x81
408#define MAC_REG_PMCC 0x82
409#define MAC_REG_STICKHW 0x83
410#define MAC_REG_MIBCR 0x84
411#define MAC_REG_EERSV 0x85
412#define MAC_REG_REVID 0x86
413#define MAC_REG_MIBREAD 0x88
414#define MAC_REG_BPMA 0x8C
415#define MAC_REG_EEWR_DATA 0x8C
416#define MAC_REG_BPMD_WR 0x8F
417#define MAC_REG_BPCMD 0x90
418#define MAC_REG_BPMD_RD 0x91
419#define MAC_REG_EECHKSUM 0x92
420#define MAC_REG_EECSR 0x93
421#define MAC_REG_EERD_DATA 0x94
422#define MAC_REG_EADDR 0x96
423#define MAC_REG_EMBCMD 0x97
424#define MAC_REG_JMPSR0 0x98
425#define MAC_REG_JMPSR1 0x99
426#define MAC_REG_JMPSR2 0x9A
427#define MAC_REG_JMPSR3 0x9B
428#define MAC_REG_CHIPGSR 0x9C
429#define MAC_REG_TESTCFG 0x9D
430#define MAC_REG_DEBUG 0x9E
431#define MAC_REG_CHIPGCR 0x9F
432#define MAC_REG_WOLCR0_SET 0xA0
433#define MAC_REG_WOLCR1_SET 0xA1
434#define MAC_REG_PWCFG_SET 0xA2
435#define MAC_REG_WOLCFG_SET 0xA3
436#define MAC_REG_WOLCR0_CLR 0xA4
437#define MAC_REG_WOLCR1_CLR 0xA5
438#define MAC_REG_PWCFG_CLR 0xA6
439#define MAC_REG_WOLCFG_CLR 0xA7
440#define MAC_REG_WOLSR0_SET 0xA8
441#define MAC_REG_WOLSR1_SET 0xA9
442#define MAC_REG_WOLSR0_CLR 0xAC
443#define MAC_REG_WOLSR1_CLR 0xAD
444#define MAC_REG_PATRN_CRC0 0xB0
445#define MAC_REG_PATRN_CRC1 0xB2
446#define MAC_REG_PATRN_CRC2 0xB4
447#define MAC_REG_PATRN_CRC3 0xB6
448#define MAC_REG_PATRN_CRC4 0xB8
449#define MAC_REG_PATRN_CRC5 0xBA
450#define MAC_REG_PATRN_CRC6 0xBC
451#define MAC_REG_PATRN_CRC7 0xBE
452#define MAC_REG_BYTEMSK0_0 0xC0
453#define MAC_REG_BYTEMSK0_1 0xC4
454#define MAC_REG_BYTEMSK0_2 0xC8
455#define MAC_REG_BYTEMSK0_3 0xCC
456#define MAC_REG_BYTEMSK1_0 0xD0
457#define MAC_REG_BYTEMSK1_1 0xD4
458#define MAC_REG_BYTEMSK1_2 0xD8
459#define MAC_REG_BYTEMSK1_3 0xDC
460#define MAC_REG_BYTEMSK2_0 0xE0
461#define MAC_REG_BYTEMSK2_1 0xE4
462#define MAC_REG_BYTEMSK2_2 0xE8
463#define MAC_REG_BYTEMSK2_3 0xEC
464#define MAC_REG_BYTEMSK3_0 0xF0
465#define MAC_REG_BYTEMSK3_1 0xF4
466#define MAC_REG_BYTEMSK3_2 0xF8
467#define MAC_REG_BYTEMSK3_3 0xFC
468
469/*
470 * Bits in the RCR register
471 */
472
473#define RCR_AS 0x80
474#define RCR_AP 0x40
475#define RCR_AL 0x20
476#define RCR_PROM 0x10
477#define RCR_AB 0x08
478#define RCR_AM 0x04
479#define RCR_AR 0x02
480#define RCR_SEP 0x01
481
482/*
483 * Bits in the TCR register
484 */
485
486#define TCR_TB2BDIS 0x80
487#define TCR_COLTMC1 0x08
488#define TCR_COLTMC0 0x04
489#define TCR_LB1 0x02 /* loopback[1] */
490#define TCR_LB0 0x01 /* loopback[0] */
491
492/*
493 * Bits in the CR0 register
494 */
495
496#define CR0_TXON 0x00000008UL
497#define CR0_RXON 0x00000004UL
498#define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
499#define CR0_STRT 0x00000001UL /* start MAC */
500#define CR0_SFRST 0x00008000UL /* software reset */
501#define CR0_TM1EN 0x00004000UL
502#define CR0_TM0EN 0x00002000UL
503#define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
504#define CR0_DISAU 0x00000100UL
505#define CR0_XONEN 0x00800000UL
506#define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
507#define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
508#define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
509#define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
510#define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
511#define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
512#define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
513#define CR0_GSPRST 0x80000000UL
514#define CR0_FORSRST 0x40000000UL
515#define CR0_FPHYRST 0x20000000UL
516#define CR0_DIAG 0x10000000UL
517#define CR0_INTPCTL 0x04000000UL
518#define CR0_GINTMSK1 0x02000000UL
519#define CR0_GINTMSK0 0x01000000UL
520
521/*
522 * Bits in the CR1 register
523 */
524
525#define CR1_SFRST 0x80 /* software reset */
526#define CR1_TM1EN 0x40
527#define CR1_TM0EN 0x20
528#define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
529#define CR1_DISAU 0x01
530
531/*
532 * Bits in the CR2 register
533 */
534
535#define CR2_XONEN 0x80
536#define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
537#define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
538#define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
539#define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
540#define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
541#define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
542#define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
543
544/*
545 * Bits in the CR3 register
546 */
547
548#define CR3_GSPRST 0x80
549#define CR3_FORSRST 0x40
550#define CR3_FPHYRST 0x20
551#define CR3_DIAG 0x10
552#define CR3_INTPCTL 0x04
553#define CR3_GINTMSK1 0x02
554#define CR3_GINTMSK0 0x01
555
556#define ISRCTL_UDPINT 0x8000
557#define ISRCTL_TSUPDIS 0x4000
558#define ISRCTL_RSUPDIS 0x2000
559#define ISRCTL_PMSK1 0x1000
560#define ISRCTL_PMSK0 0x0800
561#define ISRCTL_INTPD 0x0400
562#define ISRCTL_HCRLD 0x0200
563#define ISRCTL_SCRLD 0x0100
564
565/*
566 * Bits in the ISR_CTL1 register
567 */
568
569#define ISRCTL1_UDPINT 0x80
570#define ISRCTL1_TSUPDIS 0x40
571#define ISRCTL1_RSUPDIS 0x20
572#define ISRCTL1_PMSK1 0x10
573#define ISRCTL1_PMSK0 0x08
574#define ISRCTL1_INTPD 0x04
575#define ISRCTL1_HCRLD 0x02
576#define ISRCTL1_SCRLD 0x01
577
578/*
579 * Bits in the TXE_SR register
580 */
581
582#define TXESR_TFDBS 0x08
583#define TXESR_TDWBS 0x04
584#define TXESR_TDRBS 0x02
585#define TXESR_TDSTR 0x01
586
587/*
588 * Bits in the RXE_SR register
589 */
590
591#define RXESR_RFDBS 0x08
592#define RXESR_RDWBS 0x04
593#define RXESR_RDRBS 0x02
594#define RXESR_RDSTR 0x01
595
596/*
597 * Bits in the ISR register
598 */
599
600#define ISR_ISR3 0x80000000UL
601#define ISR_ISR2 0x40000000UL
602#define ISR_ISR1 0x20000000UL
603#define ISR_ISR0 0x10000000UL
604#define ISR_TXSTLI 0x02000000UL
605#define ISR_RXSTLI 0x01000000UL
606#define ISR_HFLD 0x00800000UL
607#define ISR_UDPI 0x00400000UL
608#define ISR_MIBFI 0x00200000UL
609#define ISR_SHDNI 0x00100000UL
610#define ISR_PHYI 0x00080000UL
611#define ISR_PWEI 0x00040000UL
612#define ISR_TMR1I 0x00020000UL
613#define ISR_TMR0I 0x00010000UL
614#define ISR_SRCI 0x00008000UL
615#define ISR_LSTPEI 0x00004000UL
616#define ISR_LSTEI 0x00002000UL
617#define ISR_OVFI 0x00001000UL
618#define ISR_FLONI 0x00000800UL
619#define ISR_RACEI 0x00000400UL
620#define ISR_TXWB1I 0x00000200UL
621#define ISR_TXWB0I 0x00000100UL
622#define ISR_PTX3I 0x00000080UL
623#define ISR_PTX2I 0x00000040UL
624#define ISR_PTX1I 0x00000020UL
625#define ISR_PTX0I 0x00000010UL
626#define ISR_PTXI 0x00000008UL
627#define ISR_PRXI 0x00000004UL
628#define ISR_PPTXI 0x00000002UL
629#define ISR_PPRXI 0x00000001UL
630
631/*
632 * Bits in the IMR register
633 */
634
635#define IMR_TXSTLM 0x02000000UL
636#define IMR_UDPIM 0x00400000UL
637#define IMR_MIBFIM 0x00200000UL
638#define IMR_SHDNIM 0x00100000UL
639#define IMR_PHYIM 0x00080000UL
640#define IMR_PWEIM 0x00040000UL
641#define IMR_TMR1IM 0x00020000UL
642#define IMR_TMR0IM 0x00010000UL
643
644#define IMR_SRCIM 0x00008000UL
645#define IMR_LSTPEIM 0x00004000UL
646#define IMR_LSTEIM 0x00002000UL
647#define IMR_OVFIM 0x00001000UL
648#define IMR_FLONIM 0x00000800UL
649#define IMR_RACEIM 0x00000400UL
650#define IMR_TXWB1IM 0x00000200UL
651#define IMR_TXWB0IM 0x00000100UL
652
653#define IMR_PTX3IM 0x00000080UL
654#define IMR_PTX2IM 0x00000040UL
655#define IMR_PTX1IM 0x00000020UL
656#define IMR_PTX0IM 0x00000010UL
657#define IMR_PTXIM 0x00000008UL
658#define IMR_PRXIM 0x00000004UL
659#define IMR_PPTXIM 0x00000002UL
660#define IMR_PPRXIM 0x00000001UL
661
662/* 0x0013FB0FUL = initial value of IMR */
663
664#define INT_MASK_DEF ( IMR_PPTXIM|IMR_PPRXIM| IMR_PTXIM|IMR_PRXIM | \
665 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM| \
666 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
667 IMR_SHDNIM |IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM )
668
669/*
670 * Bits in the TDCSR0/1, RDCSR0 register
671 */
672
673#define TRDCSR_DEAD 0x0008
674#define TRDCSR_WAK 0x0004
675#define TRDCSR_ACT 0x0002
676#define TRDCSR_RUN 0x0001
677
678/*
679 * Bits in the CAMADDR register
680 */
681
682#define CAMADDR_CAMEN 0x80
683#define CAMADDR_VCAMSL 0x40
684
685/*
686 * Bits in the CAMCR register
687 */
688
689#define CAMCR_PS1 0x80
690#define CAMCR_PS0 0x40
691#define CAMCR_AITRPKT 0x20
692#define CAMCR_AITR16 0x10
693#define CAMCR_CAMRD 0x08
694#define CAMCR_CAMWR 0x04
695#define CAMCR_PS_CAM_MASK 0x40
696#define CAMCR_PS_CAM_DATA 0x80
697#define CAMCR_PS_MAR 0x00
698
699/*
700 * Bits in the MIICFG register
701 */
702
703#define MIICFG_MPO1 0x80
704#define MIICFG_MPO0 0x40
705#define MIICFG_MFDC 0x20
706
707/*
708 * Bits in the MIISR register
709 */
710
711#define MIISR_MIDLE 0x80
712
713/*
714 * Bits in the PHYSR0 register
715 */
716
717#define PHYSR0_PHYRST 0x80
718#define PHYSR0_LINKGD 0x40
719#define PHYSR0_FDPX 0x10
720#define PHYSR0_SPDG 0x08
721#define PHYSR0_SPD10 0x04
722#define PHYSR0_RXFLC 0x02
723#define PHYSR0_TXFLC 0x01
724
725/*
726 * Bits in the PHYSR1 register
727 */
728
729#define PHYSR1_PHYTBI 0x01
730
731/*
732 * Bits in the MIICR register
733 */
734
735#define MIICR_MAUTO 0x80
736#define MIICR_RCMD 0x40
737#define MIICR_WCMD 0x20
738#define MIICR_MDPM 0x10
739#define MIICR_MOUT 0x08
740#define MIICR_MDO 0x04
741#define MIICR_MDI 0x02
742#define MIICR_MDC 0x01
743
744/*
745 * Bits in the MIIADR register
746 */
747
748#define MIIADR_SWMPL 0x80
749
750/*
751 * Bits in the CFGA register
752 */
753
754#define CFGA_PMHCTG 0x08
755#define CFGA_GPIO1PD 0x04
756#define CFGA_ABSHDN 0x02
757#define CFGA_PACPI 0x01
758
759/*
760 * Bits in the CFGB register
761 */
762
763#define CFGB_GTCKOPT 0x80
764#define CFGB_MIIOPT 0x40
765#define CFGB_CRSEOPT 0x20
766#define CFGB_OFSET 0x10
767#define CFGB_CRANDOM 0x08
768#define CFGB_CAP 0x04
769#define CFGB_MBA 0x02
770#define CFGB_BAKOPT 0x01
771
772/*
773 * Bits in the CFGC register
774 */
775
776#define CFGC_EELOAD 0x80
777#define CFGC_BROPT 0x40
778#define CFGC_DLYEN 0x20
779#define CFGC_DTSEL 0x10
780#define CFGC_BTSEL 0x08
781#define CFGC_BPS2 0x04 /* bootrom select[2] */
782#define CFGC_BPS1 0x02 /* bootrom select[1] */
783#define CFGC_BPS0 0x01 /* bootrom select[0] */
784
785/*
786 * Bits in the CFGD register
787 */
788
789#define CFGD_IODIS 0x80
790#define CFGD_MSLVDACEN 0x40
791#define CFGD_CFGDACEN 0x20
792#define CFGD_PCI64EN 0x10
793#define CFGD_HTMRL4 0x08
794
795/*
796 * Bits in the DCFG1 register
797 */
798
799#define DCFG_XMWI 0x8000
800#define DCFG_XMRM 0x4000
801#define DCFG_XMRL 0x2000
802#define DCFG_PERDIS 0x1000
803#define DCFG_MRWAIT 0x0400
804#define DCFG_MWWAIT 0x0200
805#define DCFG_LATMEN 0x0100
806
807/*
808 * Bits in the MCFG0 register
809 */
810
811#define MCFG_RXARB 0x0080
812#define MCFG_RFT1 0x0020
813#define MCFG_RFT0 0x0010
814#define MCFG_LOWTHOPT 0x0008
815#define MCFG_PQEN 0x0004
816#define MCFG_RTGOPT 0x0002
817#define MCFG_VIDFR 0x0001
818
819/*
820 * Bits in the MCFG1 register
821 */
822
823#define MCFG_TXARB 0x8000
824#define MCFG_TXQBK1 0x0800
825#define MCFG_TXQBK0 0x0400
826#define MCFG_TXQNOBK 0x0200
827#define MCFG_SNAPOPT 0x0100
828
829/*
830 * Bits in the PMCC register
831 */
832
833#define PMCC_DSI 0x80
834#define PMCC_D2_DIS 0x40
835#define PMCC_D1_DIS 0x20
836#define PMCC_D3C_EN 0x10
837#define PMCC_D3H_EN 0x08
838#define PMCC_D2_EN 0x04
839#define PMCC_D1_EN 0x02
840#define PMCC_D0_EN 0x01
841
842/*
843 * Bits in STICKHW
844 */
845
846#define STICKHW_SWPTAG 0x10
847#define STICKHW_WOLSR 0x08
848#define STICKHW_WOLEN 0x04
849#define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
850#define STICKHW_DS0 0x01 /* suspend well DS write port */
851
852/*
853 * Bits in the MIBCR register
854 */
855
856#define MIBCR_MIBISTOK 0x80
857#define MIBCR_MIBISTGO 0x40
858#define MIBCR_MIBINC 0x20
859#define MIBCR_MIBHI 0x10
860#define MIBCR_MIBFRZ 0x08
861#define MIBCR_MIBFLSH 0x04
862#define MIBCR_MPTRINI 0x02
863#define MIBCR_MIBCLR 0x01
864
865/*
866 * Bits in the EERSV register
867 */
868
869#define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
870
871#define EERSV_BOOT_MASK ((u8) 0x06)
872#define EERSV_BOOT_INT19 ((u8) 0x00)
873#define EERSV_BOOT_INT18 ((u8) 0x02)
874#define EERSV_BOOT_LOCAL ((u8) 0x04)
875#define EERSV_BOOT_BEV ((u8) 0x06)
876
877
878/*
879 * Bits in BPCMD
880 */
881
882#define BPCMD_BPDNE 0x80
883#define BPCMD_EBPWR 0x02
884#define BPCMD_EBPRD 0x01
885
886/*
887 * Bits in the EECSR register
888 */
889
890#define EECSR_EMBP 0x40 /* eeprom embeded programming */
891#define EECSR_RELOAD 0x20 /* eeprom content reload */
892#define EECSR_DPM 0x10 /* eeprom direct programming */
893#define EECSR_ECS 0x08 /* eeprom CS pin */
894#define EECSR_ECK 0x04 /* eeprom CK pin */
895#define EECSR_EDI 0x02 /* eeprom DI pin */
896#define EECSR_EDO 0x01 /* eeprom DO pin */
897
898/*
899 * Bits in the EMBCMD register
900 */
901
902#define EMBCMD_EDONE 0x80
903#define EMBCMD_EWDIS 0x08
904#define EMBCMD_EWEN 0x04
905#define EMBCMD_EWR 0x02
906#define EMBCMD_ERD 0x01
907
908/*
909 * Bits in TESTCFG register
910 */
911
912#define TESTCFG_HBDIS 0x80
913
914/*
915 * Bits in CHIPGCR register
916 */
917
918#define CHIPGCR_FCGMII 0x80
919#define CHIPGCR_FCFDX 0x40
920#define CHIPGCR_FCRESV 0x20
921#define CHIPGCR_FCMODE 0x10
922#define CHIPGCR_LPSOPT 0x08
923#define CHIPGCR_TM1US 0x04
924#define CHIPGCR_TM0US 0x02
925#define CHIPGCR_PHYINTEN 0x01
926
927/*
928 * Bits in WOLCR0
929 */
930
931#define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
932#define WOLCR_MSWOLEN6 0x0040
933#define WOLCR_MSWOLEN5 0x0020
934#define WOLCR_MSWOLEN4 0x0010
935#define WOLCR_MSWOLEN3 0x0008
936#define WOLCR_MSWOLEN2 0x0004
937#define WOLCR_MSWOLEN1 0x0002
938#define WOLCR_MSWOLEN0 0x0001
939#define WOLCR_ARP_EN 0x0001
940
941/*
942 * Bits in WOLCR1
943 */
944
945#define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
946#define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
947#define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
948#define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
949
950
951/*
952 * Bits in PWCFG
953 */
954
955#define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
956#define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
957#define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
958#define PWCFG_LEGCY_WOL 0x10
959#define PWCFG_PMCSR_PME_SR 0x08
960#define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
961#define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
962#define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
963
964/*
965 * Bits in WOLCFG
966 */
967
968#define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
969#define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
970#define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
971#define WOLCFG_SMIIACC 0x08 /* ?? */
972#define WOLCFG_SGENWH 0x02
973#define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
974 to report status change */
975/*
976 * Bits in WOLSR1
977 */
978
979#define WOLSR_LINKOFF_INT 0x0800
980#define WOLSR_LINKON_INT 0x0400
981#define WOLSR_MAGIC_INT 0x0200
982#define WOLSR_UNICAST_INT 0x0100
983
984/*
985 * Ethernet address filter type
986 */
987
988#define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
989#define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
990#define PKT_TYPE_MULTICAST 0x0002
991#define PKT_TYPE_ALL_MULTICAST 0x0004
992#define PKT_TYPE_BROADCAST 0x0008
993#define PKT_TYPE_PROMISCUOUS 0x0020
994#define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
995#define PKT_TYPE_RUNT 0x4000
996#define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
997
998/*
999 * Loopback mode
1000 */
1001
1002#define MAC_LB_NONE 0x00
1003#define MAC_LB_INTERNAL 0x01
1004#define MAC_LB_EXTERNAL 0x02
1005
1006/*
1007 * Enabled mask value of irq
1008 */
1009
1010#if defined(_SIM)
1011#define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
1012 set IMR0 to 0x0F according to spec */
1013
1014#else
1015#define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
1016 ignore MIBFI,RACEI to
1017 reduce intr. frequency
1018 NOTE.... do not enable NoBuf int mask at driver driver
1019 when (1) NoBuf -> RxThreshold = SF
1020 (2) OK -> RxThreshold = original value
1021 */
1022#endif
1023
1024/*
1025 * Revision id
1026 */
1027
1028#define REV_ID_VT3119_A0 0x00
1029#define REV_ID_VT3119_A1 0x01
1030#define REV_ID_VT3216_A0 0x10
1031
1032/*
1033 * Max time out delay time
1034 */
1035
1036#define W_MAX_TIMEOUT 0x0FFFU
1037
1038
1039/*
1040 * MAC registers as a structure. Cannot be directly accessed this
1041 * way but generates offsets for readl/writel() calls
1042 */
1043
1044struct mac_regs {
1045 volatile u8 PAR[6]; /* 0x00 */
1046 volatile u8 RCR;
1047 volatile u8 TCR;
1048
1049 volatile u32 CR0Set; /* 0x08 */
1050 volatile u32 CR0Clr; /* 0x0C */
1051
1052 volatile u8 MARCAM[8]; /* 0x10 */
1053
1054 volatile u32 DecBaseHi; /* 0x18 */
1055 volatile u16 DbfBaseHi; /* 0x1C */
1056 volatile u16 reserved_1E;
1057
1058 volatile u16 ISRCTL; /* 0x20 */
1059 volatile u8 TXESR;
1060 volatile u8 RXESR;
1061
1062 volatile u32 ISR; /* 0x24 */
1063 volatile u32 IMR;
1064
1065 volatile u32 TDStatusPort; /* 0x2C */
1066
1067 volatile u16 TDCSRSet; /* 0x30 */
1068 volatile u8 RDCSRSet;
1069 volatile u8 reserved_33;
1070 volatile u16 TDCSRClr;
1071 volatile u8 RDCSRClr;
1072 volatile u8 reserved_37;
1073
1074 volatile u32 RDBaseLo; /* 0x38 */
1075 volatile u16 RDIdx; /* 0x3C */
1076 volatile u16 reserved_3E;
1077
1078 volatile u32 TDBaseLo[4]; /* 0x40 */
1079
1080 volatile u16 RDCSize; /* 0x50 */
1081 volatile u16 TDCSize; /* 0x52 */
1082 volatile u16 TDIdx[4]; /* 0x54 */
1083 volatile u16 tx_pause_timer; /* 0x5C */
1084 volatile u16 RBRDU; /* 0x5E */
1085
1086 volatile u32 FIFOTest0; /* 0x60 */
1087 volatile u32 FIFOTest1; /* 0x64 */
1088
1089 volatile u8 CAMADDR; /* 0x68 */
1090 volatile u8 CAMCR; /* 0x69 */
1091 volatile u8 GFTEST; /* 0x6A */
1092 volatile u8 FTSTCMD; /* 0x6B */
1093
1094 volatile u8 MIICFG; /* 0x6C */
1095 volatile u8 MIISR;
1096 volatile u8 PHYSR0;
1097 volatile u8 PHYSR1;
1098 volatile u8 MIICR;
1099 volatile u8 MIIADR;
1100 volatile u16 MIIDATA;
1101
1102 volatile u16 SoftTimer0; /* 0x74 */
1103 volatile u16 SoftTimer1;
1104
1105 volatile u8 CFGA; /* 0x78 */
1106 volatile u8 CFGB;
1107 volatile u8 CFGC;
1108 volatile u8 CFGD;
1109
1110 volatile u16 DCFG; /* 0x7C */
1111 volatile u16 MCFG;
1112
1113 volatile u8 TBIST; /* 0x80 */
1114 volatile u8 RBIST;
1115 volatile u8 PMCPORT;
1116 volatile u8 STICKHW;
1117
1118 volatile u8 MIBCR; /* 0x84 */
1119 volatile u8 reserved_85;
1120 volatile u8 rev_id;
1121 volatile u8 PORSTS;
1122
1123 volatile u32 MIBData; /* 0x88 */
1124
1125 volatile u16 EEWrData;
1126
1127 volatile u8 reserved_8E;
1128 volatile u8 BPMDWr;
1129 volatile u8 BPCMD;
1130 volatile u8 BPMDRd;
1131
1132 volatile u8 EECHKSUM; /* 0x92 */
1133 volatile u8 EECSR;
1134
1135 volatile u16 EERdData; /* 0x94 */
1136 volatile u8 EADDR;
1137 volatile u8 EMBCMD;
1138
1139
1140 volatile u8 JMPSR0; /* 0x98 */
1141 volatile u8 JMPSR1;
1142 volatile u8 JMPSR2;
1143 volatile u8 JMPSR3;
1144 volatile u8 CHIPGSR; /* 0x9C */
1145 volatile u8 TESTCFG;
1146 volatile u8 DEBUG;
1147 volatile u8 CHIPGCR;
1148
1149 volatile u16 WOLCRSet; /* 0xA0 */
1150 volatile u8 PWCFGSet;
1151 volatile u8 WOLCFGSet;
1152
1153 volatile u16 WOLCRClr; /* 0xA4 */
1154 volatile u8 PWCFGCLR;
1155 volatile u8 WOLCFGClr;
1156
1157 volatile u16 WOLSRSet; /* 0xA8 */
1158 volatile u16 reserved_AA;
1159
1160 volatile u16 WOLSRClr; /* 0xAC */
1161 volatile u16 reserved_AE;
1162
1163 volatile u16 PatternCRC[8]; /* 0xB0 */
1164 volatile u32 ByteMask[4][4]; /* 0xC0 */
1165} __attribute__ ((__packed__));
1166
1167
1168enum hw_mib {
1169 HW_MIB_ifRxAllPkts = 0,
1170 HW_MIB_ifRxOkPkts,
1171 HW_MIB_ifTxOkPkts,
1172 HW_MIB_ifRxErrorPkts,
1173 HW_MIB_ifRxRuntOkPkt,
1174 HW_MIB_ifRxRuntErrPkt,
1175 HW_MIB_ifRx64Pkts,
1176 HW_MIB_ifTx64Pkts,
1177 HW_MIB_ifRx65To127Pkts,
1178 HW_MIB_ifTx65To127Pkts,
1179 HW_MIB_ifRx128To255Pkts,
1180 HW_MIB_ifTx128To255Pkts,
1181 HW_MIB_ifRx256To511Pkts,
1182 HW_MIB_ifTx256To511Pkts,
1183 HW_MIB_ifRx512To1023Pkts,
1184 HW_MIB_ifTx512To1023Pkts,
1185 HW_MIB_ifRx1024To1518Pkts,
1186 HW_MIB_ifTx1024To1518Pkts,
1187 HW_MIB_ifTxEtherCollisions,
1188 HW_MIB_ifRxPktCRCE,
1189 HW_MIB_ifRxJumboPkts,
1190 HW_MIB_ifTxJumboPkts,
1191 HW_MIB_ifRxMacControlFrames,
1192 HW_MIB_ifTxMacControlFrames,
1193 HW_MIB_ifRxPktFAE,
1194 HW_MIB_ifRxLongOkPkt,
1195 HW_MIB_ifRxLongPktErrPkt,
1196 HW_MIB_ifTXSQEErrors,
1197 HW_MIB_ifRxNobuf,
1198 HW_MIB_ifRxSymbolErrors,
1199 HW_MIB_ifInRangeLengthErrors,
1200 HW_MIB_ifLateCollisions,
1201 HW_MIB_SIZE
1202};
1203
1204enum chip_type {
1205 CHIP_TYPE_VT6110 = 1,
1206};
1207
1208struct velocity_info_tbl {
1209 enum chip_type chip_id;
1210 char *name;
1211 int io_size;
1212 int txqueue;
1213 u32 flags;
1214};
1215
1216struct velocity_info_tbl *info;
1217
1218#define mac_hw_mibs_init(regs) {\
1219 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1220 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1221 do {}\
1222 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1223 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1224}
1225
1226#define mac_read_isr(regs) readl(&((regs)->ISR))
1227#define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1228#define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
1229
1230#define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
1231#define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
1232#define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
1233
1234#define mac_hw_mibs_read(regs, MIBs) {\
1235 int i;\
1236 BYTE_REG_BITS_ON(MIBCR_MPTRINI,&((regs)->MIBCR));\
1237 for (i=0;i<HW_MIB_SIZE;i++) {\
1238 (MIBs)[i]=readl(&((regs)->MIBData));\
1239 }\
1240}
1241
1242#define mac_set_dma_length(regs, n) {\
1243 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
1244}
1245
1246#define mac_set_rx_thresh(regs, n) {\
1247 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
1248}
1249
1250#define mac_rx_queue_run(regs) {\
1251 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
1252}
1253
1254#define mac_rx_queue_wake(regs) {\
1255 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
1256}
1257
1258#define mac_tx_queue_run(regs, n) {\
1259 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
1260}
1261
1262#define mac_tx_queue_wake(regs, n) {\
1263 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
1264}
1265
1266#define mac_eeprom_reload(regs) {\
1267 int i=0;\
1268 BYTE_REG_BITS_ON(EECSR_RELOAD,&((regs)->EECSR));\
1269 do {\
1270 udelay(10);\
1271 if (i++>0x1000) {\
1272 break;\
1273 }\
1274 }while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&((regs)->EECSR)));\
1275}
1276
1277enum velocity_cam_type {
1278 VELOCITY_VLAN_ID_CAM = 0,
1279 VELOCITY_MULTICAST_CAM
1280};
1281
1282/**
1283 * mac_get_cam_mask - Read a CAM mask
1284 * @regs: register block for this velocity
1285 * @mask: buffer to store mask
1286 * @cam_type: CAM to fetch
1287 *
1288 * Fetch the mask bits of the selected CAM and store them into the
1289 * provided mask buffer.
1290 */
1291
1292static inline void mac_get_cam_mask(struct mac_regs *regs, u8 * mask,
1293 enum velocity_cam_type cam_type)
1294{
1295 int i;
1296 /* Select CAM mask */
1297 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0,
1298 &regs->CAMCR);
1299
1300 if (cam_type == VELOCITY_VLAN_ID_CAM)
1301 writeb(CAMADDR_VCAMSL, &regs->CAMADDR);
1302 else
1303 writeb(0, &regs->CAMADDR);
1304
1305 /* read mask */
1306 for (i = 0; i < 8; i++)
1307 *mask++ = readb(&(regs->MARCAM[i]));
1308
1309 /* disable CAMEN */
1310 writeb(0, &regs->CAMADDR);
1311
1312 /* Select mar */
1313 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1314 &regs->CAMCR);
1315
1316}
1317
1318/**
1319 * mac_set_cam_mask - Set a CAM mask
1320 * @regs: register block for this velocity
1321 * @mask: CAM mask to load
1322 * @cam_type: CAM to store
1323 *
1324 * Store a new mask into a CAM
1325 */
1326
1327static inline void mac_set_cam_mask(struct mac_regs *regs, u8 * mask,
1328 enum velocity_cam_type cam_type)
1329{
1330 int i;
1331 /* Select CAM mask */
1332 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0,
1333 &regs->CAMCR);
1334
1335 if (cam_type == VELOCITY_VLAN_ID_CAM)
1336 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
1337 else
1338 writeb(CAMADDR_CAMEN, &regs->CAMADDR);
1339
1340 for (i = 0; i < 8; i++) {
1341 writeb(*mask++, &(regs->MARCAM[i]));
1342 }
1343 /* disable CAMEN */
1344 writeb(0, &regs->CAMADDR);
1345
1346 /* Select mar */
1347 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1348 &regs->CAMCR);
1349}
1350
1351/**
1352 * mac_set_cam - set CAM data
1353 * @regs: register block of this velocity
1354 * @idx: Cam index
1355 * @addr: 2 or 6 bytes of CAM data
1356 * @cam_type: CAM to load
1357 *
1358 * Load an address or vlan tag into a CAM
1359 */
1360
1361static inline void mac_set_cam(struct mac_regs *regs, int idx, u8 * addr,
1362 enum velocity_cam_type cam_type)
1363{
1364 int i;
1365
1366 /* Select CAM mask */
1367 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0,
1368 &regs->CAMCR);
1369
1370 idx &= (64 - 1);
1371
1372 if (cam_type == VELOCITY_VLAN_ID_CAM)
1373 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx,
1374 &regs->CAMADDR);
1375 else
1376 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1377
1378 if (cam_type == VELOCITY_VLAN_ID_CAM)
1379 writew(*((u16 *) addr), &regs->MARCAM[0]);
1380 else {
1381 for (i = 0; i < 6; i++) {
1382 writeb(*addr++, &(regs->MARCAM[i]));
1383 }
1384 }
1385 BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
1386
1387 udelay(10);
1388
1389 writeb(0, &regs->CAMADDR);
1390
1391 /* Select mar */
1392 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1393 &regs->CAMCR);
1394}
1395
1396/**
1397 * mac_get_cam - fetch CAM data
1398 * @regs: register block of this velocity
1399 * @idx: Cam index
1400 * @addr: buffer to hold up to 6 bytes of CAM data
1401 * @cam_type: CAM to load
1402 *
1403 * Load an address or vlan tag from a CAM into the buffer provided by
1404 * the caller. VLAN tags are 2 bytes the address cam entries are 6.
1405 */
1406
1407static inline void mac_get_cam(struct mac_regs *regs, int idx, u8 * addr,
1408 enum velocity_cam_type cam_type)
1409{
1410 int i;
1411
1412 /* Select CAM mask */
1413 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0,
1414 &regs->CAMCR);
1415
1416 idx &= (64 - 1);
1417
1418 if (cam_type == VELOCITY_VLAN_ID_CAM)
1419 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx,
1420 &regs->CAMADDR);
1421 else
1422 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1423
1424 BYTE_REG_BITS_ON(CAMCR_CAMRD, &regs->CAMCR);
1425
1426 udelay(10);
1427
1428 if (cam_type == VELOCITY_VLAN_ID_CAM)
1429 *((u16 *) addr) = readw(&(regs->MARCAM[0]));
1430 else
1431 for (i = 0; i < 6; i++, addr++)
1432 *((u8 *) addr) = readb(&(regs->MARCAM[i]));
1433
1434 writeb(0, &regs->CAMADDR);
1435
1436 /* Select mar */
1437 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1438 &regs->CAMCR);
1439}
1440
1441/**
1442 * mac_wol_reset - reset WOL after exiting low power
1443 * @regs: register block of this velocity
1444 *
1445 * Called after we drop out of wake on lan mode in order to
1446 * reset the Wake on lan features. This function doesn't restore
1447 * the rest of the logic from the result of sleep/wakeup
1448 */
1449
1450inline static void mac_wol_reset(struct mac_regs *regs)
1451{
1452
1453 /* Turn off SWPTAG right after leaving power mode */
1454 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
1455 /* clear sticky bits */
1456 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
1457
1458 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
1459 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
1460 /* disable force PME-enable */
1461 writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
1462 /* disable power-event config bit */
1463 writew(0xFFFF, &regs->WOLCRClr);
1464 /* clear power status */
1465 writew(0xFFFF, &regs->WOLSRClr);
1466}
1467
1468
1469/*
1470 * Header for WOL definitions. Used to compute hashes
1471 */
1472
1473typedef u8 MCAM_ADDR[ETH_ALEN];
1474
1475struct arp_packet {
1476 u8 dest_mac[ETH_ALEN];
1477 u8 src_mac[ETH_ALEN];
1478 u16 type;
1479 u16 ar_hrd;
1480 u16 ar_pro;
1481 u8 ar_hln;
1482 u8 ar_pln;
1483 u16 ar_op;
1484 u8 ar_sha[ETH_ALEN];
1485 u8 ar_sip[4];
1486 u8 ar_tha[ETH_ALEN];
1487 u8 ar_tip[4];
1488} __attribute__ ((__packed__));
1489
1490struct _magic_packet {
1491 u8 dest_mac[6];
1492 u8 src_mac[6];
1493 u16 type;
1494 u8 MAC[16][6];
1495 u8 password[6];
1496} __attribute__ ((__packed__));
1497
1498/*
1499 * Store for chip context when saving and restoring status. Not
1500 * all fields are saved/restored currently.
1501 */
1502
1503struct velocity_context {
1504 u8 mac_reg[256];
1505 MCAM_ADDR cam_addr[MCAM_SIZE];
1506 u16 vcam[VCAM_SIZE];
1507 u32 cammask[2];
1508 u32 patcrc[2];
1509 u32 pattern[8];
1510};
1511
1512
1513/*
1514 * MII registers.
1515 */
1516
1517
1518/*
1519 * Registers in the MII (offset unit is WORD)
1520 */
1521
1522#define MII_REG_BMCR 0x00 // physical address
1523#define MII_REG_BMSR 0x01 //
1524#define MII_REG_PHYID1 0x02 // OUI
1525#define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID
1526#define MII_REG_ANAR 0x04 //
1527#define MII_REG_ANLPAR 0x05 //
1528#define MII_REG_G1000CR 0x09 //
1529#define MII_REG_G1000SR 0x0A //
1530#define MII_REG_MODCFG 0x10 //
1531#define MII_REG_TCSR 0x16 //
1532#define MII_REG_PLED 0x1B //
1533// NS, MYSON only
1534#define MII_REG_PCR 0x17 //
1535// ESI only
1536#define MII_REG_PCSR 0x17 //
1537#define MII_REG_AUXCR 0x1C //
1538
1539// Marvell 88E1000/88E1000S
1540#define MII_REG_PSCR 0x10 // PHY specific control register
1541
1542//
1543// Bits in the BMCR register
1544//
1545#define BMCR_RESET 0x8000 //
1546#define BMCR_LBK 0x4000 //
1547#define BMCR_SPEED100 0x2000 //
1548#define BMCR_AUTO 0x1000 //
1549#define BMCR_PD 0x0800 //
1550#define BMCR_ISO 0x0400 //
1551#define BMCR_REAUTO 0x0200 //
1552#define BMCR_FDX 0x0100 //
1553#define BMCR_SPEED1G 0x0040 //
1554//
1555// Bits in the BMSR register
1556//
1557#define BMSR_AUTOCM 0x0020 //
1558#define BMSR_LNK 0x0004 //
1559
1560//
1561// Bits in the ANAR register
1562//
1563#define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1564#define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support
1565#define ANAR_T4 0x0200 //
1566#define ANAR_TXFD 0x0100 //
1567#define ANAR_TX 0x0080 //
1568#define ANAR_10FD 0x0040 //
1569#define ANAR_10 0x0020 //
1570//
1571// Bits in the ANLPAR register
1572//
1573#define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1574#define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support
1575#define ANLPAR_T4 0x0200 //
1576#define ANLPAR_TXFD 0x0100 //
1577#define ANLPAR_TX 0x0080 //
1578#define ANLPAR_10FD 0x0040 //
1579#define ANLPAR_10 0x0020 //
1580
1581//
1582// Bits in the G1000CR register
1583//
1584#define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable
1585#define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable
1586
1587//
1588// Bits in the G1000SR register
1589//
1590#define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable
1591#define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable
1592
1593#define TCSR_ECHODIS 0x2000 //
1594#define AUXCR_MDPPS 0x0004 //
1595
1596// Bits in the PLED register
1597#define PLED_LALBE 0x0004 //
1598
1599// Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
1600#define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
1601
1602#define PHYID_CICADA_CS8201 0x000FC410UL
1603#define PHYID_VT3216_32BIT 0x000FC610UL
1604#define PHYID_VT3216_64BIT 0x000FC600UL
1605#define PHYID_MARVELL_1000 0x01410C50UL
1606#define PHYID_MARVELL_1000S 0x01410C40UL
1607
1608#define PHYID_REV_ID_MASK 0x0000000FUL
1609
1610#define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK)
1611#define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
1612
1613#define MII_REG_BITS_ON(x,i,p) do {\
1614 u16 w;\
1615 velocity_mii_read((p),(i),&(w));\
1616 (w)|=(x);\
1617 velocity_mii_write((p),(i),(w));\
1618} while (0)
1619
1620#define MII_REG_BITS_OFF(x,i,p) do {\
1621 u16 w;\
1622 velocity_mii_read((p),(i),&(w));\
1623 (w)&=(~(x));\
1624 velocity_mii_write((p),(i),(w));\
1625} while (0)
1626
1627#define MII_REG_BITS_IS_ON(x,i,p) ({\
1628 u16 w;\
1629 velocity_mii_read((p),(i),&(w));\
1630 ((int) ((w) & (x)));})
1631
1632#define MII_GET_PHY_ID(p) ({\
1633 u32 id;\
1634 velocity_mii_read((p),MII_REG_PHYID2,(u16 *) &id);\
1635 velocity_mii_read((p),MII_REG_PHYID1,((u16 *) &id)+1);\
1636 (id);})
1637
1638#ifdef LINUX
1639/*
1640 * Inline debug routine
1641 */
1642
1643
1644enum velocity_msg_level {
1645 MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation.
1646 MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified.
1647 MSG_LEVEL_INFO = 2, //Normal message.
1648 MSG_LEVEL_VERBOSE = 3, //Will report all trival errors.
1649 MSG_LEVEL_DEBUG = 4 //Only for debug purpose.
1650};
1651
1652#ifdef VELOCITY_DEBUG
1653#define ASSERT(x) { \
1654 if (!(x)) { \
1655 printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
1656 __FUNCTION__, __LINE__);\
1657 BUG(); \
1658 }\
1659}
1660#define VELOCITY_DBG(p,args...) printk(p, ##args)
1661#else
1662#define ASSERT(x)
1663#define VELOCITY_DBG(x)
1664#endif
1665
1666#define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printf( p ,##args);} while (0)
1667
1668#define VELOCITY_PRT_CAMMASK(p,t) {\
1669 int i;\
1670 if ((t)==VELOCITY_MULTICAST_CAM) {\
1671 for (i=0;i<(MCAM_SIZE/8);i++)\
1672 printk("%02X",(p)->mCAMmask[i]);\
1673 }\
1674 else {\
1675 for (i=0;i<(VCAM_SIZE/8);i++)\
1676 printk("%02X",(p)->vCAMmask[i]);\
1677 }\
1678 printk("\n");\
1679}
1680
1681#endif
1682
1683#define VELOCITY_WOL_MAGIC 0x00000000UL
1684#define VELOCITY_WOL_PHY 0x00000001UL
1685#define VELOCITY_WOL_ARP 0x00000002UL
1686#define VELOCITY_WOL_UCAST 0x00000004UL
1687#define VELOCITY_WOL_BCAST 0x00000010UL
1688#define VELOCITY_WOL_MCAST 0x00000020UL
1689#define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
1690
1691/*
1692 * Flags for options
1693 */
1694
1695#define VELOCITY_FLAGS_TAGGING 0x00000001UL
1696#define VELOCITY_FLAGS_TX_CSUM 0x00000002UL
1697#define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
1698#define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
1699#define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
1700
1701#define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
1702
1703/*
1704 * Flags for driver status
1705 */
1706
1707#define VELOCITY_FLAGS_OPENED 0x00010000UL
1708#define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
1709#define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
1710#define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
1711
1712/*
1713 * Flags for MII status
1714 */
1715
1716#define VELOCITY_LINK_FAIL 0x00000001UL
1717#define VELOCITY_SPEED_10 0x00000002UL
1718#define VELOCITY_SPEED_100 0x00000004UL
1719#define VELOCITY_SPEED_1000 0x00000008UL
1720#define VELOCITY_DUPLEX_FULL 0x00000010UL
1721#define VELOCITY_AUTONEG_ENABLE 0x00000020UL
1722#define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
1723
1724/*
1725 * For velocity_set_media_duplex
1726 */
1727
1728#define VELOCITY_LINK_CHANGE 0x00000001UL
1729
1730enum speed_opt {
1731 SPD_DPX_AUTO = 0,
1732 SPD_DPX_100_HALF = 1,
1733 SPD_DPX_100_FULL = 2,
1734 SPD_DPX_10_HALF = 3,
1735 SPD_DPX_10_FULL = 4
1736};
1737
1738enum velocity_init_type {
1739 VELOCITY_INIT_COLD = 0,
1740 VELOCITY_INIT_RESET,
1741 VELOCITY_INIT_WOL
1742};
1743
1744enum velocity_flow_cntl_type {
1745 FLOW_CNTL_DEFAULT = 1,
1746 FLOW_CNTL_TX,
1747 FLOW_CNTL_RX,
1748 FLOW_CNTL_TX_RX,
1749 FLOW_CNTL_DISABLE,
1750};
1751
1752struct velocity_opt {
1753 int numrx; /* Number of RX descriptors */
1754 int numtx; /* Number of TX descriptors */
1755 enum speed_opt spd_dpx; /* Media link mode */
1756 int vid; /* vlan id */
1757 int DMA_length; /* DMA length */
1758 int rx_thresh; /* RX_THRESH */
1759 int flow_cntl;
1760 int wol_opts; /* Wake on lan options */
1761 int td_int_count;
1762 int int_works;
1763 int rx_bandwidth_hi;
1764 int rx_bandwidth_lo;
1765 int rx_bandwidth_en;
1766 u32 flags;
1767};
1768
1769#define RX_DESC_MIN 4
1770#define RX_DESC_MAX 255
1771#define RX_DESC_DEF 64
1772
1773#define TX_DESC_MIN 1
1774#define TX_DESC_MAX 256
1775#define TX_DESC_DEF 4
1776
1777struct velocity_info {
1778 struct pci_device *pdev;
1779
1780#ifdef CONFIG_PM
1781 u32 pci_state[16];
1782#endif
1783
1784 enum chip_type chip_id;
1785
1786 struct mac_regs *mac_regs;
1787 unsigned long memaddr;
1788 unsigned long ioaddr;
1789 u32 io_size;
1790
1791 u8 rev_id;
1792
1793#define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)]))
1794
1795 int num_txq;
1796
1797 int td_curr;
1798 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
1799 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
1800 unsigned char *tx_buffs;
1801 unsigned char *rx_buffs;
1802
1803 unsigned char *txb;
1804 unsigned char *rxb;
1805 struct tx_desc *td_rings;
1806
1807 int rd_curr;
1808 int rd_dirty;
1809 u32 rd_filled;
1810 struct rx_desc *rd_ring;
1811
1812#define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
1813 struct velocity_opt options;
1814
1815 u32 int_mask;
1816
1817 u32 flags;
1818
1819 int rx_buf_sz;
1820 u32 mii_status;
1821 u32 phy_id;
1822 int multicast_limit;
1823
1824 u8 vCAMmask[(VCAM_SIZE / 8)];
1825 u8 mCAMmask[(MCAM_SIZE / 8)];
1826
1827 int wol_opts;
1828
1829} vptx;
1830
1831static struct velocity_info *vptr;
1832
1833#ifdef LINUX
1834/**
1835 * velocity_get_ip - find an IP address for the device
1836 * @vptr: Velocity to query
1837 *
1838 * Dig out an IP address for this interface so that we can
1839 * configure wakeup with WOL for ARP. If there are multiple IP
1840 * addresses on this chain then we use the first - multi-IP WOL is not
1841 * supported.
1842 *
1843 * CHECK ME: locking
1844 */
1845
1846inline static int velocity_get_ip(struct velocity_info *vptr)
1847{
1848 struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr;
1849 struct in_ifaddr *ifa;
1850
1851 if (in_dev != NULL) {
1852 ifa = (struct in_ifaddr *) in_dev->ifa_list;
1853 if (ifa != NULL) {
1854 memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
1855 return 0;
1856 }
1857 }
1858 return -ENOENT;
1859}
1860
1861/**
1862 * velocity_update_hw_mibs - fetch MIB counters from chip
1863 * @vptr: velocity to update
1864 *
1865 * The velocity hardware keeps certain counters in the hardware
1866 * side. We need to read these when the user asks for statistics
1867 * or when they overflow (causing an interrupt). The read of the
1868 * statistic clears it, so we keep running master counters in user
1869 * space.
1870 */
1871
1872static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
1873{
1874 u32 tmp;
1875 int i;
1876 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
1877
1878 while (BYTE_REG_BITS_IS_ON
1879 (MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
1880
1881 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
1882 for (i = 0; i < HW_MIB_SIZE; i++) {
1883 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
1884 vptr->mib_counter[i] += tmp;
1885 }
1886}
1887#endif
1888/**
1889 * init_flow_control_register - set up flow control
1890 * @vptr: velocity to configure
1891 *
1892 * Configure the flow control registers for this velocity device.
1893 */
1894
1895static inline void init_flow_control_register(struct velocity_info *vptr)
1896{
1897 struct mac_regs *regs = vptr->mac_regs;
1898
1899 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
1900 depend on RD=64, and Turn on XNOEN in FlowCR1 */
1901 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0),
1902 &regs->CR0Set);
1903 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0),
1904 &regs->CR0Clr);
1905
1906 /* Set TxPauseTimer to 0xFFFF */
1907 writew(0xFFFF, &regs->tx_pause_timer);
1908
1909 /* Initialize RBRDU to Rx buffer count. */
1910 writew(vptr->options.numrx, &regs->RBRDU);
1911}
1912
1913
1914#endif
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