VirtualBox

source: vbox/trunk/src/VBox/Devices/Security/DevTpm.cpp@ 106378

Last change on this file since 106378 was 106271, checked in by vboxsync, 4 months ago

Devices/Security: Query the buffer size of the device above and use that to set the buffer size in libtpms, bugref:10772 [scm fix]
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1/* $Id: DevTpm.cpp 106271 2024-10-10 07:36:47Z vboxsync $ */
2/** @file
3 * DevTpm - Trusted Platform Module emulation.
4 *
5 * This emulation is based on the spec available under (as of 2021-08-02):
6 * https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-TPM-Profile-for-TPM-2p0-v1p05p_r14_pub.pdf
7 */
8
9/*
10 * Copyright (C) 2021-2024 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/*********************************************************************************************************************************
33* Header Files *
34*********************************************************************************************************************************/
35#define LOG_GROUP LOG_GROUP_DEV_TPM
36#include <VBox/vmm/pdmdev.h>
37#include <VBox/vmm/pdmtpmifs.h>
38#include <iprt/assert.h>
39#include <iprt/string.h>
40#include <iprt/uuid.h>
41
42#include <iprt/formats/tpm.h>
43
44#include "VBoxDD.h"
45
46
47/*********************************************************************************************************************************
48* Defined Constants And Macros *
49*********************************************************************************************************************************/
50
51/** The TPM saved state version. */
52#define TPM_SAVED_STATE_VERSION 1
53
54/** Default vendor ID. */
55#define TPM_VID_DEFAULT 0x1014
56/** Default device ID. */
57#define TPM_DID_DEFAULT 0x0001
58/** Default revision ID. */
59#define TPM_RID_DEFAULT 0x01
60/** Maximum size of the data buffer in bytes. */
61#define TPM_DATA_BUFFER_SIZE_MAX 3968
62
63/** The TPM MMIO base default as defined in chapter 5.2. */
64#define TPM_MMIO_BASE_DEFAULT 0xfed40000
65/** The size of the TPM MMIO area. */
66#define TPM_MMIO_SIZE 0x5000
67
68/** Number of localities as mandated by the TPM spec. */
69#define TPM_LOCALITY_COUNT 5
70/** Size of each locality in the TPM MMIO area (chapter 6.5.2).*/
71#define TPM_LOCALITY_MMIO_SIZE 0x1000
72
73/** @name TPM locality register related defines for the FIFO interface.
74 * @{ */
75/** Ownership management for a particular locality. */
76#define TPM_FIFO_LOCALITY_REG_ACCESS 0x00
77/** Indicates whether a dynamic OS has been established on this platform before.. */
78# define TPM_FIFO_LOCALITY_REG_ACCESS_ESTABLISHMENT RT_BIT(0)
79/** On reads indicates whether the locality requests use of the TPM (1) or not or is already active locality (0),
80 * writing a 1 requests the locality to be granted getting the active locality.. */
81# define TPM_FIFO_LOCALITY_REG_ACCESS_REQUEST_USE RT_BIT(1)
82/** Indicates whether another locality is requesting usage of the TPM. */
83# define TPM_FIFO_LOCALITY_REG_ACCESS_PENDING_REQUEST RT_BIT(2)
84/** Writing a 1 forces the TPM to give control to the locality if it has a higher priority. */
85# define TPM_FIFO_LOCALITY_REG_ACCESS_SEIZE RT_BIT(3)
86/** On reads indicates whether this locality has been seized by a higher locality (1) or not (0), writing a 1 clears this bit. */
87# define TPM_FIFO_LOCALITY_REG_ACCESS_BEEN_SEIZED RT_BIT(4)
88/** On reads indicates whether this locality is active (1) or not (0), writing a 1 relinquishes control for this locality. */
89# define TPM_FIFO_LOCALITY_REG_ACCESS_ACTIVE RT_BIT(5)
90/** Set bit indicates whether all other bits in this register have valid data. */
91# define TPM_FIFO_LOCALITY_REG_ACCESS_VALID RT_BIT(7)
92/** Writable mask. */
93# define TPM_FIFO_LOCALITY_REG_ACCESS_WR_MASK 0x3a
94
95/** Interrupt enable register. */
96#define TPM_FIFO_LOCALITY_REG_INT_ENABLE 0x08
97/** Data available interrupt enable bit. */
98# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_DATA_AVAIL RT_BIT_32(0)
99/** Status valid interrupt enable bit. */
100# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_STS_VALID RT_BIT_32(1)
101/** Locality change interrupt enable bit. */
102# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_LOCALITY_CHANGE RT_BIT_32(2)
103/** Interrupt polarity configuration. */
104# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_MASK 0x18
105# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_SHIFT 3
106# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INT_POLARITY_SHIFT)
107# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_GET(a) (((a) & TPM_FIFO_LOCALITY_REG_INT_POLARITY_MASK) >> TPM_FIFO_LOCALITY_REG_INT_POLARITY_SHIFT)
108/** High level interrupt trigger. */
109# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_HIGH 0
110/** Low level interrupt trigger. */
111# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_LOW 1
112/** Rising edge interrupt trigger. */
113# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_RISING 2
114/** Falling edge interrupt trigger. */
115# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_FALLING 3
116/** Command ready enable bit. */
117# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_CMD_RDY RT_BIT_32(7)
118/** Global interrupt enable/disable bit. */
119# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_GLOBAL RT_BIT_32(31)
120
121/** Configured interrupt vector register. */
122#define TPM_FIFO_LOCALITY_REG_INT_VEC 0x0c
123
124/** Interrupt status register. */
125#define TPM_FIFO_LOCALITY_REG_INT_STS 0x10
126/** Data available interrupt occured bit, writing a 1 clears the bit. */
127# define TPM_FIFO_LOCALITY_REG_INT_STS_DATA_AVAIL RT_BIT_32(0)
128/** Status valid interrupt occured bit, writing a 1 clears the bit. */
129# define TPM_FIFO_LOCALITY_REG_INT_STS_STS_VALID RT_BIT_32(1)
130/** Locality change interrupt occured bit, writing a 1 clears the bit. */
131# define TPM_FIFO_LOCALITY_REG_INT_STS_LOCALITY_CHANGE RT_BIT_32(2)
132/** Command ready occured bit, writing a 1 clears the bit. */
133# define TPM_FIFO_LOCALITY_REG_INT_STS_CMD_RDY RT_BIT_32(7)
134/** Writable mask. */
135# define TPM_FIFO_LOCALITY_REG_INT_STS_WR_MASK UINT32_C(0x87)
136
137/** Interfacce capabilities register. */
138#define TPM_FIFO_LOCALITY_REG_IF_CAP 0x14
139/** Flag whether the TPM supports the data avilable interrupt. */
140# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_DATA_AVAIL RT_BIT(0)
141/** Flag whether the TPM supports the status valid interrupt. */
142# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_STS_VALID RT_BIT(1)
143/** Flag whether the TPM supports the data avilable interrupt. */
144# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LOCALITY_CHANGE RT_BIT(2)
145/** Flag whether the TPM supports high level interrupts. */
146# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LVL_HIGH RT_BIT(3)
147/** Flag whether the TPM supports low level interrupts. */
148# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LVL_LOW RT_BIT(4)
149/** Flag whether the TPM supports rising edge interrupts. */
150# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_RISING_EDGE RT_BIT(5)
151/** Flag whether the TPM supports falling edge interrupts. */
152# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_FALLING_EDGE RT_BIT(6)
153/** Flag whether the TPM supports the command ready interrupt. */
154# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_CMD_RDY RT_BIT(7)
155/** Flag whether the busrt count field is static or dynamic. */
156# define TPM_FIFO_LOCALITY_REG_IF_CAP_BURST_CNT_STATIC RT_BIT(8)
157/** Maximum transfer size support. */
158# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_MASK 0x600
159# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SHIFT 9
160# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SHIFT)
161/** Only legacy transfers supported. */
162# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_LEGACY 0x0
163/** 8B maximum transfer size. */
164# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_8B 0x1
165/** 32B maximum transfer size. */
166# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_32B 0x2
167/** 64B maximum transfer size. */
168# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_64B 0x3
169/** Interface version. */
170# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_MASK UINT32_C(0x70000000)
171# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SHIFT 28
172# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SHIFT)
173/** Interface 1.21 or ealier. */
174# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_21 0
175/** Interface 1.3. */
176# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3 2
177/** Interface 1.3 for TPM 2.0. */
178# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3_TPM2 3
179
180/** TPM status register. */
181#define TPM_FIFO_LOCALITY_REG_STS 0x18
182/** Writing a 1 forces the TPM to re-send the response. */
183# define TPM_FIFO_LOCALITY_REG_STS_RESPONSE_RETRY RT_BIT_32(1)
184/** Indicating whether the TPM has finished a self test. */
185# define TPM_FIFO_LOCALITY_REG_STS_SELF_TEST_DONE RT_BIT_32(2)
186/** Flag indicating whether the TPM expects more data for the command. */
187# define TPM_FIFO_LOCALITY_REG_STS_EXPECT RT_BIT_32(3)
188/** Flag indicating whether the TPM has more response data available. */
189# define TPM_FIFO_LOCALITY_REG_STS_DATA_AVAIL RT_BIT_32(4)
190/** Written by software to cause the TPM to execute a previously transfered command. */
191# define TPM_FIFO_LOCALITY_REG_STS_TPM_GO RT_BIT_32(5)
192/** On reads indicates whether the TPM is ready to receive a new command (1) or not (0),
193 * a write of 1 causes the TPM to transition to this state. */
194# define TPM_FIFO_LOCALITY_REG_STS_CMD_RDY RT_BIT_32(6)
195/** Indicates whether the Expect and data available bits are valid. */
196# define TPM_FIFO_LOCALITY_REG_STS_VALID RT_BIT_32(7)
197/** Sets the burst count. */
198# define TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_MASK UINT32_C(0xffff00)
199# define TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_SHIFT UINT32_C(8)
200# define TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_SHIFT)
201/** Cancels the active command. */
202# define TPM_FIFO_LOCALITY_REG_STS_CMD_CANCEL RT_BIT_32(24)
203/** Reset establishment bit. */
204# define TPM_FIFO_LOCALITY_REG_STS_RST_ESTABLISHMENT RT_BIT_32(25)
205/** Sets the TPM family. */
206# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_MASK UINT32_C(0x0c000000)
207# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_SHIFT UINT32_C(26)
208# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_SHIFT)
209# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_1_2 UINT32_C(0)
210# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_2_0 UINT32_C(1)
211
212
213/** TPM end of HASH operation signal register for locality 4. */
214#define TPM_FIFO_LOCALITY_REG_HASH_END 0x20
215/** Data FIFO read/write register. */
216#define TPM_FIFO_LOCALITY_REG_DATA_FIFO 0x24
217/** TPM start of HASH operation signal register for locality 4. */
218#define TPM_FIFO_LOCALITY_REG_HASH_START 0x28
219
220/** Locality interface ID register. */
221#define TPM_FIFO_LOCALITY_REG_INTF_ID 0x30
222/** Interface type field. */
223# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_MASK UINT32_C(0xf)
224# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SHIFT 0
225# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SHIFT)
226/** FIFO interface as defined in PTP for TPM 2.0 is active. */
227# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_FIFO_TPM20 0x0
228/** CRB interface is active. */
229# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_CRB 0x1
230/** FIFO interface as defined in TIS 1.3 is active. */
231# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_TIS1_3 0xf
232/** Interface type field. */
233# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_MASK UINT32_C(0xf)
234# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_SHIFT 4
235# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_SHIFT)
236/** FIFO interface for TPM 2.0 */
237# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_FIFO 0
238/** CRB interface version 0. */
239# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_CRB 1
240/** Only locality 0 is supported when clear, set if 5 localities are supported. */
241# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_LOCALITY RT_BIT(8)
242/** Maximum transfer size support. */
243# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_MASK 0x1800
244# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SHIFT 11
245# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SHIFT)
246/** Only legacy transfers supported. */
247# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_LEGACY 0x0
248/** 8B maximum transfer size. */
249# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_8B 0x1
250/** 32B maximum transfer size. */
251# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_32B 0x2
252/** 64B maximum transfer size. */
253# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_64B 0x3
254/** FIFO interface is supported and may be selected. */
255# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_FIFO RT_BIT(13)
256/** CRB interface is supported and may be selected. */
257# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_CRB RT_BIT(14)
258/** Interrupt polarity configuration. */
259# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_MASK 0x60000
260# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT 17
261# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT)
262# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_GET(a) (((a) & TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_MASK) >> TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT)
263/** Selects the FIFO interface, takes effect on next _TPM_INIT. */
264# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_FIFO 0
265/** Selects the CRB interface, takes effect on next _TPM_INIT. */
266# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_CRB 1
267/** Locks the interface selector field and prevents further changes. */
268# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_LOCK RT_BIT(19)
269
270
271/** Extended data FIFO read/write register. */
272#define TPM_FIFO_LOCALITY_REG_XDATA_FIFO 0x80
273/** TPM device and vendor ID. */
274#define TPM_FIFO_LOCALITY_REG_DID_VID 0xf00
275/** TPM revision ID. */
276#define TPM_FIFO_LOCALITY_REG_RID 0xf04
277/** @} */
278
279
280/** @name TPM locality register related defines for the CRB interface.
281 * @{ */
282/** Locality state register. */
283#define TPM_CRB_LOCALITY_REG_STATE 0x00
284/** Indicates whether a dynamic OS has been established on this platform before.. */
285# define TPM_CRB_LOCALITY_REG_ESTABLISHMENT RT_BIT(0)
286/** Flag whether the host has a locality assigned (1) or not (0). */
287# define TPM_CRB_LOCALITY_REG_STATE_LOC_ASSIGNED RT_BIT(1)
288/** Indicates the currently active locality. */
289# define TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_MASK UINT32_C(0x1c)
290# define TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SHIFT 2
291# define TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SET(a) ((a) << TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SHIFT)
292/** Flag whether the register contains valid values. */
293# define TPM_CRB_LOCALITY_REG_STATE_VALID RT_BIT(7)
294
295/** Locality control register. */
296#define TPM_CRB_LOCALITY_REG_CTRL 0x08
297/** Request TPM access from this locality. */
298# define TPM_CRB_LOCALITY_REG_CTRL_REQ_ACCESS RT_BIT(0)
299/** Release TPM access from this locality. */
300# define TPM_CRB_LOCALITY_REG_CTRL_RELINQUISH RT_BIT(1)
301/** Seize TPM access in favor of this locality if it has a higher priority. */
302# define TPM_CRB_LOCALITY_REG_CTRL_SEIZE RT_BIT(2)
303/** Resets the established bit if written from locality 3 or 4. */
304# define TPM_CRB_LOCALITY_REG_CTRL_RST_ESTABLISHMENT RT_BIT(3)
305
306/** Locality status register. */
307#define TPM_CRB_LOCALITY_REG_STS 0x0c
308/** Locality has been granted access to the TPM. */
309# define TPM_CRB_LOCALITY_REG_STS_GRANTED RT_BIT(0)
310/** A higher locality has seized the TPM from this locality. */
311# define TPM_CRB_LOCALITY_REG_STS_SEIZED RT_BIT(1)
312
313/** Locality interface ID register. */
314#define TPM_CRB_LOCALITY_REG_INTF_ID 0x30
315/** Interface type field. */
316# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_MASK UINT32_C(0xf)
317# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_SHIFT 0
318# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_SET(a) ((a) << TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_SHIFT)
319/** FIFO interface as defined in PTP for TPM 2.0 is active. */
320# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_FIFO_TPM20 0x0
321/** CRB interface is active. */
322# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_CRB 0x1
323/** FIFO interface as defined in TIS 1.3 is active. */
324# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_TIS1_3 0xf
325/** Interface type field. */
326# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_MASK UINT32_C(0xf)
327# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_SHIFT 4
328# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_SET(a) ((a) << TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_SHIFT)
329/** FIFO interface for TPM 2.0 */
330# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_FIFO 0
331/** CRB interface version 0. */
332# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_CRB 1
333/** Only locality 0 is supported when clear, set if 5 localities are supported. */
334# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_LOCALITY RT_BIT(8)
335/** @todo TPM supports ... */
336# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_CRB_IDLE_BYPASS RT_BIT(9)
337/** Maximum transfer size support. */
338# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_MASK 0x1800
339# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SHIFT 11
340# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SET(a) ((a) << TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SHIFT)
341/** Only legacy transfers supported. */
342# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_LEGACY 0x0
343/** 8B maximum transfer size. */
344# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_8B 0x1
345/** 32B maximum transfer size. */
346# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_32B 0x2
347/** 64B maximum transfer size. */
348# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_64B 0x3
349/** FIFO interface is supported and may be selected. */
350# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_FIFO RT_BIT(13)
351/** CRB interface is supported and may be selected. */
352# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_CRB RT_BIT(14)
353/** Interrupt polarity configuration. */
354# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_MASK 0x60000
355# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT 17
356# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_SET(a) ((a) << TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT)
357# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_GET(a) (((a) & TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_MASK) >> TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT)
358/** Selects the FIFO interface, takes effect on next _TPM_INIT. */
359# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_FIFO 0
360/** Selects the CRB interface, takes effect on next _TPM_INIT. */
361# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_CRB 1
362/** Locks the interface selector field and prevents further changes. */
363# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_LOCK RT_BIT(19)
364/** Revision ID field. */
365# define TPM_CRB_LOCALITY_REG_INTF_ID_RID_SHIFT 17
366# define TPM_CRB_LOCALITY_REG_INTF_ID_RID_SET(a) ((uint64_t)(a) << TPM_CRB_LOCALITY_REG_INTF_ID_RID_SHIFT)
367/** Vendor ID field. */
368# define TPM_CRB_LOCALITY_REG_INTF_ID_VID_SHIFT 32
369# define TPM_CRB_LOCALITY_REG_INTF_ID_VID_SET(a) ((uint64_t)(a) << TPM_CRB_LOCALITY_REG_INTF_ID_VID_SHIFT)
370/** Device ID field. */
371# define TPM_CRB_LOCALITY_REG_INTF_ID_DID_SHIFT 48
372# define TPM_CRB_LOCALITY_REG_INTF_ID_DID_SET(a) ((uint64_t)(a) << TPM_CRB_LOCALITY_REG_INTF_ID_DID_SHIFT)
373
374/** Locality CRB extension register (optional and locality 0 only). */
375#define TPM_CRB_LOCALITY_REG_CTRL_EXT 0x38
376
377/** Locality CRB request register. */
378#define TPM_CRB_LOCALITY_REG_CTRL_REQ 0x40
379/** The TPM should transition to the ready state to receive a new command. */
380# define TPM_CRB_LOCALITY_REG_CTRL_REQ_CMD_RDY RT_BIT(0)
381/** The TPM should transition to the idle state. */
382# define TPM_CRB_LOCALITY_REG_CTRL_REQ_IDLE RT_BIT(1)
383
384/** Locality CRB status register. */
385#define TPM_CRB_LOCALITY_REG_CTRL_STS 0x44
386/** This bit indicates that the TPM ran into a fatal error if set. */
387# define TPM_CRB_LOCALITY_REG_CTRL_STS_TPM_FATAL_ERR RT_BIT(0)
388/** This bit indicates that the TPM is in the idle state. */
389# define TPM_CRB_LOCALITY_REG_CTRL_STS_TPM_IDLE RT_BIT(1)
390
391/** Locality CRB cancel register. */
392#define TPM_CRB_LOCALITY_REG_CTRL_CANCEL 0x48
393/** Locality CRB start register. */
394#define TPM_CRB_LOCALITY_REG_CTRL_START 0x4c
395
396/** Locality interrupt enable register. */
397#define TPM_CRB_LOCALITY_REG_INT_ENABLE 0x50
398/** Enable the "TPM has executed a reqeust and response is available" interrupt. */
399# define TPM_CRB_LOCALITY_REG_INT_ENABLE_START RT_BIT(0)
400/** Enable the "TPM has transitioned to the command ready state" interrupt. */
401# define TPM_CRB_LOCALITY_REG_INT_CMD_RDY RT_BIT(1)
402/** Enable the "TPM has cleared the establishment flag" interrupt. */
403# define TPM_CRB_LOCALITY_REG_INT_ESTABLISHMENT_CLR RT_BIT(2)
404/** Enable the "active locality has changed" interrupt. */
405# define TPM_CRB_LOCALITY_REG_INT_LOC_CHANGED RT_BIT(3)
406/** Enables interrupts globally as defined by the individual bits in this register. */
407# define TPM_CRB_LOCALITY_REG_INT_GLOBAL_ENABLE RT_BIT(31)
408
409/** Locality interrupt status register. */
410#define TPM_CRB_LOCALITY_REG_INT_STS 0x54
411/** Indicates that the TPM as executed a command and the response is available for reading, writing a 1 clears the bit. */
412# define TPM_CRB_LOCALITY_REG_INT_STS_START RT_BIT(0)
413/** Indicates that the TPM has finished the transition to the ready state, writing a 1 clears this bit. */
414# define TPM_CRB_LOCALITY_REG_INT_STS_CMD_RDY RT_BIT(1)
415/** Indicates that the TPM has cleared the establishment flag, writing a 1 clears this bit. */
416# define TPM_CRB_LOCALITY_REG_INT_STS_ESTABLISHMENT_CLR RT_BIT(2)
417/** Indicates that a locality change has occurrec, writing a 1 clears this bit. */
418# define TPM_CRB_LOCALITY_REG_INT_STS_LOC_CHANGED RT_BIT(3)
419
420/** Locality command buffer size register. */
421#define TPM_CRB_LOCALITY_REG_CTRL_CMD_SZ 0x58
422/** Locality command buffer low address register. */
423#define TPM_CRB_LOCALITY_REG_CTRL_CMD_LADDR 0x5c
424/** Locality command buffer low address register. */
425#define TPM_CRB_LOCALITY_REG_CTRL_CMD_HADDR 0x60
426/** Locality response buffer size register. */
427#define TPM_CRB_LOCALITY_REG_CTRL_RSP_SZ 0x64
428/** Locality response buffer address register. */
429#define TPM_CRB_LOCALITY_REG_CTRL_RSP_ADDR 0x68
430/** Locality data buffer. */
431#define TPM_CRB_LOCALITY_REG_DATA_BUFFER 0x80
432/** @} */
433
434
435/*********************************************************************************************************************************
436* Structures and Typedefs *
437*********************************************************************************************************************************/
438
439/**
440 * Possible TPM states
441 * (see chapter 5.6.12.1 Figure 3 State Transition Diagram).
442 */
443typedef enum DEVTPMSTATE
444{
445 /** Invalid state, do not use. */
446 DEVTPMSTATE_INVALID = 0,
447 /** Idle state. */
448 DEVTPMSTATE_IDLE,
449 /** Ready to accept command data. */
450 DEVTPMSTATE_READY,
451 /** Command data being transfered. */
452 DEVTPMSTATE_CMD_RECEPTION,
453 /** Command is being executed by the TPM. */
454 DEVTPMSTATE_CMD_EXEC,
455 /** Command has completed and data can be read. */
456 DEVTPMSTATE_CMD_COMPLETION,
457 /** Command is being canceled. */
458 DEVTPMSTATE_CMD_CANCEL,
459 /** TPM ran into a fatal error and is not operational. */
460 DEVTPMSTATE_FATAL_ERROR,
461 /** Last valid state (used for saved state sanity check). */
462 DEVTPMSTATE_LAST_VALID = DEVTPMSTATE_FATAL_ERROR,
463 /** 32bit hack. */
464 DEVTPMSTATE_32BIT_HACK = 0x7fffffff
465} DEVTPMSTATE;
466
467
468/**
469 * Locality state.
470 */
471typedef struct DEVTPMLOCALITY
472{
473 /** The interrupt enable register. */
474 uint32_t uRegIntEn;
475 /** The interrupt status register. */
476 uint32_t uRegIntSts;
477} DEVTPMLOCALITY;
478/** Pointer to a locality state. */
479typedef DEVTPMLOCALITY *PDEVTPMLOCALITY;
480/** Pointer to a const locality state. */
481typedef const DEVTPMLOCALITY *PCDEVTPMLOCALITY;
482
483
484/**
485 * Shared TPM device state.
486 */
487typedef struct DEVTPM
488{
489 /** Base MMIO address of the TPM device. */
490 RTGCPHYS GCPhysMmio;
491 /** The handle of the MMIO region. */
492 IOMMMIOHANDLE hMmio;
493 /** The handle for the ring-3 task. */
494 PDMTASKHANDLE hTpmCmdTask;
495 /** The vendor ID configured. */
496 uint16_t uVenId;
497 /** The device ID configured. */
498 uint16_t uDevId;
499 /** The revision ID configured. */
500 uint8_t bRevId;
501 /** The IRQ value. */
502 uint8_t uIrq;
503 /** Flag whether CRB access mode is used. */
504 bool fCrb;
505 /** Flag whether the TPM driver below supportes other localities than 0. */
506 bool fLocChangeSup;
507 /** Flag whether the establishment bit is set. */
508 bool fEstablishmentSet;
509
510 /** Currently selected locality. */
511 uint8_t bLoc;
512 /** States of the implemented localities. */
513 DEVTPMLOCALITY aLoc[TPM_LOCALITY_COUNT];
514 /** Bitmask of localities having requested access to the TPM. */
515 uint32_t bmLocReqAcc;
516 /** Bitmask of localities having been seized access from the TPM. */
517 uint32_t bmLocSeizedAcc;
518 /** The current state of the TPM. */
519 DEVTPMSTATE enmState;
520 /** The TPM version being emulated. */
521 TPMVERSION enmTpmVers;
522
523 /** Size of the command/response buffer. */
524 uint32_t cbCmdResp;
525 /** Offset into the Command/Response buffer. */
526 uint32_t offCmdResp;
527 /** Command/Response buffer. */
528 uint8_t abCmdResp[TPM_DATA_BUFFER_SIZE_MAX];
529} DEVTPM;
530/** Pointer to the shared TPM device state. */
531typedef DEVTPM *PDEVTPM;
532
533/** The special no current locality selected value. */
534#define TPM_NO_LOCALITY_SELECTED 0xff
535
536
537/**
538 * TPM device state for ring-3.
539 */
540typedef struct DEVTPMR3
541{
542 /** Pointer to the device instance. */
543 PPDMDEVINS pDevIns;
544 /** The base interface for LUN\#0. */
545 PDMIBASE IBase;
546 /** The base interface for LUN\#0. */
547 PDMITPMPORT ITpmPort;
548 /** The base interface below. */
549 R3PTRTYPE(PPDMIBASE) pDrvBase;
550 /** The TPM connector interface below. */
551 R3PTRTYPE(PPDMITPMCONNECTOR) pDrvTpm;
552} DEVTPMR3;
553/** Pointer to the TPM device state for ring-3. */
554typedef DEVTPMR3 *PDEVTPMR3;
555
556
557/**
558 * TPM device state for ring-0.
559 */
560typedef struct DEVTPMR0
561{
562 uint32_t u32Dummy;
563} DEVTPMR0;
564/** Pointer to the TPM device state for ring-0. */
565typedef DEVTPMR0 *PDEVTPMR0;
566
567
568/**
569 * TPM device state for raw-mode.
570 */
571typedef struct DEVTPMRC
572{
573 uint32_t u32Dummy;
574} DEVTPMRC;
575/** Pointer to the TPM device state for raw-mode. */
576typedef DEVTPMRC *PDEVTPMRC;
577
578/** The TPM device state for the current context. */
579typedef CTX_SUFF(DEVTPM) DEVTPMCC;
580/** Pointer to the TPM device state for the current context. */
581typedef CTX_SUFF(PDEVTPM) PDEVTPMCC;
582
583
584#ifndef VBOX_DEVICE_STRUCT_TESTCASE
585
586
587/*********************************************************************************************************************************
588* Global Variables *
589*********************************************************************************************************************************/
590#ifdef IN_RING3
591/**
592 * SSM descriptor table for the TPM structure.
593 */
594static SSMFIELD const g_aTpmFields[] =
595{
596 SSMFIELD_ENTRY(DEVTPM, fEstablishmentSet),
597 SSMFIELD_ENTRY(DEVTPM, bLoc),
598 SSMFIELD_ENTRY(DEVTPM, aLoc[0].uRegIntEn),
599 SSMFIELD_ENTRY(DEVTPM, aLoc[0].uRegIntSts),
600 SSMFIELD_ENTRY(DEVTPM, aLoc[1].uRegIntEn),
601 SSMFIELD_ENTRY(DEVTPM, aLoc[1].uRegIntSts),
602 SSMFIELD_ENTRY(DEVTPM, aLoc[2].uRegIntEn),
603 SSMFIELD_ENTRY(DEVTPM, aLoc[2].uRegIntSts),
604 SSMFIELD_ENTRY(DEVTPM, aLoc[3].uRegIntEn),
605 SSMFIELD_ENTRY(DEVTPM, aLoc[3].uRegIntSts),
606 SSMFIELD_ENTRY(DEVTPM, aLoc[4].uRegIntEn),
607 SSMFIELD_ENTRY(DEVTPM, aLoc[4].uRegIntSts),
608 SSMFIELD_ENTRY(DEVTPM, bmLocReqAcc),
609 SSMFIELD_ENTRY(DEVTPM, bmLocSeizedAcc),
610 SSMFIELD_ENTRY(DEVTPM, enmState),
611 SSMFIELD_ENTRY(DEVTPM, offCmdResp),
612 SSMFIELD_ENTRY(DEVTPM, abCmdResp),
613 SSMFIELD_ENTRY_TERM()
614};
615#endif
616
617
618/**
619 * Sets the IRQ line of the given device to the given state.
620 *
621 * @param pDevIns Pointer to the PDM device instance data.
622 * @param pThis Pointer to the shared TPM device.
623 * @param iLvl The interrupt level to set.
624 */
625DECLINLINE(void) tpmIrqReq(PPDMDEVINS pDevIns, PDEVTPM pThis, int iLvl)
626{
627 PDMDevHlpISASetIrqNoWait(pDevIns, pThis->uIrq, iLvl);
628}
629
630
631/**
632 * Updates the IRQ status of the given locality.
633 *
634 * @param pDevIns Pointer to the PDM device instance data.
635 * @param pThis Pointer to the shared TPM device.
636 * @param pLoc The locality state.
637 */
638static void tpmLocIrqUpdate(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc)
639{
640 if ( (pLoc->uRegIntEn & TPM_CRB_LOCALITY_REG_INT_GLOBAL_ENABLE) /* Aliases with TPM_FIFO_LOCALITY_REG_INT_ENABLE_GLOBAL */
641 && (pLoc->uRegIntEn & pLoc->uRegIntSts))
642 tpmIrqReq(pDevIns, pThis, 1);
643 else
644 tpmIrqReq(pDevIns, pThis, 0);
645}
646
647
648/**
649 * Sets the interrupt status for the given locality, firing an interrupt if necessary.
650 *
651 * @param pDevIns Pointer to the PDM device instance data.
652 * @param pThis Pointer to the shared TPM device.
653 * @param pLoc The locality state.
654 * @param uSts The interrupt status bit to set.
655 */
656static void tpmLocSetIntSts(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc, uint32_t uSts)
657{
658 pLoc->uRegIntSts |= uSts;
659 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
660}
661
662
663/**
664 * Selects the next locality which has requested access.
665 *
666 * @param pDevIns Pointer to the PDM device instance data.
667 * @param pThis Pointer to the shared TPM device.
668 */
669static void tpmLocSelectNext(PPDMDEVINS pDevIns, PDEVTPM pThis)
670{
671 Assert(pThis->bmLocReqAcc);
672 Assert(pThis->bLoc == TPM_NO_LOCALITY_SELECTED);
673 pThis->bLoc = (uint8_t)ASMBitLastSetU32(pThis->bmLocReqAcc) - 1; /* Select one with highest priority. */
674
675 tpmLocSetIntSts(pDevIns, pThis, &pThis->aLoc[pThis->bLoc], TPM_CRB_LOCALITY_REG_INT_STS_LOC_CHANGED);
676}
677
678
679/**
680 * Returns the given locality being accessed from the given TPM MMIO offset.
681 *
682 * @returns Locality number.
683 * @param off The offset into the TPM MMIO region.
684 */
685DECLINLINE(uint8_t) tpmGetLocalityFromOffset(RTGCPHYS off)
686{
687 return off / TPM_LOCALITY_MMIO_SIZE;
688}
689
690
691/**
692 * Returns the given register of a particular locality being accessed from the given TPM MMIO offset.
693 *
694 * @returns Register index being accessed.
695 * @param off The offset into the TPM MMIO region.
696 */
697DECLINLINE(uint32_t) tpmGetRegisterFromOffset(RTGCPHYS off)
698{
699 return off % TPM_LOCALITY_MMIO_SIZE;
700}
701
702
703/**
704 * Read from a FIFO interface register.
705 *
706 * @returns VBox strict status code.
707 * @param pDevIns Pointer to the PDM device instance data.
708 * @param pThis Pointer to the shared TPM device.
709 * @param pLoc The locality state being read from.
710 * @param bLoc The locality index.
711 * @param uReg The register offset being accessed.
712 * @param pu64 Where to store the read data.
713 * @param cb Number of bytes to read.
714 */
715static VBOXSTRICTRC tpmMmioFifoRead(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc,
716 uint8_t bLoc, uint32_t uReg, uint64_t *pu64, size_t cb)
717{
718 RT_NOREF(pDevIns);
719 VBOXSTRICTRC rc = VINF_SUCCESS;
720
721 /* Special path for the data buffer. */
722 if ( ( ( uReg >= TPM_FIFO_LOCALITY_REG_DATA_FIFO
723 && uReg < TPM_FIFO_LOCALITY_REG_DATA_FIFO + sizeof(uint32_t))
724 || ( uReg >= TPM_FIFO_LOCALITY_REG_XDATA_FIFO
725 && uReg < TPM_FIFO_LOCALITY_REG_XDATA_FIFO + sizeof(uint32_t)))
726 && bLoc == pThis->bLoc
727 && pThis->enmState == DEVTPMSTATE_CMD_COMPLETION)
728 {
729 if (pThis->offCmdResp <= pThis->cbCmdResp - cb)
730 {
731 memcpy(pu64, &pThis->abCmdResp[pThis->offCmdResp], cb);
732 pThis->offCmdResp += (uint32_t)cb;
733 }
734 else
735 memset(pu64, 0xff, cb);
736 return VINF_SUCCESS;
737 }
738
739 uint64_t u64;
740 switch (uReg)
741 {
742 case TPM_FIFO_LOCALITY_REG_ACCESS:
743 u64 = TPM_FIFO_LOCALITY_REG_ACCESS_VALID;
744 if (pThis->bLoc == bLoc)
745 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_ACTIVE;
746 if (pThis->bmLocSeizedAcc & RT_BIT_32(bLoc))
747 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_BEEN_SEIZED;
748 if (pThis->bmLocReqAcc & ~RT_BIT_32(bLoc))
749 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_PENDING_REQUEST;
750 if ( pThis->bLoc != bLoc
751 && pThis->bmLocReqAcc & RT_BIT_32(bLoc))
752 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_REQUEST_USE;
753 if (pThis->fEstablishmentSet)
754 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_ESTABLISHMENT;
755 break;
756 case TPM_FIFO_LOCALITY_REG_INT_ENABLE:
757 u64 = pLoc->uRegIntEn;
758 break;
759 case TPM_FIFO_LOCALITY_REG_INT_VEC:
760 u64 = pThis->uIrq;
761 break;
762 case TPM_FIFO_LOCALITY_REG_INT_STS:
763 u64 = pLoc->uRegIntSts;
764 break;
765 case TPM_FIFO_LOCALITY_REG_IF_CAP:
766 u64 = TPM_FIFO_LOCALITY_REG_IF_CAP_INT_DATA_AVAIL
767 | TPM_FIFO_LOCALITY_REG_IF_CAP_INT_STS_VALID
768 | TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LOCALITY_CHANGE
769 | TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LVL_LOW
770 | TPM_FIFO_LOCALITY_REG_IF_CAP_INT_CMD_RDY
771 | TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SET(TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_64B); /** @todo Make some of them configurable? */
772 if (pThis->enmTpmVers == TPMVERSION_1_2)
773 u64 |= TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SET(TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3);
774 else
775 u64 |= TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SET(TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3_TPM2);
776 break;
777 case TPM_FIFO_LOCALITY_REG_STS:
778 if (bLoc != pThis->bLoc)
779 {
780 u64 = UINT64_MAX;
781 break;
782 }
783
784 u64 = TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_SET( pThis->enmTpmVers == TPMVERSION_1_2
785 ? TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_1_2
786 : TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_2_0)
787 | TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_SET(_1K)
788 | TPM_FIFO_LOCALITY_REG_STS_VALID;
789 if (pThis->enmState == DEVTPMSTATE_READY)
790 u64 |= TPM_FIFO_LOCALITY_REG_STS_CMD_RDY;
791 else if (pThis->enmState == DEVTPMSTATE_CMD_RECEPTION) /* When in the command reception state check whether all of the command data has been received. */
792 {
793 if ( pThis->offCmdResp < sizeof(TPMREQHDR)
794 || pThis->offCmdResp < RTTpmReqGetSz((PCTPMREQHDR)&pThis->abCmdResp[0]))
795 u64 |= TPM_FIFO_LOCALITY_REG_STS_EXPECT;
796 }
797 else if (pThis->enmState == DEVTPMSTATE_CMD_COMPLETION) /* Check whether there is more response data available. */
798 {
799 if (pThis->offCmdResp < RTTpmRespGetSz((PCTPMRESPHDR)&pThis->abCmdResp[0]))
800 u64 |= TPM_FIFO_LOCALITY_REG_STS_DATA_AVAIL;
801 }
802 break;
803 case TPM_FIFO_LOCALITY_REG_INTF_ID:
804 u64 = TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_SET(TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_FIFO)
805 | TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SET(TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_64B)
806 | TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_GET(TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_FIFO)
807 | TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_LOCK
808 | TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_FIFO;
809 if (pThis->enmTpmVers == TPMVERSION_1_2)
810 u64 |= TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SET(TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_TIS1_3);
811 else
812 u64 |= TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SET(TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_FIFO_TPM20);
813
814 if (pThis->fLocChangeSup) /* Only advertise the locality capability if the driver below supports it. */
815 u64 |= TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_LOCALITY;
816 break;
817 case TPM_FIFO_LOCALITY_REG_DID_VID:
818 u64 = RT_H2BE_U32(RT_MAKE_U32(pThis->uVenId, pThis->uDevId));
819 break;
820 case TPM_FIFO_LOCALITY_REG_RID:
821 u64 = pThis->bRevId;
822 break;
823 default: /* Return ~0. */
824 u64 = UINT64_MAX;
825 break;
826 }
827
828 *pu64 = u64;
829
830 return rc;
831}
832
833
834/**
835 * Read to a FIFO interface register.
836 *
837 * @returns VBox strict status code.
838 * @param pDevIns Pointer to the PDM device instance data.
839 * @param pThis Pointer to the shared TPM device.
840 * @param pLoc The locality state being written to.
841 * @param bLoc The locality index.
842 * @param uReg The register offset being accessed.
843 * @param u64 The value to write.
844 * @param cb Number of bytes to write.
845 */
846static VBOXSTRICTRC tpmMmioFifoWrite(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc,
847 uint8_t bLoc, uint32_t uReg, uint64_t u64, size_t cb)
848{
849#ifdef IN_RING3
850 PDEVTPMR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMR3);
851#endif
852
853 /* Special path for the data buffer. */
854 if ( ( ( uReg >= TPM_FIFO_LOCALITY_REG_DATA_FIFO
855 && uReg < TPM_FIFO_LOCALITY_REG_DATA_FIFO + sizeof(uint32_t))
856 || ( uReg >= TPM_FIFO_LOCALITY_REG_XDATA_FIFO
857 && uReg < TPM_FIFO_LOCALITY_REG_XDATA_FIFO + sizeof(uint32_t)))
858 && bLoc == pThis->bLoc
859 && ( pThis->enmState == DEVTPMSTATE_READY
860 || pThis->enmState == DEVTPMSTATE_CMD_RECEPTION))
861 {
862 pThis->enmState = DEVTPMSTATE_CMD_RECEPTION;
863 if (pThis->offCmdResp <= pThis->cbCmdResp - cb)
864 {
865 memcpy(&pThis->abCmdResp[pThis->offCmdResp], &u64, cb);
866 pThis->offCmdResp += (uint32_t)cb;
867 }
868 return VINF_SUCCESS;
869 }
870
871 VBOXSTRICTRC rc = VINF_SUCCESS;
872 uint32_t u32 = (uint32_t)u64;
873
874 switch (uReg)
875 {
876 case TPM_FIFO_LOCALITY_REG_ACCESS:
877 u32 &= TPM_FIFO_LOCALITY_REG_ACCESS_WR_MASK;
878 /*
879 * Chapter 5.6.11, 2 states that writing to this register with more than one
880 * bit set to '1' is vendor specific, we decide to ignore such writes to make the logic
881 * below simpler.
882 */
883 if (!RT_IS_POWER_OF_TWO(u32))
884 break;
885
886 /* Seize access only if this locality has a higher priority than the currently selected one. */
887 if ( (u32 & TPM_FIFO_LOCALITY_REG_ACCESS_SEIZE)
888 && pThis->bLoc != TPM_NO_LOCALITY_SELECTED
889 && bLoc > pThis->bLoc)
890 {
891 pThis->bmLocSeizedAcc |= RT_BIT_32(pThis->bLoc);
892 /** @todo Abort command. */
893 pThis->bLoc = bLoc;
894 }
895
896 if ( (u64 & TPM_FIFO_LOCALITY_REG_ACCESS_REQUEST_USE)
897 && !(pThis->bmLocReqAcc & RT_BIT_32(bLoc)))
898 {
899 pThis->bmLocReqAcc |= RT_BIT_32(bLoc);
900 if (pThis->bLoc == TPM_NO_LOCALITY_SELECTED)
901 {
902 pThis->bLoc = bLoc; /* Doesn't fire an interrupt. */
903 pThis->bmLocSeizedAcc &= ~RT_BIT_32(bLoc);
904 }
905 }
906
907 if ( (u64 & TPM_FIFO_LOCALITY_REG_ACCESS_ACTIVE)
908 && (pThis->bmLocReqAcc & RT_BIT_32(bLoc)))
909 {
910 pThis->bmLocReqAcc &= ~RT_BIT_32(bLoc);
911 if (pThis->bLoc == bLoc)
912 {
913 pThis->bLoc = TPM_NO_LOCALITY_SELECTED;
914 if (pThis->bmLocReqAcc)
915 tpmLocSelectNext(pDevIns, pThis); /* Select the next locality. */
916 }
917 }
918 break;
919 case TPM_FIFO_LOCALITY_REG_INT_ENABLE:
920 if (bLoc != pThis->bLoc)
921 break;
922 pLoc->uRegIntEn = u32;
923 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
924 break;
925 case TPM_FIFO_LOCALITY_REG_INT_STS:
926 if (bLoc != pThis->bLoc)
927 break;
928 pLoc->uRegIntSts &= ~(u32 & TPM_FIFO_LOCALITY_REG_INT_STS_WR_MASK);
929 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
930 break;
931 case TPM_FIFO_LOCALITY_REG_STS:
932 /*
933 * Writes are ignored completely if the locality being accessed is not the
934 * current active one or if the value has multiple bits set (not a power of two),
935 * see chapter 5.6.12.1.
936 */
937 if ( bLoc != pThis->bLoc
938 || !RT_IS_POWER_OF_TWO(u64))
939 break;
940
941 if ( (u64 & TPM_FIFO_LOCALITY_REG_STS_CMD_RDY)
942 && ( pThis->enmState == DEVTPMSTATE_IDLE
943 || pThis->enmState == DEVTPMSTATE_CMD_COMPLETION))
944 {
945 pThis->enmState = DEVTPMSTATE_READY;
946 pThis->offCmdResp = 0;
947 tpmLocSetIntSts(pDevIns, pThis, pLoc, TPM_FIFO_LOCALITY_REG_INT_STS_CMD_RDY);
948 }
949
950 if ( (u64 & TPM_FIFO_LOCALITY_REG_STS_TPM_GO)
951 && pThis->enmState == DEVTPMSTATE_CMD_RECEPTION)
952 {
953 pThis->enmState = DEVTPMSTATE_CMD_EXEC;
954 rc = PDMDevHlpTaskTrigger(pDevIns, pThis->hTpmCmdTask);
955 }
956
957 if ( (u64 & TPM_FIFO_LOCALITY_REG_STS_RST_ESTABLISHMENT)
958 && pThis->bLoc >= 3
959 && ( pThis->enmState == DEVTPMSTATE_IDLE
960 || pThis->enmState == DEVTPMSTATE_CMD_COMPLETION))
961 {
962#ifndef IN_RING3
963 rc = VINF_IOM_R3_MMIO_WRITE;
964 break;
965#else
966 if (pThisCC->pDrvTpm)
967 {
968 int rc2 = pThisCC->pDrvTpm->pfnResetEstablishedFlag(pThisCC->pDrvTpm, pThis->bLoc);
969 if (RT_SUCCESS(rc2))
970 pThis->fEstablishmentSet = false;
971 else
972 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
973 }
974 else
975 pThis->fEstablishmentSet = false;
976#endif
977 }
978
979 if ( (u64 & TPM_FIFO_LOCALITY_REG_STS_CMD_CANCEL)
980 && pThis->enmState == DEVTPMSTATE_CMD_EXEC)
981 {
982#ifndef IN_RING3
983 rc = VINF_IOM_R3_MMIO_WRITE;
984 break;
985#else
986 if (pThisCC->pDrvTpm)
987 {
988 pThis->enmState = DEVTPMSTATE_CMD_CANCEL;
989 int rc2 = pThisCC->pDrvTpm->pfnCmdCancel(pThisCC->pDrvTpm);
990 if (RT_FAILURE(rc2))
991 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
992 }
993#endif
994 }
995
996 break;
997 case TPM_FIFO_LOCALITY_REG_INT_VEC:
998 case TPM_FIFO_LOCALITY_REG_IF_CAP:
999 case TPM_FIFO_LOCALITY_REG_DID_VID:
1000 case TPM_FIFO_LOCALITY_REG_RID:
1001 default: /* Ignore. */
1002 break;
1003 }
1004
1005 return rc;
1006}
1007
1008
1009/**
1010 * Read from a CRB interface register.
1011 *
1012 * @returns VBox strict status code.
1013 * @param pDevIns Pointer to the PDM device instance data.
1014 * @param pThis Pointer to the shared TPM device.
1015 * @param pLoc The locality state being read from.
1016 * @param bLoc The locality index.
1017 * @param uReg The register offset being accessed.
1018 * @param pu64 Where to store the read data.
1019 * @param cb Size of the read in bytes.
1020 */
1021static VBOXSTRICTRC tpmMmioCrbRead(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc,
1022 uint8_t bLoc, uint32_t uReg, uint64_t *pu64, size_t cb)
1023{
1024 RT_NOREF(pDevIns);
1025
1026 /* Special path for the data buffer. */
1027 if ( uReg >= TPM_CRB_LOCALITY_REG_DATA_BUFFER
1028 && uReg < TPM_CRB_LOCALITY_REG_DATA_BUFFER + pThis->cbCmdResp
1029 && bLoc == pThis->bLoc
1030 && pThis->enmState == DEVTPMSTATE_CMD_COMPLETION)
1031 {
1032 memcpy(pu64, &pThis->abCmdResp[uReg - TPM_CRB_LOCALITY_REG_DATA_BUFFER], cb);
1033 return VINF_SUCCESS;
1034 }
1035
1036 VBOXSTRICTRC rc = VINF_SUCCESS;
1037 uint64_t u64 = UINT64_MAX;
1038 switch (uReg)
1039 {
1040 case TPM_CRB_LOCALITY_REG_STATE:
1041 u64 = TPM_CRB_LOCALITY_REG_STATE_VALID
1042 | ( pThis->bLoc != TPM_NO_LOCALITY_SELECTED
1043 ? TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SET(pThis->bLoc) | TPM_CRB_LOCALITY_REG_STATE_LOC_ASSIGNED
1044 : TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SET(0));
1045 if (pThis->fEstablishmentSet)
1046 u64 |= TPM_CRB_LOCALITY_REG_ESTABLISHMENT;
1047 break;
1048 case TPM_CRB_LOCALITY_REG_STS:
1049 u64 = pThis->bLoc == bLoc
1050 ? TPM_CRB_LOCALITY_REG_STS_GRANTED
1051 : 0;
1052 u64 |= pThis->bmLocSeizedAcc & RT_BIT_32(bLoc)
1053 ? TPM_CRB_LOCALITY_REG_STS_SEIZED
1054 : 0;
1055 break;
1056 case TPM_CRB_LOCALITY_REG_INTF_ID:
1057 u64 = TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_SET(TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_CRB)
1058 | TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_SET(TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_CRB)
1059 | TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SET(TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_64B)
1060 | TPM_CRB_LOCALITY_REG_INTF_ID_CAP_CRB
1061 | TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_GET(TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_CRB)
1062 | TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_LOCK
1063 | TPM_CRB_LOCALITY_REG_INTF_ID_RID_SET(pThis->bRevId)
1064 | TPM_CRB_LOCALITY_REG_INTF_ID_VID_SET(pThis->uVenId)
1065 | TPM_CRB_LOCALITY_REG_INTF_ID_DID_SET(pThis->uDevId);
1066
1067 if (pThis->fLocChangeSup) /* Only advertise the locality capability if the driver below supports it. */
1068 u64 |= TPM_CRB_LOCALITY_REG_INTF_ID_CAP_LOCALITY;
1069
1070 break;
1071 case TPM_CRB_LOCALITY_REG_CTRL_REQ:
1072 if (bLoc != pThis->bLoc)
1073 break;
1074 /*
1075 * Command ready and go idle are always 0 upon read
1076 * as we don't need time to transition to this state
1077 * when written by the guest.
1078 */
1079 u64 = 0;
1080 break;
1081 case TPM_CRB_LOCALITY_REG_CTRL_STS:
1082 if (bLoc != pThis->bLoc)
1083 break;
1084 if (pThis->enmState == DEVTPMSTATE_FATAL_ERROR)
1085 u64 = TPM_CRB_LOCALITY_REG_CTRL_STS_TPM_FATAL_ERR;
1086 else if (pThis->enmState == DEVTPMSTATE_IDLE)
1087 u64 = TPM_CRB_LOCALITY_REG_CTRL_STS_TPM_IDLE;
1088 else
1089 u64 = 0;
1090 break;
1091 case TPM_CRB_LOCALITY_REG_CTRL_CANCEL:
1092 if (bLoc != pThis->bLoc)
1093 break;
1094 if (pThis->enmState == DEVTPMSTATE_CMD_CANCEL)
1095 u64 = 0x1;
1096 else
1097 u64 = 0;
1098 break;
1099 case TPM_CRB_LOCALITY_REG_CTRL_START:
1100 if (bLoc != pThis->bLoc)
1101 break;
1102 if (pThis->enmState == DEVTPMSTATE_CMD_EXEC)
1103 u64 = 0x1;
1104 else
1105 u64 = 0;
1106 break;
1107 case TPM_CRB_LOCALITY_REG_INT_ENABLE:
1108 u64 = pLoc->uRegIntEn;
1109 break;
1110 case TPM_CRB_LOCALITY_REG_INT_STS:
1111 u64 = pLoc->uRegIntSts;
1112 break;
1113 case TPM_CRB_LOCALITY_REG_CTRL_CMD_LADDR:
1114 u64 = pThis->GCPhysMmio + (bLoc * TPM_LOCALITY_MMIO_SIZE) + TPM_CRB_LOCALITY_REG_DATA_BUFFER;
1115 break;
1116 case TPM_CRB_LOCALITY_REG_CTRL_CMD_HADDR:
1117 u64 = (pThis->GCPhysMmio + (bLoc * TPM_LOCALITY_MMIO_SIZE) + TPM_CRB_LOCALITY_REG_DATA_BUFFER) >> 32;
1118 break;
1119 case TPM_CRB_LOCALITY_REG_CTRL_CMD_SZ:
1120 case TPM_CRB_LOCALITY_REG_CTRL_RSP_SZ:
1121 u64 = pThis->cbCmdResp;
1122 break;
1123 case TPM_CRB_LOCALITY_REG_CTRL_RSP_ADDR:
1124 u64 = pThis->GCPhysMmio + (bLoc * TPM_LOCALITY_MMIO_SIZE) + TPM_CRB_LOCALITY_REG_DATA_BUFFER;
1125 break;
1126 case TPM_CRB_LOCALITY_REG_CTRL: /* Writeonly */
1127 u64 = 0;
1128 break;
1129 case TPM_CRB_LOCALITY_REG_CTRL_EXT:
1130 default:
1131 break; /* Return ~0 */
1132 }
1133
1134 *pu64 = u64;
1135 return rc;
1136}
1137
1138
1139/**
1140 * Read to a CRB interface register.
1141 *
1142 * @returns VBox strict status code.
1143 * @param pDevIns Pointer to the PDM device instance data.
1144 * @param pThis Pointer to the shared TPM device.
1145 * @param pLoc The locality state being written to.
1146 * @param bLoc The locality index.
1147 * @param uReg The register offset being accessed.
1148 * @param u64 The value to write.
1149 * @param cb Size of the write in bytes.
1150 */
1151static VBOXSTRICTRC tpmMmioCrbWrite(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc,
1152 uint8_t bLoc, uint32_t uReg, uint64_t u64, size_t cb)
1153{
1154#ifdef IN_RING3
1155 PDEVTPMR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMR3);
1156#endif
1157
1158 VBOXSTRICTRC rc = VINF_SUCCESS;
1159 uint32_t u32 = (uint32_t)u64;
1160
1161 /* Special path for the data buffer. */
1162 if ( uReg >= TPM_CRB_LOCALITY_REG_DATA_BUFFER
1163 && uReg < TPM_CRB_LOCALITY_REG_DATA_BUFFER + pThis->cbCmdResp
1164 && bLoc == pThis->bLoc
1165 && ( pThis->enmState == DEVTPMSTATE_READY
1166 || pThis->enmState == DEVTPMSTATE_CMD_RECEPTION))
1167 {
1168 pThis->enmState = DEVTPMSTATE_CMD_RECEPTION;
1169 memcpy(&pThis->abCmdResp[uReg - TPM_CRB_LOCALITY_REG_DATA_BUFFER], &u64, cb);
1170 return VINF_SUCCESS;
1171 }
1172
1173 switch (uReg)
1174 {
1175 case TPM_CRB_LOCALITY_REG_CTRL:
1176 {
1177 /* See chapter 6.5.3.2.2.1. */
1178 if ( (u64 & TPM_CRB_LOCALITY_REG_CTRL_RST_ESTABLISHMENT)
1179 && pThis->bLoc >= 3
1180 && ( pThis->enmState == DEVTPMSTATE_IDLE
1181 || pThis->enmState == DEVTPMSTATE_CMD_COMPLETION))
1182 {
1183#ifndef IN_RING3
1184 rc = VINF_IOM_R3_MMIO_WRITE;
1185 break;
1186#else
1187 if (pThisCC->pDrvTpm)
1188 {
1189 int rc2 = pThisCC->pDrvTpm->pfnResetEstablishedFlag(pThisCC->pDrvTpm, pThis->bLoc);
1190 if (RT_SUCCESS(rc2))
1191 pThis->fEstablishmentSet = false;
1192 else
1193 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
1194 }
1195 else
1196 pThis->fEstablishmentSet = false;
1197#endif
1198 }
1199
1200 /*
1201 * The following three checks should be mutually exclusive as the writer shouldn't
1202 * request, relinquish and seize access in the same write.
1203 */
1204 /* Seize access only if this locality has a higher priority than the currently selected one. */
1205 if ( (u64 & TPM_CRB_LOCALITY_REG_CTRL_SEIZE)
1206 && pThis->bLoc != TPM_NO_LOCALITY_SELECTED
1207 && bLoc > pThis->bLoc)
1208 {
1209 if (pThis->enmState == DEVTPMSTATE_CMD_EXEC)
1210 {
1211#ifndef IN_RING3
1212 rc = VINF_IOM_R3_MMIO_WRITE;
1213 break;
1214#else
1215 pThis->enmState = DEVTPMSTATE_CMD_CANCEL;
1216 if (pThisCC->pDrvTpm)
1217 {
1218 int rc2 = pThisCC->pDrvTpm->pfnCmdCancel(pThisCC->pDrvTpm);
1219 if (RT_FAILURE(rc2))
1220 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
1221 else
1222 {
1223 pThis->enmState = DEVTPMSTATE_CMD_COMPLETION;
1224 tpmLocSetIntSts(pDevIns, pThis, pLoc, TPM_CRB_LOCALITY_REG_INT_STS_START);
1225 }
1226 }
1227#endif
1228 }
1229
1230 pThis->bmLocSeizedAcc |= RT_BIT_32(pThis->bLoc);
1231 pThis->bLoc = bLoc;
1232 }
1233
1234 if ( (u64 & TPM_CRB_LOCALITY_REG_CTRL_REQ_ACCESS)
1235 && !(pThis->bmLocReqAcc & RT_BIT_32(bLoc)))
1236 {
1237 pThis->bmLocReqAcc |= RT_BIT_32(bLoc);
1238 if (pThis->bLoc == TPM_NO_LOCALITY_SELECTED)
1239 {
1240 pThis->bLoc = bLoc; /* Doesn't fire an interrupt. */
1241 pThis->bmLocSeizedAcc &= ~RT_BIT_32(bLoc);
1242 }
1243 }
1244
1245 if ( (u64 & TPM_CRB_LOCALITY_REG_CTRL_RELINQUISH)
1246 && (pThis->bmLocReqAcc & RT_BIT_32(bLoc)))
1247 {
1248 pThis->bmLocReqAcc &= ~RT_BIT_32(bLoc);
1249 if (pThis->bLoc == bLoc)
1250 {
1251 pThis->bLoc = TPM_NO_LOCALITY_SELECTED;
1252 if (pThis->bmLocReqAcc)
1253 tpmLocSelectNext(pDevIns, pThis); /* Select the next locality. */
1254 }
1255 }
1256 break;
1257 }
1258 case TPM_CRB_LOCALITY_REG_CTRL_REQ:
1259 if ( bLoc != pThis->bLoc
1260 || !RT_IS_POWER_OF_TWO(u32)) /* Ignore if multiple bits are set. */
1261 break;
1262 if ( (u32 & TPM_CRB_LOCALITY_REG_CTRL_REQ_CMD_RDY)
1263 && ( pThis->enmState == DEVTPMSTATE_IDLE
1264 || pThis->enmState == DEVTPMSTATE_CMD_COMPLETION))
1265 {
1266 pThis->enmState = DEVTPMSTATE_READY;
1267 tpmLocSetIntSts(pDevIns, pThis, pLoc, TPM_CRB_LOCALITY_REG_INT_STS_CMD_RDY);
1268 }
1269 else if ( (u32 & TPM_CRB_LOCALITY_REG_CTRL_REQ_IDLE)
1270 && pThis->enmState != DEVTPMSTATE_CMD_EXEC)
1271 {
1272 /* Invalidate the command/response buffer. */
1273 RT_ZERO(pThis->abCmdResp);
1274 pThis->offCmdResp = 0;
1275 pThis->enmState = DEVTPMSTATE_IDLE;
1276 }
1277 break;
1278 case TPM_CRB_LOCALITY_REG_CTRL_CANCEL:
1279 if (bLoc != pThis->bLoc)
1280 break;
1281 if ( pThis->enmState == DEVTPMSTATE_CMD_EXEC
1282 && u32 == 0x1)
1283 {
1284#ifndef IN_RING3
1285 rc = VINF_IOM_R3_MMIO_WRITE;
1286 break;
1287#else
1288 pThis->enmState = DEVTPMSTATE_CMD_CANCEL;
1289 if (pThisCC->pDrvTpm)
1290 {
1291 int rc2 = pThisCC->pDrvTpm->pfnCmdCancel(pThisCC->pDrvTpm);
1292 if (RT_FAILURE(rc2))
1293 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
1294 else
1295 {
1296 pThis->enmState = DEVTPMSTATE_CMD_COMPLETION;
1297 tpmLocSetIntSts(pDevIns, pThis, pLoc, TPM_CRB_LOCALITY_REG_INT_STS_START);
1298 }
1299 }
1300#endif
1301 }
1302 break;
1303 case TPM_CRB_LOCALITY_REG_CTRL_START:
1304 if (bLoc != pThis->bLoc)
1305 break;
1306 if ( pThis->enmState == DEVTPMSTATE_CMD_RECEPTION
1307 && u32 == 0x1)
1308 {
1309 pThis->enmState = DEVTPMSTATE_CMD_EXEC;
1310 rc = PDMDevHlpTaskTrigger(pDevIns, pThis->hTpmCmdTask);
1311 }
1312 break;
1313 case TPM_CRB_LOCALITY_REG_INT_ENABLE:
1314 pLoc->uRegIntEn = u32;
1315 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
1316 break;
1317 case TPM_CRB_LOCALITY_REG_INT_STS:
1318 pLoc->uRegIntSts &= ~u32;
1319 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
1320 break;
1321 case TPM_CRB_LOCALITY_REG_CTRL_EXT: /* Not implemented. */
1322 case TPM_CRB_LOCALITY_REG_STATE: /* Readonly */
1323 case TPM_CRB_LOCALITY_REG_INTF_ID:
1324 case TPM_CRB_LOCALITY_REG_CTRL_STS:
1325 case TPM_CRB_LOCALITY_REG_CTRL_CMD_LADDR:
1326 case TPM_CRB_LOCALITY_REG_CTRL_CMD_HADDR:
1327 case TPM_CRB_LOCALITY_REG_CTRL_CMD_SZ:
1328 case TPM_CRB_LOCALITY_REG_CTRL_RSP_SZ:
1329 case TPM_CRB_LOCALITY_REG_CTRL_RSP_ADDR:
1330 default: /* Ignore. */
1331 break;
1332 }
1333
1334 return rc;
1335}
1336
1337
1338/* -=-=-=-=-=- MMIO callbacks -=-=-=-=-=- */
1339
1340/**
1341 * @callback_method_impl{FNIOMMMIONEWREAD}
1342 */
1343static DECLCALLBACK(VBOXSTRICTRC) tpmMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
1344{
1345 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1346 RT_NOREF(pvUser);
1347
1348 AssertReturn(cb <= sizeof(uint64_t), VERR_INTERNAL_ERROR);
1349
1350 RTGCPHYS offAligned = off & ~UINT64_C(0x3);
1351 uint8_t cBitsShift = (off & 0x3) * 8;
1352
1353 VBOXSTRICTRC rc = VINF_SUCCESS;
1354 uint32_t uReg = tpmGetRegisterFromOffset(offAligned);
1355 uint8_t bLoc = tpmGetLocalityFromOffset(offAligned);
1356 PDEVTPMLOCALITY pLoc = &pThis->aLoc[bLoc];
1357
1358 uint64_t u64;
1359 if (pThis->fCrb)
1360 rc = tpmMmioCrbRead(pDevIns, pThis, pLoc, bLoc, uReg, &u64, cb);
1361 else
1362 rc = tpmMmioFifoRead(pDevIns, pThis, pLoc, bLoc, uReg, &u64, cb);
1363
1364 LogFlowFunc((": %RGp %#x %#llx\n", off, cb, u64));
1365
1366 if (rc == VINF_SUCCESS)
1367 {
1368 switch (cb)
1369 {
1370 case 1: *(uint8_t *)pv = (uint8_t)(u64 >> cBitsShift); break;
1371 case 2: *(uint16_t *)pv = (uint16_t)(u64 >> cBitsShift); break;
1372 case 4: *(uint32_t *)pv = (uint32_t)(u64 >> cBitsShift); break;
1373 case 8: *(uint64_t *)pv = u64; break;
1374 default: AssertFailedBreakStmt(rc = VERR_INTERNAL_ERROR);
1375 }
1376 }
1377
1378 return rc;
1379}
1380
1381
1382/**
1383 * @callback_method_impl{FNIOMMMIONEWWRITE}
1384 */
1385static DECLCALLBACK(VBOXSTRICTRC) tpmMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
1386{
1387 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1388 RT_NOREF(pvUser);
1389
1390 Assert(!(off & (cb - 1)));
1391
1392 uint64_t u64;
1393 switch (cb)
1394 {
1395 case 1: u64 = *(const uint8_t *)pv; break;
1396 case 2: u64 = *(const uint16_t *)pv; break;
1397 case 4: u64 = *(const uint32_t *)pv; break;
1398 case 8: u64 = *(const uint64_t *)pv; break;
1399 default: AssertFailedReturn(VERR_INTERNAL_ERROR);
1400 }
1401
1402 LogFlowFunc((": %RGp %#llx\n", off, u64));
1403
1404 VBOXSTRICTRC rc = VINF_SUCCESS;
1405 uint32_t uReg = tpmGetRegisterFromOffset(off);
1406 uint8_t bLoc = tpmGetLocalityFromOffset(off);
1407 PDEVTPMLOCALITY pLoc = &pThis->aLoc[bLoc];
1408
1409 if (pThis->fCrb)
1410 rc = tpmMmioCrbWrite(pDevIns, pThis, pLoc, bLoc, uReg, u64, cb);
1411 else
1412 rc = tpmMmioFifoWrite(pDevIns, pThis, pLoc, bLoc, uReg, u64, cb);
1413
1414 return rc;
1415}
1416
1417
1418#ifdef IN_RING3
1419
1420/**
1421 * @callback_method_impl{FNPDMTASKDEV, Execute a command in ring-3}
1422 */
1423static DECLCALLBACK(void) tpmR3CmdExecWorker(PPDMDEVINS pDevIns, void *pvUser)
1424{
1425 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1426 PDEVTPMR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMR3);
1427 RT_NOREF(pvUser);
1428 LogFlowFunc(("\n"));
1429
1430 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
1431 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
1432
1433 if (pThisCC->pDrvTpm)
1434 {
1435 size_t cbCmd = RTTpmReqGetSz((PCTPMREQHDR)&pThis->abCmdResp[0]);
1436 int rc = pThisCC->pDrvTpm->pfnCmdExec(pThisCC->pDrvTpm, pThis->bLoc, &pThis->abCmdResp[0], cbCmd,
1437 &pThis->abCmdResp[0], sizeof(pThis->abCmdResp));
1438 if (RT_SUCCESS(rc))
1439 {
1440 pThis->enmState = DEVTPMSTATE_CMD_COMPLETION;
1441 pThis->offCmdResp = 0;
1442 if (pThis->fCrb)
1443 tpmLocSetIntSts(pThisCC->pDevIns, pThis, &pThis->aLoc[pThis->bLoc], TPM_CRB_LOCALITY_REG_INT_STS_START);
1444 else
1445 tpmLocSetIntSts(pThisCC->pDevIns, pThis, &pThis->aLoc[pThis->bLoc], TPM_FIFO_LOCALITY_REG_INT_STS_DATA_AVAIL | TPM_FIFO_LOCALITY_REG_INT_STS_STS_VALID);
1446 }
1447 else
1448 {
1449 /* Set fatal error. */
1450 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
1451 }
1452 }
1453
1454 PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
1455}
1456
1457
1458/**
1459 * Resets the shared hardware TPM state.
1460 *
1461 * @param pThis Pointer to the shared TPM device.
1462 */
1463static void tpmR3HwReset(PDEVTPM pThis)
1464{
1465 pThis->enmState = DEVTPMSTATE_IDLE;
1466 pThis->bLoc = TPM_NO_LOCALITY_SELECTED;
1467 pThis->bmLocReqAcc = 0;
1468 pThis->bmLocSeizedAcc = 0;
1469 pThis->offCmdResp = 0;
1470 RT_ZERO(pThis->abCmdResp);
1471
1472 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aLoc); i++)
1473 {
1474 PDEVTPMLOCALITY pLoc = &pThis->aLoc[i];
1475 pLoc->uRegIntEn = 0;
1476 pLoc->uRegIntSts = 0;
1477 }
1478}
1479
1480
1481/* -=-=-=-=-=-=-=-=- Saved State -=-=-=-=-=-=-=-=- */
1482
1483/**
1484 * @callback_method_impl{FNSSMDEVLIVEEXEC}
1485 */
1486static DECLCALLBACK(int) tpmR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1487{
1488 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1489 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1490 RT_NOREF(uPass);
1491
1492 /* Save the part of the config used for verification purposes when restoring. */
1493 pHlp->pfnSSMPutGCPhys(pSSM, pThis->GCPhysMmio);
1494 pHlp->pfnSSMPutU16( pSSM, pThis->uVenId);
1495 pHlp->pfnSSMPutU16( pSSM, pThis->uDevId);
1496 pHlp->pfnSSMPutU8( pSSM, pThis->bRevId);
1497 pHlp->pfnSSMPutU8( pSSM, pThis->uIrq);
1498 pHlp->pfnSSMPutBool( pSSM, pThis->fLocChangeSup);
1499 pHlp->pfnSSMPutU32( pSSM, (uint32_t)pThis->enmTpmVers);
1500 pHlp->pfnSSMPutU32( pSSM, pThis->cbCmdResp);
1501
1502 return VINF_SSM_DONT_CALL_AGAIN;
1503}
1504
1505
1506/**
1507 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1508 */
1509static DECLCALLBACK(int) tpmR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1510{
1511 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1512 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1513
1514 tpmR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1515
1516 int rc = pHlp->pfnSSMPutStructEx(pSSM, pThis, sizeof(*pThis), 0 /*fFlags*/, &g_aTpmFields[0], NULL);
1517 AssertRCReturn(rc, rc);
1518
1519 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* sanity/terminator */
1520}
1521
1522
1523/**
1524 * @callback_method_impl{FNSSMDEVLOADEXEC}
1525 */
1526static DECLCALLBACK(int) tpmR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1527{
1528 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1529 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1530 uint8_t u8;
1531 uint16_t u16;
1532 uint32_t u32;
1533 bool f;
1534 RTGCPHYS GCPhysMmio;
1535 TPMVERSION enmTpmVers;
1536
1537 Assert(uPass == SSM_PASS_FINAL); RT_NOREF(uPass);
1538 AssertMsgReturn(uVersion == TPM_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1539
1540 /* Verify the config first. */
1541 int rc = pHlp->pfnSSMGetGCPhys(pSSM, &GCPhysMmio);
1542 AssertRCReturn(rc, rc);
1543 if (GCPhysMmio != pThis->GCPhysMmio)
1544 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1545 N_("Config mismatch - saved GCPhysMmio=%#RGp; configured GCPhysMmio=%#RGp"),
1546 GCPhysMmio, pThis->GCPhysMmio);
1547
1548 rc = pHlp->pfnSSMGetU16(pSSM, &u16);
1549 AssertRCReturn(rc, rc);
1550 if (u16 != pThis->uVenId)
1551 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1552 N_("Config mismatch - saved uVenId=%#RX16; configured uVenId=%#RX16"),
1553 u16, pThis->uVenId);
1554
1555 rc = pHlp->pfnSSMGetU16(pSSM, &u16);
1556 AssertRCReturn(rc, rc);
1557 if (u16 != pThis->uDevId)
1558 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1559 N_("Config mismatch - saved uDevId=%#RX16; configured uDevId=%#RX16"),
1560 u16, pThis->uDevId);
1561
1562 rc = pHlp->pfnSSMGetU8(pSSM, &u8);
1563 AssertRCReturn(rc, rc);
1564 if (u8 != pThis->bRevId)
1565 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1566 N_("Config mismatch - saved bRevId=%#RX8; configured bDevId=%#RX8"),
1567 u8, pThis->bRevId);
1568
1569 rc = pHlp->pfnSSMGetU8(pSSM, &u8);
1570 AssertRCReturn(rc, rc);
1571 if (u8 != pThis->uIrq)
1572 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1573 N_("Config mismatch - saved uIrq=%#RX8; configured uIrq=%#RX8"),
1574 u8, pThis->uIrq);
1575
1576 rc = pHlp->pfnSSMGetBool(pSSM, &f);
1577 AssertRCReturn(rc, rc);
1578 if (f != pThis->fLocChangeSup)
1579 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1580 N_("Config mismatch - saved fLocChangeSup=%RTbool; configured fLocChangeSup=%RTbool"),
1581 f, pThis->fLocChangeSup);
1582
1583 rc = pHlp->pfnSSMGetU32(pSSM, (uint32_t *)&enmTpmVers);
1584 AssertRCReturn(rc, rc);
1585 if (enmTpmVers != pThis->enmTpmVers)
1586 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1587 N_("Config mismatch - saved enmTpmVers=%RU32; configured enmTpmVers=%RU32"),
1588 enmTpmVers, pThis->enmTpmVers);
1589
1590 rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1591 AssertRCReturn(rc, rc);
1592 if (u32 != pThis->cbCmdResp)
1593 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1594 N_("Config mismatch - saved cbCmdResp=%RU32; configured cbCmdResp=%RU32"),
1595 u32, pThis->cbCmdResp);
1596
1597 if (uPass == SSM_PASS_FINAL)
1598 {
1599 rc = pHlp->pfnSSMGetStructEx(pSSM, pThis, sizeof(*pThis), 0 /*fFlags*/, &g_aTpmFields[0], NULL);
1600 AssertRCReturn(rc, rc);
1601
1602 /* The marker. */
1603 rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1604 AssertRCReturn(rc, rc);
1605 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1606
1607 /* Verify device state sanity. */
1608 AssertLogRelMsgReturn( pThis->enmState > DEVTPMSTATE_INVALID
1609 && pThis->enmState <= DEVTPMSTATE_LAST_VALID,
1610 ("Invalid TPM state loaded from saved state: %#x\n", pThis->enmState),
1611 VERR_SSM_UNEXPECTED_DATA);
1612
1613 AssertLogRelMsgReturn(pThis->offCmdResp <= pThis->cbCmdResp,
1614 ("Invalid TPM command/response buffer offset loaded from saved state: %#x\n", pThis->offCmdResp),
1615 VERR_SSM_UNEXPECTED_DATA);
1616 }
1617
1618 return VINF_SUCCESS;
1619}
1620
1621
1622/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1623
1624/**
1625 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1626 */
1627static DECLCALLBACK(void *) tpmR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
1628{
1629 PDEVTPMCC pThisCC = RT_FROM_MEMBER(pInterface, DEVTPMCC, IBase);
1630 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
1631 PDMIBASE_RETURN_INTERFACE(pszIID, PDMITPMPORT, &pThisCC->ITpmPort);
1632 return NULL;
1633}
1634
1635
1636/* -=-=-=-=-=-=-=-=- PDMITPMPORT -=-=-=-=-=-=-=-=- */
1637
1638/**
1639 * @interface_method_impl{PDMITPMPORT,pfnGetMaxBufferSize}
1640 */
1641static DECLCALLBACK(uint32_t) tpmR3TpmPortGetMaxBufferSize(PPDMITPMPORT pInterface)
1642{
1643 RT_NOREF(pInterface);
1644 return TPM_DATA_BUFFER_SIZE_MAX;
1645}
1646
1647
1648/* -=-=-=-=-=-=-=-=- PDMDEVREG -=-=-=-=-=-=-=-=- */
1649
1650/**
1651 * @interface_method_impl{PDMDEVREG,pfnPowerOn}
1652 */
1653static DECLCALLBACK(void) tpmR3PowerOn(PPDMDEVINS pDevIns)
1654{
1655 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1656 PDEVTPMCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMCC);
1657
1658 if (pThisCC->pDrvTpm)
1659 pThis->fEstablishmentSet = pThisCC->pDrvTpm->pfnGetEstablishedFlag(pThisCC->pDrvTpm);
1660}
1661
1662
1663/**
1664 * @interface_method_impl{PDMDEVREG,pfnReset}
1665 */
1666static DECLCALLBACK(void) tpmR3Reset(PPDMDEVINS pDevIns)
1667{
1668 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1669 PDEVTPMCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMCC);
1670
1671 tpmR3HwReset(pThis);
1672 if (pThisCC->pDrvTpm)
1673 pThis->fEstablishmentSet = pThisCC->pDrvTpm->pfnGetEstablishedFlag(pThisCC->pDrvTpm);
1674}
1675
1676
1677/**
1678 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1679 */
1680static DECLCALLBACK(int) tpmR3Destruct(PPDMDEVINS pDevIns)
1681{
1682 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1683 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1684
1685 /** @todo */
1686 RT_NOREF(pThis);
1687 return VINF_SUCCESS;
1688}
1689
1690
1691/**
1692 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1693 */
1694static DECLCALLBACK(int) tpmR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1695{
1696 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1697 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1698 PDEVTPMCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMCC);
1699 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1700 int rc;
1701
1702 RT_NOREF(iInstance);
1703
1704 pThis->hTpmCmdTask = NIL_PDMTASKHANDLE;
1705
1706 pThisCC->pDevIns = pDevIns;
1707
1708 /* IBase */
1709 pThisCC->IBase.pfnQueryInterface = tpmR3QueryInterface;
1710
1711 /* ITpmPort */
1712 pThisCC->ITpmPort.pfnGetMaxBufferSize = tpmR3TpmPortGetMaxBufferSize;
1713
1714
1715 /*
1716 * Validate and read the configuration.
1717 */
1718 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Irq"
1719 "|MmioBase"
1720 "|VendorId"
1721 "|DeviceId"
1722 "|RevisionId"
1723 "|Crb",
1724 "");
1725
1726 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Irq", &pThis->uIrq, 10);
1727 if (RT_FAILURE(rc))
1728 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"Irq\" value"));
1729
1730 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioBase", &pThis->GCPhysMmio, TPM_MMIO_BASE_DEFAULT);
1731 if (RT_FAILURE(rc))
1732 return PDMDEV_SET_ERROR(pDevIns, rc,
1733 N_("Configuration error: Failed to get the \"MmioBase\" value"));
1734
1735 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "VendorId", &pThis->uDevId, TPM_VID_DEFAULT);
1736 if (RT_FAILURE(rc))
1737 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"VendorId\" value"));
1738
1739 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "DeviceId", &pThis->uDevId, TPM_DID_DEFAULT);
1740 if (RT_FAILURE(rc))
1741 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"DeviceId\" value"));
1742
1743 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "RevisionId", &pThis->bRevId, TPM_RID_DEFAULT);
1744 if (RT_FAILURE(rc))
1745 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"RevisionId\" value"));
1746
1747 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Crb", &pThis->fCrb, false);
1748 if (RT_FAILURE(rc))
1749 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"Crb\" value"));
1750
1751 /*
1752 * Register the MMIO range, PDM API requests page aligned
1753 * addresses and sizes.
1754 */
1755 rc = PDMDevHlpMmioCreateAndMap(pDevIns, pThis->GCPhysMmio, TPM_MMIO_SIZE, tpmMmioWrite, tpmMmioRead,
1756 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
1757 "TPM MMIO", &pThis->hMmio);
1758 AssertRCReturn(rc, rc);
1759
1760 /*
1761 * Attach any TPM driver below.
1762 */
1763 rc = PDMDevHlpDriverAttach(pDevIns, 0 /*iLUN*/, &pThisCC->IBase, &pThisCC->pDrvBase, "TPM");
1764 if (RT_SUCCESS(rc))
1765 {
1766 pThisCC->pDrvTpm = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMITPMCONNECTOR);
1767 AssertLogRelMsgReturn(pThisCC->pDrvTpm, ("TPM#%d: Driver is missing the TPM interface.\n", iInstance), VERR_PDM_MISSING_INTERFACE);
1768
1769 uint32_t cbBufDrv = pThisCC->pDrvTpm->pfnGetBufferSize(pThisCC->pDrvTpm);
1770 pThis->cbCmdResp = RT_MIN(cbBufDrv, TPM_DATA_BUFFER_SIZE_MAX);
1771 pThis->fLocChangeSup = pThisCC->pDrvTpm->pfnGetLocalityMax(pThisCC->pDrvTpm) > 0;
1772
1773 pThis->enmTpmVers = pThisCC->pDrvTpm->pfnGetVersion(pThisCC->pDrvTpm);
1774 if (pThis->enmTpmVers == TPMVERSION_UNKNOWN)
1775 return PDMDEV_SET_ERROR(pDevIns, VERR_NOT_SUPPORTED, N_("The emulated TPM version is not supported"));
1776 }
1777 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1778 {
1779 pThis->fLocChangeSup = false;
1780 pThis->fEstablishmentSet = false;
1781 pThis->cbCmdResp = TPM_DATA_BUFFER_SIZE_MAX;
1782
1783 pThisCC->pDrvBase = NULL;
1784 pThisCC->pDrvTpm = NULL;
1785 LogRel(("TPM#%d: no unit\n", iInstance));
1786 }
1787 else
1788 AssertLogRelMsgRCReturn(rc, ("TPM#%d: Failed to attach to TPM driver. rc=%Rrc\n", iInstance, rc), rc);
1789
1790 /* Create task for executing requests in ring-3. */
1791 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "TPMCmdWrk",
1792 tpmR3CmdExecWorker, NULL /*pvUser*/, &pThis->hTpmCmdTask);
1793 AssertRCReturn(rc,rc);
1794
1795 /*
1796 * Saved state.
1797 */
1798 rc = PDMDevHlpSSMRegister3(pDevIns, TPM_SAVED_STATE_VERSION, sizeof(*pThis),
1799 tpmR3LiveExec, tpmR3SaveExec, tpmR3LoadExec);
1800 AssertRCReturn(rc, rc);
1801
1802 tpmR3HwReset(pThis);
1803 return VINF_SUCCESS;
1804}
1805
1806#else /* !IN_RING3 */
1807
1808/**
1809 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1810 */
1811static DECLCALLBACK(int) tpmRZConstruct(PPDMDEVINS pDevIns)
1812{
1813 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1814 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1815
1816 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, tpmMmioWrite, tpmMmioRead, NULL /*pvUser*/);
1817 AssertRCReturn(rc, rc);
1818
1819 return VINF_SUCCESS;
1820}
1821
1822#endif /* !IN_RING3 */
1823
1824/**
1825 * The device registration structure.
1826 */
1827const PDMDEVREG g_DeviceTpm =
1828{
1829 /* .u32Version = */ PDM_DEVREG_VERSION,
1830 /* .uReserved0 = */ 0,
1831 /* .szName = */ "tpm",
1832 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
1833 /* .fClass = */ PDM_DEVREG_CLASS_SERIAL,
1834 /* .cMaxInstances = */ 1,
1835 /* .uSharedVersion = */ 42,
1836 /* .cbInstanceShared = */ sizeof(DEVTPM),
1837 /* .cbInstanceCC = */ sizeof(DEVTPMCC),
1838 /* .cbInstanceRC = */ sizeof(DEVTPMRC),
1839 /* .cMaxPciDevices = */ 0,
1840 /* .cMaxMsixVectors = */ 0,
1841 /* .pszDescription = */ "Trusted Platform Module",
1842#if defined(IN_RING3)
1843 /* .pszRCMod = */ "VBoxDDRC.rc",
1844 /* .pszR0Mod = */ "VBoxDDR0.r0",
1845 /* .pfnConstruct = */ tpmR3Construct,
1846 /* .pfnDestruct = */ tpmR3Destruct,
1847 /* .pfnRelocate = */ NULL,
1848 /* .pfnMemSetup = */ NULL,
1849 /* .pfnPowerOn = */ tpmR3PowerOn,
1850 /* .pfnReset = */ tpmR3Reset,
1851 /* .pfnSuspend = */ NULL,
1852 /* .pfnResume = */ NULL,
1853 /* .pfnAttach = */ NULL,
1854 /* .pfnDetach = */ NULL,
1855 /* .pfnQueryInterface = */ NULL,
1856 /* .pfnInitComplete = */ NULL,
1857 /* .pfnPowerOff = */ NULL,
1858 /* .pfnSoftReset = */ NULL,
1859 /* .pfnReserved0 = */ NULL,
1860 /* .pfnReserved1 = */ NULL,
1861 /* .pfnReserved2 = */ NULL,
1862 /* .pfnReserved3 = */ NULL,
1863 /* .pfnReserved4 = */ NULL,
1864 /* .pfnReserved5 = */ NULL,
1865 /* .pfnReserved6 = */ NULL,
1866 /* .pfnReserved7 = */ NULL,
1867#elif defined(IN_RING0)
1868 /* .pfnEarlyConstruct = */ NULL,
1869 /* .pfnConstruct = */ tpmRZConstruct,
1870 /* .pfnDestruct = */ NULL,
1871 /* .pfnFinalDestruct = */ NULL,
1872 /* .pfnRequest = */ NULL,
1873 /* .pfnReserved0 = */ NULL,
1874 /* .pfnReserved1 = */ NULL,
1875 /* .pfnReserved2 = */ NULL,
1876 /* .pfnReserved3 = */ NULL,
1877 /* .pfnReserved4 = */ NULL,
1878 /* .pfnReserved5 = */ NULL,
1879 /* .pfnReserved6 = */ NULL,
1880 /* .pfnReserved7 = */ NULL,
1881#elif defined(IN_RC)
1882 /* .pfnConstruct = */ tpmRZConstruct,
1883 /* .pfnReserved0 = */ NULL,
1884 /* .pfnReserved1 = */ NULL,
1885 /* .pfnReserved2 = */ NULL,
1886 /* .pfnReserved3 = */ NULL,
1887 /* .pfnReserved4 = */ NULL,
1888 /* .pfnReserved5 = */ NULL,
1889 /* .pfnReserved6 = */ NULL,
1890 /* .pfnReserved7 = */ NULL,
1891#else
1892# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1893#endif
1894 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
1895};
1896
1897#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1898
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