1 | /* $Id: DevTpm.cpp 90492 2021-08-03 10:16:28Z vboxsync $ */
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2 | /** @file
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3 | * DevTpm - Trusted Platform Module emulation.
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4 | *
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5 | * This emulation is based on the spec available under (as of 2021-08-02):
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6 | * https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-TPM-Profile-for-TPM-2p0-v1p05p_r14_pub.pdf
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7 | */
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8 |
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9 | /*
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10 | * Copyright (C) 2021 Oracle Corporation
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11 | *
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12 | * This file is part of VirtualBox Open Source Edition (OSE), as
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13 | * available from http://www.virtualbox.org. This file is free software;
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14 | * you can redistribute it and/or modify it under the terms of the GNU
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15 | * General Public License (GPL) as published by the Free Software
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16 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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17 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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18 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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19 | */
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20 |
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21 |
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22 | /*********************************************************************************************************************************
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23 | * Header Files *
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24 | *********************************************************************************************************************************/
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25 | #define LOG_GROUP LOG_GROUP_DEFAULT /** @todo DEV_TPM */
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26 | #include <VBox/vmm/pdmdev.h>
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27 | #include <iprt/assert.h>
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28 | #include <iprt/string.h>
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29 |
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30 | #include "VBoxDD.h"
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31 |
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32 |
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33 | /*********************************************************************************************************************************
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34 | * Defined Constants And Macros *
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35 | *********************************************************************************************************************************/
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36 |
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37 | /** The TPM saved state version. */
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38 | #define TPM_SAVED_STATE_VERSION 1
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39 |
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40 | /** Default vendor ID. */
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41 | #define TPM_VID_DEFAULT 0x1014
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42 | /** Default device ID. */
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43 | #define TPM_DID_DEFAULT 0x0001
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44 | /** Default revision ID. */
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45 | #define TPM_RID_DEFAULT 0x01
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46 |
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47 | /** The TPM MMIO base default as defined in chapter 5.2. */
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48 | #define TPM_MMIO_BASE_DEFAULT 0xfed40000
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49 | /** The size of the TPM MMIO area. */
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50 | #define TPM_MMIO_SIZE 0x5000
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51 |
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52 | /** Number of localities as mandated by the TPM spec. */
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53 | #define TPM_LOCALITY_COUNT 5
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54 | /** Size of each locality in the TPM MMIO area (chapter 6.5.2).*/
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55 | #define TPM_LOCALITY_MMIO_SIZE 0x1000
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56 |
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57 | /** @name TPM locality register related defines.
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58 | * @{ */
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59 | /** Ownership management for a particular locality. */
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60 | #define TPM_LOCALITY_REG_ACCESS 0x00
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61 | /** INdicates whether a dynamic OS has been established on this platform before.. */
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62 | # define TPM_LOCALITY_REG_ESTABLISHMENT RT_BIT(0)
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63 | /** On reads indicates whether the locality requests use of the TPM (1) or not or is already active locality (0),
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64 | * writing a 1 requests the locality to be granted getting the active locality.. */
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65 | # define TPM_LOCALITY_REG_REQUEST_USE RT_BIT(1)
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66 | /** Indicates whether another locality is requesting usage of the TPM. */
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67 | # define TPM_LOCALITY_REG_PENDING_REQUEST RT_BIT(2)
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68 | /** Writing a 1 forces the TPM to give control to the locality if it has a higher priority. */
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69 | # define TPM_LOCALITY_REG_ACCESS_SEIZE RT_BIT(3)
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70 | /** On reads indicates whether this locality has been seized by a higher locality (1) or not (0), writing a 1 clears this bit. */
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71 | # define TPM_LOCALITY_REG_ACCESS_BEEN_SEIZED RT_BIT(4)
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72 | /** On reads indicates whether this locality is active (1) or not (0), writing a 1 relinquishes control for this locality. */
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73 | # define TPM_LOCALITY_REG_ACCESS_ACTIVE RT_BIT(5)
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74 | /** Set bit indicates whether all other bits in this register have valid data. */
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75 | # define TPM_LOCALITY_REG_ACCESS_VALID RT_BIT(7)
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76 | /** Writable mask. */
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77 | # define TPM_LOCALITY_REG_ACCESS_WR_MASK 0x3a
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78 |
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79 | /** Interrupt enable register. */
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80 | #define TPM_LOCALITY_REG_INT_ENABLE 0x08
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81 | /** Data available interrupt enable bit. */
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82 | # define TPM_LOCALITY_REG_INT_ENABLE_DATA_AVAIL RT_BIT_32(0)
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83 | /** Status valid interrupt enable bit. */
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84 | # define TPM_LOCALITY_REG_INT_ENABLE_STS_VALID RT_BIT_32(1)
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85 | /** Locality change interrupt enable bit. */
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86 | # define TPM_LOCALITY_REG_INT_ENABLE_LOCALITY_CHANGE RT_BIT_32(2)
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87 | /** Interrupt polarity configuration. */
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88 | # define TPM_LOCALITY_REG_INT_ENABLE_POLARITY_MASK 0x18
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89 | # define TPM_LOCALITY_REG_INT_ENABLE_POLARITY_SHIFT 3
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90 | # define TPM_LOCALITY_REG_INT_ENABLE_POLARITY_SET(a) ((a) << TPM_LOCALITY_REG_INT_POLARITY_SHIFT)
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91 | # define TPM_LOCALITY_REG_INT_ENABLE_POLARITY_GET(a) (((a) & TPM_LOCALITY_REG_INT_POLARITY_MASK) >> TPM_LOCALITY_REG_INT_POLARITY_SHIFT)
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92 | /** High level interrupt trigger. */
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93 | # define TPM_LOCALITY_REG_INT_ENABLE_POLARITY_HIGH 0
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94 | /** Low level interrupt trigger. */
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95 | # define TPM_LOCALITY_REG_INT_ENABLE_POLARITY_LOW 1
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96 | /** Rising edge interrupt trigger. */
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97 | # define TPM_LOCALITY_REG_INT_ENABLE_POLARITY_RISING 2
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98 | /** Falling edge interrupt trigger. */
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99 | # define TPM_LOCALITY_REG_INT_ENABLE_POLARITY_FALLING 3
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100 | /** Command ready enable bit. */
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101 | # define TPM_LOCALITY_REG_INT_ENABLE_CMD_RDY RT_BIT_32(7)
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102 | /** Global interrupt enable/disable bit. */
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103 | # define TPM_LOCALITY_REG_INT_ENABLE_GLOBAL RT_BIT_32(31)
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104 |
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105 | /** Configured interrupt vector register. */
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106 | #define TPM_LOCALITY_REG_INT_VEC 0x0c
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107 |
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108 | /** Interrupt status register. */
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109 | #define TPM_LOCALITY_REG_INT_STS 0x10
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110 | /** Data available interrupt occured bit, writing a 1 clears the bit. */
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111 | # define TPM_LOCALITY_REG_INT_STS_DATA_AVAIL RT_BIT_32(0)
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112 | /** Status valid interrupt occured bit, writing a 1 clears the bit. */
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113 | # define TPM_LOCALITY_REG_INT_STS_STS_VALID RT_BIT_32(1)
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114 | /** Locality change interrupt occured bit, writing a 1 clears the bit. */
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115 | # define TPM_LOCALITY_REG_INT_STS_LOCALITY_CHANGE RT_BIT_32(2)
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116 | /** Command ready occured bit, writing a 1 clears the bit. */
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117 | # define TPM_LOCALITY_REG_INT_STS_CMD_RDY RT_BIT_32(7)
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118 | /** Writable mask. */
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119 | # define TPM_LOCALITY_REG_INT_STS_WR_MASK UINT32_C(0x87)
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120 |
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121 | /** Interfacce capabilities register. */
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122 | #define TPM_LOCALITY_REG_IF_CAP 0x14
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123 | /** Flag whether the TPM supports the data avilable interrupt. */
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124 | # define TPM_LOCALITY_REG_IF_CAP_INT_DATA_AVAIL RT_BIT(0)
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125 | /** Flag whether the TPM supports the status valid interrupt. */
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126 | # define TPM_LOCALITY_REG_IF_CAP_INT_STS_VALID RT_BIT(1)
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127 | /** Flag whether the TPM supports the data avilable interrupt. */
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128 | # define TPM_LOCALITY_REG_IF_CAP_INT_LOCALITY_CHANGE RT_BIT(2)
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129 | /** Flag whether the TPM supports high level interrupts. */
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130 | # define TPM_LOCALITY_REG_IF_CAP_INT_LVL_HIGH RT_BIT(3)
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131 | /** Flag whether the TPM supports low level interrupts. */
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132 | # define TPM_LOCALITY_REG_IF_CAP_INT_LVL_LOW RT_BIT(4)
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133 | /** Flag whether the TPM supports rising edge interrupts. */
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134 | # define TPM_LOCALITY_REG_IF_CAP_INT_RISING_EDGE RT_BIT(5)
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135 | /** Flag whether the TPM supports falling edge interrupts. */
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136 | # define TPM_LOCALITY_REG_IF_CAP_INT_FALLING_EDGE RT_BIT(6)
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137 | /** Flag whether the TPM supports the command ready interrupt. */
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138 | # define TPM_LOCALITY_REG_IF_CAP_INT_CMD_RDY RT_BIT(7)
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139 | /** Flag whether the busrt count field is static or dynamic. */
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140 | # define TPM_LOCALITY_REG_IF_CAP_BURST_CNT_STATIC RT_BIT(8)
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141 | /** Maximum transfer size support. */
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142 | # define TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_MASK 0x600
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143 | # define TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SHIFT 9
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144 | # define TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SET(a) ((a) << TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SHIFT)
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145 | /** Only legacy transfers supported. */
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146 | # define TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_LEGACY 0x0
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147 | /** 8B maximum transfer size. */
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148 | # define TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_8B 0x1
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149 | /** 32B maximum transfer size. */
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150 | # define TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_32B 0x2
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151 | /** 64B maximum transfer size. */
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152 | # define TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_64B 0x3
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153 | /** Interface version. */
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154 | # define TPM_LOCALITY_REG_IF_CAP_IF_VERSION_MASK UINT32_C(0x70000000)
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155 | # define TPM_LOCALITY_REG_IF_CAP_IF_VERSION_SHIFT 28
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156 | # define TPM_LOCALITY_REG_IF_CAP_IF_VERSION_SET(a) ((a) << TPM_LOCALITY_REG_IF_CAP_IF_VERSION_SHIFT)
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157 | /** Interface 1.21 or ealier. */
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158 | # define TPM_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_21 0
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159 | /** Interface 1.3. */
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160 | # define TPM_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3 2
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161 | /** Interface 1.3 for TPM 2.0. */
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162 | # define TPM_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3_TPM2 3
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163 |
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164 | /** TPM status register. */
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165 | #define TPM_LOCALITY_REG_STS 0x18
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166 | /** Writing a 1 forces the TPM to re-send the response. */
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167 | # define TPM_LOCALITY_REG_STS_RESPONSE_RETRY RT_BIT_32(1)
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168 | /** Indicating whether the TPM has finished a self test. */
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169 | # define TPM_LOCALITY_REG_STS_SELF_TEST_DONE RT_BIT_32(2)
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170 | /** Flag indicating whether the TPM expects more data for the command. */
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171 | # define TPM_LOCALITY_REG_STS_EXPECT RT_BIT_32(3)
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172 | /** Flag indicating whether the TPM has more response data available. */
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173 | # define TPM_LOCALITY_REG_STS_DATA_AVAIL RT_BIT_32(4)
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174 | /** Written by software to cause the TPM to execute a previously transfered command. */
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175 | # define TPM_LOCALITY_REG_STS_TPM_GO RT_BIT_32(5)
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176 | /** On reads indicates whether the TPM is ready to receive a new command (1) or not (0),
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177 | * a write of 1 causes the TPM to transition to this state. */
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178 | # define TPM_LOCALITY_REG_STS_CMD_RDY RT_BIT_32(6)
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179 | /** Indicates whether the Expect and data available bits are valid. */
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180 | # define TPM_LOCALITY_REG_STS_VALID RT_BIT_32(7)
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181 | # define TPM_LOCALITY_REG_STS_BURST_CNT_MASK UINT32_C(0xffff00)
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182 | # define TPM_LOCALITY_REG_STS_BURST_CNT_SHIFT 8
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183 | # define TPM_LOCALITY_REG_STS_BURST_CNT_SET(a) ((a) << TPM_LOCALITY_REG_STS_BURST_CNT_SHIFT)
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184 |
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185 | /** TPM end of HASH operation signal register for locality 4. */
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186 | #define TPM_LOCALITY_REG_HASH_END 0x20
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187 | /** Data FIFO read/write register. */
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188 | #define TPM_LOCALITY_REG_DATA_FIFO 0x24
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189 | /** TPM start of HASH operation signal register for locality 4. */
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190 | #define TPM_LOCALITY_REG_HASH_START 0x28
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191 | /** Extended data FIFO read/write register. */
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192 | #define TPM_LOCALITY_REG_XDATA_FIFO 0x80
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193 | /** TPM device and vendor ID. */
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194 | #define TPM_LOCALITY_REG_DID_VID 0xf00
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195 | /** TPM revision ID. */
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196 | #define TPM_LOCALITY_REG_RID 0xf04
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197 | /** @} */
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198 |
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199 |
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200 | /*********************************************************************************************************************************
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201 | * Structures and Typedefs *
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202 | *********************************************************************************************************************************/
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203 |
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204 | /**
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205 | * Possible locality states
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206 | * (see chapter 5.6.12.1 Figure 3 State Transition Diagram).
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207 | */
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208 | typedef enum DEVTPMLOCALITYSTATE
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209 | {
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210 | /** Invalid state, do not use. */
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211 | DEVTPMLOCALITYSTATE_INVALID = 0,
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212 | /** Init state. */
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213 | DEVTPMLOCALITYSTATE_INIT,
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214 | /** Ready to accept command data. */
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215 | DEVTPMLOCALITYSTATE_READY,
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216 | /** Command data being transfered. */
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217 | DEVTPMLOCALITYSTATE_CMD_RECEPTION,
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218 | /** Command is being executed by the TPM. */
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219 | DEVTPMLOCALITYSTATE_CMD_EXEC,
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220 | /** Command has completed and data can be read. */
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221 | DEVTPMLOCALITYSTATE_CMD_COMPLETION,
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222 | /** 32bit hack. */
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223 | DEVTPMLOCALITYSTATE_32BIT_HACK = 0x7fffffff
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224 | } DEVTPMLOCALITYSTATE;
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225 |
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226 |
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227 | /**
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228 | * Locality state.
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229 | */
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230 | typedef struct DEVTPMLOCALITY
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231 | {
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232 | /** The current state of the locality. */
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233 | DEVTPMLOCALITYSTATE enmState;
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234 | /** Access register state. */
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235 | uint32_t uRegAccess;
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236 | /** The interrupt enable register. */
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237 | uint32_t uRegIntEn;
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238 | /** The interrupt status register. */
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239 | uint32_t uRegIntSts;
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240 | } DEVTPMLOCALITY;
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241 | typedef DEVTPMLOCALITY *PDEVTPMLOCALITY;
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242 | typedef const DEVTPMLOCALITY *PCDEVTPMLOCALITY;
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243 |
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244 |
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245 | /**
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246 | * Shared TPM device state.
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247 | */
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248 | typedef struct DEVTPM
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249 | {
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250 | /** The handle of the MMIO region. */
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251 | IOMMMIOHANDLE hMmio;
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252 | /** The vendor ID configured. */
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253 | uint16_t uVenId;
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254 | /** The device ID configured. */
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255 | uint16_t uDevId;
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256 | /** The revision ID configured. */
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257 | uint8_t bRevId;
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258 | /** The IRQ value. */
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259 | uint8_t uIrq;
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260 |
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261 | /** Currently selected locality. */
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262 | uint8_t bLoc;
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263 | /** States of the implemented localities. */
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264 | DEVTPMLOCALITY aLoc[TPM_LOCALITY_COUNT];
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265 |
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266 | } DEVTPM;
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267 | /** Pointer to the shared TPM device state. */
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268 | typedef DEVTPM *PDEVTPM;
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269 |
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270 | /** The special no current locality selected value. */
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271 | #define TPM_NO_LOCALITY_SELECTED 0xff
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272 |
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273 |
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274 | /**
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275 | * TPM device state for ring-3.
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276 | */
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277 | typedef struct DEVTPMR3
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278 | {
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279 | uint8_t bDummy;
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280 | } DEVTPMR3;
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281 | /** Pointer to the TPM device state for ring-3. */
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282 | typedef DEVTPMR3 *PDEVTPMR3;
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283 |
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284 |
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285 | /**
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286 | * TPM device state for ring-0.
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287 | */
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288 | typedef struct DEVTPMR0
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289 | {
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290 | uint8_t bDummy;
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291 | } DEVTPMR0;
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292 | /** Pointer to the TPM device state for ring-0. */
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293 | typedef DEVTPMR0 *PDEVTPMR0;
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294 |
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295 |
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296 | /**
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297 | * TPM device state for raw-mode.
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298 | */
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299 | typedef struct DEVTPMRC
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300 | {
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301 | uint8_t bDummy;
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302 | } DEVTPMRC;
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303 | /** Pointer to the TPM device state for raw-mode. */
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304 | typedef DEVTPMRC *PDEVTPMRC;
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305 |
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306 | /** The TPM device state for the current context. */
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307 | typedef CTX_SUFF(DEVTPM) DEVTPMCC;
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308 | /** Pointer to the TPM device state for the current context. */
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309 | typedef CTX_SUFF(PDEVTPM) PDEVTPMCC;
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310 |
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311 |
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312 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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313 |
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314 |
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315 |
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316 | /**
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317 | * Sets the IRQ line of the given device to the given state.
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318 | *
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319 | * @returns nothing.
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320 | * @param pDevIns Pointer to the PDM device instance data.
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321 | * @param pThis Pointer to the shared TPM device.
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322 | * @param iLvl The interrupt level to set.
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323 | */
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324 | DECLINLINE(void) tpmIrqReq(PPDMDEVINS pDevIns, PDEVTPM pThis, int iLvl)
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325 | {
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326 | PDMDevHlpISASetIrqNoWait(pDevIns, pThis->uIrq, iLvl);
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327 | }
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328 |
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329 |
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330 | /**
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331 | * Updates the IRQ status of the given locality.
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332 | *
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333 | * @returns nothing.
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334 | * @param pDevIns Pointer to the PDM device instance data.
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335 | * @param pThis Pointer to the shared TPM device.
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336 | * @param pLoc The locality state.
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337 | */
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338 | PDMBOTHCBDECL(void) tpmLocIrqUpdate(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc)
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339 | {
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340 | if (pLoc->uRegIntEn & pLoc->uRegIntSts)
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341 | tpmIrqReq(pDevIns, pThis, 1);
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342 | else
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343 | tpmIrqReq(pDevIns, pThis, 0);
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344 | }
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345 |
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346 |
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347 | /**
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348 | * Returns the given locality being accessed from the given TPM MMIO offset.
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349 | *
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350 | * @returns Locality number.
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351 | * @param off The offset into the TPM MMIO region.
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352 | */
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353 | DECLINLINE(uint8_t) tpmGetLocalityFromOffset(RTGCPHYS off)
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354 | {
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355 | return off / TPM_LOCALITY_MMIO_SIZE;
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356 | }
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357 |
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358 |
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359 | /**
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360 | * Returns the given register of a particular locality being accessed from the given TPM MMIO offset.
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361 | *
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362 | * @returns Register index being accessed.
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363 | * @param off The offset into the TPM MMIO region.
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364 | */
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365 | DECLINLINE(uint32_t) tpmGetRegisterFromOffset(RTGCPHYS off)
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366 | {
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367 | return off % TPM_LOCALITY_MMIO_SIZE;
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368 | }
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369 |
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370 |
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371 | /* -=-=-=-=-=- MMIO callbacks -=-=-=-=-=- */
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372 |
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373 |
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374 | /**
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375 | * @callback_method_impl{FNIOMMMIONEWREAD}
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376 | */
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377 | static DECLCALLBACK(VBOXSTRICTRC) tpmMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
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378 | {
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379 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
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380 | RT_NOREF(pvUser);
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381 |
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382 | Assert(!(off & (cb - 1)));
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383 |
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384 | LogFlowFunc((": %RGp %#x\n", off, cb));
|
---|
385 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
386 | uint32_t uReg = tpmGetRegisterFromOffset(off);
|
---|
387 | uint8_t bLoc = tpmGetLocalityFromOffset(off);
|
---|
388 | PDEVTPMLOCALITY pLoc = &pThis->aLoc[bLoc];
|
---|
389 | uint32_t u32;
|
---|
390 | switch (uReg)
|
---|
391 | {
|
---|
392 | case TPM_LOCALITY_REG_ACCESS:
|
---|
393 | u32 = 0;
|
---|
394 | break;
|
---|
395 | case TPM_LOCALITY_REG_INT_ENABLE:
|
---|
396 | u32 = pLoc->uRegIntEn;
|
---|
397 | break;
|
---|
398 | case TPM_LOCALITY_REG_INT_VEC:
|
---|
399 | u32 = pThis->uIrq;
|
---|
400 | break;
|
---|
401 | case TPM_LOCALITY_REG_INT_STS:
|
---|
402 | u32 = pLoc->uRegIntSts;
|
---|
403 | break;
|
---|
404 | case TPM_LOCALITY_REG_IF_CAP:
|
---|
405 | u32 = TPM_LOCALITY_REG_IF_CAP_INT_DATA_AVAIL
|
---|
406 | | TPM_LOCALITY_REG_IF_CAP_INT_STS_VALID
|
---|
407 | | TPM_LOCALITY_REG_IF_CAP_INT_LOCALITY_CHANGE
|
---|
408 | | TPM_LOCALITY_REG_IF_CAP_INT_LVL_LOW
|
---|
409 | | TPM_LOCALITY_REG_IF_CAP_INT_CMD_RDY
|
---|
410 | | TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SET(TPM_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_64B)
|
---|
411 | | TPM_LOCALITY_REG_IF_CAP_IF_VERSION_SET(TPM_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3); /** @todo Make some of them configurable? */
|
---|
412 | break;
|
---|
413 | case TPM_LOCALITY_REG_STS:
|
---|
414 | if (bLoc != pThis->bLoc)
|
---|
415 | {
|
---|
416 | u32 = UINT32_MAX;
|
---|
417 | break;
|
---|
418 | }
|
---|
419 | /** @todo */
|
---|
420 | break;
|
---|
421 | case TPM_LOCALITY_REG_DATA_FIFO:
|
---|
422 | case TPM_LOCALITY_REG_DATA_XFIFO:
|
---|
423 | /** @todo */
|
---|
424 | break;
|
---|
425 | case TPM_LOCALITY_REG_DID_VID:
|
---|
426 | u32 = RT_H2BE_U32(RT_MAKE_U32(pThis->uVenId, pThis->uDevId));
|
---|
427 | break;
|
---|
428 | case TPM_LOCALITY_REG_RID:
|
---|
429 | u32 = pThis->bRevId;
|
---|
430 | break;
|
---|
431 | default: /* Return ~0. */
|
---|
432 | u32 = UINT32_MAX;
|
---|
433 | break;
|
---|
434 | }
|
---|
435 |
|
---|
436 | switch (cb)
|
---|
437 | {
|
---|
438 | case 1: *(uint8_t *)pv = (uint8_t)u32; break;
|
---|
439 | case 2: *(uint16_t *)pv = (uint16_t)u32; break;
|
---|
440 | case 4: *(uint32_t *)pv = u32; break;
|
---|
441 | default: AssertFailedBreakStmt(rc = VERR_INTERNAL_ERROR);
|
---|
442 | }
|
---|
443 |
|
---|
444 | return rc;
|
---|
445 | }
|
---|
446 |
|
---|
447 |
|
---|
448 | /**
|
---|
449 | * @callback_method_impl{FNIOMMMIONEWWRITE}
|
---|
450 | */
|
---|
451 | static DECLCALLBACK(VBOXSTRICTRC) tpmMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
|
---|
452 | {
|
---|
453 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
|
---|
454 | RT_NOREF(pvUser);
|
---|
455 |
|
---|
456 | Assert(!(off & (cb - 1)));
|
---|
457 |
|
---|
458 | uint32_t u32;
|
---|
459 | switch (cb)
|
---|
460 | {
|
---|
461 | case 1: u32 = *(const uint8_t *)pv; break;
|
---|
462 | case 2: u32 = *(const uint16_t *)pv; break;
|
---|
463 | case 4: u32 = *(const uint32_t *)pv; break;
|
---|
464 | default: AssertFailedReturn(VERR_INTERNAL_ERROR);
|
---|
465 | }
|
---|
466 |
|
---|
467 | LogFlowFunc((": %RGp %#x\n", off, u32));
|
---|
468 |
|
---|
469 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
470 | uint32_t uReg = tpmGetRegisterFromOffset(off);
|
---|
471 | uint8_t bLoc = tpmGetLocalityFromOffset(off);
|
---|
472 | PDEVTPMLOCALITY pLoc = &pThis->aLoc[bLoc];
|
---|
473 | switch (uReg)
|
---|
474 | {
|
---|
475 | case TPM_LOCALITY_REG_ACCESS:
|
---|
476 | u32 &= TPM_LOCALITY_REG_ACCESS_WR_MASK;
|
---|
477 | /*
|
---|
478 | * Chapter 5.6.11, 2 states that writing to this register with more than one
|
---|
479 | * bit set to '1' is vendor specific, we decide to ignore such writes to make the logic
|
---|
480 | * below simpler.
|
---|
481 | */
|
---|
482 | if (!RT_IS_POWER_OF_TWO(u32))
|
---|
483 | break;
|
---|
484 | /** @todo */
|
---|
485 | break;
|
---|
486 | case TPM_LOCALITY_REG_INT_ENABLE:
|
---|
487 | if (bLoc != pThis->bLoc)
|
---|
488 | break;
|
---|
489 | /** @todo */
|
---|
490 | break;
|
---|
491 | case TPM_LOCALITY_REG_INT_STS:
|
---|
492 | if (bLoc != pThis->bLoc)
|
---|
493 | break;
|
---|
494 | pLoc->uRegSts &= ~(u32 & TPM_LOCALITY_REG_INT_STS_WR_MASK);
|
---|
495 | tpmLocIrqUpdate(pDevIns, pThis, pLoc);
|
---|
496 | break;
|
---|
497 | case TPM_LOCALITY_REG_STS:
|
---|
498 | /*
|
---|
499 | * Writes are ignored completely if the locality being accessed is not the
|
---|
500 | * current active one or if the value has multiple bits set (not a power of two),
|
---|
501 | * see chapter 5.6.12.1.
|
---|
502 | */
|
---|
503 | if ( bLoc != pThis->bLoc
|
---|
504 | || !RT_IS_POWER_OF_TWO(u32))
|
---|
505 | break;
|
---|
506 | /** @todo */
|
---|
507 | break;
|
---|
508 | case TPM_LOCALITY_REG_DATA_FIFO:
|
---|
509 | case TPM_LOCALITY_REG_DATA_XFIFO:
|
---|
510 | if (bLoc != pThis->bLoc)
|
---|
511 | break;
|
---|
512 | /** @todo */
|
---|
513 | break;
|
---|
514 | case TPM_LOCALITY_REG_INT_VEC:
|
---|
515 | case TPM_LOCALITY_REG_IF_CAP:
|
---|
516 | case TPM_LOCALITY_REG_DID_VID:
|
---|
517 | case TPM_LOCALITY_REG_RID:
|
---|
518 | default: /* Ignore. */
|
---|
519 | break;
|
---|
520 | }
|
---|
521 |
|
---|
522 | return rc;
|
---|
523 | }
|
---|
524 |
|
---|
525 |
|
---|
526 | #ifdef IN_RING3
|
---|
527 |
|
---|
528 |
|
---|
529 | /* -=-=-=-=-=-=-=-=- Saved State -=-=-=-=-=-=-=-=- */
|
---|
530 |
|
---|
531 | /**
|
---|
532 | * @callback_method_impl{FNSSMDEVLIVEEXEC}
|
---|
533 | */
|
---|
534 | static DECLCALLBACK(int) tpmR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
|
---|
535 | {
|
---|
536 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
|
---|
537 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
538 | RT_NOREF(uPass);
|
---|
539 |
|
---|
540 | pHlp->pfnSSMPutU8(pSSM, pThis->uIrq);
|
---|
541 | return VINF_SSM_DONT_CALL_AGAIN;
|
---|
542 | }
|
---|
543 |
|
---|
544 |
|
---|
545 | /**
|
---|
546 | * @callback_method_impl{FNSSMDEVSAVEEXEC}
|
---|
547 | */
|
---|
548 | static DECLCALLBACK(int) tpmR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
549 | {
|
---|
550 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
|
---|
551 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
552 |
|
---|
553 | pHlp->pfnSSMPutU8(pSSM, pThis->uIrq);
|
---|
554 |
|
---|
555 | return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* sanity/terminator */
|
---|
556 | }
|
---|
557 |
|
---|
558 |
|
---|
559 | /**
|
---|
560 | * @callback_method_impl{FNSSMDEVLOADEXEC}
|
---|
561 | */
|
---|
562 | static DECLCALLBACK(int) tpmR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
563 | {
|
---|
564 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
|
---|
565 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
566 | uint8_t bIrq;
|
---|
567 | int rc;
|
---|
568 |
|
---|
569 | AssertMsgReturn(uVersion >= TPM_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
|
---|
570 | pHlp->pfnSSMGetU8( pSSM, &bIrq);
|
---|
571 | if (uPass == SSM_PASS_FINAL)
|
---|
572 | {
|
---|
573 | /* The marker. */
|
---|
574 | uint32_t u32;
|
---|
575 | rc = pHlp->pfnSSMGetU32(pSSM, &u32);
|
---|
576 | AssertRCReturn(rc, rc);
|
---|
577 | AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
|
---|
578 | }
|
---|
579 |
|
---|
580 | /*
|
---|
581 | * Check the config.
|
---|
582 | */
|
---|
583 | if (pThis->uIrq != bIrq)
|
---|
584 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
|
---|
585 | N_("Config mismatch - saved IRQ=%#x; configured IRQ=%#x"),
|
---|
586 | bIrq, pThis->uIrq);
|
---|
587 |
|
---|
588 | return VINF_SUCCESS;
|
---|
589 | }
|
---|
590 |
|
---|
591 |
|
---|
592 | /* -=-=-=-=-=-=-=-=- PDMDEVREG -=-=-=-=-=-=-=-=- */
|
---|
593 |
|
---|
594 | /**
|
---|
595 | * @interface_method_impl{PDMDEVREG,pfnReset}
|
---|
596 | */
|
---|
597 | static DECLCALLBACK(void) tpmR3Reset(PPDMDEVINS pDevIns)
|
---|
598 | {
|
---|
599 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
|
---|
600 |
|
---|
601 | pThis->bLoc = TPM_NO_LOCALITY_SELECTED;
|
---|
602 | for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aLoc); i++)
|
---|
603 | {
|
---|
604 | PDEVTPMLOCALITY pLoc = &pThis->aLoc[i];
|
---|
605 |
|
---|
606 | pLoc->enmState = DEVTPMLOCALITYSTATE_INIT;
|
---|
607 | pLoc->aRegIntEn = 0;
|
---|
608 | pLoc->aRegIntSts = 0;
|
---|
609 | }
|
---|
610 | }
|
---|
611 |
|
---|
612 |
|
---|
613 | /**
|
---|
614 | * @interface_method_impl{PDMDEVREG,pfnDestruct}
|
---|
615 | */
|
---|
616 | static DECLCALLBACK(int) tpmR3Destruct(PPDMDEVINS pDevIns)
|
---|
617 | {
|
---|
618 | PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
|
---|
619 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
|
---|
620 |
|
---|
621 | /** @todo */
|
---|
622 | RT_NOREF(pThis);
|
---|
623 | return VINF_SUCCESS;
|
---|
624 | }
|
---|
625 |
|
---|
626 |
|
---|
627 | /**
|
---|
628 | * @interface_method_impl{PDMDEVREG,pfnConstruct}
|
---|
629 | */
|
---|
630 | static DECLCALLBACK(int) tpmR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
|
---|
631 | {
|
---|
632 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
633 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
|
---|
634 | //PDEVTPMCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMCC);
|
---|
635 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
636 | int rc;
|
---|
637 |
|
---|
638 | RT_NOREF(iInstance);
|
---|
639 |
|
---|
640 | /*
|
---|
641 | * Validate and read the configuration.
|
---|
642 | */
|
---|
643 | PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Irq"
|
---|
644 | "|MmioBase"
|
---|
645 | "|VendorId"
|
---|
646 | "|DeviceId"
|
---|
647 | "|RevisionId",
|
---|
648 | "");
|
---|
649 |
|
---|
650 | uint8_t uIrq = 0;
|
---|
651 | rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Irq", &uIrq, 10);
|
---|
652 | if (RT_FAILURE(rc))
|
---|
653 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"Irq\" value"));
|
---|
654 |
|
---|
655 | RTGCPHYS GCPhysMmio;
|
---|
656 | rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioBase", &GCPhysMmio, TPM_MMIO_BASE_DEFAULT);
|
---|
657 | if (RT_FAILURE(rc))
|
---|
658 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
659 | N_("Configuration error: Failed to get the \"MmioBase\" value"));
|
---|
660 |
|
---|
661 | rc = pHlp->pfnCFGMQueryU16Def(pCfg, "VendorId", &pThis->uDevId, TPM_VID_DEFAULT);
|
---|
662 | if (RT_FAILURE(rc))
|
---|
663 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"VendorId\" value"));
|
---|
664 |
|
---|
665 | rc = pHlp->pfnCFGMQueryU16Def(pCfg, "DeviceId", &pThis->uDevId, TPM_DID_DEFAULT);
|
---|
666 | if (RT_FAILURE(rc))
|
---|
667 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"DeviceId\" value"));
|
---|
668 |
|
---|
669 | rc = pHlp->pfnCFGMQueryU8Def(pCfg, "RevisionId", &pThis->bRevId, TPM_RID_DEFAULT);
|
---|
670 | if (RT_FAILURE(rc))
|
---|
671 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"RevisionId\" value"));
|
---|
672 |
|
---|
673 | pThis->uIrq = uIrq;
|
---|
674 |
|
---|
675 | /*
|
---|
676 | * Register the MMIO range, PDM API requests page aligned
|
---|
677 | * addresses and sizes.
|
---|
678 | */
|
---|
679 | rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmio, TPM_MMIO_SIZE, tpmMmioWrite, tpmMmioRead,
|
---|
680 | IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
|
---|
681 | "TPM MMIO", &pThis->hMmio);
|
---|
682 | AssertRCReturn(rc, rc);
|
---|
683 |
|
---|
684 | /*
|
---|
685 | * Saved state.
|
---|
686 | */
|
---|
687 | rc = PDMDevHlpSSMRegister3(pDevIns, TPM_SAVED_STATE_VERSION, sizeof(*pThis),
|
---|
688 | tpmR3LiveExec, tpmR3SaveExec, tpmR3LoadExec);
|
---|
689 | AssertRCReturn(rc, rc);
|
---|
690 |
|
---|
691 | tpmR3Reset(pDevIns);
|
---|
692 | return VINF_SUCCESS;
|
---|
693 | }
|
---|
694 |
|
---|
695 | #else /* !IN_RING3 */
|
---|
696 |
|
---|
697 | /**
|
---|
698 | * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
|
---|
699 | */
|
---|
700 | static DECLCALLBACK(int) tpmRZConstruct(PPDMDEVINS pDevIns)
|
---|
701 | {
|
---|
702 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
703 | PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
|
---|
704 | PDEVTPMCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMCC);
|
---|
705 |
|
---|
706 | int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, tpmMmioWrite, tpmMmioRead, NULL /*pvUser*/);
|
---|
707 | AssertRCReturn(rc, rc);
|
---|
708 |
|
---|
709 | return VINF_SUCCESS;
|
---|
710 | }
|
---|
711 |
|
---|
712 | #endif /* !IN_RING3 */
|
---|
713 |
|
---|
714 | /**
|
---|
715 | * The device registration structure.
|
---|
716 | */
|
---|
717 | const PDMDEVREG g_DeviceTpm =
|
---|
718 | {
|
---|
719 | /* .u32Version = */ PDM_DEVREG_VERSION,
|
---|
720 | /* .uReserved0 = */ 0,
|
---|
721 | /* .szName = */ "tpm",
|
---|
722 | /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
|
---|
723 | /* .fClass = */ PDM_DEVREG_CLASS_SERIAL,
|
---|
724 | /* .cMaxInstances = */ 1,
|
---|
725 | /* .uSharedVersion = */ 42,
|
---|
726 | /* .cbInstanceShared = */ sizeof(DEVTPM),
|
---|
727 | /* .cbInstanceCC = */ sizeof(DEVTPMCC),
|
---|
728 | /* .cbInstanceRC = */ sizeof(DEVTPMRC),
|
---|
729 | /* .cMaxPciDevices = */ 0,
|
---|
730 | /* .cMaxMsixVectors = */ 0,
|
---|
731 | /* .pszDescription = */ "Trusted Platform Module",
|
---|
732 | #if defined(IN_RING3)
|
---|
733 | /* .pszRCMod = */ "VBoxDDRC.rc",
|
---|
734 | /* .pszR0Mod = */ "VBoxDDR0.r0",
|
---|
735 | /* .pfnConstruct = */ tpmR3Construct,
|
---|
736 | /* .pfnDestruct = */ tpmR3Destruct,
|
---|
737 | /* .pfnRelocate = */ NULL,
|
---|
738 | /* .pfnMemSetup = */ NULL,
|
---|
739 | /* .pfnPowerOn = */ NULL,
|
---|
740 | /* .pfnReset = */ tpmR3Reset,
|
---|
741 | /* .pfnSuspend = */ NULL,
|
---|
742 | /* .pfnResume = */ NULL,
|
---|
743 | /* .pfnAttach = */ NULL,
|
---|
744 | /* .pfnDetach = */ NULL,
|
---|
745 | /* .pfnQueryInterface = */ NULL,
|
---|
746 | /* .pfnInitComplete = */ NULL,
|
---|
747 | /* .pfnPowerOff = */ NULL,
|
---|
748 | /* .pfnSoftReset = */ NULL,
|
---|
749 | /* .pfnReserved0 = */ NULL,
|
---|
750 | /* .pfnReserved1 = */ NULL,
|
---|
751 | /* .pfnReserved2 = */ NULL,
|
---|
752 | /* .pfnReserved3 = */ NULL,
|
---|
753 | /* .pfnReserved4 = */ NULL,
|
---|
754 | /* .pfnReserved5 = */ NULL,
|
---|
755 | /* .pfnReserved6 = */ NULL,
|
---|
756 | /* .pfnReserved7 = */ NULL,
|
---|
757 | #elif defined(IN_RING0)
|
---|
758 | /* .pfnEarlyConstruct = */ NULL,
|
---|
759 | /* .pfnConstruct = */ tpmRZConstruct,
|
---|
760 | /* .pfnDestruct = */ NULL,
|
---|
761 | /* .pfnFinalDestruct = */ NULL,
|
---|
762 | /* .pfnRequest = */ NULL,
|
---|
763 | /* .pfnReserved0 = */ NULL,
|
---|
764 | /* .pfnReserved1 = */ NULL,
|
---|
765 | /* .pfnReserved2 = */ NULL,
|
---|
766 | /* .pfnReserved3 = */ NULL,
|
---|
767 | /* .pfnReserved4 = */ NULL,
|
---|
768 | /* .pfnReserved5 = */ NULL,
|
---|
769 | /* .pfnReserved6 = */ NULL,
|
---|
770 | /* .pfnReserved7 = */ NULL,
|
---|
771 | #elif defined(IN_RC)
|
---|
772 | /* .pfnConstruct = */ tpmRZConstruct,
|
---|
773 | /* .pfnReserved0 = */ NULL,
|
---|
774 | /* .pfnReserved1 = */ NULL,
|
---|
775 | /* .pfnReserved2 = */ NULL,
|
---|
776 | /* .pfnReserved3 = */ NULL,
|
---|
777 | /* .pfnReserved4 = */ NULL,
|
---|
778 | /* .pfnReserved5 = */ NULL,
|
---|
779 | /* .pfnReserved6 = */ NULL,
|
---|
780 | /* .pfnReserved7 = */ NULL,
|
---|
781 | #else
|
---|
782 | # error "Not in IN_RING3, IN_RING0 or IN_RC!"
|
---|
783 | #endif
|
---|
784 | /* .u32VersionEnd = */ PDM_DEVREG_VERSION
|
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785 | };
|
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786 |
|
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787 | #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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788 |
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