VirtualBox

source: vbox/trunk/src/VBox/Devices/Serial/DevSerial.cpp@ 29853

Last change on this file since 29853 was 29846, checked in by vboxsync, 15 years ago

Devices/Serial: update the implementation to 16550A
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1/* $Id: DevSerial.cpp 29846 2010-05-27 16:25:28Z vboxsync $ */
2/** @file
3 * DevSerial - 16550A UART emulation.
4 * (taken from hw/serial.c 2010/05/15 with modifications)
5 */
6
7/*
8 * Copyright (C) 2006-2010 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 */
18
19/*
20 * This code is based on:
21 *
22 * QEMU 16550A UART emulation
23 *
24 * Copyright (c) 2003-2004 Fabrice Bellard
25 * Copyright (c) 2008 Citrix Systems, Inc.
26 *
27 * Permission is hereby granted, free of charge, to any person obtaining a copy
28 * of this software and associated documentation files (the "Software"), to deal
29 * in the Software without restriction, including without limitation the rights
30 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
31 * copies of the Software, and to permit persons to whom the Software is
32 * furnished to do so, subject to the following conditions:
33 *
34 * The above copyright notice and this permission notice shall be included in
35 * all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
38 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
39 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
40 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
41 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
42 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
43 * THE SOFTWARE.
44 */
45
46/*******************************************************************************
47* Header Files *
48*******************************************************************************/
49#define LOG_GROUP LOG_GROUP_DEV_SERIAL
50#include <VBox/pdmdev.h>
51#include <iprt/assert.h>
52#include <iprt/uuid.h>
53#include <iprt/string.h>
54#include <iprt/semaphore.h>
55#include <iprt/critsect.h>
56
57#include "../Builtins.h"
58
59#undef VBOX_SERIAL_PCI /* The PCI variant has lots of problems: wrong IRQ line and wrong IO base assigned. */
60
61#ifdef VBOX_SERIAL_PCI
62# include <VBox/pci.h>
63#endif /* VBOX_SERIAL_PCI */
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69#define SERIAL_SAVED_STATE_VERSION 3
70
71#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
72
73#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
74#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
75#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
76#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
77
78#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
79#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
80
81#define UART_IIR_MSI 0x00 /* Modem status interrupt */
82#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
83#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
84#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
85#define UART_IIR_CTI 0x0C /* Character Timeout Indication */
86
87#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
88#define UART_IIR_FE 0xC0 /* Fifo enabled */
89
90/*
91 * These are the definitions for the Modem Control Register
92 */
93#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
94#define UART_MCR_OUT2 0x08 /* Out2 complement */
95#define UART_MCR_OUT1 0x04 /* Out1 complement */
96#define UART_MCR_RTS 0x02 /* RTS complement */
97#define UART_MCR_DTR 0x01 /* DTR complement */
98
99/*
100 * These are the definitions for the Modem Status Register
101 */
102#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
103#define UART_MSR_RI 0x40 /* Ring Indicator */
104#define UART_MSR_DSR 0x20 /* Data Set Ready */
105#define UART_MSR_CTS 0x10 /* Clear to Send */
106#define UART_MSR_DDCD 0x08 /* Delta DCD */
107#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
108#define UART_MSR_DDSR 0x02 /* Delta DSR */
109#define UART_MSR_DCTS 0x01 /* Delta CTS */
110#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
111
112#define UART_LSR_TEMT 0x40 /* Transmitter empty */
113#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
114#define UART_LSR_BI 0x10 /* Break interrupt indicator */
115#define UART_LSR_FE 0x08 /* Frame error indicator */
116#define UART_LSR_PE 0x04 /* Parity error indicator */
117#define UART_LSR_OE 0x02 /* Overrun error indicator */
118#define UART_LSR_DR 0x01 /* Receiver data ready */
119#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
120
121/*
122 * Interrupt trigger levels.
123 * The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher.
124 */
125#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
126#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
127#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
128#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
129
130#define UART_FCR_DMS 0x08 /* DMA Mode Select */
131#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
132#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
133#define UART_FCR_FE 0x01 /* FIFO Enable */
134
135#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
136
137#define XMIT_FIFO 0
138#define RECV_FIFO 1
139#define MAX_XMIT_RETRY 8
140
141/*******************************************************************************
142* Structures and Typedefs *
143*******************************************************************************/
144
145struct SerialFifo
146{
147 uint8_t data[UART_FIFO_LENGTH];
148 uint8_t count;
149 uint8_t itl;
150 uint8_t tail;
151 uint8_t head;
152};
153
154/**
155 * Serial device.
156 *
157 * @implements PDMIBASE
158 * @implements PDMICHARPORT
159 */
160struct SerialState
161{
162 /** Access critical section. */
163 PDMCRITSECT CritSect;
164 /** Pointer to the device instance - R3 Ptr. */
165 PPDMDEVINSR3 pDevInsR3;
166 /** Pointer to the device instance - R0 Ptr. */
167 PPDMDEVINSR0 pDevInsR0;
168 /** Pointer to the device instance - RC Ptr. */
169 PPDMDEVINSRC pDevInsRC;
170 /** Alignment. */
171 RTRCPTR Alignment0;
172 /** LUN\#0: The base interface. */
173 PDMIBASE IBase;
174 /** LUN\#0: The character port interface. */
175 PDMICHARPORT ICharPort;
176 /** Pointer to the attached base driver. */
177 R3PTRTYPE(PPDMIBASE) pDrvBase;
178 /** Pointer to the attached character driver. */
179 R3PTRTYPE(PPDMICHARCONNECTOR) pDrvChar;
180
181 RTSEMEVENT ReceiveSem;
182 PTMTIMERR3 fifo_timeout_timer;
183 PTMTIMERR3 transmit_timerR3;
184 PTMTIMERR0 transmit_timerR0; /* currently not used */
185 PTMTIMERRC transmit_timerRC; /* currently not used */
186 RTRCPTR Alignment1;
187 SerialFifo recv_fifo;
188 SerialFifo xmit_fifo;
189
190 uint32_t base;
191 uint16_t divider;
192 uint16_t Alignment2[1];
193 uint8_t rbr; /**< receive register */
194 uint8_t thr; /**< transmit holding register */
195 uint8_t tsr; /**< transmit shift register */
196 uint8_t ier; /**< interrupt enable register */
197 uint8_t iir; /**< interrupt itentification register, R/O */
198 uint8_t lcr; /**< line control register */
199 uint8_t mcr; /**< modem control register */
200 uint8_t lsr; /**< line status register, R/O */
201 uint8_t msr; /**< modem status register, R/O */
202 uint8_t scr; /**< scratch register */
203 uint8_t fcr; /**< fifo control register */
204 uint8_t fcr_vmstate;
205 /* NOTE: this hidden state is necessary for tx irq generation as
206 it can be reset while reading iir */
207 int thr_ipending;
208 int timeout_ipending;
209 int irq;
210 int last_break_enable;
211 /** Counter for retrying xmit */
212 int tsr_retry;
213 bool msr_changed;
214 bool fGCEnabled;
215 bool fR0Enabled;
216 bool fYieldOnLSRRead;
217 bool volatile fRecvWaiting;
218 bool Alignment3[3];
219 /** Time it takes to transmit a character */
220 uint64_t char_transmit_time;
221
222#ifdef VBOX_SERIAL_PCI
223 PCIDEVICE dev;
224#endif /* VBOX_SERIAL_PCI */
225};
226
227#ifndef VBOX_DEVICE_STRUCT_TESTCASE
228
229
230#ifdef VBOX_SERIAL_PCI
231#define PCIDEV_2_SERIALSTATE(pPciDev) ( (SerialState *)((uintptr_t)(pPciDev) - RT_OFFSETOF(SerialState, dev)) )
232#endif /* VBOX_SERIAL_PCI */
233#define PDMIBASE_2_SERIALSTATE(pInstance) ( (SerialState *)((uintptr_t)(pInterface) - RT_OFFSETOF(SerialState, IBase)) )
234#define PDMICHARPORT_2_SERIALSTATE(pInstance) ( (SerialState *)((uintptr_t)(pInterface) - RT_OFFSETOF(SerialState, ICharPort)) )
235
236
237/*******************************************************************************
238* Internal Functions *
239*******************************************************************************/
240RT_C_DECLS_BEGIN
241PDMBOTHCBDECL(int) serialIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
242PDMBOTHCBDECL(int) serialIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
243RT_C_DECLS_END
244
245#ifdef IN_RING3
246
247static int serial_can_receive(SerialState *s);
248static void serial_receive(void *opaque, const uint8_t *buf, int size);
249
250static void fifo_clear(SerialState *s, int fifo)
251{
252 SerialFifo *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
253 memset(f->data, 0, UART_FIFO_LENGTH);
254 f->count = 0;
255 f->head = 0;
256 f->tail = 0;
257}
258
259static int fifo_put(SerialState *s, int fifo, uint8_t chr)
260{
261 SerialFifo *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
262
263 /* Receive overruns do not overwrite FIFO contents. */
264 if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH)
265 {
266 f->data[f->head++] = chr;
267 if (f->head == UART_FIFO_LENGTH)
268 f->head = 0;
269 }
270
271 if (f->count < UART_FIFO_LENGTH)
272 f->count++;
273 else if (fifo == RECV_FIFO)
274 s->lsr |= UART_LSR_OE;
275
276 return 1;
277}
278
279static uint8_t fifo_get(SerialState *s, int fifo)
280{
281 SerialFifo *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
282 uint8_t c;
283
284 if (f->count == 0)
285 return 0;
286
287 c = f->data[f->tail++];
288 if (f->tail == UART_FIFO_LENGTH)
289 f->tail = 0;
290 f->count--;
291
292 return c;
293}
294
295static void serial_update_irq(SerialState *s)
296{
297 uint8_t tmp_iir = UART_IIR_NO_INT;
298
299 if ( (s->ier & UART_IER_RLSI)
300 && (s->lsr & UART_LSR_INT_ANY)) {
301 tmp_iir = UART_IIR_RLSI;
302 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
303 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
304 * this is not in the specification but is observed on existing
305 * hardware. */
306 tmp_iir = UART_IIR_CTI;
307 } else if ( (s->ier & UART_IER_RDI)
308 && (s->lsr & UART_LSR_DR)
309 && ( !(s->fcr & UART_FCR_FE)
310 || s->recv_fifo.count >= s->recv_fifo.itl)) {
311 tmp_iir = UART_IIR_RDI;
312 } else if ( (s->ier & UART_IER_THRI)
313 && s->thr_ipending) {
314 tmp_iir = UART_IIR_THRI;
315 } else if ( (s->ier & UART_IER_MSI)
316 && (s->msr & UART_MSR_ANY_DELTA)) {
317 tmp_iir = UART_IIR_MSI;
318 }
319 s->iir = tmp_iir | (s->iir & 0xF0);
320
321 /** XXX only call the SetIrq function if the state really changes! */
322 if (tmp_iir != UART_IIR_NO_INT) {
323 Log(("serial_update_irq %d 1\n", s->irq));
324# ifdef VBOX_SERIAL_PCI
325 PDMDevHlpPCISetIrqNoWait(s->CTX_SUFF(pDevIns), 0, 1);
326# else /* !VBOX_SERIAL_PCI */
327 PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 1);
328# endif /* !VBOX_SERIAL_PCI */
329 } else {
330 Log(("serial_update_irq %d 0\n", s->irq));
331# ifdef VBOX_SERIAL_PCI
332 PDMDevHlpPCISetIrqNoWait(s->CTX_SUFF(pDevIns), 0, 0);
333# else /* !VBOX_SERIAL_PCI */
334 PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 0);
335# endif /* !VBOX_SERIAL_PCI */
336 }
337}
338
339static void serial_update_parameters(SerialState *s)
340{
341 int speed, parity, data_bits, stop_bits, frame_size;
342
343 if (s->divider == 0)
344 return;
345
346 frame_size = 1;
347 if (s->lcr & 0x08) {
348 frame_size++;
349 if (s->lcr & 0x10)
350 parity = 'E';
351 else
352 parity = 'O';
353 } else {
354 parity = 'N';
355 }
356 if (s->lcr & 0x04)
357 stop_bits = 2;
358 else
359 stop_bits = 1;
360
361 data_bits = (s->lcr & 0x03) + 5;
362 frame_size += data_bits + stop_bits;
363 speed = 115200 / s->divider;
364 s->char_transmit_time = (TMTimerGetFreq(CTX_SUFF(s->transmit_timer)) / speed) * frame_size;
365 Log(("speed=%d parity=%c data=%d stop=%d\n", speed, parity, data_bits, stop_bits));
366
367 if (RT_LIKELY(s->pDrvChar))
368 s->pDrvChar->pfnSetParameters(s->pDrvChar, speed, parity, data_bits, stop_bits);
369}
370
371static void serial_xmit(void *opaque)
372{
373 SerialState *s = (SerialState*)opaque;
374 uint64_t new_xmit_ts = TMTimerGet(CTX_SUFF(s->transmit_timer));
375
376 if (s->tsr_retry <= 0) {
377 if (s->fcr & UART_FCR_FE) {
378 s->tsr = fifo_get(s, XMIT_FIFO);
379 if (!s->xmit_fifo.count)
380 s->lsr |= UART_LSR_THRE;
381 } else {
382 s->tsr = s->thr;
383 s->lsr |= UART_LSR_THRE;
384 }
385 }
386
387 if (s->mcr & UART_MCR_LOOP) {
388 /* in loopback mode, say that we just received a char */
389 serial_receive(s, &s->tsr, 1);
390 } else if ( RT_LIKELY(s->pDrvChar)
391 && RT_FAILURE(s->pDrvChar->pfnWrite(s->pDrvChar, &s->tsr, 1))) {
392 if ((s->tsr_retry >= 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
393 s->tsr_retry++;
394 TMTimerSet(CTX_SUFF(s->transmit_timer), new_xmit_ts + s->char_transmit_time);
395 return;
396 } else {
397 /* drop this character. */
398 s->tsr_retry = 0;
399 }
400 }
401 else {
402 s->tsr_retry = 0;
403 }
404
405 if (!(s->lsr & UART_LSR_THRE))
406 TMTimerSet(CTX_SUFF(s->transmit_timer),
407 TMTimerGet(CTX_SUFF(s->transmit_timer)) + s->char_transmit_time);
408
409 if (s->lsr & UART_LSR_THRE) {
410 s->lsr |= UART_LSR_TEMT;
411 s->thr_ipending = 1;
412 serial_update_irq(s);
413 }
414}
415
416#endif /* IN_RING3 */
417
418static int serial_ioport_write(SerialState *s, uint32_t addr, uint32_t val)
419{
420 addr &= 7;
421
422#ifndef IN_RING3
423 NOREF(s);
424 return VINF_IOM_HC_IOPORT_WRITE;
425#else
426 switch(addr) {
427 default:
428 case 0:
429 if (s->lcr & UART_LCR_DLAB) {
430 s->divider = (s->divider & 0xff00) | val;
431 serial_update_parameters(s);
432 } else {
433 s->thr = (uint8_t) val;
434 if (s->fcr & UART_FCR_FE) {
435 fifo_put(s, XMIT_FIFO, s->thr);
436 s->thr_ipending = 0;
437 s->lsr &= ~UART_LSR_TEMT;
438 s->lsr &= ~UART_LSR_THRE;
439 serial_update_irq(s);
440 } else {
441 s->thr_ipending = 0;
442 s->lsr &= ~UART_LSR_THRE;
443 serial_update_irq(s);
444 }
445 serial_xmit(s);
446 }
447 break;
448 case 1:
449 if (s->lcr & UART_LCR_DLAB) {
450 s->divider = (s->divider & 0x00ff) | (val << 8);
451 serial_update_parameters(s);
452 } else {
453 s->ier = val & 0x0f;
454 if (s->lsr & UART_LSR_THRE) {
455 s->thr_ipending = 1;
456 serial_update_irq(s);
457 }
458 }
459 break;
460 case 2:
461 val = val & 0xFF;
462
463 if (s->fcr == val)
464 break;
465
466 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
467 if ((val ^ s->fcr) & UART_FCR_FE)
468 val |= UART_FCR_XFR | UART_FCR_RFR;
469
470 /* FIFO clear */
471 if (val & UART_FCR_RFR) {
472 TMTimerStop(s->fifo_timeout_timer);
473 s->timeout_ipending = 0;
474 fifo_clear(s, RECV_FIFO);
475 }
476 if (val & UART_FCR_XFR) {
477 fifo_clear(s, XMIT_FIFO);
478 }
479
480 if (val & UART_FCR_FE) {
481 s->iir |= UART_IIR_FE;
482 /* Set RECV_FIFO trigger Level */
483 switch (val & 0xC0) {
484 case UART_FCR_ITL_1:
485 s->recv_fifo.itl = 1;
486 break;
487 case UART_FCR_ITL_2:
488 s->recv_fifo.itl = 4;
489 break;
490 case UART_FCR_ITL_3:
491 s->recv_fifo.itl = 8;
492 break;
493 case UART_FCR_ITL_4:
494 s->recv_fifo.itl = 14;
495 break;
496 }
497 } else
498 s->iir &= ~UART_IIR_FE;
499
500 /* Set fcr - or at least the bits in it that are supposed to "stick" */
501 s->fcr = val & 0xC9;
502 serial_update_irq(s);
503 break;
504 case 3:
505 {
506 int break_enable;
507 s->lcr = val;
508 serial_update_parameters(s);
509 break_enable = (val >> 6) & 1;
510 if (break_enable != s->last_break_enable) {
511 s->last_break_enable = break_enable;
512 if (RT_LIKELY(s->pDrvChar))
513 {
514 Log(("serial_ioport_write: Set break %d\n", break_enable));
515 int rc = s->pDrvChar->pfnSetBreak(s->pDrvChar, !!break_enable);
516 AssertRC(rc);
517 }
518 }
519 }
520 break;
521 case 4:
522 s->mcr = val & 0x1f;
523 if (RT_LIKELY(s->pDrvChar))
524 {
525 int rc = s->pDrvChar->pfnSetModemLines(s->pDrvChar,
526 !!(s->mcr & UART_MCR_RTS),
527 !!(s->mcr & UART_MCR_DTR));
528 AssertRC(rc);
529 }
530 break;
531 case 5:
532 break;
533 case 6:
534 break;
535 case 7:
536 s->scr = val;
537 break;
538 }
539 return VINF_SUCCESS;
540#endif
541}
542
543static uint32_t serial_ioport_read(void *opaque, uint32_t addr, int *pRC)
544{
545 SerialState *s = (SerialState *)opaque;
546 uint32_t ret = ~0U;
547
548 *pRC = VINF_SUCCESS;
549
550 addr &= 7;
551 switch(addr) {
552 default:
553 case 0:
554 if (s->lcr & UART_LCR_DLAB) {
555 /* DLAB == 1: divisor latch (LS) */
556 ret = s->divider & 0xff;
557 } else {
558#ifndef IN_RING3
559 *pRC = VINF_IOM_HC_IOPORT_READ;
560#else
561 if (s->fcr & UART_FCR_FE) {
562 ret = fifo_get(s, RECV_FIFO);
563 if (s->recv_fifo.count == 0)
564 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
565 else
566 TMTimerSet(s->fifo_timeout_timer,
567 TMTimerGet(s->fifo_timeout_timer) + s->char_transmit_time * 4);
568 s->timeout_ipending = 0;
569 } else {
570 Log(("serial_io_port_read: read 0x%X\n", s->rbr));
571 ret = s->rbr;
572 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
573 }
574 serial_update_irq(s);
575 if (s->fRecvWaiting)
576 {
577 s->fRecvWaiting = false;
578 int rc = RTSemEventSignal(s->ReceiveSem);
579 AssertRC(rc);
580 }
581#endif
582 }
583 break;
584 case 1:
585 if (s->lcr & UART_LCR_DLAB) {
586 /* DLAB == 1: divisor latch (MS) */
587 ret = (s->divider >> 8) & 0xff;
588 } else {
589 ret = s->ier;
590 }
591 break;
592 case 2:
593#ifndef IN_RING3
594 *pRC = VINF_IOM_HC_IOPORT_READ;
595#else
596 ret = s->iir;
597 if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
598 s->thr_ipending = 0;
599 serial_update_irq(s);
600 }
601 /* reset msr changed bit */
602 s->msr_changed = false;
603#endif
604 break;
605 case 3:
606 ret = s->lcr;
607 break;
608 case 4:
609 ret = s->mcr;
610 break;
611 case 5:
612 if ((s->lsr & UART_LSR_DR) == 0 && s->fYieldOnLSRRead)
613 {
614 /* No data available and yielding is enabled, so yield in ring3. */
615#ifndef IN_RING3
616 *pRC = VINF_IOM_HC_IOPORT_READ;
617 break;
618#else
619 RTThreadYield ();
620#endif
621 }
622 ret = s->lsr;
623 /* Clear break and overrun interrupts */
624 if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
625#ifndef IN_RING3
626 *pRC = VINF_IOM_HC_IOPORT_READ;
627#else
628 s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
629 serial_update_irq(s);
630#endif
631 }
632 break;
633 case 6:
634 if (s->mcr & UART_MCR_LOOP) {
635 /* in loopback, the modem output pins are connected to the
636 inputs */
637 ret = (s->mcr & 0x0c) << 4;
638 ret |= (s->mcr & 0x02) << 3;
639 ret |= (s->mcr & 0x01) << 5;
640 } else {
641 ret = s->msr;
642 /* Clear delta bits & msr int after read, if they were set */
643 if (s->msr & UART_MSR_ANY_DELTA) {
644#ifndef IN_RING3
645 *pRC = VINF_IOM_HC_IOPORT_READ;
646#else
647 s->msr &= 0xF0;
648 serial_update_irq(s);
649#endif
650 }
651 }
652 break;
653 case 7:
654 ret = s->scr;
655 break;
656 }
657 return ret;
658}
659
660#ifdef IN_RING3
661
662static int serial_can_receive(SerialState *s)
663{
664 if (s->fcr & UART_FCR_FE) {
665 if (s->recv_fifo.count < UART_FIFO_LENGTH)
666 return (s->recv_fifo.count <= s->recv_fifo.itl)
667 ? s->recv_fifo.itl - s->recv_fifo.count : 1;
668 else
669 return 0;
670 } else {
671 return !(s->lsr & UART_LSR_DR);
672 }
673}
674
675static void serial_receive(void *opaque, const uint8_t *buf, int size)
676{
677 SerialState *s = (SerialState*)opaque;
678 if (s->fcr & UART_FCR_FE) {
679 int i;
680 for (i = 0; i < size; i++) {
681 fifo_put(s, RECV_FIFO, buf[i]);
682 }
683 s->lsr |= UART_LSR_DR;
684 /* call the timeout receive callback in 4 char transmit time */
685 TMTimerSet(s->fifo_timeout_timer, TMTimerGet(s->fifo_timeout_timer) + s->char_transmit_time * 4);
686 } else {
687 if (s->lsr & UART_LSR_DR)
688 s->lsr |= UART_LSR_OE;
689 s->rbr = buf[0];
690 s->lsr |= UART_LSR_DR;
691 }
692 serial_update_irq(s);
693}
694
695/** @copydoc PDMICHARPORT::pfnNotifyRead */
696static DECLCALLBACK(int) serialNotifyRead(PPDMICHARPORT pInterface, const void *pvBuf, size_t *pcbRead)
697{
698 SerialState *pThis = PDMICHARPORT_2_SERIALSTATE(pInterface);
699 const uint8_t *pu8Buf = (const uint8_t*)pvBuf;
700 size_t cbRead = *pcbRead;
701
702 PDMCritSectEnter(&pThis->CritSect, VERR_PERMISSION_DENIED);
703 for (; cbRead > 0; cbRead--, pu8Buf++)
704 {
705 if (!serial_can_receive(pThis))
706 {
707 /* If we cannot receive then wait for not more than 250ms. If we still
708 * cannot receive then the new character will either overwrite rbr
709 * or it will be dropped at fifo_put(). */
710 pThis->fRecvWaiting = true;
711 PDMCritSectLeave(&pThis->CritSect);
712 int rc = RTSemEventWait(pThis->ReceiveSem, 250);
713 PDMCritSectEnter(&pThis->CritSect, VERR_PERMISSION_DENIED);
714 }
715 serial_receive(pThis, &pu8Buf[0], 1);
716 }
717 PDMCritSectLeave(&pThis->CritSect);
718 return VINF_SUCCESS;
719}
720
721/** @copydoc PDMICHARPORT::pfnNotifyStatusLinesChanged */
722static DECLCALLBACK(int) serialNotifyStatusLinesChanged(PPDMICHARPORT pInterface, uint32_t newStatusLines)
723{
724 SerialState *pThis = PDMICHARPORT_2_SERIALSTATE(pInterface);
725 uint8_t newMsr = 0;
726
727 Log(("%s: pInterface=%p newStatusLines=%u\n", __FUNCTION__, pInterface, newStatusLines));
728
729 PDMCritSectEnter(&pThis->CritSect, VERR_PERMISSION_DENIED);
730
731 /* Set new states. */
732 if (newStatusLines & PDMICHARPORT_STATUS_LINES_DCD)
733 newMsr |= UART_MSR_DCD;
734 if (newStatusLines & PDMICHARPORT_STATUS_LINES_RI)
735 newMsr |= UART_MSR_RI;
736 if (newStatusLines & PDMICHARPORT_STATUS_LINES_DSR)
737 newMsr |= UART_MSR_DSR;
738 if (newStatusLines & PDMICHARPORT_STATUS_LINES_CTS)
739 newMsr |= UART_MSR_CTS;
740
741 /* Compare the old and the new states and set the delta bits accordingly. */
742 if ((newMsr & UART_MSR_DCD) != (pThis->msr & UART_MSR_DCD))
743 newMsr |= UART_MSR_DDCD;
744 if ((newMsr & UART_MSR_RI) == 1 && (pThis->msr & UART_MSR_RI) == 0)
745 newMsr |= UART_MSR_TERI;
746 if ((newMsr & UART_MSR_DSR) != (pThis->msr & UART_MSR_DSR))
747 newMsr |= UART_MSR_DDSR;
748 if ((newMsr & UART_MSR_CTS) != (pThis->msr & UART_MSR_CTS))
749 newMsr |= UART_MSR_DCTS;
750
751 pThis->msr = newMsr;
752 pThis->msr_changed = true;
753 serial_update_irq(pThis);
754
755 PDMCritSectLeave(&pThis->CritSect);
756
757 return VINF_SUCCESS;
758}
759
760/** @copydoc PDMICHARPORT::pfnNotifyBufferFull */
761static DECLCALLBACK(int) serialNotifyBufferFull(PPDMICHARPORT pInterface, bool fFull)
762{
763 return VINF_SUCCESS;
764}
765
766/** @copydoc PDMICHARPORT::pfnNotifyBreak */
767static DECLCALLBACK(int) serialNotifyBreak(PPDMICHARPORT pInterface)
768{
769 SerialState *pThis = PDMICHARPORT_2_SERIALSTATE(pInterface);
770
771 Log(("%s: pInterface=%p\n", __FUNCTION__, pInterface));
772
773 PDMCritSectEnter(&pThis->CritSect, VERR_PERMISSION_DENIED);
774
775 pThis->lsr |= UART_LSR_BI;
776 serial_update_irq(pThis);
777
778 PDMCritSectLeave(&pThis->CritSect);
779
780 return VINF_SUCCESS;
781}
782
783/**
784 * Fifo timer functions.
785 */
786static DECLCALLBACK(void) serialFifoTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
787{
788 SerialState *s = (SerialState*)pvUser;
789 if (s->recv_fifo.count)
790 {
791 s->timeout_ipending = 1;
792 serial_update_irq(s);
793 }
794}
795
796/**
797 * Transmit timer function.
798 * Just retry to transmit a character.
799 *
800 * @param pTimer The timer handle.
801 * @param pDevIns The device instance.
802 * @param pvUser The user pointer.
803 */
804static DECLCALLBACK(void) serialTransmitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
805{
806 SerialState *s = (SerialState*)pvUser;
807 serial_xmit(s);
808}
809
810/**
811 * Reset the serial device.
812 *
813 * @param pDevIns The device instance.
814 */
815static DECLCALLBACK(void) serialReset(PPDMDEVINS pDevIns)
816{
817 SerialState *s = PDMINS_2_DATA(pDevIns, SerialState *);
818
819 s->rbr = 0;
820 s->ier = 0;
821 s->iir = UART_IIR_NO_INT;
822 s->lcr = 0;
823 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
824 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
825 /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
826 s->divider = 0x0C;
827 s->mcr = UART_MCR_OUT2;
828 s->scr = 0;
829 s->tsr_retry = 0;
830 s->char_transmit_time = (TMTimerGetFreq(CTX_SUFF(s->transmit_timer)) / 9600) * 10;
831
832 fifo_clear(s, RECV_FIFO);
833 fifo_clear(s, XMIT_FIFO);
834
835 s->thr_ipending = 0;
836 s->last_break_enable = 0;
837# ifdef VBOX_SERIAL_PCI
838 PDMDevHlpPCISetIrqNoWait(s->CTX_SUFF(pDevIns), 0, 0);
839# else /* !VBOX_SERIAL_PCI */
840 PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 0);
841# endif /* !VBOX_SERIAL_PCI */
842}
843
844#endif /* IN_RING3 */
845
846/**
847 * Port I/O Handler for OUT operations.
848 *
849 * @returns VBox status code.
850 *
851 * @param pDevIns The device instance.
852 * @param pvUser User argument.
853 * @param Port Port number used for the IN operation.
854 * @param u32 The value to output.
855 * @param cb The value size in bytes.
856 */
857PDMBOTHCBDECL(int) serialIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,
858 RTIOPORT Port, uint32_t u32, unsigned cb)
859{
860 SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
861 int rc = VINF_SUCCESS;
862
863 if (cb == 1)
864 {
865 rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_IOPORT_WRITE);
866 if (rc == VINF_SUCCESS)
867 {
868 Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, Port, u32));
869 rc = serial_ioport_write(pThis, Port, u32);
870 PDMCritSectLeave(&pThis->CritSect);
871 }
872 }
873 else
874 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
875
876 return rc;
877}
878
879/**
880 * Port I/O Handler for IN operations.
881 *
882 * @returns VBox status code.
883 *
884 * @param pDevIns The device instance.
885 * @param pvUser User argument.
886 * @param Port Port number used for the IN operation.
887 * @param u32 The value to output.
888 * @param cb The value size in bytes.
889 */
890PDMBOTHCBDECL(int) serialIOPortRead(PPDMDEVINS pDevIns, void *pvUser,
891 RTIOPORT Port, uint32_t *pu32, unsigned cb)
892{
893 SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
894 int rc = VINF_SUCCESS;
895
896 if (cb == 1)
897 {
898 rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_IOPORT_READ);
899 if (rc == VINF_SUCCESS)
900 {
901 *pu32 = serial_ioport_read(pThis, Port, &rc);
902 Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, Port, *pu32));
903 PDMCritSectLeave(&pThis->CritSect);
904 }
905 }
906 else
907 rc = VERR_IOM_IOPORT_UNUSED;
908
909 return rc;
910}
911
912#ifdef IN_RING3
913
914/**
915 * @copydoc FNSSMDEVLIVEEXEC
916 */
917static DECLCALLBACK(int) serialLiveExec(PPDMDEVINS pDevIns,
918 PSSMHANDLE pSSM,
919 uint32_t uPass)
920{
921 SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
922 SSMR3PutS32(pSSM, pThis->irq);
923 SSMR3PutU32(pSSM, pThis->base);
924 return VINF_SSM_DONT_CALL_AGAIN;
925}
926
927/**
928 * @copydoc FNSSMDEVSAVEEXEC
929 */
930static DECLCALLBACK(int) serialSaveExec(PPDMDEVINS pDevIns,
931 PSSMHANDLE pSSM)
932{
933 SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
934
935 SSMR3PutU16(pSSM, pThis->divider);
936 SSMR3PutU8(pSSM, pThis->rbr);
937 SSMR3PutU8(pSSM, pThis->ier);
938 SSMR3PutU8(pSSM, pThis->lcr);
939 SSMR3PutU8(pSSM, pThis->mcr);
940 SSMR3PutU8(pSSM, pThis->lsr);
941 SSMR3PutU8(pSSM, pThis->msr);
942 SSMR3PutU8(pSSM, pThis->scr);
943 SSMR3PutS32(pSSM, pThis->thr_ipending);
944 SSMR3PutS32(pSSM, pThis->irq);
945 SSMR3PutS32(pSSM, pThis->last_break_enable);
946 SSMR3PutU32(pSSM, pThis->base);
947 SSMR3PutBool(pSSM, pThis->msr_changed);
948 return SSMR3PutU32(pSSM, ~0); /* sanity/terminator */
949}
950
951/**
952 * @copydoc FNSSMDEVLOADEXEC
953 */
954static DECLCALLBACK(int) serialLoadExec(PPDMDEVINS pDevIns,
955 PSSMHANDLE pSSM,
956 uint32_t uVersion,
957 uint32_t uPass)
958{
959 SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
960
961 AssertMsgReturn(uVersion == SERIAL_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
962
963 if (uPass == SSM_PASS_FINAL)
964 {
965 SSMR3GetU16(pSSM, &pThis->divider);
966 SSMR3GetU8(pSSM, &pThis->rbr);
967 SSMR3GetU8(pSSM, &pThis->ier);
968 SSMR3GetU8(pSSM, &pThis->lcr);
969 SSMR3GetU8(pSSM, &pThis->mcr);
970 SSMR3GetU8(pSSM, &pThis->lsr);
971 SSMR3GetU8(pSSM, &pThis->msr);
972 SSMR3GetU8(pSSM, &pThis->scr);
973 SSMR3GetS32(pSSM, &pThis->thr_ipending);
974 }
975
976 int32_t iIrq;
977 SSMR3GetS32(pSSM, &iIrq);
978
979 if (uPass == SSM_PASS_FINAL)
980 SSMR3GetS32(pSSM, &pThis->last_break_enable);
981
982 uint32_t IOBase;
983 int rc = SSMR3GetU32(pSSM, &IOBase);
984 AssertRCReturn(rc, rc);
985
986 if ( pThis->irq != iIrq
987 || pThis->base != IOBase)
988 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
989 N_("Config mismatch - saved irq=%#x iobase=%#x; configured irq=%#x iobase=%#x"),
990 iIrq, IOBase, pThis->irq, pThis->base);
991
992 if (uPass == SSM_PASS_FINAL)
993 {
994 SSMR3GetBool(pSSM, &pThis->msr_changed);
995
996 uint32_t u32;
997 rc = SSMR3GetU32(pSSM, &u32);
998 if (RT_FAILURE(rc))
999 return rc;
1000 AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1001
1002 if (pThis->lsr & UART_LSR_DR)
1003 {
1004 rc = RTSemEventSignal(pThis->ReceiveSem);
1005 AssertRC(rc);
1006 }
1007
1008 /* this isn't strictly necessary but cannot hurt... */
1009 pThis->pDevInsR3 = pDevIns;
1010 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1011 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1012 }
1013
1014 return VINF_SUCCESS;
1015}
1016
1017
1018/**
1019 * @copydoc FNPDMDEVRELOCATE
1020 */
1021static DECLCALLBACK(void) serialRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1022{
1023 SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
1024 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1025 pThis->transmit_timerRC = TMTimerRCPtr(pThis->transmit_timerR3);
1026}
1027
1028#ifdef VBOX_SERIAL_PCI
1029
1030static DECLCALLBACK(int) serialIOPortRegionMap(PPCIDEVICE pPciDev, /* unsigned */ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
1031{
1032 SerialState *pThis = PCIDEV_2_SERIALSTATE(pPciDev);
1033 int rc = VINF_SUCCESS;
1034
1035 Assert(enmType == PCI_ADDRESS_SPACE_IO);
1036 Assert(iRegion == 0);
1037 Assert(cb == 8);
1038 AssertMsg(RT_ALIGN(GCPhysAddress, 8) == GCPhysAddress, ("Expected 8 byte alignment. GCPhysAddress=%#x\n", GCPhysAddress));
1039
1040 pThis->base = (RTIOPORT)GCPhysAddress;
1041 LogRel(("Serial#%d: mapping I/O at %#06x\n", pThis->pDevIns->iInstance, pThis->base));
1042
1043 /*
1044 * Register our port IO handlers.
1045 */
1046 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress, 8, (void *)pThis,
1047 serial_io_write, serial_io_read, NULL, NULL, "SERIAL");
1048 AssertRC(rc);
1049 return rc;
1050}
1051
1052#endif /* VBOX_SERIAL_PCI */
1053
1054/**
1055 * @interface_method_impl{PDMIBASE, pfnQueryInterface}
1056 */
1057static DECLCALLBACK(void *) serialQueryInterface(PPDMIBASE pInterface, const char *pszIID)
1058{
1059 SerialState *pThis = PDMIBASE_2_SERIALSTATE(pInterface);
1060 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1061 PDMIBASE_RETURN_INTERFACE(pszIID, PDMICHARPORT, &pThis->ICharPort);
1062 return NULL;
1063}
1064
1065/**
1066 * Destruct a device instance.
1067 *
1068 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
1069 * resources can be freed correctly.
1070 *
1071 * @returns VBox status.
1072 * @param pDevIns The device instance data.
1073 */
1074static DECLCALLBACK(int) serialDestruct(PPDMDEVINS pDevIns)
1075{
1076 SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
1077 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1078
1079 RTSemEventDestroy(pThis->ReceiveSem);
1080 pThis->ReceiveSem = NIL_RTSEMEVENT;
1081
1082 PDMR3CritSectDelete(&pThis->CritSect);
1083 return VINF_SUCCESS;
1084}
1085
1086
1087/**
1088 * @interface_method_impl{PDMDEVREG, pfnConstruct}
1089 */
1090static DECLCALLBACK(int) serialConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1091{
1092 int rc;
1093 SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState*);
1094 uint16_t io_base;
1095 uint8_t irq_lvl;
1096
1097 Assert(iInstance < 4);
1098 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1099
1100 /*
1101 * Initialize the instance data.
1102 * (Do this early or the destructor might choke on something!)
1103 */
1104 pThis->pDevInsR3 = pDevIns;
1105 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1106 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1107
1108 /* IBase */
1109 pThis->IBase.pfnQueryInterface = serialQueryInterface;
1110
1111 /* ICharPort */
1112 pThis->ICharPort.pfnNotifyRead = serialNotifyRead;
1113 pThis->ICharPort.pfnNotifyStatusLinesChanged = serialNotifyStatusLinesChanged;
1114 pThis->ICharPort.pfnNotifyBufferFull = serialNotifyBufferFull;
1115 pThis->ICharPort.pfnNotifyBreak = serialNotifyBreak;
1116
1117#ifdef VBOX_SERIAL_PCI
1118 /* the PCI device */
1119 pThis->dev.config[0x00] = 0xee; /* Vendor: ??? */
1120 pThis->dev.config[0x01] = 0x80;
1121 pThis->dev.config[0x02] = 0x01; /* Device: ??? */
1122 pThis->dev.config[0x03] = 0x01;
1123 pThis->dev.config[0x04] = PCI_COMMAND_IOACCESS;
1124 pThis->dev.config[0x09] = 0x01; /* Programming interface: 16450 */
1125 pThis->dev.config[0x0a] = 0x00; /* Subclass: Serial controller */
1126 pThis->dev.config[0x0b] = 0x07; /* Class: Communication controller */
1127 pThis->dev.config[0x0e] = 0x00; /* Header type: standard */
1128 pThis->dev.config[0x3c] = irq_lvl; /* preconfigure IRQ number (0 = autoconfig)*/
1129 pThis->dev.config[0x3d] = 1; /* interrupt pin 0 */
1130#endif /* VBOX_SERIAL_PCI */
1131
1132 /*
1133 * Validate and read the configuration.
1134 */
1135 if (!CFGMR3AreValuesValid(pCfg, "IRQ\0" "IOBase\0" "GCEnabled\0" "R0Enabled\0" "YieldOnLSRRead\0"))
1136 {
1137 AssertMsgFailed(("serialConstruct Invalid configuration values\n"));
1138 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1139 }
1140
1141 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
1142 if (RT_FAILURE(rc))
1143 return PDMDEV_SET_ERROR(pDevIns, rc,
1144 N_("Configuration error: Failed to get the \"GCEnabled\" value"));
1145
1146 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
1147 if (RT_FAILURE(rc))
1148 return PDMDEV_SET_ERROR(pDevIns, rc,
1149 N_("Configuration error: Failed to get the \"R0Enabled\" value"));
1150
1151 rc = CFGMR3QueryBoolDef(pCfg, "YieldOnLSRRead", &pThis->fYieldOnLSRRead, false);
1152 if (RT_FAILURE(rc))
1153 return PDMDEV_SET_ERROR(pDevIns, rc,
1154 N_("Configuration error: Failed to get the \"YieldOnLSRRead\" value"));
1155
1156 rc = CFGMR3QueryU8(pCfg, "IRQ", &irq_lvl);
1157 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1158 {
1159 /* Provide sensible defaults. */
1160 if (iInstance == 0)
1161 irq_lvl = 4;
1162 else if (iInstance == 1)
1163 irq_lvl = 3;
1164 else
1165 AssertReleaseFailed(); /* irq_lvl is undefined. */
1166 }
1167 else if (RT_FAILURE(rc))
1168 return PDMDEV_SET_ERROR(pDevIns, rc,
1169 N_("Configuration error: Failed to get the \"IRQ\" value"));
1170
1171 rc = CFGMR3QueryU16(pCfg, "IOBase", &io_base);
1172 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1173 {
1174 if (iInstance == 0)
1175 io_base = 0x3f8;
1176 else if (iInstance == 1)
1177 io_base = 0x2f8;
1178 else
1179 AssertReleaseFailed(); /* io_base is undefined */
1180 }
1181 else if (RT_FAILURE(rc))
1182 return PDMDEV_SET_ERROR(pDevIns, rc,
1183 N_("Configuration error: Failed to get the \"IOBase\" value"));
1184
1185 Log(("DevSerial: instance %d iobase=%04x irq=%d\n", iInstance, io_base, irq_lvl));
1186
1187 pThis->irq = irq_lvl;
1188#ifdef VBOX_SERIAL_PCI
1189 pThis->base = -1;
1190#else
1191 pThis->base = io_base;
1192#endif
1193
1194 /*
1195 * Initialize critical section and the semaphore.
1196 * This must of course be done before attaching drivers or anything else which can call us back..
1197 */
1198 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "Serial#%d", iInstance);
1199 if (RT_FAILURE(rc))
1200 return rc;
1201
1202 rc = RTSemEventCreate(&pThis->ReceiveSem);
1203 AssertRC(rc);
1204
1205 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, serialFifoTimer, pThis,
1206 TMTIMER_FLAGS_NO_CRIT_SECT, "Serial Fifo Timer",
1207 &pThis->fifo_timeout_timer);
1208 AssertRC(rc);
1209
1210 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, serialTransmitTimer, pThis,
1211 TMTIMER_FLAGS_NO_CRIT_SECT, "Serial Transmit Timer",
1212 &pThis->transmit_timerR3);
1213 AssertRC(rc);
1214 pThis->transmit_timerR0 = TMTimerR0Ptr(pThis->transmit_timerR3);
1215 pThis->transmit_timerRC = TMTimerRCPtr(pThis->transmit_timerR3);
1216
1217 serialReset(pDevIns);
1218
1219#ifdef VBOX_SERIAL_PCI
1220 /*
1221 * Register the PCI Device and region.
1222 */
1223 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
1224 if (RT_FAILURE(rc))
1225 return rc;
1226 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 8, PCI_ADDRESS_SPACE_IO, serialIOPortRegionMap);
1227 if (RT_FAILURE(rc))
1228 return rc;
1229
1230#else /* !VBOX_SERIAL_PCI */
1231 /*
1232 * Register the I/O ports.
1233 */
1234 pThis->base = io_base;
1235 rc = PDMDevHlpIOPortRegister(pDevIns, io_base, 8, 0,
1236 serialIOPortWrite, serialIOPortRead,
1237 NULL, NULL, "SERIAL");
1238 if (RT_FAILURE(rc))
1239 return rc;
1240
1241 if (pThis->fGCEnabled)
1242 {
1243 rc = PDMDevHlpIOPortRegisterRC(pDevIns, io_base, 8, 0, "serialIOPortWrite",
1244 "serialIOPortRead", NULL, NULL, "Serial");
1245 if (RT_FAILURE(rc))
1246 return rc;
1247 }
1248
1249
1250 if (pThis->fR0Enabled)
1251 {
1252 rc = PDMDevHlpIOPortRegisterR0(pDevIns, io_base, 8, 0, "serialIOPortWrite",
1253 "serialIOPortRead", NULL, NULL, "Serial");
1254 if (RT_FAILURE(rc))
1255 return rc;
1256 }
1257#endif /* !VBOX_SERIAL_PCI */
1258
1259 /*
1260 * Saved state.
1261 */
1262 rc = PDMDevHlpSSMRegister3(pDevIns, SERIAL_SAVED_STATE_VERSION, sizeof (*pThis),
1263 serialLiveExec, serialSaveExec, serialLoadExec);
1264 if (RT_FAILURE(rc))
1265 return rc;
1266
1267 /*
1268 * Attach the char driver and get the interfaces.
1269 * For now no run-time changes are supported.
1270 */
1271 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
1272 if (RT_SUCCESS(rc))
1273 {
1274 pThis->pDrvChar = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMICHARCONNECTOR);
1275 if (!pThis->pDrvChar)
1276 {
1277 AssertLogRelMsgFailed(("Configuration error: instance %d has no char interface!\n", iInstance));
1278 return VERR_PDM_MISSING_INTERFACE;
1279 }
1280 /** @todo provide read notification interface!!!! */
1281 }
1282 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1283 {
1284 pThis->pDrvBase = NULL;
1285 pThis->pDrvChar = NULL;
1286 LogRel(("Serial%d: no unit\n", iInstance));
1287 }
1288 else
1289 {
1290 AssertLogRelMsgFailed(("Serial%d: Failed to attach to char driver. rc=%Rrc\n", iInstance, rc));
1291 /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1292 return rc;
1293 }
1294
1295 return VINF_SUCCESS;
1296}
1297
1298
1299/**
1300 * The device registration structure.
1301 */
1302const PDMDEVREG g_DeviceSerialPort =
1303{
1304 /* u32Version */
1305 PDM_DEVREG_VERSION,
1306 /* szName */
1307 "serial",
1308 /* szRCMod */
1309 "VBoxDDGC.gc",
1310 /* szR0Mod */
1311 "VBoxDDR0.r0",
1312 /* pszDescription */
1313 "Serial Communication Port",
1314 /* fFlags */
1315 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1316 /* fClass */
1317 PDM_DEVREG_CLASS_SERIAL,
1318 /* cMaxInstances */
1319 UINT32_MAX,
1320 /* cbInstance */
1321 sizeof(SerialState),
1322 /* pfnConstruct */
1323 serialConstruct,
1324 /* pfnDestruct */
1325 serialDestruct,
1326 /* pfnRelocate */
1327 serialRelocate,
1328 /* pfnIOCtl */
1329 NULL,
1330 /* pfnPowerOn */
1331 NULL,
1332 /* pfnReset */
1333 serialReset,
1334 /* pfnSuspend */
1335 NULL,
1336 /* pfnResume */
1337 NULL,
1338 /* pfnAttach */
1339 NULL,
1340 /* pfnDetach */
1341 NULL,
1342 /* pfnQueryInterface. */
1343 NULL,
1344 /* pfnInitComplete */
1345 NULL,
1346 /* pfnPowerOff */
1347 NULL,
1348 /* pfnSoftReset */
1349 NULL,
1350 /* u32VersionEnd */
1351 PDM_DEVREG_VERSION
1352};
1353#endif /* IN_RING3 */
1354
1355#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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