DevSerial.cpp@ 4237

Last change on this file since 4237 was 4182, checked in by vboxsync, 17 years ago
Fixed a pagefault in the guest serial device on L4
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 27.5 KB

Line
1	/** @file
2	*
3	* VBox serial device:
4	* Serial communication port driver
5	*/
6
7	/*
8	* Copyright (C) 2006-2007 innotek GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*/
18
19	/*
20	* This code is based on:
21	*
22	* QEMU 16450 UART emulation
23	*
24	* Copyright (c) 2003-2004 Fabrice Bellard
25	*
26	* Permission is hereby granted, free of charge, to any person obtaining a copy
27	* of this software and associated documentation files (the "Software"), to deal
28	* in the Software without restriction, including without limitation the rights
29	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
30	* copies of the Software, and to permit persons to whom the Software is
31	* furnished to do so, subject to the following conditions:
32	*
33	* The above copyright notice and this permission notice shall be included in
34	* all copies or substantial portions of the Software.
35	*
36	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
37	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
38	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
39	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
40	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
42	* THE SOFTWARE.
43	*
44	*/
45
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_SERIAL
51	#include <VBox/pdmdev.h>
52	#include <iprt/assert.h>
53	#include <iprt/uuid.h>
54	#include <iprt/string.h>
55	#include <iprt/semaphore.h>
56	#include <iprt/critsect.h>
57
58	#include "Builtins.h"
59
60	#undef VBOX_SERIAL_PCI /* The PCI variant has lots of problems: wrong IRQ line and wrong IO base assigned. */
61
62	#ifdef VBOX_SERIAL_PCI
63	#include <VBox/pci.h>
64	#endif /* VBOX_SERIAL_PCI */
65
66	#define SERIAL_SAVED_STATE_VERSION 2
67
68	#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
69
70	#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
71	#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
72	#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
73	#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
74
75	#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
76	#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
77
78	#define UART_IIR_MSI 0x00 /* Modem status interrupt */
79	#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
80	#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
81	#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
82
83	/*
84	* These are the definitions for the Modem Control Register
85	*/
86	#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
87	#define UART_MCR_OUT2 0x08 /* Out2 complement */
88	#define UART_MCR_OUT1 0x04 /* Out1 complement */
89	#define UART_MCR_RTS 0x02 /* RTS complement */
90	#define UART_MCR_DTR 0x01 /* DTR complement */
91
92	/*
93	* These are the definitions for the Modem Status Register
94	*/
95	#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
96	#define UART_MSR_RI 0x40 /* Ring Indicator */
97	#define UART_MSR_DSR 0x20 /* Data Set Ready */
98	#define UART_MSR_CTS 0x10 /* Clear to Send */
99	#define UART_MSR_DDCD 0x08 /* Delta DCD */
100	#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
101	#define UART_MSR_DDSR 0x02 /* Delta DSR */
102	#define UART_MSR_DCTS 0x01 /* Delta CTS */
103	#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
104
105	#define UART_LSR_TEMT 0x40 /* Transmitter empty */
106	#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
107	#define UART_LSR_BI 0x10 /* Break interrupt indicator */
108	#define UART_LSR_FE 0x08 /* Frame error indicator */
109	#define UART_LSR_PE 0x04 /* Parity error indicator */
110	#define UART_LSR_OE 0x02 /* Overrun error indicator */
111	#define UART_LSR_DR 0x01 /* Receiver data ready */
112
113	struct SerialState
114	{
115	/** Access critical section. */
116	PDMCRITSECT CritSect;
117
118	/** Pointer to the device instance. */
119	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
120	/** Pointer to the device instance. */
121	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
122	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS != 64
123	RTGCPTR Alignment0;
124	#endif
125	/** The base interface. */
126	HCPTRTYPE(PDMIBASE) IBase;
127	/** The character port interface. */
128	HCPTRTYPE(PDMICHARPORT) ICharPort;
129	/** Pointer to the attached base driver. */
130	HCPTRTYPE(PPDMIBASE) pDrvBase;
131	/** Pointer to the attached character driver. */
132	HCPTRTYPE(PPDMICHAR) pDrvChar;
133
134	uint16_t divider;
135	uint16_t auAlignment[3];
136	uint8_t rbr; /* receive register */
137	uint8_t ier;
138	uint8_t iir; /* read only */
139	uint8_t lcr;
140	uint8_t mcr;
141	uint8_t lsr; /* read only */
142	uint8_t msr; /* read only */
143	uint8_t scr;
144	/* NOTE: this hidden state is necessary for tx irq generation as
145	it can be reset while reading iir */
146	int thr_ipending;
147	int irq;
148
149	bool fGCEnabled;
150	bool fR0Enabled;
151	bool afAlignment[6];
152
153	RTSEMEVENT ReceiveSem;
154	int last_break_enable;
155	uint32_t base;
156
157	#ifdef VBOX_SERIAL_PCI
158	PCIDEVICE dev;
159	#endif /* VBOX_SERIAL_PCI */
160	};
161
162	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
163
164
165	#ifdef VBOX_SERIAL_PCI
166	#define PCIDEV_2_SERIALSTATE(pPciDev) ( (SerialState *)((uintptr_t)(pPciDev) - RT_OFFSETOF(SerialState, dev)) )
167	#endif /* VBOX_SERIAL_PCI */
168	#define PDMIBASE_2_SERIALSTATE(pInstance) ( (SerialState *)((uintptr_t)(pInterface) - RT_OFFSETOF(SerialState, IBase)) )
169	#define PDMICHARPORT_2_SERIALSTATE(pInstance) ( (SerialState *)((uintptr_t)(pInterface) - RT_OFFSETOF(SerialState, ICharPort)) )
170
171
172	__BEGIN_DECLS
173	PDMBOTHCBDECL(int) serialIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
174	PDMBOTHCBDECL(int) serialIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
175	__END_DECLS
176
177	#ifdef IN_RING3
178	static void serial_update_irq(SerialState *s)
179	{
180	if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
181	s->iir = UART_IIR_RDI;
182	} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
183	s->iir = UART_IIR_THRI;
184	} else {
185	s->iir = UART_IIR_NO_INT;
186	}
187	if (s->iir != UART_IIR_NO_INT) {
188	Log(("serial_update_irq %d 1\n", s->irq));
189	#ifdef VBOX_SERIAL_PCI
190	PDMDevHlpPCISetIrqNoWait(CTXSUFF(s->pDevIns), 0, 1);
191	#else /* !VBOX_SERIAL_PCI */
192	PDMDevHlpISASetIrqNoWait(CTXSUFF(s->pDevIns), s->irq, 1);
193	#endif /* !VBOX_SERIAL_PCI */
194	} else {
195	Log(("serial_update_irq %d 0\n", s->irq));
196	#ifdef VBOX_SERIAL_PCI
197	PDMDevHlpPCISetIrqNoWait(CTXSUFF(s->pDevIns), 0, 0);
198	#else /* !VBOX_SERIAL_PCI */
199	PDMDevHlpISASetIrqNoWait(CTXSUFF(s->pDevIns), s->irq, 0);
200	#endif /* !VBOX_SERIAL_PCI */
201	}
202	}
203
204	static void serial_update_parameters(SerialState *s)
205	{
206	int speed, parity, data_bits, stop_bits;
207
208	if (s->lcr & 0x08) {
209	if (s->lcr & 0x10)
210	parity = 'E';
211	else
212	parity = 'O';
213	} else {
214	parity = 'N';
215	}
216	if (s->lcr & 0x04)
217	stop_bits = 2;
218	else
219	stop_bits = 1;
220	data_bits = (s->lcr & 0x03) + 5;
221	if (s->divider == 0)
222	return;
223	speed = 115200 / s->divider;
224	Log(("speed=%d parity=%c data=%d stop=%d\n", speed, parity, data_bits, stop_bits));
225	if (RT_LIKELY(s->pDrvChar))
226	s->pDrvChar->pfnSetParameters(s->pDrvChar, speed, parity, data_bits, stop_bits);
227	}
228	#endif
229
230	static int serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
231	{
232	SerialState s = (SerialState )opaque;
233	unsigned char ch;
234
235	addr &= 7;
236	LogFlow(("serial: write addr=0x%02x val=0x%02x\n", addr, val));
237
238	#ifndef IN_RING3
239	NOREF(ch);
240	NOREF(s);
241	return VINF_IOM_HC_IOPORT_WRITE;
242	#else
243	switch(addr) {
244	default:
245	case 0:
246	if (s->lcr & UART_LCR_DLAB) {
247	s->divider = (s->divider & 0xff00) \| val;
248	serial_update_parameters(s);
249	} else {
250	s->thr_ipending = 0;
251	s->lsr &= ~UART_LSR_THRE;
252	serial_update_irq(s);
253	ch = val;
254	if (RT_LIKELY(s->pDrvChar))
255	{
256	Log(("serial_io_port_write: write 0x%X\n", ch));
257	int rc = s->pDrvChar->pfnWrite(s->pDrvChar, &ch, 1);
258	AssertRC(rc);
259	}
260	s->thr_ipending = 1;
261	s->lsr \|= UART_LSR_THRE;
262	s->lsr \|= UART_LSR_TEMT;
263	serial_update_irq(s);
264	}
265	break;
266	case 1:
267	if (s->lcr & UART_LCR_DLAB) {
268	s->divider = (s->divider & 0x00ff) \| (val << 8);
269	serial_update_parameters(s);
270	} else {
271	s->ier = val & 0x0f;
272	if (s->lsr & UART_LSR_THRE) {
273	s->thr_ipending = 1;
274	}
275	serial_update_irq(s);
276	}
277	break;
278	case 2:
279	break;
280	case 3:
281	{
282	int break_enable;
283	s->lcr = val;
284	serial_update_parameters(s);
285	break_enable = (val >> 6) & 1;
286	if (break_enable != s->last_break_enable) {
287	s->last_break_enable = break_enable;
288	}
289	}
290	break;
291	case 4:
292	s->mcr = val & 0x1f;
293	break;
294	case 5:
295	break;
296	case 6:
297	break;
298	case 7:
299	s->scr = val;
300	break;
301	}
302	return VINF_SUCCESS;
303	#endif
304	}
305
306	static uint32_t serial_ioport_read(void opaque, uint32_t addr, int pRC)
307	{
308	SerialState s = (SerialState )opaque;
309	uint32_t ret = ~0U;
310
311	*pRC = VINF_SUCCESS;
312
313	addr &= 7;
314	switch(addr) {
315	default:
316	case 0:
317	if (s->lcr & UART_LCR_DLAB) {
318	ret = s->divider & 0xff;
319	} else {
320	#ifndef IN_RING3
321	*pRC = VINF_IOM_HC_IOPORT_READ;
322	#else
323	Log(("serial_io_port_read: read 0x%X\n", s->rbr));
324	ret = s->rbr;
325	s->lsr &= ~(UART_LSR_DR \| UART_LSR_BI);
326	serial_update_irq(s);
327	{
328	int rc = RTSemEventSignal(s->ReceiveSem);
329	AssertRC(rc);
330	}
331	#endif
332	}
333	break;
334	case 1:
335	if (s->lcr & UART_LCR_DLAB) {
336	ret = (s->divider >> 8) & 0xff;
337	} else {
338	ret = s->ier;
339	}
340	break;
341	case 2:
342	#ifndef IN_RING3
343	*pRC = VINF_IOM_HC_IOPORT_READ;
344	#else
345	ret = s->iir;
346	/* reset THR pending bit */
347	if ((ret & 0x7) == UART_IIR_THRI)
348	s->thr_ipending = 0;
349	serial_update_irq(s);
350	#endif
351	break;
352	case 3:
353	ret = s->lcr;
354	break;
355	case 4:
356	ret = s->mcr;
357	break;
358	case 5:
359	ret = s->lsr;
360	break;
361	case 6:
362	if (s->mcr & UART_MCR_LOOP) {
363	/* in loopback, the modem output pins are connected to the
364	inputs */
365	ret = (s->mcr & 0x0c) << 4;
366	ret \|= (s->mcr & 0x02) << 3;
367	ret \|= (s->mcr & 0x01) << 5;
368	} else {
369	ret = s->msr;
370	}
371	break;
372	case 7:
373	ret = s->scr;
374	break;
375	}
376	LogFlow(("serial: read addr=0x%02x val=0x%02x\n", addr, ret));
377	return ret;
378	}
379
380	#ifdef IN_RING3
381	static DECLCALLBACK(int) serialNotifyRead(PPDMICHARPORT pInterface, const void pvBuf, size_t pcbRead)
382	{
383	SerialState *pData = PDMICHARPORT_2_SERIALSTATE(pInterface);
384	int rc;
385
386	Assert(*pcbRead != 0);
387
388	PDMCritSectEnter(&pData->CritSect, VERR_PERMISSION_DENIED);
389	if (pData->lsr & UART_LSR_DR)
390	{
391	/* If a character is still in the read queue, then wait for it to be emptied. */
392	PDMCritSectLeave(&pData->CritSect);
393	rc = RTSemEventWait(pData->ReceiveSem, 250);
394	if (VBOX_FAILURE(rc))
395	return rc;
396
397	PDMCritSectEnter(&pData->CritSect, VERR_PERMISSION_DENIED);
398	}
399
400	if (!(pData->lsr & UART_LSR_DR))
401	{
402	pData->rbr = (const char )pvBuf;
403	pData->lsr \|= UART_LSR_DR;
404	serial_update_irq(pData);
405	*pcbRead = 1;
406	rc = VINF_SUCCESS;
407	}
408	else
409	rc = VERR_TIMEOUT;
410
411	PDMCritSectLeave(&pData->CritSect);
412
413	return rc;
414	}
415	#endif /* IN_RING3 */
416
417	/**
418	* Port I/O Handler for OUT operations.
419	*
420	* @returns VBox status code.
421	*
422	* @param pDevIns The device instance.
423	* @param pvUser User argument.
424	* @param Port Port number used for the IN operation.
425	* @param u32 The value to output.
426	* @param cb The value size in bytes.
427	*/
428	PDMBOTHCBDECL(int) serialIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,
429	RTIOPORT Port, uint32_t u32, unsigned cb)
430	{
431	SerialState pData = PDMINS2DATA(pDevIns, SerialState );
432	int rc = VINF_SUCCESS;
433
434	if (cb == 1)
435	{
436	rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_WRITE);
437	if (rc == VINF_SUCCESS)
438	{
439	Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, Port, u32));
440	rc = serial_ioport_write (pData, Port, u32);
441	PDMCritSectLeave(&pData->CritSect);
442	}
443	}
444	else
445	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
446
447	return rc;
448	}
449
450	/**
451	* Port I/O Handler for IN operations.
452	*
453	* @returns VBox status code.
454	*
455	* @param pDevIns The device instance.
456	* @param pvUser User argument.
457	* @param Port Port number used for the IN operation.
458	* @param u32 The value to output.
459	* @param cb The value size in bytes.
460	*/
461	PDMBOTHCBDECL(int) serialIOPortRead(PPDMDEVINS pDevIns, void *pvUser,
462	RTIOPORT Port, uint32_t *pu32, unsigned cb)
463	{
464	SerialState pData = PDMINS2DATA(pDevIns, SerialState );
465	int rc = VINF_SUCCESS;
466
467	if (cb == 1)
468	{
469	rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_READ);
470	if (rc == VINF_SUCCESS)
471	{
472	*pu32 = serial_ioport_read (pData, Port, &rc);
473	Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, Port, *pu32));
474	PDMCritSectLeave(&pData->CritSect);
475	}
476	}
477	else
478	rc = VERR_IOM_IOPORT_UNUSED;
479
480	return rc;
481	}
482
483	#ifdef IN_RING3
484	/**
485	* Saves a state of the serial port device.
486	*
487	* @returns VBox status code.
488	* @param pDevIns The device instance.
489	* @param pSSMHandle The handle to save the state to.
490	*/
491	static DECLCALLBACK(int) serialSaveExec(PPDMDEVINS pDevIns,
492	PSSMHANDLE pSSMHandle)
493	{
494	SerialState pData = PDMINS2DATA(pDevIns, SerialState );
495
496	SSMR3PutU16(pSSMHandle, pData->divider);
497	SSMR3PutU8(pSSMHandle, pData->rbr);
498	SSMR3PutU8(pSSMHandle, pData->ier);
499	SSMR3PutU8(pSSMHandle, pData->lcr);
500	SSMR3PutU8(pSSMHandle, pData->mcr);
501	SSMR3PutU8(pSSMHandle, pData->lsr);
502	SSMR3PutU8(pSSMHandle, pData->msr);
503	SSMR3PutU8(pSSMHandle, pData->scr);
504	SSMR3PutS32(pSSMHandle, pData->thr_ipending);
505	SSMR3PutS32(pSSMHandle, pData->irq);
506	SSMR3PutS32(pSSMHandle, pData->last_break_enable);
507	SSMR3PutU32(pSSMHandle, pData->base);
508	return SSMR3PutU32(pSSMHandle, ~0); /* sanity/terminator */
509	}
510
511	/**
512	* Loads a saved serial port device state.
513	*
514	* @returns VBox status code.
515	* @param pDevIns The device instance.
516	* @param pSSMHandle The handle to the saved state.
517	* @param u32Version The data unit version number.
518	*/
519	static DECLCALLBACK(int) serialLoadExec(PPDMDEVINS pDevIns,
520	PSSMHANDLE pSSMHandle,
521	uint32_t u32Version)
522	{
523	int rc;
524	uint32_t u32;
525	SerialState pData = PDMINS2DATA(pDevIns, SerialState );
526
527	if (u32Version != SERIAL_SAVED_STATE_VERSION)
528	{
529	AssertMsgFailed(("u32Version=%d\n", u32Version));
530	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
531	}
532
533	SSMR3GetU16(pSSMHandle, &pData->divider);
534	SSMR3GetU8(pSSMHandle, &pData->rbr);
535	SSMR3GetU8(pSSMHandle, &pData->ier);
536	SSMR3GetU8(pSSMHandle, &pData->lcr);
537	SSMR3GetU8(pSSMHandle, &pData->mcr);
538	SSMR3GetU8(pSSMHandle, &pData->lsr);
539	SSMR3GetU8(pSSMHandle, &pData->msr);
540	SSMR3GetU8(pSSMHandle, &pData->scr);
541	SSMR3GetS32(pSSMHandle, &pData->thr_ipending);
542	SSMR3GetS32(pSSMHandle, &pData->irq);
543	SSMR3GetS32(pSSMHandle, &pData->last_break_enable);
544	SSMR3GetU32(pSSMHandle, &pData->base);
545
546	rc = SSMR3GetU32(pSSMHandle, &u32);
547	if (VBOX_FAILURE(rc))
548	return rc;
549
550	if (u32 != ~0U)
551	{
552	AssertMsgFailed(("u32=%#x expected ~0\n", u32));
553	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
554	}
555	/* Be careful with pointers in the structure; they are not preserved
556	* in the saved state. */
557
558	if (pData->lsr & UART_LSR_DR)
559	{
560	int rc = RTSemEventSignal(pData->ReceiveSem);
561	AssertRC(rc);
562	}
563	pData->pDevInsHC = pDevIns;
564	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
565	return VINF_SUCCESS;
566	}
567
568
569	/**
570	* @copydoc FNPDMDEVRELOCATE
571	*/
572	static DECLCALLBACK(void) serialRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
573	{
574	SerialState pData = PDMINS2DATA(pDevIns, SerialState );
575	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
576	}
577
578	#ifdef VBOX_SERIAL_PCI
579
580	static DECLCALLBACK(int) serialIOPortRegionMap(PPCIDEVICE pPciDev, /* unsigned */ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
581	{
582	SerialState *pData = PCIDEV_2_SERIALSTATE(pPciDev);
583	int rc = VINF_SUCCESS;
584
585	Assert(enmType == PCI_ADDRESS_SPACE_IO);
586	Assert(iRegion == 0);
587	Assert(cb == 8);
588	AssertMsg(RT_ALIGN(GCPhysAddress, 8) == GCPhysAddress, ("Expected 8 byte alignment. GCPhysAddress=%#x\n", GCPhysAddress));
589
590	pData->base = (RTIOPORT)GCPhysAddress;
591	LogRel(("Serial#%d: mapping I/O at %#06x\n", pData->pDevIns->iInstance, pData->base));
592
593	/*
594	* Register our port IO handlers.
595	*/
596	rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress, 8, (void *)pData,
597	serial_io_write, serial_io_read, NULL, NULL, "SERIAL");
598	AssertRC(rc);
599	return rc;
600	}
601
602	#endif /* VBOX_SERIAL_PCI */
603
604
605	/** @copyfrom PIBASE::pfnqueryInterface */
606	static DECLCALLBACK(void *) serialQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
607	{
608	SerialState *pData = PDMIBASE_2_SERIALSTATE(pInterface);
609	switch (enmInterface)
610	{
611	case PDMINTERFACE_BASE:
612	return &pData->IBase;
613	case PDMINTERFACE_CHAR_PORT:
614	return &pData->ICharPort;
615	default:
616	return NULL;
617	}
618	}
619
620	/**
621	* Destruct a device instance.
622	*
623	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
624	* resources can be freed correctly.
625	*
626	* @returns VBox status.
627	* @param pDevIns The device instance data.
628	*/
629	static DECLCALLBACK(int) serialDestruct(PPDMDEVINS pDevIns)
630	{
631	SerialState pData = PDMINS2DATA(pDevIns, SerialState );
632
633	RTSemEventDestroy(pData->ReceiveSem);
634	pData->ReceiveSem = NIL_RTSEMEVENT;
635
636	PDMR3CritSectDelete(&pData->CritSect);
637	return VINF_SUCCESS;
638	}
639
640
641	/**
642	* Construct a device instance for a VM.
643	*
644	* @returns VBox status.
645	* @param pDevIns The device instance data.
646	* If the registration structure is needed, pDevIns->pDevReg points to it.
647	* @param iInstance Instance number. Use this to figure out which registers and such to use.
648	* The device number is also found in pDevIns->iInstance, but since it's
649	* likely to be freqently used PDM passes it as parameter.
650	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
651	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
652	* iInstance it's expected to be used a bit in this function.
653	*/
654	static DECLCALLBACK(int) serialConstruct(PPDMDEVINS pDevIns,
655	int iInstance,
656	PCFGMNODE pCfgHandle)
657	{
658	int rc;
659	SerialState pData = PDMINS2DATA(pDevIns, SerialState);
660	uint16_t io_base;
661	uint8_t irq_lvl;
662
663	Assert(iInstance < 4);
664
665	pData->pDevInsHC = pDevIns;
666	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
667
668	/*
669	* Validate configuration.
670	*/
671	if (!CFGMR3AreValuesValid(pCfgHandle, "IRQ\0IOBase\0"))
672	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
673
674	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &pData->fGCEnabled);
675	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
676	pData->fGCEnabled = true;
677	else if (VBOX_FAILURE(rc))
678	return PDMDEV_SET_ERROR(pDevIns, rc,
679	N_("Configuration error: Failed to get the \"GCEnabled\" value"));
680
681	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &pData->fR0Enabled);
682	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
683	pData->fR0Enabled = true;
684	else if (VBOX_FAILURE(rc))
685	return PDMDEV_SET_ERROR(pDevIns, rc,
686	N_("Configuration error: Failed to get the \"R0Enabled\" value"));
687
688	/* IBase */
689	pData->IBase.pfnQueryInterface = serialQueryInterface;
690
691	/* ICharPort */
692	pData->ICharPort.pfnNotifyRead = serialNotifyRead;
693
694	rc = RTSemEventCreate(&pData->ReceiveSem);
695	AssertRC(rc);
696
697	/*
698	* Initialize critical section.
699	* This must of course be done before attaching drivers or anything else which can call us back..
700	*/
701	char szName[24];
702	RTStrPrintf(szName, sizeof(szName), "Serial#%d", iInstance);
703	rc = PDMDevHlpCritSectInit(pDevIns, &pData->CritSect, szName);
704	if (VBOX_FAILURE(rc))
705	return rc;
706
707	/** @todo r=bird: Check for VERR_CFGM_VALUE_NOT_FOUND and provide sensible defaults.
708	* Also do AssertMsgFailed(("Configuration error:....)) in the failure cases of CFGMR3Query*()
709	* and CFGR3AreValuesValid() like we're doing in the other devices. */
710	rc = CFGMR3QueryU8 (pCfgHandle, "IRQ", &irq_lvl);
711	if (VBOX_FAILURE (rc))
712	return rc;
713
714	rc = CFGMR3QueryU16 (pCfgHandle, "IOBase", &io_base);
715	if (VBOX_FAILURE (rc))
716	return rc;
717
718	Log(("serialConstruct instance %d iobase=%04x irq=%d\n", iInstance, io_base, irq_lvl));
719
720	pData->irq = irq_lvl;
721	pData->lsr = UART_LSR_TEMT \| UART_LSR_THRE;
722	pData->iir = UART_IIR_NO_INT;
723	pData->msr = UART_MSR_DCD \| UART_MSR_DSR \| UART_MSR_CTS;
724	#ifdef VBOX_SERIAL_PCI
725	pData->base = -1;
726	pData->dev.config[0x00] = 0xee; /* Vendor: ??? */
727	pData->dev.config[0x01] = 0x80;
728	pData->dev.config[0x02] = 0x01; /* Device: ??? */
729	pData->dev.config[0x03] = 0x01;
730	pData->dev.config[0x04] = PCI_COMMAND_IOACCESS;
731	pData->dev.config[0x09] = 0x01; /* Programming interface: 16450 */
732	pData->dev.config[0x0a] = 0x00; /* Subclass: Serial controller */
733	pData->dev.config[0x0b] = 0x07; /* Class: Communication controller */
734	pData->dev.config[0x0e] = 0x00; /* Header type: standard */
735	pData->dev.config[0x3c] = irq_lvl; /* preconfigure IRQ number (0 = autoconfig)*/
736	pData->dev.config[0x3d] = 1; /* interrupt pin 0 */
737	rc = PDMDevHlpPCIRegister(pDevIns, &pData->dev);
738	if (VBOX_FAILURE(rc))
739	return rc;
740	/*
741	* Register the PCI I/O ports.
742	*/
743	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 8, PCI_ADDRESS_SPACE_IO, serialIOPortRegionMap);
744	if (VBOX_FAILURE(rc))
745	return rc;
746	#else /* !VBOX_SERIAL_PCI */
747	pData->base = io_base;
748	rc = PDMDevHlpIOPortRegister(pDevIns, io_base, 8, 0,
749	serialIOPortWrite, serialIOPortRead,
750	NULL, NULL, "SERIAL");
751	if (VBOX_FAILURE (rc))
752	return rc;
753
754	if (pData->fGCEnabled)
755	rc = PDMDevHlpIOPortRegisterGC(pDevIns, io_base, 8, 0, "serialIOPortWrite",
756	"serialIOPortRead", NULL, NULL, "Serial");
757
758	if (pData->fR0Enabled)
759	rc = PDMDevHlpIOPortRegisterR0(pDevIns, io_base, 8, 0, "serialIOPortWrite",
760	"serialIOPortRead", NULL, NULL, "Serial");
761
762	#endif /* !VBOX_SERIAL_PCI */
763
764	/* Attach the char driver and get the interfaces. For now no run-time
765	* changes are supported. */
766	rc = PDMDevHlpDriverAttach(pDevIns, 0, &pData->IBase, &pData->pDrvBase, "Serial Char");
767	if (VBOX_SUCCESS(rc))
768	{
769	pData->pDrvChar = (PDMICHAR *)pData->pDrvBase->pfnQueryInterface(pData->pDrvBase, PDMINTERFACE_CHAR);
770	if (!pData->pDrvChar)
771	{
772	AssertMsgFailed(("Configuration error: instance %d has no char interface!\n", iInstance));
773	return VERR_PDM_MISSING_INTERFACE;
774	}
775	/** @todo provide read notification interface!!!! */
776	}
777	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
778	{
779	pData->pDrvBase = NULL;
780	pData->pDrvChar = NULL;
781	LogRel(("Serial%d: no unit\n", iInstance));
782	}
783	else
784	{
785	AssertMsgFailed(("Serial%d: Failed to attach to char driver. rc=%Vrc\n", iInstance, rc));
786	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
787	N_("Serial device %d cannot attach to char driver\n"), iInstance);
788	}
789
790	rc = PDMDevHlpSSMRegister (
791	pDevIns, /* pDevIns */
792	pDevIns->pDevReg->szDeviceName, /* pszName */
793	iInstance, /* u32Instance */
794	SERIAL_SAVED_STATE_VERSION, /* u32Version */
795	sizeof (pData), / cbGuess */
796	NULL, /* pfnSavePrep */
797	serialSaveExec, /* pfnSaveExec */
798	NULL, /* pfnSaveDone */
799	NULL, /* pfnLoadPrep */
800	serialLoadExec, /* pfnLoadExec */
801	NULL /* pfnLoadDone */
802	);
803	if (VBOX_FAILURE(rc))
804	return rc;
805
806	return VINF_SUCCESS;
807	}
808
809	/**
810	* The device registration structure.
811	*/
812	const PDMDEVREG g_DeviceSerialPort =
813	{
814	/* u32Version */
815	PDM_DEVREG_VERSION,
816	/* szDeviceName */
817	"serial",
818	/* szGCMod */
819	"VBoxDDGC.gc",
820	/* szR0Mod */
821	"VBoxDDR0.r0",
822	/* pszDescription */
823	"Serial Communication Port",
824	/* fFlags */
825	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
826	/* fClass */
827	PDM_DEVREG_CLASS_SERIAL,
828	/* cMaxInstances */
829	1,
830	/* cbInstance */
831	sizeof(SerialState),
832	/* pfnConstruct */
833	serialConstruct,
834	/* pfnDestruct */
835	serialDestruct,
836	/* pfnRelocate */
837	serialRelocate,
838	/* pfnIOCtl */
839	NULL,
840	/* pfnPowerOn */
841	NULL,
842	/* pfnReset */
843	NULL,
844	/* pfnSuspend */
845	NULL,
846	/* pfnResume */
847	NULL,
848	/* pfnAttach */
849	NULL,
850	/* pfnDetach */
851	NULL,
852	/* pfnQueryInterface. */
853	NULL
854	};
855	#endif /* IN_RING3 */
856
857
858	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Serial/DevSerial.cpp@ 4237

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