UartCore.cpp@ 73558

Last change on this file since 73558 was 73528, checked in by vboxsync, 6 years ago
Devices/Serial/UartCore: Fix adjusting the amount of available bytes to read when the FIFO is enabled while there is something in the RBR register
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1	/* $Id: UartCore.cpp 73528 2018-08-06 15:15:09Z vboxsync $ */
2	/** @file
3	* UartCore - UART (16550A up to 16950) emulation.
4	*
5	* The documentation for this device was taken from the PC16550D spec from TI.
6	*/
7
8	/*
9	* Copyright (C) 2018 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*********************************************************************************************************************************
22	* Header Files *
23	*********************************************************************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25	#include <VBox/vmm/tm.h>
26	#include <iprt/log.h>
27	#include <iprt/uuid.h>
28	#include <iprt/assert.h>
29
30	#include "VBoxDD.h"
31	#include "UartCore.h"
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37
38	/** The RBR/DLL register index (from the base of the port range). */
39	#define UART_REG_RBR_DLL_INDEX 0
40
41	/** The THR/DLL register index (from the base of the port range). */
42	#define UART_REG_THR_DLL_INDEX 0
43
44	/** The IER/DLM register index (from the base of the port range). */
45	#define UART_REG_IER_DLM_INDEX 1
46	/** Enable received data available interrupt */
47	# define UART_REG_IER_ERBFI RT_BIT(0)
48	/** Enable transmitter holding register empty interrupt */
49	# define UART_REG_IER_ETBEI RT_BIT(1)
50	/** Enable receiver line status interrupt */
51	# define UART_REG_IER_ELSI RT_BIT(2)
52	/** Enable modem status interrupt. */
53	# define UART_REG_IER_EDSSI RT_BIT(3)
54	/** Sleep mode enable. */
55	# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56	/** Low power mode enable. */
57	# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58	/** Mask of writeable bits. */
59	# define UART_REG_IER_MASK_WR 0x0f
60	/** Mask of writeable bits for 16750+. */
61	# define UART_REG_IER_MASK_WR_16750 0x3f
62
63	/** The IIR register index (from the base of the port range). */
64	#define UART_REG_IIR_INDEX 2
65	/** Interrupt Pending - high means no interrupt pending. */
66	# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67	/** Interrupt identification mask. */
68	# define UART_REG_IIR_ID_MASK 0x0e
69	/** Sets the interrupt identification to the given value. */
70	# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71	/** Receiver Line Status interrupt. */
72	# define UART_REG_IIR_ID_RCL 0x3
73	/** Received Data Available interrupt. */
74	# define UART_REG_IIR_ID_RDA 0x2
75	/** Character Timeou Indicator interrupt. */
76	# define UART_REG_IIR_ID_CTI 0x6
77	/** Transmitter Holding Register Empty interrupt. */
78	# define UART_REG_IIR_ID_THRE 0x1
79	/** Modem Status interrupt. */
80	# define UART_REG_IIR_ID_MS 0x0
81	/** 64 byte FIFOs enabled (15750+ only). */
82	# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
83	/** FIFOs enabled. */
84	# define UART_REG_IIR_FIFOS_EN 0xc0
85	/** Bits relevant for checking whether the interrupt status has changed. */
86	# define UART_REG_IIR_CHANGED_MASK 0x0f
87
88	/** The FCR register index (from the base of the port range). */
89	#define UART_REG_FCR_INDEX 2
90	/** Enable the TX/RX FIFOs. */
91	# define UART_REG_FCR_FIFO_EN RT_BIT(0)
92	/** Reset the receive FIFO. */
93	# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
94	/** Reset the transmit FIFO. */
95	# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
96	/** DMA Mode Select. */
97	# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
98	/** 64 Byte FIFO enable (15750+ only). */
99	# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
100	/** Receiver level interrupt trigger. */
101	# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
102	/** Returns the receive level trigger value from the given FCR register. */
103	# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
104	/** RCV Interrupt trigger level - 1 byte. */
105	# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
106	/** RCV Interrupt trigger level - 4 bytes. */
107	# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
108	/** RCV Interrupt trigger level - 8 bytes. */
109	# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
110	/** RCV Interrupt trigger level - 14 bytes. */
111	# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
112	/** Mask of writeable bits. */
113	# define UART_REG_FCR_MASK_WR 0xcf
114	/** Mask of sticky bits. */
115	# define UART_REG_FCR_MASK_STICKY 0xe9
116
117	/** The LCR register index (from the base of the port range). */
118	#define UART_REG_LCR_INDEX 3
119	/** Word Length Select Mask. */
120	# define UART_REG_LCR_WLS_MASK 0x3
121	/** Returns the WLS value form the given LCR register value. */
122	# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
123	/** Number of stop bits. */
124	# define UART_REG_LCR_STB RT_BIT(2)
125	/** Parity Enable. */
126	# define UART_REG_LCR_PEN RT_BIT(3)
127	/** Even Parity. */
128	# define UART_REG_LCR_EPS RT_BIT(4)
129	/** Stick parity. */
130	# define UART_REG_LCR_PAR_STICK RT_BIT(5)
131	/** Set Break. */
132	# define UART_REG_LCR_BRK_SET RT_BIT(6)
133	/** Divisor Latch Access Bit. */
134	# define UART_REG_LCR_DLAB RT_BIT(7)
135
136	/** The MCR register index (from the base of the port range). */
137	#define UART_REG_MCR_INDEX 4
138	/** Data Terminal Ready. */
139	# define UART_REG_MCR_DTR RT_BIT(0)
140	/** Request To Send. */
141	# define UART_REG_MCR_RTS RT_BIT(1)
142	/** Out1. */
143	# define UART_REG_MCR_OUT1 RT_BIT(2)
144	/** Out2. */
145	# define UART_REG_MCR_OUT2 RT_BIT(3)
146	/** Loopback connection. */
147	# define UART_REG_MCR_LOOP RT_BIT(4)
148	/** Flow Control Enable (15750+ only). */
149	# define UART_REG_MCR_AFE RT_BIT(5)
150	/** Mask of writeable bits (15450 and 15550A). */
151	# define UART_REG_MCR_MASK_WR 0x1f
152	/** Mask of writeable bits (15750+). */
153	# define UART_REG_MCR_MASK_WR_15750 0x3f
154
155	/** The LSR register index (from the base of the port range). */
156	#define UART_REG_LSR_INDEX 5
157	/** Data Ready. */
158	# define UART_REG_LSR_DR RT_BIT(0)
159	/** Overrun Error. */
160	# define UART_REG_LSR_OE RT_BIT(1)
161	/** Parity Error. */
162	# define UART_REG_LSR_PE RT_BIT(2)
163	/** Framing Error. */
164	# define UART_REG_LSR_FE RT_BIT(3)
165	/** Break Interrupt. */
166	# define UART_REG_LSR_BI RT_BIT(4)
167	/** Transmitter Holding Register. */
168	# define UART_REG_LSR_THRE RT_BIT(5)
169	/** Transmitter Empty. */
170	# define UART_REG_LSR_TEMT RT_BIT(6)
171	/** Error in receiver FIFO. */
172	# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
173	/** The bits to check in this register when checking for the RCL interrupt. */
174	# define UART_REG_LSR_BITS_IIR_RCL 0x1e
175
176	/** The MSR register index (from the base of the port range). */
177	#define UART_REG_MSR_INDEX 6
178	/** Delta Clear to Send. */
179	# define UART_REG_MSR_DCTS RT_BIT(0)
180	/** Delta Data Set Ready. */
181	# define UART_REG_MSR_DDSR RT_BIT(1)
182	/** Trailing Edge Ring Indicator. */
183	# define UART_REG_MSR_TERI RT_BIT(2)
184	/** Delta Data Carrier Detect. */
185	# define UART_REG_MSR_DDCD RT_BIT(3)
186	/** Clear to Send. */
187	# define UART_REG_MSR_CTS RT_BIT(4)
188	/** Data Set Ready. */
189	# define UART_REG_MSR_DSR RT_BIT(5)
190	/** Ring Indicator. */
191	# define UART_REG_MSR_RI RT_BIT(6)
192	/** Data Carrier Detect. */
193	# define UART_REG_MSR_DCD RT_BIT(7)
194	/** The bits to check in this register when checking for the MS interrupt. */
195	# define UART_REG_MSR_BITS_IIR_MS 0x0f
196
197	/** The SCR register index (from the base of the port range). */
198	#define UART_REG_SCR_INDEX 7
199
200	/** Set the specified bits in the given register. */
201	#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) \|= (a_Set))
202	/** Clear the specified bits in the given register. */
203	#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
204
205
206	/*********************************************************************************************************************************
207	* Structures and Typedefs *
208	*********************************************************************************************************************************/
209
210	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
211
212
213	/*********************************************************************************************************************************
214	* Global Variables *
215	*********************************************************************************************************************************/
216
217	#ifdef IN_RING3
218	/**
219	* FIFO ITL levels.
220	*/
221	static struct
222	{
223	/** ITL level for a 16byte FIFO. */
224	uint8_t cbItl16;
225	/** ITL level for a 64byte FIFO. */
226	uint8_t cbItl64;
227	} s_aFifoItl[] =
228	{
229	/* cbItl16 cbItl64 */
230	{ 1, 1 },
231	{ 4, 16 },
232	{ 8, 32 },
233	{ 14, 56 }
234	};
235
236
237	/**
238	* String versions of the parity enum.
239	*/
240	static const char *s_aszParity[] =
241	{
242	"INVALID",
243	"NONE",
244	"EVEN",
245	"ODD",
246	"MARK",
247	"SPACE",
248	"INVALID"
249	};
250
251
252	/**
253	* String versions of the stop bits enum.
254	*/
255	static const char *s_aszStopBits[] =
256	{
257	"INVALID",
258	"1",
259	"1.5",
260	"2",
261	"INVALID"
262	};
263	#endif
264
265
266	/*********************************************************************************************************************************
267	* Internal Functions *
268	*********************************************************************************************************************************/
269
270
271	/**
272	* Updates the IRQ state based on the current device state.
273	*
274	* @returns nothing.
275	* @param pThis The UART core instance.
276	*/
277	static void uartIrqUpdate(PUARTCORE pThis)
278	{
279	LogFlowFunc(("pThis=%#p\n", pThis));
280
281	/*
282	* The interrupt uses a priority scheme, only the interrupt with the
283	* highest priority is indicated in the interrupt identification register.
284	*
285	* The priorities are as follows (high to low):
286	* * Receiver line status
287	* * Received data available
288	* * Character timeout indication (only in FIFO mode).
289	* * Transmitter holding register empty
290	* * Modem status change.
291	*/
292	uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
293	if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
294	&& (pThis->uRegIer & UART_REG_IER_ELSI))
295	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
296	else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
297	&& pThis->fIrqCtiPending)
298	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
299	else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
300	&& (pThis->uRegIer & UART_REG_IER_ERBFI)
301	&& ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
302	\|\| pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
303	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
304	else if ( (pThis->uRegLsr & UART_REG_LSR_THRE)
305	&& (pThis->uRegIer & UART_REG_IER_ETBEI))
306	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
307	else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
308	&& (pThis->uRegIer & UART_REG_IER_EDSSI))
309	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
310
311	LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
312
313	/* Change interrupt only if the interrupt status really changed from the previous value. */
314	if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
315	{
316	LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
317	pThis->uRegIir, uRegIirNew,
318	pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
319	uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
320	if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
321	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 0);
322	else
323	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 1);
324	}
325	else
326	LogFlow((" No change in interrupt source\n"));
327
328	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
329	uRegIirNew \|= UART_REG_IIR_FIFOS_EN;
330	if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
331	uRegIirNew \|= UART_REG_IIR_64BYTE_FIFOS_EN;
332
333	pThis->uRegIir = uRegIirNew;
334	}
335
336
337	#ifdef IN_RING3
338	/**
339	* Clears the given FIFO.
340	*
341	* @returns nothing.
342	* @param pFifo The FIFO to clear.
343	*/
344	DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
345	{
346	memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
347	pFifo->cbUsed = 0;
348	pFifo->offWrite = 0;
349	pFifo->offRead = 0;
350	}
351
352
353	/**
354	* Returns the amount of free bytes in the given FIFO.
355	*
356	* @returns The amount of bytes free in the given FIFO.
357	* @param pFifo The FIFO.
358	*/
359	DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
360	{
361	return pFifo->cbMax - pFifo->cbUsed;
362	}
363
364
365	/**
366	* Puts a new character into the given FIFO.
367	*
368	* @returns Flag whether the FIFO overflowed.
369	* @param pFifo The FIFO to put the data into.
370	* @param fOvrWr Flag whether to overwrite data if the FIFO is full.
371	* @param bData The data to add.
372	*/
373	DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
374	{
375	if (fOvrWr \|\| pFifo->cbUsed < pFifo->cbMax)
376	{
377	pFifo->abBuf[pFifo->offWrite] = bData;
378	pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
379	}
380
381	bool fOverFlow = false;
382	if (pFifo->cbUsed < pFifo->cbMax)
383	pFifo->cbUsed++;
384	else
385	{
386	fOverFlow = true;
387	if (fOvrWr) /* Advance the read position to account for the lost character. */
388	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
389	}
390
391	return fOverFlow;
392	}
393	#endif
394
395
396	/**
397	* Returns the next character in the FIFO.
398	*
399	* @return Next byte in the FIFO.
400	* @param pFifo The FIFO to get data from.
401	*/
402	DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
403	{
404	uint8_t bRet = 0;
405
406	if (pFifo->cbUsed)
407	{
408	bRet = pFifo->abBuf[pFifo->offRead];
409	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
410	pFifo->cbUsed--;
411	}
412
413	return bRet;
414	}
415
416
417	#ifdef IN_RING3
418	/**
419	* Tries to copy the requested amount of data from the given FIFO into the provided buffer.
420	*
421	* @returns Amount of bytes actually copied.
422	* @param pFifo The FIFO to copy data from.
423	* @param pvDst Where to copy the data to.
424	* @param cbCopy How much to copy.
425	*/
426	DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
427	{
428	size_t cbCopied = 0;
429	uint8_t pbDst = (uint8_t )pvDst;
430
431	cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
432	while (cbCopy)
433	{
434	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
435	memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
436
437	pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
438	pFifo->cbUsed -= cbThisCopy;
439	pbDst += cbThisCopy;
440	cbCopied += cbThisCopy;
441	cbCopy -= cbThisCopy;
442	}
443
444	return cbCopied;
445	}
446
447
448	#if 0 /* unused */
449	/**
450	* Tries to copy the requested amount of data from the provided buffer into the given FIFO.
451	*
452	* @returns Amount of bytes actually copied.
453	* @param pFifo The FIFO to copy data to.
454	* @param pvSrc Where to copy the data from.
455	* @param cbCopy How much to copy.
456	*/
457	DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
458	{
459	size_t cbCopied = 0;
460	uint8_t pbSrc = (uint8_t )pvSrc;
461
462	cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
463	while (cbCopy)
464	{
465	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
466	memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
467
468	pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
469	pFifo->cbUsed += cbThisCopy;
470	pbSrc += cbThisCopy;
471	cbCopied += cbThisCopy;
472	cbCopy -= cbThisCopy;
473	}
474
475	return cbCopied;
476	}
477	#endif
478
479
480	/**
481	* Updates the delta bits for the given MSR register value which has the status line
482	* bits set.
483	*
484	* @returns nothing.
485	* @param pThis The serial port instance.
486	* @param uMsrSts MSR value with the appropriate status bits set.
487	*/
488	static void uartR3MsrUpdate(PUARTCORE pThis, uint8_t uMsrSts)
489	{
490	/* Compare current and new states and set remaining bits accordingly. */
491	if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
492	uMsrSts \|= UART_REG_MSR_DCTS;
493	if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
494	uMsrSts \|= UART_REG_MSR_DDSR;
495	if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
496	uMsrSts \|= UART_REG_MSR_TERI;
497	if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
498	uMsrSts \|= UART_REG_MSR_DDCD;
499
500	pThis->uRegMsr = uMsrSts;
501
502	uartIrqUpdate(pThis);
503	}
504
505
506	/**
507	* Updates the serial port parameters of the attached driver with the current configuration.
508	*
509	* @returns nothing.
510	* @param pThis The serial port instance.
511	*/
512	static void uartR3ParamsUpdate(PUARTCORE pThis)
513	{
514	if ( pThis->uRegDivisor != 0
515	&& pThis->pDrvSerial)
516	{
517	uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
518	unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
519	uint32_t cFrameBits = cDataBits;
520	PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
521	PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
522
523	if (pThis->uRegLcr & UART_REG_LCR_STB)
524	{
525	enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
526	cFrameBits += 2;
527	}
528	else
529	cFrameBits++;
530
531	if (pThis->uRegLcr & UART_REG_LCR_PEN)
532	{
533	/* Select the correct parity mode based on the even and stick parity bits. */
534	switch (pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK))
535	{
536	case 0:
537	enmParity = PDMSERIALPARITY_ODD;
538	break;
539	case UART_REG_LCR_EPS:
540	enmParity = PDMSERIALPARITY_EVEN;
541	break;
542	case UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK:
543	enmParity = PDMSERIALPARITY_SPACE;
544	break;
545	case UART_REG_LCR_PAR_STICK:
546	enmParity = PDMSERIALPARITY_MARK;
547	break;
548	default:
549	/* We should never get here as all cases where caught earlier. */
550	AssertMsgFailed(("This shouldn't happen at all: %#x\n",
551	pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK)));
552	}
553
554	cFrameBits++;
555	}
556
557	uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
558	pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
559
560	LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
561	uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
562
563	int rc = pThis->pDrvSerial->pfnChgParams(pThis->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
564	if (RT_FAILURE(rc))
565	LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
566	pThis->pDevInsR3->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
567
568	/* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
569	ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
570	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
571	}
572	}
573
574
575	/**
576	* Updates the internal device state with the given PDM status line states.
577	*
578	* @returns nothing.
579	* @param pThis The serial port instance.
580	* @param fStsLines The PDM status line states.
581	*/
582	static void uartR3StsLinesUpdate(PUARTCORE pThis, uint32_t fStsLines)
583	{
584	uint8_t uRegMsrNew = 0; /* The new MSR value. */
585
586	if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
587	uRegMsrNew \|= UART_REG_MSR_DCD;
588	if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
589	uRegMsrNew \|= UART_REG_MSR_RI;
590	if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
591	uRegMsrNew \|= UART_REG_MSR_DSR;
592	if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
593	uRegMsrNew \|= UART_REG_MSR_CTS;
594
595	uartR3MsrUpdate(pThis, uRegMsrNew);
596	}
597
598
599	/**
600	* Fills up the receive FIFO with as much data as possible.
601	*
602	* @returns nothing.
603	* @param pThis The serial port instance.
604	*/
605	static void uartR3RecvFifoFill(PUARTCORE pThis)
606	{
607	LogFlowFunc(("pThis=%#p\n", pThis));
608
609	PUARTFIFO pFifo = &pThis->FifoRecv;
610	size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
611	ASMAtomicReadU32(&pThis->cbAvailRdr));
612	size_t cbFilled = 0;
613
614	while (cbFilled < cbFill)
615	{
616	size_t cbThisRead = cbFill - cbFilled;
617
618	if (pFifo->offRead <= pFifo->offWrite)
619	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
620	else
621	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
622
623	size_t cbRead = 0;
624	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
625	AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
626
627	pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
628	pFifo->cbUsed += (uint8_t)cbRead;
629	cbFilled += cbRead;
630
631	if (cbRead < cbThisRead)
632	break;
633	}
634
635	if (cbFilled)
636	{
637	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
638	uartIrqUpdate(pThis);
639	}
640
641	Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
642	ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
643	}
644
645
646	/**
647	* Fetches a single byte and writes it to RBR.
648	*
649	* @returns nothing.
650	* @param pThis The serial port instance.
651	*/
652	static void uartR3ByteFetch(PUARTCORE pThis)
653	{
654	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
655	{
656	AssertPtr(pThis->pDrvSerial);
657	size_t cbRead = 0;
658	int rc2 = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
659	AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
660	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
661	uartIrqUpdate(pThis);
662	}
663	}
664
665
666	/**
667	* Fetches a ready data based on the FIFO setting.
668	*
669	* @returns nothing.
670	* @param pThis The serial port instance.
671	*/
672	static void uartR3DataFetch(PUARTCORE pThis)
673	{
674	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
675	uartR3RecvFifoFill(pThis);
676	else
677	uartR3ByteFetch(pThis);
678	}
679
680
681	/**
682	* Reset the transmit/receive related bits to the standard values
683	* (after a detach/attach/reset event).
684	*
685	* @returns nothing.
686	* @param pThis The serial port instance.
687	*/
688	static void uartR3XferReset(PUARTCORE pThis)
689	{
690	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
691
692	uartFifoClear(&pThis->FifoXmit);
693	uartFifoClear(&pThis->FifoRecv);
694	uartR3ParamsUpdate(pThis);
695	uartIrqUpdate(pThis);
696
697	if (pThis->pDrvSerial)
698	{
699	/* Set the modem lines to reflect the current state. */
700	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
701	if (RT_FAILURE(rc))
702	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
703	pThis->pDevInsR3->iInstance, rc));
704
705	uint32_t fStsLines = 0;
706	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
707	if (RT_SUCCESS(rc))
708	uartR3StsLinesUpdate(pThis, fStsLines);
709	else
710	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
711	pThis->pDevInsR3->iInstance, rc));
712	}
713
714	}
715	#endif
716
717
718	/**
719	* Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
720	*
721	* @returns VBox status code.
722	* @param pThis The serial port instance.
723	* @param uVal The value to write.
724	*/
725	DECLINLINE(int) uartRegThrDllWrite(PUARTCORE pThis, uint8_t uVal)
726	{
727	int rc = VINF_SUCCESS;
728
729	/* A set DLAB causes a write to the lower 8bits of the divisor latch. */
730	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
731	{
732	if (uVal != (pThis->uRegDivisor & 0xff))
733	{
734	#ifndef IN_RING3
735	rc = VINF_IOM_R3_IOPORT_WRITE;
736	#else
737	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) \| uVal;
738	uartR3ParamsUpdate(pThis);
739	#endif
740	}
741	}
742	else
743	{
744	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
745	{
746	#ifndef IN_RING3
747	rc = VINF_IOM_R3_IOPORT_WRITE;
748	#else
749	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, uVal);
750	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
751	uartIrqUpdate(pThis);
752	if (pThis->pDrvSerial)
753	{
754	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial, 1);
755	if (RT_FAILURE(rc2))
756	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
757	}
758	#endif
759	}
760	else
761	{
762	/* Notify the lower driver about available data only if the register was empty before. */
763	if (pThis->uRegLsr & UART_REG_LSR_THRE)
764	{
765	#ifndef IN_RING3
766	rc = VINF_IOM_R3_IOPORT_WRITE;
767	#else
768	pThis->uRegThr = uVal;
769	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
770	uartIrqUpdate(pThis);
771	if (pThis->pDrvSerial)
772	{
773	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial, 1);
774	if (RT_FAILURE(rc2))
775	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
776	}
777	#endif
778	}
779	else
780	pThis->uRegThr = uVal;
781	}
782	}
783
784	return rc;
785	}
786
787
788	/**
789	* Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
790	*
791	* @returns VBox status code.
792	* @param pThis The serial port instance.
793	* @param uVal The value to write.
794	*/
795	DECLINLINE(int) uartRegIerDlmWrite(PUARTCORE pThis, uint8_t uVal)
796	{
797	int rc = VINF_SUCCESS;
798
799	/* A set DLAB causes a write to the higher 8bits of the divisor latch. */
800	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
801	{
802	if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
803	{
804	#ifndef IN_RING3
805	rc = VINF_IOM_R3_IOPORT_WRITE;
806	#else
807	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) \| (uVal << 8);
808	uartR3ParamsUpdate(pThis);
809	#endif
810	}
811	}
812	else
813	{
814	if (pThis->enmType < UARTTYPE_16750)
815	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
816	else
817	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
818	uartIrqUpdate(pThis);
819	}
820
821	return rc;
822	}
823
824
825	/**
826	* Write handler for the FCR register.
827	*
828	* @returns VBox status code.
829	* @param pThis The serial port instance.
830	* @param uVal The value to write.
831	*/
832	DECLINLINE(int) uartRegFcrWrite(PUARTCORE pThis, uint8_t uVal)
833	{
834	#ifndef IN_RING3
835	RT_NOREF(pThis, uVal);
836	return VINF_IOM_R3_IOPORT_WRITE;
837	#else
838	int rc = VINF_SUCCESS;
839	if ( pThis->enmType >= UARTTYPE_16550A
840	&& uVal != pThis->uRegFcr)
841	{
842	/* A change in the FIFO enable bit clears both FIFOs automatically. */
843	if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
844	{
845	uartFifoClear(&pThis->FifoXmit);
846	uartFifoClear(&pThis->FifoRecv);
847
848	/*
849	* If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
850	* byte in the RBR register which will be lost so we have to adjust the available bytes.
851	*/
852	if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
853	&& (uVal & UART_REG_FCR_FIFO_EN))
854	ASMAtomicDecU32(&pThis->cbAvailRdr);
855
856	/* Clear the DR bit too. */
857	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
858	}
859
860	if (rc == VINF_SUCCESS)
861	{
862	if (uVal & UART_REG_FCR_RCV_FIFO_RST)
863	{
864	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
865	pThis->fIrqCtiPending = false;
866	uartFifoClear(&pThis->FifoRecv);
867	}
868	if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
869	uartFifoClear(&pThis->FifoXmit);
870
871	/*
872	* The 64byte FIFO enable bit is only changeable for 16750
873	* and if the DLAB bit in LCR is set.
874	*/
875	if ( pThis->enmType < UARTTYPE_16750
876	\|\| !(pThis->uRegLcr & UART_REG_LCR_DLAB))
877	uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
878	else /* Use previous value. */
879	uVal \|= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
880
881	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
882	{
883	pThis->FifoRecv.cbMax = 64;
884	pThis->FifoXmit.cbMax = 64;
885	}
886	else
887	{
888	pThis->FifoRecv.cbMax = 16;
889	pThis->FifoXmit.cbMax = 16;
890	}
891
892	if (uVal & UART_REG_FCR_FIFO_EN)
893	{
894	uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
895	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
896	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
897	else
898	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
899	}
900
901	/* The FIFO reset bits are self clearing. */
902	pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
903	uartIrqUpdate(pThis);
904	}
905
906	/* Fill in the next data. */
907	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
908	uartR3DataFetch(pThis);
909	}
910
911	return rc;
912	#endif
913	}
914
915
916	/**
917	* Write handler for the LCR register.
918	*
919	* @returns VBox status code.
920	* @param pThis The serial port instance.
921	* @param uVal The value to write.
922	*/
923	DECLINLINE(int) uartRegLcrWrite(PUARTCORE pThis, uint8_t uVal)
924	{
925	int rc = VINF_SUCCESS;
926
927	/* Any change except the DLAB bit causes a switch to R3. */
928	if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
929	{
930	#ifndef IN_RING3
931	rc = VINF_IOM_R3_IOPORT_WRITE;
932	#else
933	/* Check whether the BREAK bit changed before updating the LCR value. */
934	bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
935	bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
936	pThis->uRegLcr = uVal;
937	uartR3ParamsUpdate(pThis);
938
939	if ( fBrkChg
940	&& pThis->pDrvSerial)
941	pThis->pDrvSerial->pfnChgBrk(pThis->pDrvSerial, fBrkEn);
942	#endif
943	}
944	else
945	pThis->uRegLcr = uVal;
946
947	return rc;
948	}
949
950
951	/**
952	* Write handler for the MCR register.
953	*
954	* @returns VBox status code.
955	* @param pThis The serial port instance.
956	* @param uVal The value to write.
957	*/
958	DECLINLINE(int) uartRegMcrWrite(PUARTCORE pThis, uint8_t uVal)
959	{
960	int rc = VINF_SUCCESS;
961
962	if (pThis->enmType < UARTTYPE_16750)
963	uVal &= UART_REG_MCR_MASK_WR;
964	else
965	uVal &= UART_REG_MCR_MASK_WR_15750;
966	if (pThis->uRegMcr != uVal)
967	{
968	#ifndef IN_RING3
969	rc = VINF_IOM_R3_IOPORT_WRITE;
970	#else
971	/*
972	* When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
973	* disconnected and looped back to MSR.
974	*/
975	if ( (uVal & UART_REG_MCR_LOOP)
976	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP)
977	&& pThis->pDrvSerial)
978	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
979
980	pThis->uRegMcr = uVal;
981	if (uVal & UART_REG_MCR_LOOP)
982	{
983	uint8_t uRegMsrSts = 0;
984
985	if (uVal & UART_REG_MCR_RTS)
986	uRegMsrSts \|= UART_REG_MSR_CTS;
987	if (uVal & UART_REG_MCR_DTR)
988	uRegMsrSts \|= UART_REG_MSR_DSR;
989	if (uVal & UART_REG_MCR_OUT1)
990	uRegMsrSts \|= UART_REG_MSR_RI;
991	if (uVal & UART_REG_MCR_OUT2)
992	uRegMsrSts \|= UART_REG_MSR_DCD;
993	uartR3MsrUpdate(pThis, uRegMsrSts);
994	}
995	else if (pThis->pDrvSerial)
996	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
997	RT_BOOL(uVal & UART_REG_MCR_RTS),
998	RT_BOOL(uVal & UART_REG_MCR_DTR));
999	#endif
1000	}
1001
1002	return rc;
1003	}
1004
1005
1006	/**
1007	* Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
1008	*
1009	* @returns VBox status code.
1010	* @param pThis The serial port instance.
1011	* @param puVal Where to store the read value on success.
1012	*/
1013	DECLINLINE(int) uartRegRbrDllRead(PUARTCORE pThis, uint32_t *puVal)
1014	{
1015	int rc = VINF_SUCCESS;
1016
1017	/* A set DLAB causes a read from the lower 8bits of the divisor latch. */
1018	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1019	*puVal = pThis->uRegDivisor & 0xff;
1020	else
1021	{
1022	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1023	{
1024	/*
1025	* Only go back to R3 if there is new data available for the FIFO
1026	* and we would clear the interrupt to fill it up again.
1027	*/
1028	if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
1029	&& ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
1030	{
1031	#ifndef IN_RING3
1032	rc = VINF_IOM_R3_IOPORT_READ;
1033	#else
1034	uartR3RecvFifoFill(pThis);
1035	#endif
1036	}
1037
1038	if (rc == VINF_SUCCESS)
1039	{
1040	*puVal = uartFifoGet(&pThis->FifoRecv);
1041	pThis->fIrqCtiPending = false;
1042	if (!pThis->FifoRecv.cbUsed)
1043	{
1044	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
1045	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1046	}
1047	else
1048	{
1049	uint64_t tsCtiFire = TMTimerGet(pThis->CTX_SUFF(pTimerRcvFifoTimeout)) + pThis->cSymbolXferTicks * 4;
1050	TMTimerSet(pThis->CTX_SUFF(pTimerRcvFifoTimeout), tsCtiFire);
1051	}
1052	uartIrqUpdate(pThis);
1053	}
1054	}
1055	else
1056	{
1057	*puVal = pThis->uRegRbr;
1058
1059	if (pThis->uRegLsr & UART_REG_LSR_DR)
1060	{
1061	Assert(pThis->cbAvailRdr);
1062	uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1063	if (!cbAvail)
1064	{
1065	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1066	uartIrqUpdate(pThis);
1067	}
1068	else
1069	{
1070	#ifndef IN_RING3
1071	/* Restore state and go back to R3. */
1072	ASMAtomicIncU32(&pThis->cbAvailRdr);
1073	rc = VINF_IOM_R3_IOPORT_READ;
1074	#else
1075	/* Fetch new data and keep the DR bit set. */
1076	uartR3DataFetch(pThis);
1077	#endif
1078	}
1079	}
1080	}
1081	}
1082
1083	return rc;
1084	}
1085
1086
1087	/**
1088	* Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1089	*
1090	* @returns VBox status code.
1091	* @param pThis The serial port instance.
1092	* @param puVal Where to store the read value on success.
1093	*/
1094	DECLINLINE(int) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1095	{
1096	int rc = VINF_SUCCESS;
1097
1098	/* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1099	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1100	*puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1101	else
1102	*puVal = pThis->uRegIer;
1103
1104	return rc;
1105	}
1106
1107
1108	/**
1109	* Read handler for the IIR register.
1110	*
1111	* @returns VBox status code.
1112	* @param pThis The serial port instance.
1113	* @param puVal Where to store the read value on success.
1114	*/
1115	DECLINLINE(int) uartRegIirRead(PUARTCORE pThis, uint32_t *puVal)
1116	{
1117	*puVal = pThis->uRegIir;
1118	return VINF_SUCCESS;
1119	}
1120
1121
1122	/**
1123	* Read handler for the LSR register.
1124	*
1125	* @returns VBox status code.
1126	* @param pThis The serial port instance.
1127	* @param puVal Where to store the read value on success.
1128	*/
1129	DECLINLINE(int) uartRegLsrRead(PUARTCORE pThis, uint32_t *puVal)
1130	{
1131	int rc = VINF_SUCCESS;
1132
1133	/* Yield if configured and there is no data available. */
1134	if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1135	&& (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1136	{
1137	#ifndef IN_RING3
1138	return VINF_IOM_R3_IOPORT_READ;
1139	#else
1140	RTThreadYield();
1141	#endif
1142	}
1143
1144	*puVal = pThis->uRegLsr;
1145	/*
1146	* Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1147	* as well as the Break Interrupt (BI).
1148	*/
1149	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1150	uartIrqUpdate(pThis);
1151
1152	return rc;
1153	}
1154
1155
1156	/**
1157	* Read handler for the MSR register.
1158	*
1159	* @returns VBox status code.
1160	* @param pThis The serial port instance.
1161	* @param puVal Where to store the read value on success.
1162	*/
1163	DECLINLINE(int) uartRegMsrRead(PUARTCORE pThis, uint32_t *puVal)
1164	{
1165	*puVal = pThis->uRegMsr;
1166
1167	/* Clear any of the delta bits. */
1168	UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1169	uartIrqUpdate(pThis);
1170	return VINF_SUCCESS;
1171	}
1172
1173
1174	#ifdef LOG_ENABLED
1175	/**
1176	* Converts the register index into a sensible memnonic.
1177	*
1178	* @returns Register memnonic.
1179	* @param pThis The serial port instance.
1180	* @param idxReg Register index.
1181	* @param fWrite Flag whether the register gets written.
1182	*/
1183	DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1184	{
1185	const char *psz = "INV";
1186
1187	switch (idxReg)
1188	{
1189	/case UART_REG_THR_DLL_INDEX:/
1190	case UART_REG_RBR_DLL_INDEX:
1191	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1192	psz = "DLL";
1193	else if (fWrite)
1194	psz = "THR";
1195	else
1196	psz = "RBR";
1197	break;
1198	case UART_REG_IER_DLM_INDEX:
1199	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1200	psz = "DLM";
1201	else
1202	psz = "IER";
1203	break;
1204	/case UART_REG_IIR_INDEX:/
1205	case UART_REG_FCR_INDEX:
1206	if (fWrite)
1207	psz = "FCR";
1208	else
1209	psz = "IIR";
1210	break;
1211	case UART_REG_LCR_INDEX:
1212	psz = "LCR";
1213	break;
1214	case UART_REG_MCR_INDEX:
1215	psz = "MCR";
1216	break;
1217	case UART_REG_LSR_INDEX:
1218	psz = "LSR";
1219	break;
1220	case UART_REG_MSR_INDEX:
1221	psz = "MSR";
1222	break;
1223	case UART_REG_SCR_INDEX:
1224	psz = "SCR";
1225	break;
1226	}
1227
1228	return psz;
1229	}
1230	#endif
1231
1232
1233	DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb)
1234	{
1235	AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1236
1237	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1238	if (rc != VINF_SUCCESS)
1239	return rc;
1240
1241	uint8_t idxReg = uReg & 0x7;
1242	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1243	pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /fWrite/), u32, cb));
1244
1245	uint8_t uVal = (uint8_t)u32;
1246	switch (idxReg)
1247	{
1248	case UART_REG_THR_DLL_INDEX:
1249	rc = uartRegThrDllWrite(pThis, uVal);
1250	break;
1251	case UART_REG_IER_DLM_INDEX:
1252	rc = uartRegIerDlmWrite(pThis, uVal);
1253	break;
1254	case UART_REG_FCR_INDEX:
1255	rc = uartRegFcrWrite(pThis, uVal);
1256	break;
1257	case UART_REG_LCR_INDEX:
1258	rc = uartRegLcrWrite(pThis, uVal);
1259	break;
1260	case UART_REG_MCR_INDEX:
1261	rc = uartRegMcrWrite(pThis, uVal);
1262	break;
1263	case UART_REG_SCR_INDEX:
1264	pThis->uRegScr = u32;
1265	break;
1266	default:
1267	break;
1268	}
1269
1270	PDMCritSectLeave(&pThis->CritSect);
1271	LogFlowFunc(("-> %Rrc\n", rc));
1272	return rc;
1273	}
1274
1275
1276	DECLHIDDEN(int) uartRegRead(PUARTCORE pThis, uint32_t uReg, uint32_t *pu32, size_t cb)
1277	{
1278	if (cb != 1)
1279	return VERR_IOM_IOPORT_UNUSED;
1280
1281	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1282	if (rc != VINF_SUCCESS)
1283	return rc;
1284
1285	uint8_t idxReg = uReg & 0x7;
1286	switch (idxReg)
1287	{
1288	case UART_REG_RBR_DLL_INDEX:
1289	rc = uartRegRbrDllRead(pThis, pu32);
1290	break;
1291	case UART_REG_IER_DLM_INDEX:
1292	rc = uartRegIerDlmRead(pThis, pu32);
1293	break;
1294	case UART_REG_IIR_INDEX:
1295	rc = uartRegIirRead(pThis, pu32);
1296	break;
1297	case UART_REG_LCR_INDEX:
1298	*pu32 = pThis->uRegLcr;
1299	break;
1300	case UART_REG_MCR_INDEX:
1301	*pu32 = pThis->uRegMcr;
1302	break;
1303	case UART_REG_LSR_INDEX:
1304	rc = uartRegLsrRead(pThis, pu32);
1305	break;
1306	case UART_REG_MSR_INDEX:
1307	rc = uartRegMsrRead(pThis, pu32);
1308	break;
1309	case UART_REG_SCR_INDEX:
1310	*pu32 = pThis->uRegScr;
1311	break;
1312	default:
1313	rc = VERR_IOM_IOPORT_UNUSED;
1314	}
1315
1316	PDMCritSectLeave(&pThis->CritSect);
1317	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1318	pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /fWrite/), *pu32, cb, rc));
1319	return rc;
1320	}
1321
1322
1323	#ifdef IN_RING3
1324
1325	/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1326
1327	/**
1328	* @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1329	*/
1330	static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1331	{
1332	RT_NOREF(pDevIns, pTimer);
1333	PUARTCORE pThis = (PUARTCORE)pvUser;
1334	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1335	if (pThis->FifoRecv.cbUsed)
1336	{
1337	pThis->fIrqCtiPending = true;
1338	uartIrqUpdate(pThis);
1339	}
1340	PDMCritSectLeave(&pThis->CritSect);
1341	}
1342
1343
1344	/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1345
1346
1347	/**
1348	* @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1349	*/
1350	static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1351	{
1352	LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1353	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1354
1355	AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1356
1357	uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1358	LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
1359	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1360	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1361	uartR3RecvFifoFill(pThis);
1362	else if (!cbAvailOld)
1363	{
1364	size_t cbRead = 0;
1365	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1366	AssertMsg(RT_SUCCESS(rc) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc);
1367	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1368	uartIrqUpdate(pThis);
1369	}
1370	PDMCritSectLeave(&pThis->CritSect);
1371
1372	return VINF_SUCCESS;
1373	}
1374
1375
1376	/**
1377	* @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1378	*/
1379	static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1380	{
1381	LogFlowFunc(("pInterface=%#p\n", pInterface));
1382	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1383
1384	/* Set the transmitter empty bit because everything was sent. */
1385	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1386	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1387	uartIrqUpdate(pThis);
1388	PDMCritSectLeave(&pThis->CritSect);
1389	return VINF_SUCCESS;
1390	}
1391
1392
1393	/**
1394	* @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1395	*/
1396	static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void pvBuf, size_t cbRead, size_t pcbRead)
1397	{
1398	LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1399	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1400
1401	AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1402
1403	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1404	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1405	{
1406	*pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
1407	if (!pThis->FifoXmit.cbUsed)
1408	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
1409	if (*pcbRead)
1410	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
1411	uartIrqUpdate(pThis);
1412	}
1413	else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
1414	{
1415	(uint8_t )pvBuf = pThis->uRegThr;
1416	*pcbRead = 1;
1417	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
1418	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
1419	uartIrqUpdate(pThis);
1420	}
1421	else
1422	{
1423	/*
1424	* This can happen if there was data in the FIFO when the connection was closed,
1425	* idicate this condition to the lower driver by returning 0 bytes.
1426	*/
1427	*pcbRead = 0;
1428	}
1429	PDMCritSectLeave(&pThis->CritSect);
1430
1431	LogFlowFunc(("-> VINF_SUCCESS{pcbRead=%zu}\n", pcbRead));
1432	return VINF_SUCCESS;
1433	}
1434
1435
1436	/**
1437	* @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1438	*/
1439	static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1440	{
1441	LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1442	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1443
1444	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1445	uartR3StsLinesUpdate(pThis, fNewStatusLines);
1446	PDMCritSectLeave(&pThis->CritSect);
1447	return VINF_SUCCESS;
1448	}
1449
1450
1451	/**
1452	* @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1453	*/
1454	static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1455	{
1456	LogFlowFunc(("pInterface=%#p\n", pInterface));
1457	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1458
1459	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1460	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1461	uartIrqUpdate(pThis);
1462	PDMCritSectLeave(&pThis->CritSect);
1463	return VINF_SUCCESS;
1464	}
1465
1466
1467	/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1468
1469	/**
1470	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1471	*/
1472	static DECLCALLBACK(void ) uartR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
1473	{
1474	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, IBase);
1475	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1476	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThis->ISerialPort);
1477	return NULL;
1478	}
1479
1480
1481	DECLHIDDEN(int) uartR3SaveExec(PUARTCORE pThis, PSSMHANDLE pSSM)
1482	{
1483	SSMR3PutU16(pSSM, pThis->uRegDivisor);
1484	SSMR3PutU8(pSSM, pThis->uRegRbr);
1485	SSMR3PutU8(pSSM, pThis->uRegThr);
1486	SSMR3PutU8(pSSM, pThis->uRegIer);
1487	SSMR3PutU8(pSSM, pThis->uRegIir);
1488	SSMR3PutU8(pSSM, pThis->uRegFcr);
1489	SSMR3PutU8(pSSM, pThis->uRegLcr);
1490	SSMR3PutU8(pSSM, pThis->uRegMcr);
1491	SSMR3PutU8(pSSM, pThis->uRegLsr);
1492	SSMR3PutU8(pSSM, pThis->uRegMsr);
1493	SSMR3PutU8(pSSM, pThis->uRegScr);
1494	SSMR3PutBool(pSSM, pThis->fIrqCtiPending);
1495	SSMR3PutU8(pSSM, pThis->FifoXmit.cbMax);
1496	SSMR3PutU8(pSSM, pThis->FifoXmit.cbItl);
1497	SSMR3PutU8(pSSM, pThis->FifoRecv.cbMax);
1498	SSMR3PutU8(pSSM, pThis->FifoRecv.cbItl);
1499
1500	return TMR3TimerSave(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1501	}
1502
1503
1504	DECLHIDDEN(int) uartR3LoadExec(PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1505	uint8_t puIrq, RTIOPORT pPortBase)
1506	{
1507	RT_NOREF(uPass);
1508	int rc = VINF_SUCCESS;
1509
1510	if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1511	{
1512	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1513	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1514	SSMR3GetU8(pSSM, &pThis->uRegThr);
1515	SSMR3GetU8(pSSM, &pThis->uRegIer);
1516	SSMR3GetU8(pSSM, &pThis->uRegIir);
1517	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1518	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1519	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1520	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1521	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1522	SSMR3GetU8(pSSM, &pThis->uRegScr);
1523	SSMR3GetBool(pSSM, &pThis->fIrqCtiPending);
1524	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbMax);
1525	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbItl);
1526	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbMax);
1527	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1528
1529	TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1530	}
1531	else
1532	{
1533	if (uVersion == UART_SAVED_STATE_VERSION_16450)
1534	{
1535	pThis->enmType = UARTTYPE_16450;
1536	LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pThis->pDevInsR3->iInstance));
1537	}
1538
1539	int uIrq;
1540	uint32_t PortBase;
1541
1542	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1543	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1544	SSMR3GetU8(pSSM, &pThis->uRegIer);
1545	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1546	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1547	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1548	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1549	SSMR3GetU8(pSSM, &pThis->uRegScr);
1550	if (uVersion > UART_SAVED_STATE_VERSION_16450)
1551	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1552	SSMR3Skip(pSSM, sizeof(int32_t));
1553	SSMR3GetS32(pSSM, &uIrq);
1554	SSMR3Skip(pSSM, sizeof(int32_t));
1555	SSMR3GetU32(pSSM, &PortBase);
1556	rc = SSMR3Skip(pSSM, sizeof(int32_t));
1557
1558	if ( RT_SUCCESS(rc)
1559	&& uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1560	{
1561	SSMR3GetU8(pSSM, &pThis->uRegThr);
1562	SSMR3Skip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1563	SSMR3GetU8(pSSM, &pThis->uRegIir);
1564
1565	int iTimeoutPending = 0;
1566	SSMR3GetS32(pSSM, &iTimeoutPending);
1567	pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1568
1569	TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1570	TMR3TimerSkip(pSSM, NULL);
1571	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1572	rc = SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1573	}
1574
1575	if (RT_SUCCESS(rc))
1576	{
1577	AssertPtr(puIrq);
1578	AssertPtr(pPortBase);
1579	*puIrq = (uint8_t)uIrq;
1580	*pPortBase = (RTIOPORT)PortBase;
1581	}
1582	}
1583
1584	return rc;
1585	}
1586
1587
1588	DECLHIDDEN(int) uartR3LoadDone(PUARTCORE pThis, PSSMHANDLE pSSM)
1589	{
1590	RT_NOREF(pSSM);
1591
1592	uartR3ParamsUpdate(pThis);
1593	uartIrqUpdate(pThis);
1594
1595	if (pThis->pDrvSerial)
1596	{
1597	/* Set the modem lines to reflect the current state. */
1598	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1599	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1600	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1601	if (RT_FAILURE(rc))
1602	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1603	pThis->pDevInsR3->iInstance, rc));
1604
1605	uint32_t fStsLines = 0;
1606	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
1607	if (RT_SUCCESS(rc))
1608	uartR3StsLinesUpdate(pThis, fStsLines);
1609	else
1610	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1611	pThis->pDevInsR3->iInstance, rc));
1612	}
1613
1614	return VINF_SUCCESS;
1615	}
1616
1617
1618	DECLHIDDEN(void) uartR3Relocate(PUARTCORE pThis, RTGCINTPTR offDelta)
1619	{
1620	RT_NOREF(offDelta);
1621	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
1622	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1623	}
1624
1625
1626	DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis)
1627	{
1628	pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1629	pThis->uRegRbr = 0;
1630	pThis->uRegThr = 0;
1631	pThis->uRegIer = 0;
1632	pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1633	pThis->uRegFcr = 0;
1634	pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1635	pThis->uRegMcr = 0;
1636	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
1637	pThis->uRegMsr = 0; /* Updated below. */
1638	pThis->uRegScr = 0;
1639	pThis->fIrqCtiPending = false;
1640
1641	/* Standard FIFO size for 15550A. */
1642	pThis->FifoXmit.cbMax = 16;
1643	pThis->FifoRecv.cbMax = 16;
1644	pThis->FifoRecv.cbItl = 1;
1645
1646	uartR3XferReset(pThis);
1647	}
1648
1649
1650	DECLHIDDEN(int) uartR3Attach(PUARTCORE pThis, unsigned iLUN)
1651	{
1652	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
1653	if (RT_SUCCESS(rc))
1654	{
1655	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1656	if (!pThis->pDrvSerial)
1657	{
1658	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pThis->pDevInsR3->iInstance));
1659	return VERR_PDM_MISSING_INTERFACE;
1660	}
1661	uartR3XferReset(pThis);
1662	}
1663	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1664	{
1665	pThis->pDrvBase = NULL;
1666	pThis->pDrvSerial = NULL;
1667	rc = VINF_SUCCESS;
1668	uartR3XferReset(pThis);
1669	LogRel(("Serial#%d: no unit\n", pThis->pDevInsR3->iInstance));
1670	}
1671	else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1672	LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pThis->pDevInsR3->iInstance, rc));
1673
1674	return rc;
1675	}
1676
1677
1678	DECLHIDDEN(void) uartR3Detach(PUARTCORE pThis)
1679	{
1680	/* Zero out important members. */
1681	pThis->pDrvBase = NULL;
1682	pThis->pDrvSerial = NULL;
1683	uartR3XferReset(pThis);
1684	}
1685
1686
1687	DECLHIDDEN(void) uartR3Destruct(PUARTCORE pThis)
1688	{
1689	PDMR3CritSectDelete(&pThis->CritSect);
1690	}
1691
1692
1693	DECLHIDDEN(int) uartR3Init(PUARTCORE pThis, PPDMDEVINS pDevInsR3, UARTTYPE enmType, unsigned iLUN, uint32_t fFlags,
1694	R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3, R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0,
1695	RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC)
1696	{
1697	int rc = VINF_SUCCESS;
1698
1699	/*
1700	* Initialize the instance data.
1701	* (Do this early or the destructor might choke on something!)
1702	*/
1703	pThis->pDevInsR3 = pDevInsR3;
1704	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevInsR3);
1705	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevInsR3);
1706	pThis->iLUN = iLUN;
1707	pThis->enmType = enmType;
1708	pThis->fFlags = fFlags;
1709	pThis->pfnUartIrqReqR3 = pfnUartIrqReqR3;
1710	pThis->pfnUartIrqReqR0 = pfnUartIrqReqR0;
1711	pThis->pfnUartIrqReqRC = pfnUartIrqReqRC;
1712
1713	/* IBase */
1714	pThis->IBase.pfnQueryInterface = uartR3QueryInterface;
1715
1716	/* ISerialPort */
1717	pThis->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
1718	pThis->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
1719	pThis->ISerialPort.pfnReadWr = uartR3ReadWr;
1720	pThis->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
1721	pThis->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
1722
1723	rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
1724	pDevInsR3->pReg->szName, pDevInsR3->iInstance, iLUN);
1725	AssertRCReturn(rc, rc);
1726
1727	/*
1728	* Attach the char driver and get the interfaces.
1729	*/
1730	rc = PDMDevHlpDriverAttach(pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "UART");
1731	if (RT_SUCCESS(rc))
1732	{
1733	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1734	if (!pThis->pDrvSerial)
1735	{
1736	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
1737	return VERR_PDM_MISSING_INTERFACE;
1738	}
1739	}
1740	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1741	{
1742	pThis->pDrvBase = NULL;
1743	pThis->pDrvSerial = NULL;
1744	LogRel(("Serial#%d: no unit\n", iLUN));
1745	}
1746	else
1747	{
1748	AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
1749	/* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1750	return rc;
1751	}
1752
1753	/*
1754	* Create the receive FIFO character timeout indicator timer.
1755	*/
1756	rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThis,
1757	TMTIMER_FLAGS_NO_CRIT_SECT, "UART Rcv FIFO Timer",
1758	&pThis->pTimerRcvFifoTimeoutR3);
1759	AssertRCReturn(rc, rc);
1760
1761	rc = TMR3TimerSetCritSect(pThis->pTimerRcvFifoTimeoutR3, &pThis->CritSect);
1762	AssertRCReturn(rc, rc);
1763
1764	pThis->pTimerRcvFifoTimeoutR0 = TMTimerR0Ptr(pThis->pTimerRcvFifoTimeoutR3);
1765	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1766
1767	uartR3Reset(pThis);
1768	return VINF_SUCCESS;
1769	}
1770
1771	#endif /* IN_RING3 */
1772
1773	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 73558

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